System-level verification platform for PCIe bus network interface cards

Abstract

The present invention provides a system-level verification platform for a PCIe bus network interface card, comprising: a PCIe UVC component, a GMAC UVC component, a scoreboard module, a checker component, a JTAG UVC component, and a design under test (DUT); the PCIe UVC component is connected to the design under test (DUT); the PCIe UVC component is connected to the scoreboard module; the DUT is connected to the GMAC UVC component; the GMAC UVC component is connected to the scoreboard module; the GMAC UVC component is connected to the checker component; the checker component is connected to the scoreboard module; an external send test sequence sends data frames to the PCIe UVC component, and an external receive test sequence sends data frames to the GMAC UVC component. The present invention has multi-level checksum detection, enabling real-time verification of data frames.

Description

Technical Field

[0001] The present invention relates to the technical field of network systems, and in particular to a system-level verification platform for a PCIe bus network interface card, and in particular to a system-level verification platform for a PCIe bus 10 / 100 / 1000Mbps network interface card. Background Art

[0002] Chips, known as the "food of industry," are core technologies for the manufacturing industry, and the chip industry is a crucial component. Currently, the structures of integrated circuits (ICs) are becoming increasingly complex, with an increasing number of logic gates integrated within a single chip. Chip verification technology, a crucial component of IC design, must continue to evolve alongside this increasing complexity. my country's development in the field of IC design and verification is relatively lagging. Existing traditional Verilog-based verification methods suffer from low efficiency, poor reusability, difficulty increasing verification coverage, and the often significant human and material resources required, making it difficult to guarantee verification accuracy. The System Verilog-based UVM verification methodology introduces a universal verification platform featuring object-oriented programming, dynamic threading and multi-threaded communication, random testing, and automatic collection of functional and code coverage, significantly improving chip verification efficiency.

[0003] PCIe-based Ethernet interface cards typically feature complex, high-speed bus interfaces, including an Ethernet interface and a high-speed PCIe interface on the host side. Furthermore, the characteristics of each interface are often directly related to the interface card, and coordination between these interfaces is essential for the proper functioning of the network interface card. Therefore, even using the UVM verification methodology to build a verification platform still presents challenges such as high verification complexity and difficulty in platform establishment. Currently, no relevant system-level verification platform has been released, which undoubtedly severely restricts the rapid development and verification of Ethernet interface card chips and hinders the localization of these chips.

[0004] Therefore, how to use the UVM verification methodology to build a system-level verification platform for PCIe-based Ethernet interface cards and complete high-coverage, high-efficiency, and high-reusability verification is an urgent problem that needs to be solved. Summary of the Invention

[0005] In view of the defects in the prior art, the present invention aims to provide a system-level verification platform for a PCIe bus network interface card.

[0006] According to the present invention, a system-level verification platform for a PCIe bus network interface card is provided, comprising: a PCIe UVC component, a GMAC UVC component, a scoreboard module, a checker component, a JTAG UVC component, and a design under test (DUT);

[0007] The PCIe UVC component is connected to the DUT to be tested, and data frames are transmitted between the PCIe UVC component and the DUT to be tested; the PCIe UVC component is connected to the scoreboard module, and the PCIe UVC component sends frame records to the scoreboard module;

[0008] The DUT to be tested is connected to the GMAC UVC component, and data frames are transmitted between the DUT to be tested and the GMAC UVC component; the GMAC UVC component is connected to the scoreboard module, and the GMAC UVC component sends frame records to the scoreboard module;

[0009] The GMAC UVC component is connected to the checker component, and data frames are transmitted between the GMAC UVC component and the checker component; the checker component is connected to the scoreboard module, and the checker component sends frame records to the scoreboard module;

[0010] The external sending test sequence sends a data frame to the PCIe UVC component, and the external receiving test sequence sends a data frame to the GMAC UVC component.

[0011] Preferably, the PCIe UVC component includes a first Driver component, a first Monitor component, a first Sequencer component and a first configuration module;

[0012] The first Driver component completes the mapping of PCIe transactions to PCIe VIP underlying read and write;

[0013] The first Monitor component monitors data communication of the PCIe interface and sends the detected data to the scoreboard of the scoreboard module through TLM communication for data comparison;

[0014] The first Sequencer component connects the first Driver component and an external sequence;

[0015] The first configuration module is used to configure configuration information of the PCIe UVC component.

[0016] Preferably, the GMAC UVC component includes a second Driver component, a second Monitor component, a second Sequencer component and a second configuration module;

[0017] The second Driver component converts the GMII transaction into a GMII interface signal;

[0018] The second Monitor component simultaneously detects changes in interface signals on both the receiving and transmitting sides of the network interface, automatically identifies the transmission of data frames, and reports the identified data frames to the scoreboard of the scoreboard module;

[0019] The second Sequencer component connects the second Driver component and an external sequence.

[0020] Preferably, the configuration parameters of the first configuration module include the following parameters:

[0021] The number of PCIe channels, the memory base address of the lane, the interrupt memory base address of the channel lane, the basic information of sending and receiving Ring, and the timeout period for sending confirmation and recovery.

[0022] Preferably, the first Driver component has a built-in transmitting TX Ring module and a receiving RX Ring module to implement the transmitting and receiving Ring rings.

[0023] Preferably, the TX Ring module implements the following tasks:

[0024] Init Task: Executes the initialization of the Ring, so that the information of each entry in the Ring is written to the on-chip register of the design under test (DUT) through the PCIe memory write task MemWr_DW task;

[0025] Enable Task: Notifies the design under test (DUT) to enable the sending operation of the sending ring;

[0026] Recycle Task: A resident infinite loop task responsible for reading the head register update of the DUT and sequentially checking whether the specific bit corresponding to each entry in the ring head is written back by the DUT after the update, indicating that the transmission is completed; if the specific bit is updated, indicating that the transmission is complete, the corresponding transaction layer data packet is sent to the scoreboard module and the entry is marked as idle;

[0027] SendFrame Task: Responsible for encapsulating the data frame represented by the transaction layer into a data packet in the Ring. The data frame data is simulated by the software through the PCIe VIP backdoor access Backdoor MemWr_dw task and written to the host memory. At the same time, the Tail position of the Ring is updated to point to the next available free entry. Based on the sending mechanism, the platform automatically identifies the first bit of the frame data. When the first bit is 0, the platform will sequentially place the data frame into the send buffer without moving the Tail position of the Ring. When the first bit is 1, the platform will sequentially place the data frame into the buffer and move the Tail position of the Ring to notify the hardware to execute the send operation.

[0028] Preferably, the RX Ring module implements the following tasks:

[0029] Init Task: Executes the initialization of the Ring, so that the information of each entry in the Ring is written to the on-chip register of the design under test (DUT) through the PCIe MemWr_DW task;

[0030] Enable Task: Notifies the design under test (DUT) to enable the receiving operation of the receiving ring;

[0031] Recycle Task: A resident infinite loop task responsible for reading the head register update of the design under test (DUT). It sequentially checks whether the specific bit corresponding to each entry in the ring head after the update has been written back by the design under test (DUT) to indicate that reception is complete. If the specific bit has been updated, indicating that reception is complete, the receive data frame memory corresponding to this entry is read in its entirety through the PCIe VIP backdoor access Backdoor MemRd_dw task, encapsulated into a transaction layer data packet, and sent to the scoreboard. The entry is also marked as idle and the tail is moved backward to set the idle entry to the receivable state.

[0032] Preferably, the configuration parameters of the second configuration module include the following parameters:

[0033] Number of network ports, whether Reduce mode is enabled, whether auto-negotiation is enabled, the rate supported by the interface, whether full-duplex mode is supported, and interface connection status.

[0034] Preferably, the following two processes are included:

[0035] Data frame sending: calling PCIe VIP through the built-in interface of the PCIe UVC component to send data frames to the DUT and send frame records to the scoreboard of the scoreboard module at the same time; after the DUT is processed, it sends data frames to the GMAC interface of the GMAC UVC component. The corresponding GMAC UVC in the GMAC UVC component receives the data frames and sends data frame records to the scoreboard of the final scoreboard module through a set of checksums and the checker component; after receiving the frame records from both ends, the scoreboard of the scoreboard module performs a data consistency comparison;

[0036] Data frame reception: The GMAC of the GMAC UVC component is configured to send and receive data frames through the test sequence. The GMAC sends and receives data frames to the GMAC interface of the DUT and, at the same time, sends and receives data frame records to the scoreboard of the scoreboard module. After the DUT completes processing, it sends data frames to the PCIe VIP. After receiving the data frames, the PCIe VIP sends data frame records to the scoreboard of the scoreboard module through the internal components of the PCIe UVC component. After receiving the frame records from both ends, the scoreboard of the scoreboard module performs a data consistency comparison.

[0037] Preferably, the configuration parameters of the operating environment of the entire platform include the following parameters:

[0038] The timeout limit of the platform's automatic comparison, the path used for the DUT register configuration, the transmitter checksum detection level, the reporting period for data frame transmission and reception statistics, and the channels enabled by the configuration platform.

[0039] Compared with the prior art, the present invention has the following beneficial effects:

[0040] 1. The present invention provides a universal verification environment with multiple configuration parameters and flexible design, which can realize the rapid replacement of various PCIe bus network interface card DUT designs to be tested, and facilitate the rapid implementation of a network interface card DUT pre-silicon verification platform with high efficiency and low cost;

[0041] 2. This invention solves the problem of complex setup and poor reusability of the current network interface card verification environment, significantly improving the work efficiency of verification personnel and reducing the time required to build the verification environment;

[0042] 3. The present invention has its own multi-level verification and detection checker, which can realize real-time verification and inspection of data frames, avoiding the problems of low efficiency and poor accuracy of manual detection in traditional verification structures, and greatly improving verification efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Other features, objects and advantages of the present invention will become more apparent upon reading the detailed description of non-limiting embodiments with reference to the following drawings:

[0044] Figure 1 This is a schematic structural diagram of a system-level verification platform for a PCIe bus network interface card according to the present invention;

[0045] Figure 2 Schematic diagram of the structure of the TX Ring of the present invention;

[0046] Figure 3 This is a schematic structural diagram of the RX Ring of the present invention;

[0047] Figure 4 The figure is a schematic diagram of the transaction flow operation of the scoreboard of the scoreboard module of the present invention. DETAILED DESCRIPTION

[0048] The present invention will be described in detail below with reference to specific embodiments. The following examples will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those skilled in the art, several changes and improvements can be made without departing from the scope of the present invention. These all fall within the scope of protection of the present invention.

[0049] Example 1:

[0050] like Figures 1 to 4As shown, this embodiment provides a system-level verification platform for a PCIe (Peripheral Component Interconnect Express) bus network interface card, including: a PCIe UVC (Universal Verification Component) component, a GMAC (Gbps Media Access Control) UVC component, a scoreboard module, a checker component, a JTAG UVC component, and a design under test (DUT). The PCIe UVC component is connected to the design under test (DUT), and data frames are transmitted between the PCIe UVC component and the design under test (DUT). The PCIe UVC component is connected to the scoreboard module, and the PCIe UVC component sends frame records to the scoreboard module. The design under test (DUT) is connected to the GMAC UVC component, and data frames are transmitted between the design under test (DUT) and the GMAC UVC component. The GMAC UVC component is connected to the scoreboard module, and the GMAC UVC component sends frame records to the scoreboard module. The GMAC UVC component is connected to the checker component. Data frames are transmitted between the UVC component and the checker component. The checker component is connected to the scoreboard module. The checker component sends frame records to the scoreboard module. The external send test sequence sends data frames to the PCIe UVC component. The external receive test sequence sends data frames to the GMAC UVC component.

[0051] It includes the following two processes:

[0052] Data frame transmission: The PCIe VIP is called through the built-in interface of the PCIe UVC component to send data frames to the DUT and simultaneously send frame records to the scoreboard of the scoreboard module. After the DUT is processed, it sends data frames to the GMAC interface of the GMACUVC component. The corresponding GMAC UVC in the GMAC UVC component receives the data frames and sends the data frame records to the scoreboard of the final scoreboard module through a set of checksum checker components. After receiving the frame records from both ends, the scoreboard of the scoreboard module performs a data consistency comparison.

[0053] Data frame reception: The test sequence configures the GMAC UVC component's GMAC to send and receive data frames. The GMAC sends and receives data frames to the GMAC interface of the DUT and, at the same time, sends received data frame records to the scoreboard of the scoreboard module. After the DUT completes processing, it sends data frames to the PCIe VIP. After the PCIe VIP receives the data frames, it sends data frame records to the scoreboard of the scoreboard module through the internal components of the PCIe UVC component. After the scoreboard of the scoreboard module receives the frame records from both ends, it performs a data consistency comparison.

[0054] The configuration parameters of the operating environment of the entire platform include the following parameters: the timeout limit of the platform's automatic comparison, the use path of the DUT register configuration, the sender checksum detection level, the reporting period of data frame transmission and reception statistics, and the channels enabled by the configuration platform.

[0055] The PCIe UVC component includes a first Driver component, a first Monitor component, a first Sequencer component and a first configuration module. The first Driver component completes the mapping of PCIe transactions to the underlying read and write of PCIe VIP (PCIe Verification Intellectual Property Core). The first Monitor component monitors the data communication of the PCIe interface and sends the detected data to the scoreboard of the scoreboard module for data comparison through TLM (Transaction Level Modeling) communication. The first Sequencer component connects the first Driver component and the external sequence. The first configuration module is used to configure the configuration information of the PCIe UVC component.

[0056] The configuration parameters of the first configuration module include the following parameters: the number of PCIe channels, the memory base address of the lane, the interrupt memory base address of the channel lane, the basic information of the transceiver ring, and the timeout period for sending confirmation recovery.

[0057] The first Driver component has a built-in TX Ring module and a RX Ring (receive descriptor ring) module to implement the transmit and receive rings. The TX Ring module performs the following tasks:

[0058] Init Task: Initializes the Ring and writes the information of each entry in the Ring to the on-chip register of the design under test (DUT) through the PCIe memory write task MemWr_DW task.

[0059] Enable Task (Send Enable Task): Notify the design under test (DUT) to enable the sending operation of the sending ring;

[0060] Recycle Task (polling task): A resident infinite loop task responsible for reading the head register update of the design under test (DUT) and sequentially checking whether the specific bit corresponding to each entry in the ring head after the update has been written back by the design under test (DUT) to indicate that the transmission is complete; if the specific bit is updated, indicating that the transmission is complete, the corresponding transaction layer data packet is sent to the scoreboard module and the entry is marked as idle;

[0061] SendFrame Task (Frame Send Task): Responsible for encapsulating the data frame represented by the transaction layer into a data packet in the Ring ring. The data of the data frame is simulated by the software through the PCIe VIP backdoor access Backdoor MemWr_dw task (backdoor four-byte memory write task) and written to the host memory. At the same time, the Tail (descriptor tail pointer) position of the Ring ring is updated to point to the next available free entry. Based on the sending mechanism, the platform automatically identifies the first bit of the frame data. When the first bit is 0, the platform will place the data frame in the send buffer in sequence without moving the Tail position of the Ring ring. When the first bit is 1, the platform will place the data frame in the buffer in sequence and move the Tail position of the Ring ring to notify the hardware to perform the send operation.

[0062] The RX Ring module implements the following tasks:

[0063] Init Task: Executes the initialization of the Ring, so that the information of each entry in the Ring is written to the on-chip register of the design under test (DUT) through the PCIe MemWr_DW task;

[0064] Enable Task: Notifies the design under test (DUT) to enable the receiving operation of the receiving ring;

[0065] Recycle Task: A resident infinite loop task responsible for reading the head register update of the design under test (DUT). It sequentially checks whether the specific bit corresponding to each entry in the ring head after the update has been written back by the design under test (DUT) to indicate that reception is complete. If the specific bit has been updated, indicating that reception is complete, the received data frame memory corresponding to this entry is read in full through the PCIe VIP backdoor access Backdoor MemRd_dw task (backdoor four-byte memory read task), encapsulated into a transaction layer data packet and sent to the scoreboard. At the same time, the entry is marked as idle and the tail is moved backward to set the idle entry to the receivable state.

[0066] The GMAC UVC component includes a second Driver component, a second Monitor component, a second Sequencer component, and a second configuration module. The second Driver component converts GMII (Gigabit Media Independent Interface) transactions into GMII interface signals. The second Monitor component detects changes in interface signals on both the transmit and receive sides of the network interface, automatically identifies the transmission of data frames, and reports the identified data frames to the scoreboard module. The second Sequencer component connects the second Driver component to the external sequence. The configuration parameters of the second configuration module include the following parameters: the number of network ports, whether Reduce mode (referring to RMII and RGMII interface modes) is enabled, whether auto-negotiation is enabled, the interface's supported rates, whether full-duplex mode is supported, and the interface connection status.

[0067] Example 2:

[0068] Those skilled in the art may understand this embodiment as a more specific description of Embodiment 1.

[0069] like Figures 1 to 4 As shown, this embodiment discloses a system-level verification platform for PCIe bus network interface cards based on the universal verification methodology UVM. Through flexible design, the platform can realize the rapid replacement of different types of PCIe bus network interface card designs under test (DUTs), facilitating the rapid implementation of a pre-silicon verification platform for network interface card DUTs with high efficiency and low cost.

[0070] The verification platform is built on UVM and PCIe VIP. The platform design implements the ability to receive and send Ethernet data frames through the PCIe verification component UVC. Simultaneously, the GMAC verification component UVC can receive and send Ethernet frames on the network. Furthermore, the platform includes a built-in multi-level checksum checker, enabling real-time verification of data frames. Configuration flexibility depends on factors such as the type and number of network interfaces and the interface type of the PCIe bus. This article systematically introduces the overall concept of the verification method and specifically describes the system architecture of the verification platform.

[0071] This embodiment provides a system-level verification platform for a PCIe bus network interface card based on the universal verification methodology UVM, specifically including:

[0072] PCIe UVC, a universal verification component (UVC) that encapsulates the PCIe VIP, simulates the PCIe host's Root Complex (RC) mode, enabling PCIe data communication with the design under test (DUT). The PCIe UVC component is implemented based on UVM and includes a driver, monitor, sequencer, and configuration components. The driver maps PCIe transactions to the underlying read and write functionality of the PCIe VIP. Furthermore, the built-in transmit and receive rings (TX and RX rings) simulate the transmit and receive rings (which store the corresponding data frame receive and transmit descriptors).

[0073] The characteristics of the Ring are as follows: The structure of the TX Ring is as follows: Figure 2As shown in the figure, it mainly includes the following tasks: (1) InitTask: performs the initialization of the Ring, including writing the information of each entry in the Ring into the on-chip register of the DUT through the PCIe memory write task MemWr_DW; (2) Enable Task: notifies the DUT to enable the sending operation of the Ring; (3) Recycle: a resident infinite loop task, responsible for reading the update of the Head register of the DUT, and then sequentially checking whether the specific bit corresponding to each entry in the Ring Head after the update is written back by the DUT to indicate that the sending is completed; if the specific bit is updated, it means that the sending is completed. At this time, the corresponding transaction layer data packet is sent to the scoreboard and the entry is marked as idle; (4) SendFrame: responsible for encapsulating the data frame represented by the transaction layer into a data packet in the Ring, where the data of the data frame is simulated by the software through the backdoor access of the PCIe VIP Backdoor MemWr_dw task to write to the host memory. At the same time, the Tail position of the Ring is updated to point to the next available idle entry. Based on the particularity of the sending mechanism, the platform automatically identifies the first bit of the frame data. When the first bit is 0, the platform will place the data frame in the sending buffer in sequence and will not move the Tail position of the Ring. When the first bit is 1, the platform will place the data frame in the buffer in sequence and then move the Tail position of the Ring to notify the hardware to perform the sending operation.

[0074] The structure of RX Ring is as follows Figure 3As shown in the figure, it mainly includes the following tasks: (1) Init Task: executes the initialization of the Ring, including writing the information of each entry in the Ring into the on-chip register of the design under test (DUT) through the MemWr_DW task of PCIe; (2) Enable Task: notifies the design under test (DUT) to enable the receiving operation of the receiving Ring; (3) Recycle: a resident infinite loop task, responsible for reading the update of the Head register of the design under test (DUT), and then successively detecting whether the specific bit corresponding to each entry after the head of the Ring is updated has been written back by the design under test (DUT) to indicate that the reception is completed; if the specific bit is updated, it means that the reception is completed. At this time, the receive data frame memory corresponding to this entry is read through the backdoor access Backdoor MemRd_dw task of PCIe VIP, and then encapsulated into a transaction layer data packet and sent to the scoreboard; at the same time, the entry is marked as idle; then, the tail is moved backward to set as many idle entries as possible to the receivable state. The Monitor component monitors data communication on the PCIe interface and sends the detected data to the scoreboard via TLM communication for comparison. The Sequencer connects the Driver to the external sequencer. The Configuration module primarily contains PCIe UVC configuration information, including the number of PCIe lanes (x1 / x2 / x4 / x8 / x16), the lane memory base address, the lane interrupt memory base address, basic information about sending and receiving Rings, and the timeout for sending, confirming, and recovering data.

[0075] GMAC UVC, this component can realize the simulation of end-to-end network devices of network interface, thereby realizing Ethernet communication with the design under test (DUT). GMAC UVC component is implemented based on UVM and includes Driver, Monitor, Sequencer and configuration components. Driver is responsible for converting GMII transactions into GMII interface signals and supports four modes: GMII / MII / RGMII / RMII. For example, GMII transmit data includes the following: (1) Preamble[7]: 0x55, 0x55, 0x55, 0x55, 0x55, 0x55; (2) SDF (frame start delimiter: 0xD5); (3) Frame data: For RMII and RGMII in Reduce mode, it is necessary to send an 8-bit link information code before sending the formal frame data: {4'b0000, linkup[0], speed[1:0], duplex[0]}. The Monitor is responsible for detecting changes in interface signals on both the transmit and receive sides of the network interface, automatically identifying the transmission of data frames, and reporting the identified data frames to the scoreboard. The Sequencer is responsible for connecting the Driver and the external sequence to initiate different test sequences to complete the verification of specific functions. The configuration module mainly includes GMAC UVC configuration information, including the number of network ports, whether Reduce mode is enabled, whether auto-negotiation is enabled, the interface supported rate (10Mbps / 100Mbps / 1000Mbps), whether full-duplex mode is supported, and the interface connection status.

[0076] The data comparison module scoreboard and various detection checkers, the platform scoreboard scoreboard provides a series of interface functions to facilitate users to access the things in the scoreboard, so as to realize the need of on-demand transaction processing. Usually in the main_phase of the test case, after completing the transaction, the transaction flow operation is performed to check whether the transaction flow in and out is normal. Standard transaction flow operation Figure 4 The detection checker is mainly used to classify data frames to facilitate further comparison on the scoreboard.

[0077] JTAG UVC, a universal verification component, is responsible for communicating with the JTAG interface of the DUT and configuring all internal registers within the DUT. Typically, register configuration within the DUT is performed via the PCIe interface provided by the PCIe VIP within the PCIe UVC. Using a low-speed interface like JTAG can complement register configuration on the high-speed PCIe interface.

[0078] The DUT uses a PCIe bus gigabit network interface card as the DUT. The DUT interface module PCIe interface and the interface module GMAC interface are used for data communication between the verification platform and the DUT.

[0079] The verification platform is mainly composed of PCIe UVC, GMAC UVC, data comparison module scoreboard and various detection checkers, JTAG UVC and DUT. The overall structure of the verification platform is as follows: Figure 1 As shown in the figure, the data frame sending and receiving process is as follows: (1) Data frame sending: The built-in interface of PCIe UVC calls PCIe VIP to send data frames to the design under test DUT, and at the same time sends frame records to the scoreboard; after the design under test DUT completes processing, it sends data frames to the GMAC interface. The corresponding GMAC UVC will complete the reception of the data frames and send data frame records to the final scoreboard through a set of checksum checkers. After the scoreboard receives the frame records at both ends, it will perform a data consistency comparison to ensure that the data in the sending path is correct. (2) Data frame reception: The data frame is configured to send and receive data frames through the test sequence. GMAC sends and receives data frames to the GMAC interface of the design under test DUT, and at the same time, sends the received data frame records to the scoreboard. After the design under test DUT completes processing, it sends data frames to PCIe VIP. After PCIe VIP receives the data frames, it sends data frame records to the scoreboard through the internal components of PCIeUVC. After the scoreboard receives the frame records at both ends, it will perform a data consistency comparison. Ensure the data in the transmission path is correct. The full platform operating environment also includes some configurable parameters, including: the timeout limit for the platform's automatic comparison, the path used for the DUT register configuration (PCIe / JTAG), the transmitter checksum detection level, the reporting period for data frame transmission and reception statistics, and the channels enabled by the configuration platform.

[0080] The present invention provides a universal verification environment with multiple configuration parameters and flexible design, which can realize the rapid replacement of various PCIe bus network interface card DUT designs under test, and facilitate the rapid implementation of a network interface card DUT pre-silicon verification platform with high efficiency and low cost.

[0081] The above describes specific embodiments of the present invention. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art may make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. The embodiments of this application and the features in the embodiments may be combined with each other in any manner unless there is a conflict.

Claims

1. A system-level verification platform for a PCIe bus network interface card, characterized in that: include: PCIe UVC components, GMAC UVC components, scoreboard modules, checker components, JTAG UVC components, and the design under test (DUT); The PCIe UVC component is connected to the DUT to be tested, and data frames are transmitted between the PCIe UVC component and the DUT to be tested; The PCIe UVC component is connected to the scoreboard module, and the PCIe UVC component sends a frame record to the scoreboard module; The DUT to be tested is connected to the GMAC UVC component, and data frames are transmitted between the DUT to be tested and the GMAC UVC component; the GMAC UVC component is connected to the scoreboard module, and the GMAC UVC component sends frame records to the scoreboard module; The GMAC UVC component is connected to the checker component, and data frames are transmitted between the GMAC UVC component and the checker component; the checker component is connected to the scoreboard module, and the checker component sends frame records to the scoreboard module; An external sending test sequence sends a data frame to the PCIe UVC component, and an external receiving test sequence sends a data frame to the GMAC UVC component; The PCIe UVC component includes a first Driver component, a first Monitor component, a first Sequencer component and a first configuration module; The first Driver component completes the mapping of PCIe transactions to PCIe VIP underlying read and write; The first Monitor component monitors data communication of the PCIe interface and sends the detected data to the scoreboard of the scoreboard module through TLM communication for data comparison; The first Sequencer component connects the first Driver component and an external sequence; The first configuration module is used to configure configuration information of the PCIe UVC component; The first Driver component has a built-in transmitting TX Ring module and receiving RX Ring module to implement the transmitting and receiving Ring rings; The TX Ring module performs the following tasks: Init Task: Executes the initialization of the Ring, so that the information of each entry in the Ring is written to the on-chip register of the design under test (DUT) through the PCIe memory write task MemWr_DW task; Enable Task: Notifies the design under test (DUT) to enable the sending operation of the sending ring; Recycle Task: A resident infinite loop task responsible for reading the head register update of the design under test (DUT) and sequentially checking whether the specific bit corresponding to each entry in the ring head update has been written back by the design under test (DUT) to indicate that the transmission is complete. If a specific bit is updated, indicating that the transmission is completed, the corresponding transaction layer data packet is sent to the scoreboard module; at the same time, the entry is marked as idle; The SendFrame Task is responsible for encapsulating the data frame represented by the transaction layer into a data packet in the ring. The data frame data is simulated by the software through the PCIe VIP backdoor access Backdoor MemWr_dw task to write to the host memory. At the same time, the ring tail position is updated to point to the next available free entry. Based on the sending mechanism, the platform automatically identifies the first bit of the frame data. If the first bit is 0, the platform will sequentially place the data frame into the send buffer without moving the ring tail position. When the first bit is 1, the platform places the data frames into the cache in sequence, moves the Tail position of the Ring, and notifies the hardware to perform the sending operation.

2. The system-level verification platform for a PCIe bus network interface card according to claim 1, wherein: The GMAC UVC component includes a second Driver component, a second Monitor component, a second Sequencer component and a second configuration module; The second Driver component converts the GMII transaction into a GMII interface signal; The second Monitor component simultaneously detects changes in interface signals on both the transmitting and receiving sides of the network interface, automatically identifies the transmission of data frames, and reports the identified data frames to the scoreboard of the scoreboard module; The second Sequencer component connects the second Driver component and an external sequence.

3. The system-level verification platform for a PCIe bus network interface card according to claim 1, wherein: The configuration parameters of the first configuration module include the following parameters: The number of PCIe channels, the memory base address of the lane, the interrupt memory base address of the channel lane, the basic information of sending and receiving Ring, and the timeout period for sending confirmation and recovery.

4. The system-level verification platform for a PCIe bus network interface card according to claim 1, wherein: The RXRing module implements the following tasks: Init Task: Executes the initialization of the Ring, so that the information of each entry in the Ring is written to the on-chip register of the design under test (DUT) through the PCIe MemWr_DWtask; Enable Task: Notifies the design under test (DUT) to enable the receiving operation of the receiving ring; Recycle Task: A resident infinite loop task responsible for reading the head register update of the design under test (DUT). It sequentially checks whether the specific bit corresponding to each entry in the ring head after the update has been written back by the design under test (DUT) to indicate that reception is complete. If the specific bit has been updated, indicating that reception is complete, the receive data frame memory corresponding to this entry is read in its entirety through the PCIeVIP backdoor access Backdoor MemRd_dw task, encapsulated into a transaction layer data packet, and sent to the scoreboard. At the same time, the entry is marked as idle and the tail is moved backward to set the idle entry to the receivable state.

5. The system-level verification platform for a PCIe bus network interface card according to claim 2, wherein: The configuration parameters of the second configuration module include the following parameters: Number of network ports, whether Reduce mode is enabled, whether auto-negotiation is enabled, the rate supported by the interface, whether full-duplex mode is supported, and interface connection status.

6. The system-level verification platform for a PCIe bus network interface card according to claim 1, wherein: It includes the following two processes: Data frame sending: calling PCIe VIP through the built-in interface of the PCIe UVC component to send data frames to the DUT and send frame records to the scoreboard of the scoreboard module at the same time; after the DUT is processed, it sends data frames to the GMAC interface of the GMAC UVC component. The corresponding GMAC UVC in the GMAC UVC component receives the data frames and sends data frame records to the scoreboard of the final scoreboard module through a set of checksums and the checker component; after receiving the frame records from both ends, the scoreboard of the scoreboard module performs a data consistency comparison; Data frame reception: The data frame is configured by the test sequence to send and receive the GMAC of the GMAC UVC component. The GMAC sends and receives the data frame to the GMAC interface of the DUT and, at the same time, sends a record of the received data frame to the scoreboard of the scoreboard module. After the DUT completes processing, it sends a data frame to the PCIe VIP. After receiving the data frame, the PCIe VIP sends a data frame record to the scoreboard of the scoreboard module through the internal component of the PCIe UVC component. After receiving the frame records from both ends, the scoreboard of the scoreboard module performs a data consistency comparison.

7. The system-level verification platform for a PCIe bus network interface card according to claim 1, wherein: The configuration parameters of the operating environment for the entire platform include the following parameters: The timeout limit of the platform's automatic comparison, the path used for the DUT register configuration, the transmitter checksum detection level, the reporting period for data frame transmission and reception statistics, and the channels enabled by the configuration platform.

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