Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The present disclosure provides a semiconductor structure and a preparation method thereof. The preparation method comprises: providing a substrate; forming a patterned barrier structure and a contact material layer on the substrate, the barrier structure comprising an electrical connection layer and a protection layer arranged in a stack, an opening of the barrier structure defining a position of a bit line contact hole, the contact material layer being formed in the bit line contact hole, a top surface of the contact material layer being higher than a top surface of the electrical connection layer; obtaining an initial distance between the top surface of the contact material layer and the top surface of the electrical connection layer; if the initial distance is greater than a preset distance, causing the contact material layer located at a surface layer to react to form a sacrifice layer, the contact material layer located below the sacrifice layer serving as a contact layer, so that a distance between the top surface of the contact layer and the top surface of the electrical connection layer is not greater than the preset distance; and removing the sacrifice layer. In this way, the problem that the bit line material above the bit line contact is etched earlier in the prior art can be effectively avoided, and the problem of the bit line above the bit line contact being too thin can be improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and in particular, to a preparation method of a semiconductor structure and the semiconductor structure. BACKGROUND

[0002] Dynamic random access memory (DRAM) is a commonly used semiconductor device for storing data. The dynamic random access memory generally includes a plurality of memory cells, each of which includes a transistor and a capacitor, wherein the source and drain of the transistor are electrically connected to a bit line and the capacitor, respectively. A word line is used to control the opening and closing of the transistor, and data information stored in the capacitor is read through the bit line, or data information is written into the capacitor.

[0003] The main structure of the transistor includes an active region separated by a shallow trench isolation structure, and the bit line is electrically connected to the active region through a bit line contact. The bit line contact directly contacts the active region, and the bit line generally includes a plurality of layers of conductive materials, and the conductive material at the uppermost layer is generally metal. In the actual preparation process, the material of the bit line contact, the material of the bit line, and the insulating material on the surface of the bit line are generally deposited on the entire substrate in sequence, and then etched to form the final bit line. However, the top layer of the bit line above the bit line contact will be over-etched, and the final result is that the metal conductive material (such as tungsten) of the bit line above the bit line contact will be thin. This will affect the physical and conductive properties of the bit line, and thus affect the response speed of the semiconductor device. SUMMARY

[0004] Therefore, in order to improve or avoid the thinning of the metal conductive material (such as tungsten) of the bit line, it is necessary to provide a preparation method of a semiconductor structure.

[0005] According to some embodiments of the present disclosure, a preparation method of a semiconductor structure is provided, which includes the following steps:

[0006] providing a substrate;

[0007] forming a patterned barrier structure and a contact material layer on the substrate, the barrier structure including an electrically connected layer and a protective layer arranged in layers, the electrically connected layer being located between the substrate and the protective layer, an opening of the barrier structure defining the position of a bit line contact hole, the contact material layer being formed in the bit line contact hole, and a top surface of the contact material layer being higher than a top surface of the electrically connected layer;

[0008] acquiring an initial distance between a top surface of the contact material layer and a top surface of the electrical connection layer, if the initial distance is greater than a preset distance, causing the contact material layer located at a surface layer to react to form a sacrificial layer, the contact material layer located below the sacrificial layer as a contact layer, so that a distance between a top surface of the contact layer and a top surface of the electrical connection layer is not greater than the preset distance; and

[0009] removing the sacrificial layer.

[0010] In some embodiments of the present disclosure, in the step of causing the contact material layer located at a surface layer to react to form a sacrificial layer, the top surface of the contact layer is leveled with the top surface of the electrical connection layer by controlling the amount of reaction.

[0011] In some embodiments of the present disclosure, the material of the contact material layer includes silicon, and the step of causing the contact material layer located at a surface layer to react to form a sacrificial layer includes: performing an oxidation treatment on the contact material layer to form silicon oxide as the sacrificial layer.

[0012] In some embodiments of the present disclosure, an oxidizing gas is used to perform the oxidation treatment on the contact material layer.

[0013] In some embodiments of the present disclosure, the reaction temperature is 80-100°C when the oxidation treatment is performed.

[0014] In some embodiments of the present disclosure, the gas flow of the oxidizing gas is 100-200 sccm when the oxidation treatment is performed.

[0015] In some embodiments of the present disclosure, the oxidizing gas includes one or more of oxygen, nitrogen dioxide, carbon oxysulfide, and sulfur dioxide.

[0016] In some embodiments of the present disclosure, the material of the protective layer is the same as the material of the sacrificial layer, and the protective layer is removed simultaneously in the step of removing the sacrificial layer.

[0017] In some embodiments of the present disclosure, the substrate includes a shallow trench isolation structure therein, the shallow trench isolation structure isolates a plurality of active regions arranged at intervals in the substrate, and after the sacrificial layer is removed, the method further includes:

[0018] forming a bit line and a bit line contact, the bit line contact being etched via the contact layer, the bit line being located on the bit line contact, and the bit line being electrically connected to the active region via the bit line contact.

[0019] In some embodiments of the present disclosure, the step of forming the bit line includes:

[0020] forming a first conductive material layer covering the contact layer and the electric connection layer;

[0021] forming a second conductive material layer on the first conductive material layer;

[0022] forming an insulating medium material layer on the second conductive material layer;

[0023] etching the insulating medium material layer, the second conductive material layer and the first conductive material layer to form a bit line insulating layer, a second bit line conductive layer and a first bit line conductive layer respectively, the bit line comprising the bit line insulating layer, the second bit line conductive layer and the first bit line conductive layer.

[0024] In some embodiments of the present disclosure, the material of the second bit line conductive layer comprises tungsten.

[0025] In some embodiments of the present disclosure, the material of the electric connection layer is the same as the material of the contact material layer.

[0026] In some embodiments of the present disclosure, the step of forming a patterned barrier structure on the substrate comprises:

[0027] forming the electric connection layer on the substrate;

[0028] forming the protective layer on the electric connection layer;

[0029] forming a patterned mask structure on the protective layer, the mask structure exposing a portion of the protective layer to be etched;

[0030] etching the protective layer and the electric connection layer based on the mask structure to form the barrier structure.

[0031] In some embodiments of the present disclosure, the barrier structure further comprises an isolation layer disposed between the substrate and the electric connection layer.

[0032] In another aspect of the present disclosure, a semiconductor structure is provided, which is prepared by the method of preparing a semiconductor structure according to any one of the above embodiments.

[0033] The inventors of this disclosure have discovered that during the fabrication of bit lines, a conductive material needs to be deposited integrally on a substrate first, then bit line contact holes are etched within it, and finally, bit line contact material is filled into the bit line contact holes. Since the bit line contact material is formed after the conductive material is deposited, the top surface of the bit line contact material is usually higher than the top surface of the surrounding conductive material. This results in the bit line material (such as tungsten) above the bit line contact being etched earlier during subsequent bit line fabrication, ultimately leading to a thinner metallic conductive material (such as tungsten) above the bit line contact.

[0034] In the semiconductor structure fabrication method provided in this disclosure, after forming a contact material layer in the bit line contact hole, if the initial distance is greater than a preset distance, the contact material layer on the surface is reacted to form a sacrificial layer, which is then removed. By partially reacting the contact material layer, the distance between the top surface of the contact layer and the top surface of the electrical connection layer is reduced until it is no greater than the preset distance or the top surface of the contact layer is flush with the top surface of the electrical connection layer, resulting in a smoother surface for both. This makes the subsequent etching process for fabricating bit lines above the contact layer and electrical connection layer more synchronized. Therefore, this method effectively avoids the problem of earlier etching of the bit line material above the bit line contact in conventional technologies, thereby solving the problem of the thinner metallic conductive material (such as tungsten) of the bit lines above the bit line contact.

[0035] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, the preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0036] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a schematic diagram of the steps in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

[0038] Figure 2 for Figure 1 A top view of the substrate used in step S1;

[0039] Figure 3 for Figure 2 A schematic cross-sectional view of the substrate in the AA' region;

[0040] Figure 4 In order to be inFigure 3 Structure diagram for forming a barrier structure on the basis of the structure shown in Fig. 4;

[0041] Figure 5A To form a mask structure on the basis of the structure shown in Fig. 4; Figure 4 Structure diagram for forming a mask structure on the basis of the structure shown in Fig. 4;

[0042] Figure 5B To form a mask structure on the basis of the structure shown in Fig. 4; Figure 5A Structure diagram for etching on the basis of the structure shown in Fig. 4;

[0043] Figure 5C To form a mask structure on the basis of the structure shown in Fig. 4; Figure 5B Structure diagram for etching on the basis of the structure shown in Fig. 4;

[0044] Figure 5D To form a mask structure on the basis of the structure shown in Fig. 4; Figure 5C Structure diagram for forming a bit line contact hole on the basis of the structure shown in Fig. 4;

[0045] Figure 6 Structure diagram for filling a contact material layer on the basis of the structure shown in Fig. 5;

[0046] Figure 7 To form a mask structure on the basis of the structure shown in Fig. 4; Figure 6 Structure diagram for forming a sacrificial layer on the basis of the structure shown in Fig. 4;

[0047] Figure 8 To form a mask structure on the basis of the structure shown in Fig. 4; Figure 7 Structure diagram for removing a protective layer and a sacrificial layer on the basis of the structure shown in Fig. 4;

[0048] Figure 9 To form a mask structure on the basis of the structure shown in Fig. 4; Figure 8 Structure diagram for forming a bit line material layer and an insulating layer on the basis of the structure shown in Fig. 4;

[0049] Figure 10 To form a mask structure on the basis of the structure shown in Fig. 4; Figure 9 Structure diagram for etching an insulating layer, a bit line material layer and a contact material layer on the basis of the structure shown in Fig. 4;

[0050] Figure 11 The structure shown in Fig. 4 corresponds to a top view. Figure 10

[0051] In the drawings, the reference signs and their meanings are as follows:

[0052] ​110, active region; 120, shallow trench isolation structure; 210, barrier structure; 211, electrically connecting layer; 212, protective layer; 213, isolation layer; 221, first mask material layer; 222, first etching stop layer; 223, second mask material layer; 224, second etching stop layer; 225, mask pattern transfer layer; 226, third mask material layer; 230, mask shielding layer; 310, contact material layer; 311, contact layer; 312, bit line contact; 320, sacrificial layer; 410, first conductive material layer; 411, first bit line conductive layer; 420, second conductive material layer; 421, second bit line conductive layer; 430, insulating dielectric material layer; 431, bit line insulating layer. DETAILED DESCRIPTION

[0053] For the purpose of promoting an understanding of the disclosure, the present disclosure will now be described more fully with reference to the associated drawings. The preferred embodiments of the disclosure are shown in the drawings. However, the disclosure can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the disclosure to those skilled in the art.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0055] It will be understood that when an element or layer is referred to as being "on" or "adjacent" or "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected" or "directly coupled" to another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

[0056] Spatial terms, such as "below," "under," "lower," "below and / or "on" can be used herein for ease of description to describe the relationships of one element or feature to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatial terms are intended to encompass different orientations of the device in use or operation, in addition to the orientations depicted in the figures. For example, if a device is turned over, then a portion described as "below" or "under" another portion would then be oriented "above" the other portion. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptions used herein interpreted accordingly.

[0057] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0058] One embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, comprising the steps of:

[0059] providing a substrate;

[0060] forming a patterned barrier structure and a contact material layer on the substrate, the barrier structure comprising an electrically connecting layer and a protective layer stacked, the electrically connecting layer being between the substrate and the protective layer, an opening of the barrier structure defining a position of a bit line contact hole, the contact material layer being formed in the bit line contact hole, a top surface of the contact material layer being higher than a top surface of the electrically connecting layer;

[0061] obtaining an initial distance between the top surface of the contact material layer and the top surface of the electrically connecting layer, if the initial distance is greater than a preset distance, causing the contact material layer at a surface layer to react to form a sacrificial layer, the contact material layer below the sacrificial layer serving as a contact layer, so that a distance between a top surface of the contact layer and the top surface of the electrically connecting layer is not greater than the preset distance; and removing the sacrificial layer.

[0062] In the method for manufacturing the semiconductor structure provided in the present disclosure, after forming the contact material layer in the bit line contact hole, if the initial distance is greater than the preset distance, the contact material layer located at the surface layer is allowed to react to form a sacrificial layer, and then the sacrificial layer is removed. In this way, the spacing between the top surface of the contact layer and the top surface of the electrical connection layer is reduced until it is not greater than the preset distance or the top surface of the contact layer is flush with the top surface of the electrical connection layer, so that the top surface of the contact layer and the top surface of the electrical connection layer are more flat. This makes the etching process of the bit line subsequently manufactured above the contact layer and the electrical connection layer more synchronized. Thus, by this way, the problem that the bit line material above the bit line contact is etched earlier in the traditional technology can be effectively avoided, and thus the problem that the metal conductive material (such as tungsten) of the bit line above the bit line contact is too thin can be solved.

[0063] Figure 1 A schematic diagram of steps of one embodiment of the method for manufacturing the semiconductor structure of the present disclosure is shown. Referring to Figure 1 The method for manufacturing the semiconductor structure includes steps S1-S6.

[0064] In step S1, a substrate including a shallow trench isolation structure 120 and an active region 110 is provided.

[0065] Figure 2 A top view of a substrate is shown. Referring to Figure 2 The substrate has a shallow trench isolation structure 120 therein, and the shallow trench isolation structure 120 isolates a plurality of spaced active regions 110 in the substrate. Figure 3 A cross-sectional view of the substrate in Figure 2 at AA' is shown.

[0066] In some examples of this embodiment, the material of the active region 110 can include silicon, germanium or silicon germanium. For example, the material of the substrate can include silicon. It can be understood that the active region 110 can be silicon after a specific doping treatment. The shallow trench isolation structure 120 is used to insulate the spaced active regions 110, and the shallow trench isolation structure 120 can include an insulating material. Optionally, the shallow trench isolation structure 120 can include silicon oxide, silicon nitride or silicon oxynitride. In this example, the shallow trench isolation structure 120 includes silicon oxide.

[0067] In some examples of this embodiment, the shallow trench isolation structure 120 can be formed by etching the substrate having the active region 110, and filling an insulating material in the substrate.

[0068] Referring to Figure 3As shown, in some examples of this embodiment, the substrate further comprises a dielectric layer disposed above the active region 110 and the shallow trench isolation structure 120. The dielectric layer is used to insulate the active region 110 from a subsequently prepared bit line. Optionally, the material of the dielectric layer comprises an insulating material. Further, the material of the dielectric layer can be the same as the material of the shallow trench isolation structure 120, for example, the material of the dielectric layer comprises silicon oxide.

[0069] At step S2, a patterned barrier structure 210 is formed on the substrate.

[0070] The barrier structure 210 comprises an electrically connecting layer 211 and a protective layer 212 disposed in a stack, and the electrically connecting layer 211 is located between the substrate and the protective layer 212. The patterned barrier structure 210 has a bit line contact hole therebetween, which exposes part of the active region 110, and the bit line contact hole is used to fill a material of a bit line contact in a subsequent preparation process.

[0071] In some examples of this embodiment, the barrier structure 210 further comprises an isolation layer 213 disposed between the substrate and the electrically connecting layer 211. Optionally, the material of the barrier structure 210 comprises silicon nitride.

[0072] The material of the electrically connecting layer 211 is a conductive material. Optionally, the material of the electrically connecting layer 211 can comprise metal or silicon. In this example, the material of the electrically connecting layer 211 comprises polysilicon.

[0073] The protective layer 212 is used to protect the electrically connecting layer 211 located thereunder during etching. In some examples of this embodiment, the material of the protective layer 212 can comprise silicon oxide.

[0074] Referring to Figure 4 As shown, in some examples of this embodiment, the step of forming the patterned barrier structure 210 on the substrate comprises forming the barrier structure 210 and patterning the barrier structure 210. The step of forming the barrier structure 210 comprises forming the electrically connecting layer 211 on the substrate, and forming the protective layer 212 on the electrically connecting layer 211. The materials of the electrically connecting layer 211 and the protective layer 212 can be sequentially deposited on the substrate by, for example, physical vapor deposition or chemical vapor deposition. At this time, the electrically connecting layer 211 and the protective layer 212 prepared as a whole cover the substrate, and therefore a bit line contact hole needs to be prepared therein to expose part of the active region 110. Optionally, the step of forming the isolation layer 213 on the substrate is further included before forming the electrically connecting layer 211. The isolation layer 213 can also cover the substrate as a whole.

[0075] In some examples of this embodiment, referring to Figures 5A-5DBefore the step of patterning the barrier structure 210, there is a step of forming a patterned mask structure on the protection layer 212, the mask structure exposes the portion of the protection layer 212 to be etched.

[0076] Referring to Figure 5A The mask structure is formed on the barrier structure. The mask structure can include a first mask material layer 221, a first etch stop layer 222, a second mask material layer 223, a second etch stop layer 224, a mask pattern transfer layer 225, and a third mask material layer 226, which are sequentially stacked from bottom to top.

[0077] After the mask structure is formed, there is a step of etching the mask structure. Since the etching is performed from top to bottom, specifically, the third mask material layer 226, the mask pattern transfer layer 225, the second etch stop layer 224, the second mask material layer 223, the first etch stop layer 222, and the first mask material layer 221 are etched in sequence. The material of the first mask material layer 221, the second mask material layer 223, and the third mask material layer 226 can include a spin-on hard mask material. The material of the mask pattern transfer layer 225 can include an oxide layer, such as silicon oxide. The second etch stop layer 224 is used to block the etchant after etching through the mask pattern transfer layer, to protect the second mask material layer 223 below. The first etch stop layer 222 is used to block the etchant after etching through the second mask material layer 223, to protect the first mask material layer 221 below. Optionally, the first etch stop layer 222 and the second etch stop layer 224 can include a nitride layer, such as silicon nitride.

[0078] Referring to Figure 5BAs shown, the step of etching the mask structure includes etching the third mask material layer 226 and the mask pattern transfer layer 225 to form a pattern corresponding to the bit line contact hole in the mask pattern transfer layer 225. In order to ensure the precision of etching, the pattern corresponding to the bit line contact hole in the mask pattern transfer layer 225 can be formed in two times. For example, when etching the mask structure, a first pattern layer (not shown in the figure) can be first formed on the surface of the third mask material layer 226, and the material of the first pattern layer can be photoresist. Under the shielding of the first pattern layer, the third mask material layer 226 and the mask pattern transfer layer 225 are etched in sequence to form a first pattern on the mask pattern transfer layer 225. Then, after removing the first pattern layer and the third mask material layer 226, a fourth mask material layer (not shown in the figure) and a second pattern layer (not shown in the figure) are formed on the mask pattern transfer layer 225 with the first pattern. Under the shielding of the second pattern layer, the fourth mask material layer and the mask pattern transfer layer 225 are etched in sequence to form a second pattern on the mask pattern transfer layer 225. The material of the fourth mask material layer can be the same as that of the third mask material layer, and the second pattern layer can also be photoresist. Thus, the mask pattern transfer layer 225 has both the first pattern and the second pattern corresponding to the bit line contact hole.

[0079] Referring to Figure 5C As shown, after forming the pattern corresponding to the bit line contact hole on the mask pattern transfer layer 225, the method further includes etching the second etching stop layer 224 and the second mask material layer 223, and forming a mask shielding layer 230 in the etched hole. The material of the mask shielding layer 230 is different from that of the second etching stop layer 224 and the second mask material layer 223, and optionally, the material of the mask shielding layer 230 can include an oxide, such as silicon oxide.

[0080] Referring to Figure 5D As shown, after forming the mask shielding layer 230, the second etching stop layer 224, the second mask material layer 223, the first etching stop layer 222, the first mask material layer 221 and the barrier structure are etched in sequence to form a patterned barrier structure. Optionally, the mask shielding layer can be removed at the same time as the protective layer. It can be understood that after forming the patterned barrier structure, the step of removing the first etching stop layer and the first mask material layer under the mask shielding layer is further included.

[0081] Figure 5DThe patterned barrier structure 210 formed after etching is shown. The openings in the barrier structure 210 define the positions of the bit line contact holes. It can be understood that in the present disclosure, the bit line contact hole is only used to define the area for preparing the bit line contact, the top surface of which is lower than the top surface of the adjacent barrier structure. The bit line contact hole does not necessarily have a strictly hole structure, and can also be not limited to a hole or groove structure, as long as it is an area formed on the substrate for preparing the bit line contact which is lower than the top surface of the barrier structure.

[0082] In some examples of this embodiment, after the patterned barrier structure 210 is formed, the substrate is etched based on the barrier structure 210 to form a bit line contact hole exposing the active region 110. Referring to Figure 5D As shown, the barrier structure 210 defines the opening of the bit line contact hole, and the active region 110 serves as the bottom of the bit line contact hole. When etching the substrate, the dielectric layer and the active region 110 can be etched in sequence to form a bit line contact hole exposing the active region 110. The way of etching the dielectric layer and the active region 110 can be dry etching.

[0083] Step S3: Forming a contact material layer 310 in the bit line contact hole.

[0084] Referring to Figure 6 As shown, in some examples of this embodiment, the way of forming the contact material layer 310 in the bit line contact hole can include but is not limited to vapor deposition. The bit line contact material layer 310 can be filled in the bit line contact hole by vapor deposition. It can be understood that corresponding to the active region 110, there can be multiple bit line contact holes, and the contact material layers 310 in adjacent bit line contact holes are connected to each other through the electrical connection layer 211.

[0085] The contact material layer 310 is used to form a bit line contact through etching in the subsequent preparation process. The material of the contact material layer 310 can be selected from conductive materials. Optionally, the material of the contact material layer 310 is the same as the material of the electrical connection layer 211. For example, the material of the contact material layer 310 includes polysilicon.

[0086] Step S4: Reacting part of the contact material layer 310 located on the surface layer to form a sacrificial layer 320.

[0087] It can be understood that the contact material layer 310 and the electrical connection layer 211 are not formed at the same time. In actual preparation process, the surface height of the contact material layer 310 is usually controlled to be slightly higher than that of the electrical connection layer 211. In the research of the present disclosure, it is found that due to the surface height of the contact material layer 310 being slightly higher than that of the electrical connection layer 211, and the subsequent need to further form the bit line material layer 410 on the surfaces of the contact material layer 310 and the electrical connection layer 211 and perform etching. In the etching step, due to the surface of the contact material layer 310 being slightly higher, the part of the bit line material layer 410 above the contact material layer 310 is also slightly higher, which makes the top of this part of the bit line material layer 410 start to be etched earlier, thereby causing the problem of the metal conductive material (such as tungsten) of the bit line above the bit line contact being too thin.

[0088] To solve this problem, the present disclosure further proposes the following processing mode.

[0089] In some examples of this embodiment, before the part of the contact material layer 310 located at the surface layer is reacted to form the sacrificial layer 320, further comprising: obtaining an initial distance between the top surface of the contact material layer 310 and the top surface of the electrical connection layer 211. If the initial distance is greater than a preset distance, the contact material layer 310 can be further processed to solve the problem of the bit line being too thin.

[0090] Referring to Figure 7 The part of the contact material layer 310 located at the surface layer is reacted to make the reacted part of the contact material layer 310 be converted into the sacrificial layer 320, and the contact material layer 310 below the sacrificial layer 320 is basically unchanged and can be used as the contact layer 311. By reacting the part of the contact material layer 310 located at the surface layer, the top surface of the contact layer 311 can be made lower than the top surface of the contact material layer 310, so that the distance between the top surface of the contact layer 311 and the top surface of the electrical connection layer 211 is less than the initial distance, and is reduced to be not greater than the preset distance or the top surface of the contact layer is flush with the top surface of the electrical connection layer.

[0091] In some examples of this embodiment, the step of reacting the part of the contact material layer 310 located at the surface layer includes: performing oxidation treatment on the part of the contact material layer 310 located at the surface layer to form the sacrificial layer 320 including silicon oxide. The way of reacting the part of the contact material layer 310 located at the surface layer can be various. For example, the contact material layer 310 can be placed in a reaction gas atmosphere to make the contact material layer 310 react with the reaction gas.

[0092] In some examples of this embodiment, the oxidizing gas can include one or more of oxygen, nitrogen dioxide, carbon oxysulfide, and sulfur dioxide.

[0093] Referring to Figure 7As shown, in some examples of the embodiment, in the step of reacting the portion of the contact material layer 310 located at the surface layer to form the sacrificial layer 320, the top surface of the contact layer 311 can be leveled with the top surface of the electrical connection layer 211 by controlling the amount of the contact material layer 310 to be reacted. It can be understood that, when the contact material layer 310 is reacted, the reaction gradually proceeds from the surface layer to the inside of the contact material layer 310, and by controlling the reaction time, the actual reaction depth of the contact material layer 310 can be controlled, and thus the top surface of the contact layer 311 can be leveled with the top surface of the electrical connection layer 211.

[0094] Further, in the reaction of the contact material layer 310, different reaction conditions can affect the reaction rate and the reaction uniformity of the contact material layer 310. In actual reaction, in order to more accurately control the reaction depth of the contact material layer 310, it is necessary to control the reaction rate to be relatively stable and the reaction uniformity to be relatively high. In some examples of the embodiment, the oxidation treatment of the contact material layer 310 can be performed by placing the contact material layer 310 in an atmosphere of oxidizing gas. Alternatively, the oxidizing gas can include oxygen. In this case, the process of the oxidation reaction of the contact material layer 310 with the oxidizing gas can be approximated as the process of active oxygen (or oxygen radical, oxygen ion) diffusing into the contact material layer 310, and the reaction rate of the process can be expressed as: where k is the diffusion coefficient of active oxygen in the medium, is the concentration gradient of active oxygen. Thus, by placing the contact material layer 310 in an atmosphere of oxidizing gas, the reaction uniformity can be higher and the reaction rate can be more controllable.

[0095] In some examples of the embodiment, the reaction temperature is 80-100°C when the portion of the contact material layer 310 located at the surface layer is subjected to the oxidation treatment. In most of the reaction chamber, it can be considered that the concentration of active oxygen is maintained constant. In the portion close to the contact material layer 310, since the active oxygen is consumed when the surface of the contact material layer 310 is oxidized, the concentration of active oxygen close to the surface of the contact material layer 310 is relatively low and the concentration gradient is relatively large, and thus the reaction rate is relatively high. In the inside of the contact material layer 310, since the concentration gradient of active oxygen is relatively small and the diffusion coefficient of active oxygen in the inside of the contact material layer 310 is also relatively low, the reaction rate in the inside of the contact material layer 310 is significantly lower. By controlling the reaction temperature to be 80-100°C, the diffusion coefficient of active oxygen in the inside of the contact material layer 310 can be appropriately increased, and thus the reaction can be performed at a relatively appropriate rate.

[0096] In some examples of the embodiment, the partial contact material layer 310 located at the surface layer is subjected to an oxidation treatment by an oxidizing gas, and the flow rate of the oxidizing gas is 100-200sccm. By controlling the flow rate of the oxidizing gas, the concentration of the oxidizing gas in the reaction chamber can be stabilized as much as possible, so that the reaction rate of the contact material layer 310 is more appropriate and the reaction uniformity is higher.

[0097] In some examples of the embodiment, the initial distance between the top surface of the contact material layer 310 and the top surface of the electrical connection layer 211, in combination with the control of the reaction time of the contact material layer 310, can be used to control the reaction depth of the contact material layer 310 as accurately as possible. For example, assuming that the height difference between the top surface of the contact material layer 310 and the top surface of the electrical connection layer 211 is h, and the reaction rate of the contact material layer 310 under certain conditions is v, in order to make the top surface of the contact material layer 310 level with the top surface of the electrical connection layer 211, the reaction time can be controlled to be h / v.

[0098] The preset distance can be determined according to the width reduction of the bit line top end above the contact. For example, when the distance between the top surface of the contact material layer and the top surface of the electrical connection layer is greater than the preset distance, the width reduction of the bit line top end above the contact exceeds the preset reduction. When the initial distance between the top surface of the contact material layer and the top surface of the electrical connection layer is less than the preset distance, the width reduction of the bit line top end above the contact is below the preset reduction. The preset reduction can be determined according to the actual demand for the performance of the bit line. In step S5, the protective layer 212 and the sacrificial layer 320 are removed.

[0099] Referring to Figure 8 As shown in FIG. 12, after the sacrificial layer 320 is formed, the protective layer 212 and the sacrificial layer 320 can be removed to expose the electrical connection layer 211 and the contact layer 311 located below. The top surfaces of the electrical connection layer 211 and the contact layer 311 are substantially level.

[0100] In some examples of the embodiment, the material of the protective layer 212 is the same as the material of the sacrificial layer 320, and in the step of removing the protective layer 212 and the sacrificial layer 320, the protective layer 212 and the sacrificial layer 320 can be removed at the same time. For example, the material of the protective layer 212 is selected from silicon oxide, and the material of the sacrificial layer 320 is also selected from silicon oxide. When the protective layer 212 and the sacrificial layer 320 are removed, the protective layer 212 and the sacrificial layer 320 can be removed at the same time by removing the silicon oxide. It can be understood that the material of the sacrificial layer 320 is related to the material of the contact material layer 310. Therefore, if the material of the sacrificial layer 320 is silicon oxide, the material of the contact material layer 310 can be silicon, such as polysilicon.

[0101] In some examples of this embodiment, the removal of the protective layer 212 and the sacrificial layer 320 can be achieved through etching, which can be selected from dry etching or wet etching. The etchant used for etching can have a high etch selectivity for the sacrificial layer 320 and the contact material layer 310, a high reaction rate for the sacrificial layer 320, and a low reaction rate or no reaction for the contact material layer 310. Similarly, the etchant used for etching can have a high etch selectivity for the protective layer 212 and the electrical connection layer 211.

[0102] Step S6, forming bit lines and bit line contacts 312.

[0103] Reference Figure 9 and Figure 10 As shown, in some examples of this embodiment, the bit line contact 312 can be obtained by etching through the contact layer 311. The bit line is located on the bit line contact 312 and is electrically connected to the active region 110 through the bit line contact 312.

[0104] In some examples of this embodiment, the step of forming the bit line includes: forming a first conductive material layer 410, the first conductive material layer 410 covering the contact layer 311 and the electrical connection layer 211;

[0105] A second conductive material layer 420 is formed on the first conductive material layer 410;

[0106] An insulating dielectric material layer 430 is formed on the second conductive material layer 420;

[0107] An insulating dielectric material layer 430, a second conductive material layer 420, and a first conductive material layer 410 are etched to form a bit line insulating layer 431, a second bit line conductive layer 421, and a first bit line conductive layer 411, respectively. The bit line includes the bit line insulating layer 431, the second bit line conductive layer 421, and the first bit line conductive layer 411. The first conductive material layer 410 completely covers the contact layer 311 and the electrical connection layer 211.

[0108] In some examples of this embodiment, the first conductive material layer 410 can be used to improve the adhesion between the second conductive material layer 420 and the contact layer 311 and between the second conductive material layer 420 and the electrical connection layer 211, and the second conductive material layer 420 can serve as the main conductive part of the bit line, providing higher conductivity.

[0109] In some examples of this embodiment, the material of the first conductive material layer 410 may include one or more of metallic titanium and titanium nitride. The first conductive material layer 410 may be formed by physical vapor deposition or chemical vapor deposition. For example, metallic titanium may be prepared by chemical vapor deposition using a raw material including titanium chloride in a reducing gas atmosphere.

[0110] In some examples of this embodiment, the material of the second conductive material layer 420 can include tungsten metal, so that the bit line has higher conductivity and stability. The way of forming the second conductive material layer 420 can be physical vapor deposition or chemical vapor deposition. For example, the way of preparing tungsten metal by chemical vapor deposition can be: using tungsten hexafluoride as raw material to deposit the second conductive material layer 420.

[0111] Referring to Figure 9 As shown, after the second conductive material layer 420 is formed, a layer of insulating medium material layer 430 can be formed on the second conductive material layer 420. The insulating medium material layer 430 is mainly used to close the second conductive material layer 420 from the top, preventing the second bit line conductive layer 421 from shorting with other components.

[0112] In some examples of this embodiment, the material of the insulating medium material layer 430 can include silicon nitride. The way of forming the insulating medium material layer 430 can be physical vapor deposition or chemical vapor deposition.

[0113] Referring to Figure 10 As shown, the insulating medium material layer 430, the second conductive material layer 420 and the first conductive material layer 410 are etched to form a bit line including a bit line insulating layer 431, a second bit line conductive layer 421 and a first bit line conductive layer 411. It can be understood that in the step of etching the insulating medium material layer 430, the second conductive material layer 420 and the first conductive material layer 410, an etchant containing fluorine can be used for etching.

[0114] In some examples of this embodiment, before etching the insulating medium material layer 430, the second conductive material layer 420 and the first conductive material layer 410, a layer of photoresist layer can also be coated on the insulating medium material layer 430, and then the photoresist layer is exposed and developed according to a predetermined pattern to perform a patterning process. The opening of the patterned photoresist layer defines the area of the insulating medium material layer 430 that needs to be etched.

[0115] In the above preparation process, if the surface layer of the contact material layer 310 is not subjected to a reaction process to form a sacrificial layer 320 and removed, the top surface of the contact material layer 310 is often higher than the top surface of the electrical connection layer 211, and then the top surface of the part of the second conductive material layer 420 above the contact material layer 310 is also higher than the top surface of the part of the second conductive material layer 420 above the electrical connection layer 211. In the preparation of the bit line, the etchant will etch to the second conductive material layer 420 after etching the insulating medium material layer 430. Since the part of the second conductive material layer 420 above the contact material layer 310 is more prominent, the sidewall of its top end will also contact the etchant earlier than other parts, thereby causing excessive etching of the top end.

[0116] In the above-mentioned steps S4 and S5, the distance between the top surface of the contact layer 311 and the top surface of the electrical connection layer 211 is made lower than the initial distance by forming the sacrificial layer 320 after the partial contact layer 310 is reacted and then removing the sacrificial layer 320, so that the top surface of the contact layer 311 and the top surface of the electrical connection layer 211 are more flat. Then in this step, the first conductive material layer 410, the second conductive material layer 420 and the insulating medium material layer 430 which cover the contact layer 311 and the electrical connection layer 211 as a whole are also more flat. Compared with the prior art without the planarization process, in the steps of etching the insulating medium material layer 430 and etching the second conductive material layer 420, the part of the second conductive material layer 420 above the contact layer 311 contacts the etchant later than before, so that the problem of over-etching of the top end of the second conductive material layer 420 can be alleviated.

[0117] In some examples of this embodiment, by controlling the top surface of the contact layer 311 to be flush with the top surface of the electrical connection layer 211, it is possible to ensure that the top surface of the second conductive material layer 420 is as flat as possible, thereby avoiding the problem of the top end of the bit line being too thin as much as possible when etching the second conductive material layer 420.

[0118] In some examples of this embodiment, after etching the part of the insulating medium material layer 430, the second conductive material layer 420 and the first conductive material layer 410 in the predetermined area, the electrical connection layer 211 and the contact layer 311 can also be etched until the substrate is etched, i.e. the etching can be stopped. The contact layer 311 after etching can be used as the bit line contact 312. Referring to Figure 11 the semiconductor structure shown in FIG. 6, which shows a top view of the semiconductor structure. Figure 10 the semiconductor structure shown in FIG. 6, which shows a top view of the semiconductor structure. Figure 11 the circle in FIG. 6 represents the position of the reserved isolation layer 213, and the area outside the circle represents the area of the bit line contact hole, Figure 11 the bit line contact 312 in FIG. 6 is located in the bit line contact hole below the bit line insulating layer 431.

[0119] By the above steps S1-S6, the preparation of the semiconductor structure can be completed.

[0120] It can be understood that after the bit line is formed, a step of preparing a bit line side wall around the bit line can also be included. In some examples of this embodiment, the step of forming the bit line side wall can include: forming a first nitride layer on the sidewall of the bit line and the sidewall of the exposed bit line contact; then forming an oxide layer on the surface of the first nitride layer; and then forming a second nitride layer on the surface of the oxide layer and the top of the bit line. The material of the first nitride layer can include silicon nitride, the material of the oxide layer can include silicon oxide, and the material of the second nitride layer can include silicon nitride.

[0121] The present disclosure also provides a semiconductor structure prepared by the method for preparing a semiconductor structure.

[0122] Referring to Figure 10 and Figure 11 The semiconductor structure includes a substrate, an electrical connection layer 211, a bit line contact 312, and a bit line. The substrate includes a shallow trench isolation structure 120 and an active region 110, and the shallow trench isolation structure 120 separates a plurality of active regions 110 arranged at intervals in the substrate. The substrate has a bit line contact hole exposing the active region 110, the bit line contact 312 is arranged in the bit line contact hole, the electrical connection layer 211 is arranged on the substrate outside the bit line contact hole, and the bit line is arranged on the electrical connection layer 211 and the bit line contact 312. The bit line contact 312 can be formed by etching the contact layer 311.

[0123] In some examples of the embodiment, the top surface of the bit line contact in the semiconductor structure is flush with the top surface of the electrical connection layer.

[0124] Please note that the above embodiments are only for illustrative purposes and do not mean to limit the present disclosure.

[0125] It should be understood that, unless otherwise explicitly stated herein, the execution of the steps of the method is not strictly limited in order, and the steps can be executed in other orders. Moreover, at least a part of the steps of the method can include a plurality of sub-steps or a plurality of stages, which do not necessarily be executed at the same time, but can be executed at different times, and the execution order of the sub-steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least a part of other steps or sub-steps or stages of other steps.

[0126] Each of the embodiments in the specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other.

[0127] The technical features of the above embodiments can be combined in any manner. In order to make the description concise, not all possible combinations of the technical features in the above embodiments are described, however, as long as the combination of the technical features does not exist contradictory, it should be considered as the scope of the present disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: Provide substrate; A patterned barrier structure and a contact material layer are formed on the substrate. The barrier structure includes a stacked electrical connection layer and a protective layer. The electrical connection layer is located between the substrate and the protective layer. The opening of the barrier structure defines the position of the bit line contact hole. The contact material layer is formed in the bit line contact hole. The top surface of the contact material layer is higher than the top surface of the electrical connection layer. The initial distance between the top surface of the contact material layer and the top surface of the electrical connection layer is obtained. If the initial distance is greater than a preset distance, the contact material layer on the surface is reacted to form a sacrificial layer, and the contact material layer below the sacrificial layer serves as the contact layer, so that the distance between the top surface of the contact layer and the top surface of the electrical connection layer is not greater than the preset distance. as well as Remove the sacrificial layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, In the step of reacting the contact material layer located on the surface to form a sacrificial layer, the amount of reaction is controlled so that the top surface of the contact layer is flush with the top surface of the electrical connection layer.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, The contact material layer is made of silicon, and the step of reacting the contact material layer located on the surface to form a sacrificial layer includes: oxidizing the contact material layer to form silicon oxide as the sacrificial layer.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, The contact material layer is oxidized using an oxidizing gas.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, The reaction temperature during oxidation treatment is 80℃~100℃.

6. The method for preparing a semiconductor structure according to claim 4, characterized in that, During oxidation treatment, the flow rate of the oxidizing gas is 100 sccm to 200 sccm.

7. The method for preparing a semiconductor structure according to claim 4, characterized in that, The oxidizing gas includes one or more of oxygen, nitrogen dioxide, carbon oxysulfide, and sulfur dioxide.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that, The protective layer is made of the same material as the sacrificial layer, and the protective layer is removed simultaneously during the step of removing the sacrificial layer.

9. The method for preparing a semiconductor structure according to any one of claims 1 to 8, characterized in that, The substrate includes a shallow trench isolation structure that isolates multiple spaced active regions within the substrate. After removing the sacrificial layer, the substrate further includes: Bit lines and bit line contacts are formed, the bit line contacts are obtained by etching the contact layer, the bit lines are located on the bit line contacts, and the bit lines are electrically connected to the active region through the bit line contacts.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that, The steps for forming the bit line include: A first conductive material layer is formed, which covers the contact layer and the electrical connection layer; A second conductive material layer is formed on the first conductive material layer; An insulating dielectric material layer is formed on the second conductive material layer; The insulating dielectric material layer, the second conductive material layer, and the first conductive material layer are etched to form a bit line insulating layer, a second bit line conductive layer, and a first bit line conductive layer, respectively. The bit line includes the bit line insulating layer, the second bit line conductive layer, and the first bit line conductive layer.

11. The method for preparing a semiconductor structure according to claim 10, characterized in that, The material of the second bit line conductive layer includes tungsten.

12. The method for preparing a semiconductor structure according to any one of claims 1 to 8 and 10 to 11, characterized in that, The material of the electrical connection layer is the same as the material of the contact material layer.

13. The method for preparing a semiconductor structure according to any one of claims 1-8 and 10-11, characterized in that, The step of forming a patterned barrier structure on the substrate includes: The electrical connection layer is formed on the substrate; The protective layer is formed on the electrical connection layer; A patterned mask structure is formed on the protective layer, in which the portion of the protective layer to be etched is exposed; Based on the mask structure, the protective layer and the electrical connection layer are etched to form the barrier structure.

14. The method for preparing a semiconductor structure according to any one of claims 1 to 8 and 10 to 11, characterized in that, The barrier structure further includes an isolation layer disposed between the substrate and the electrical connection layer.

15. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the method for preparing the semiconductor structure according to any one of claims 1-14.

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