Semiconductor structure and method of forming the same

Abstract

The application provides a semiconductor structure and a forming method thereof. The semiconductor structure comprises: a semiconductor substrate, a floating gate and a gate dielectric layer formed on the semiconductor substrate in sequence, a control gate on a surface of the gate dielectric layer, a floating gate connection structure on both sides of the control gate, a part of the floating gate connection structure penetrating through the gate dielectric layer and extending into the floating gate, an isolation structure between the control gate and the floating gate connection structure for isolating the control gate and the floating gate connection structure, an interlayer dielectric layer covering the semiconductor substrate, the control gate, the floating gate connection structure and the isolation structure, a first contact structure, a second contact structure and a third contact structure penetrating through the interlayer dielectric layer and electrically connected with the control gate, the floating gate connection structure and an active device in the semiconductor substrate respectively.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] The oxygen / nitrogen / oxygen dielectric layer comb-shaped capacitor structure in the 2D and NAND gate memory device has always existed the silicon burnout phenomenon caused by the potential induced decay problem in the high temperature reliability test. The abnormal position is located near the corner of the floating gate polysilicon of the oxygen / nitrogen / oxygen dielectric layer comb-shaped capacitor structure. In the device nanometer probe analysis process, the current leakage from the floating gate to the active region of the abnormal position is high, and a bright VC is displayed on the contact structure of the floating gate.

[0003] Therefore, it is necessary to provide a more effective and reliable technical solution. SUMMARY

[0004] The present application provides a semiconductor structure and a forming method thereof, which can solve the PID problem and the silicon burnout problem of the capacitor device.

[0005] One aspect of the present application provides a forming method of a semiconductor structure, comprising: providing a semiconductor substrate, sequentially forming a floating gate material layer and a gate dielectric material layer on the semiconductor substrate; etching the gate dielectric material layer into the floating gate material layer to form a first opening; forming a control gate material layer in the first opening and on the surface of the gate dielectric material layer; etching the control gate material layer, the gate dielectric material layer and the floating gate material layer located at the edge of the semiconductor substrate to form a second opening, the remaining floating gate material layer being a floating gate, and the remaining gate dielectric material layer being a gate dielectric layer; etching the remaining control gate material layer to form a third opening for isolating the control gate material layer, wherein the part of the control gate material layer connected with the floating gate is a floating gate connection structure, and the part of the control gate material layer not connected with the floating gate is a control gate; forming an isolation structure in the third opening; forming an interlayer dielectric layer on the surface of the second opening, the floating gate connection structure, the control gate and the isolation structure; and forming a first contact structure, a second contact structure and a third contact structure penetrating through the interlayer dielectric layer and respectively electrically connected with the control gate, the floating gate connection structure, and an active device in the semiconductor substrate.

[0006] In some embodiments of the present application, the width ratio of the control gate and the floating gate connection structure is (6-15):1.

[0007] In some embodiments of the present application, the method of etching the gate dielectric layer into the floating gate layer to form a first opening comprises: forming a patterned photoresist layer on the surface of the gate dielectric layer, the patterned photoresist layer defining the position of the first opening; etching the gate dielectric layer to form the first opening using the patterned photoresist layer as a mask; and etching into the floating gate layer along the first opening.

[0008] In some embodiments of the present application, the first opening has a depth of 80-120 angstroms in the floating gate layer.

[0009] In some embodiments of the present application, forming an isolation structure in the third opening and forming an interlayer dielectric layer on the surface of the floating gate connection structure, the surface of the control gate and the surface of the isolation structure are performed in one step.

[0010] In some embodiments of the present application, the gate dielectric layer is a silicon oxide-silicon nitride-silicon oxide three-layer structure.

[0011] One aspect of the present application also provides a semiconductor structure, comprising: a semiconductor substrate, a floating gate and a gate dielectric layer formed on the semiconductor substrate in sequence; a control gate on the surface of the gate dielectric layer; a floating gate connection structure on both sides of the control gate, a portion of the floating gate connection structure extending through the gate dielectric layer and into the floating gate; an isolation structure between the control gate and the floating gate connection structure for isolating the control gate and the floating gate connection structure; an interlayer dielectric layer covering the semiconductor substrate, the control gate, the floating gate connection structure and the isolation structure; a first contact structure, a second contact structure and a third contact structure extending through the interlayer dielectric layer and electrically connected to the control gate, the floating gate connection structure and an active device in the semiconductor substrate, respectively.

[0012] In some embodiments of the present application, the width ratio of the control gate and the floating gate connection structure is (6-15):1.

[0013] In some embodiments of the present application, a portion of the floating gate connection structure extends into the floating gate to a depth of 80-120 angstroms.

[0014] In some embodiments of the present application, the gate dielectric layer is a silicon oxide-silicon nitride-silicon oxide three-layer structure.

[0015] The present application provides a semiconductor structure and a method for forming the same, which indirectly electrically connects the third contact structure and the floating gate through the floating gate connection structure, thereby solving the problem of silicon burnout of capacitor devices. Attached Figure Description

[0016] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale.

[0017] in:

[0018] Figure 1 This is a schematic diagram of a semiconductor structure;

[0019] Figures 2 to 13 This is a schematic diagram of each step in the method for forming a semiconductor structure according to the embodiments of this application. Detailed Implementation

[0020] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0021] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.

[0022] Figure 1 This is a schematic diagram of a semiconductor structure.

[0023] refer to Figure 1As shown, the semiconductor structure can be an oxygen / nitrogen / oxygen dielectric layer comb-shaped capacitor structure. The semiconductor structure comprises: a semiconductor substrate 100, a floating gate 110 and a gate dielectric layer 120 formed on the semiconductor substrate 100 in sequence, a control gate 130 located on the surface of the gate dielectric layer 120, an isolation structure 140 penetrating the control gate 130 for isolating the control gate 130 and a second contact structure 162, an interlayer dielectric layer 150 covering the semiconductor substrate 100, the control gate 130 and the isolation structure 140, a first contact structure 161, a second contact structure 162 and a third contact structure 163 penetrating the interlayer dielectric layer 150 and electrically connected to the control gate 130, the floating gate 110 and an active device (such as a source 181 and a drain 182) in the semiconductor substrate 100 respectively, an intermetallic dielectric layer 170 located on the surface of the interlayer dielectric layer 150, a first metal layer 171, a second metal layer 172 and a third metal layer 173 penetrating the intermetallic dielectric layer 170 and electrically connected to the first contact structure 161, the second contact structure 162 and the third contact structure 163 respectively.

[0024] In the semiconductor structure described above, the second contact structure 162 and the floating gate 110 are electrically connected by direct contact, which may cause plasma to gather at the corner of the floating gate. When the voltage of the device is increased, the abnormal corner may be burned out due to the PID problem, thereby affecting the reliability of the device.

[0025] To solve the above problems, the present application provides a semiconductor structure and a forming method thereof, so that the third contact structure and the floating gate are not directly contacted but indirectly electrically connected through a floating gate connecting structure, thereby solving the problem of silicon burning of the capacitor device.

[0026] Figures 2 to 13 The semiconductor structure forming method described in the embodiments of the present application is shown in the structure schematic diagram of each step. The semiconductor structure forming method described in the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0027] In some embodiments of the present application, the present application is demonstrated by an oxygen / nitrogen / oxygen dielectric layer comb-shaped capacitor structure.

[0028] Reference Figure 2 As shown, a semiconductor substrate 200 is provided, and a floating gate material layer 210a and a gate dielectric material layer 220a are formed on the semiconductor substrate 200 in sequence.

[0029] In some embodiments of the application, the material of the semiconductor substrate 200 includes (i) an elemental semiconductor, such as silicon or germanium, etc.; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide, etc.; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or indium gallium phosphide, etc.; or (iv) a combination thereof. In addition, the semiconductor substrate 200 can be doped (e.g., a P-type substrate or an N-type substrate). In some embodiments of the application, the semiconductor substrate 200 can be doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium) or an N-type dopant (e.g., phosphorus or arsenic).

[0030] In some embodiments of the application, the method of forming the floating gate material layer 210a includes a chemical vapor deposition process or a physical vapor deposition process, etc. The material of the floating gate material layer 210a is, for example, polysilicon.

[0031] In some embodiments of the application, the method of forming the gate dielectric material layer 220a includes a chemical vapor deposition process or a physical vapor deposition process, etc. The gate dielectric material layer 220a is, for example, a silicon oxide-silicon nitride-silicon oxide (ONO) three-layer structure.

[0032] In some embodiments of the application, a gate oxide layer (not shown) can also be formed between the semiconductor substrate 200 and the floating gate material layer 210a.

[0033] Referring to Figures 3 to 6 The gate dielectric material layer 220a is etched to form a first opening 201 in the floating gate material layer 210a.

[0034] Referring to Figure 3 A patterned photoresist layer 201a is formed on the surface of the gate dielectric material layer 220a, which defines the position of the first opening 201.

[0035] In some embodiments of the application, the method of forming the patterned photoresist layer 201a includes a spin coating process.

[0036] Referring to Figure 4 The gate dielectric material layer 220a is etched to form the first opening 201 using the patterned photoresist layer 201a as a mask.

[0037] In some embodiments of the application, the method of forming the first opening 201 includes a wet etching process or a dry etching process, etc.

[0038] Referring to Figure 5 The floating gate material layer 210a is etched along the first opening 201. The etching includes a wet etching process or a dry etching process, etc.

[0039] In some embodiments of the present application, the first opening 201 has a depth of 80-120 angstroms in the floating gate material layer 210a. The depth cannot be too deep, otherwise the volume of the floating gate will be reduced too much, affecting the performance of the floating gate.

[0040] Reference is made to Fig. 2, which shows a semiconductor structure after the patterned photoresist layer 201a is removed. Figure 6 Reference is made to Fig. 2, which shows a semiconductor structure after the patterned photoresist layer 201a is removed.

[0041] In some embodiments of the present application, the method of removing the patterned photoresist layer 201a is, for example, a gray ash process.

[0042] Reference is made to Fig. 3, which shows a semiconductor structure after the first opening 201 is formed. Figure 1 In the semiconductor structure shown in Fig. 3, the floating gate 110 is completely covered and shielded by the gate dielectric layer 120 and the control gate 130 (also electrically isolated), so the second contact structure 162 must extend through the gate dielectric layer 120 and the control gate 130 to the floating gate 110 to achieve electrical connection between the second contact structure 162 and the floating gate 110. In the technical solution of the present application, in order to avoid the above situation, the gate dielectric layer is penetrated through the first opening 201, thereby making part of the control gate (i.e., the floating gate connection structure hereinafter) and the floating gate contact connected, so that the second contact structure only needs to be connected to this part of the control gate to indirectly achieve electrical connection between the second contact structure and the floating gate.

[0043] In some embodiments of the present application, since the purpose of the first opening 210 is to enable contact connection between the control gate material layer 230a and the floating gate material layer 210a, the first opening 210 can be a trench or a hole.

[0044] Reference is made to Fig. 4, which shows a semiconductor structure after the control gate material layer 230a is formed in the first opening 201 and on the surface of the gate dielectric material layer 220a. Figure 7 Reference is made to Fig. 4, which shows a semiconductor structure after the control gate material layer 230a is formed in the first opening 201 and on the surface of the gate dielectric material layer 220a. Due to the presence of the first opening 201, contact connection between part of the control gate material layer 230a and the floating gate material layer 210a is achieved.

[0045] In some embodiments of the present application, the method of forming the control gate material layer 230a includes a chemical vapor deposition process or a physical vapor deposition process, etc. The material of the control gate material layer 230a includes polysilicon.

[0046] Reference is made to Fig. 5, which shows a semiconductor structure after the second contact structure 162 is formed. Figure 8As shown, the control gate material layer 230a, the gate dielectric material layer 220a and the floating gate material layer 210a located at the edge of the semiconductor substrate 200 are etched to form a second opening 202, the remaining floating gate material layer 210a is the floating gate 210, and the remaining gate dielectric material layer 220a is the gate dielectric layer 220.

[0047] On the one hand, the second opening 202 can expose a portion of the semiconductor substrate 200 to form the source and drain; on the other hand, the second opening 202 is also used to form a third contact structure that electrically connects the source and drain.

[0048] In some embodiments of this application, the gate dielectric layer 220 is a silicon oxide-silicon nitride-silicon oxide three-layer structure.

[0049] refer to Figure 9 As shown, a source 281 and a drain 282 are formed in the exposed semiconductor substrate 200. The method for forming the source 281 and drain 282 is, for example, an ion implantation process.

[0050] refer to Figure 10 As shown, etching the remaining control gate material layer 230a forms a third opening 203 that blocks the control gate material layer 230a. The portion of the control gate material layer 230a connected to the floating gate 210 is a floating gate connection structure 241, and the portion of the control gate material layer 230a not connected to the floating gate 210 is a control gate 230.

[0051] Since the control gate material layer 230a and the floating gate 210 are connected in contact, and in this device, the final formed control gate and floating gate need to operate independently and cannot be electrically connected together, the third opening 203 is needed to isolate the control gate material layer 230a (that is, to divide the control gate 230a into two parts, one part is still used to fabricate the control gate, and the other part is used to contact and connect the floating gate). The part used to fabricate the control gate becomes the control gate 230, and the other part used to contact and connect the floating gate becomes the floating gate connection structure 241.

[0052] It should be noted that, for the sake of simplicity and convenience, the structures in the accompanying drawings are not drawn to actual scale. For example, although the widths of the control gate 230 and the floating gate connection structure 241 in the drawings are relatively close, in some embodiments of this application, the width ratio of the control gate 230 and the floating gate connection structure 241 is (6-15):1, such as 6:1, 8:1, 10:1, 12:1, or 15:1. Where process technology allows, the size of the control gate 230 is increased as much as possible to increase capacitance.

[0053] refer to Figure 11 As shown, an isolation structure 240 is formed in the third opening 203, and an interlayer dielectric layer 250 is formed in the second opening 202, on the surface of the floating gate connection structure 241, on the surface of the control gate 230, and on the surface of the isolation structure 240.

[0054] In some embodiments of this application, forming the isolation structure 240 in the third opening 203 and forming the interlayer dielectric layer 250 in the second opening 202, on the surface of the floating gate connection structure 241, on the surface of the control gate 230, and on the surface of the isolation structure 240 are the same step. For example, an insulating dielectric material (e.g., silicon oxide) is deposited in the third opening 203, the second opening 202, on the surface of the floating gate connection structure 241, on the surface of the control gate 230, and on the surface of the isolation structure 241, and then the surfaces are polished using a chemical mechanical polishing process to make them flat, thereby forming an integrally connected isolation structure 240 and interlayer dielectric layer 250.

[0055] In some other embodiments of this application, the isolation structure 240 and the interlayer dielectric layer 250 may also be formed in steps.

[0056] The isolation structure 240 is used to isolate the control gate 230 and the floating gate connection structure 241. The isolation structure 240 is made of an insulating material, such as silicon oxide or silicon nitride. The interlayer dielectric layer 250 is made of silicon oxide.

[0057] refer to Figure 12 As shown, a first contact structure 261, a second contact structure 262, and a third contact structure 263 are formed, penetrating the interlayer dielectric layer 250 and electrically connecting the control gate 230, the floating gate connection structure 241, and the active devices (e.g., source 281 and drain 282) in the semiconductor substrate. Specifically, the first contact structure 261 is electrically connected to the control gate 230; the second contact structure 262 is electrically connected to the floating gate connection structure 241 (further electrically connected to the floating gate 210 via the floating gate connection structure 241); and the third contact structure 263 is electrically connected to the source 281 and the drain 282.

[0058] In the technical solution of this application, the second contact structure 262 does not directly contact the floating gate 210, but is indirectly electrically connected to the floating gate 210 through the floating gate connection structure 241. Plasma will not accumulate at the corner of the floating gate 210, which can solve the problem of silicon burnout of capacitor devices.

[0059] In some embodiments of this application, the materials of the first contact structure 261, the second contact structure 262, and the third contact structure 263 include conductive materials such as copper and tungsten.

[0060] In some embodiments of this application, the methods for forming the first contact structure 261, the second contact structure 262, and the third contact structure 263 include etching processes and chemical vapor deposition processes or physical vapor deposition processes.

[0061] refer to Figure 13 As shown, an intermetallic dielectric layer 270 is formed on the surface of the interlayer dielectric layer 250, and then a first metal layer 271, a second metal layer 272, and a third metal layer 273 are formed, penetrating the intermetallic dielectric layer 270 and electrically connected to the first contact structure 261, the second contact structure 262, and the third contact structure 263, respectively. Specifically, the first metal layer 271 is electrically connected to the first contact structure 261; the second metal layer 272 is electrically connected to the second contact structure 262; and the third metal layer 273 is electrically connected to the third contact structure 263.

[0062] This application provides a method for forming a semiconductor structure in which the third contact structure and the floating gate are not in direct contact, but are indirectly electrically connected through the floating gate connection structure, which can solve the problem of silicon burn-out in capacitor devices.

[0063] Embodiments of this application also provide a semiconductor structure, referencing Figure 13 As shown, the system includes: a semiconductor substrate 200 on which a floating gate 210 and a gate dielectric layer 220 are sequentially formed; a control gate 230 located on the surface of the gate dielectric layer 220; a floating gate connection structure 241 located on both sides of the control gate 230, a portion of the floating gate connection structure 241 penetrating the gate dielectric layer 220 and extending into the floating gate 210; and an isolation structure 240 located between the control gate 230 and the floating gate connection structure 241 for isolating the... The control gate 230 and the floating gate connection structure 241 are described; an interlayer dielectric layer 250 covers the semiconductor substrate 200, the control gate 230, the floating gate connection structure 241 and the isolation structure 210; a first contact structure 261, a second contact structure 262 and a third contact structure 263 penetrate the interlayer dielectric layer 250 and are respectively electrically connected to the active devices (e.g., source 281 and drain 282) in the control gate 230, the floating gate connection structure 241 and the semiconductor substrate 200.

[0064] refer to Figure 13As shown, the semiconductor structure described in this application includes: a semiconductor substrate 200, on which a floating gate 210 and a gate dielectric layer 220 are sequentially formed.

[0065] In some embodiments of this application, the semiconductor substrate 200 is made of (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or gallium indium phosphide; or (iv) a combination of the above. Furthermore, the semiconductor substrate 200 may be doped (e.g., a P-type substrate or an N-type substrate). In some embodiments of this application, the semiconductor substrate 200 may be doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium) or an N-type dopant (e.g., phosphorus or arsenic).

[0066] In some embodiments of this application, an active region, such as a source 281 and a drain 282, is also formed in the semiconductor substrate 200.

[0067] In some embodiments of this application, the floating gate 210 is made of, for example, polysilicon. In some embodiments of this application, the gate dielectric layer 220 is, for example, a silicon oxide-silicon nitride-silicon oxide (ONO) three-layer structure.

[0068] In some embodiments of this application, a gate oxide layer (not shown in the figure) may also be formed between the semiconductor substrate 200 and the floating gate 210.

[0069] Continue to refer to Figure 13 As shown, the semiconductor structure further includes a control gate 230 located on the surface of the gate dielectric layer 220.

[0070] In some embodiments of this application, the material of the control gate 230 includes polycrystalline silicon.

[0071] Continue to refer to Figure 13 As shown, the semiconductor structure further includes a floating gate connection structure 241 located on both sides of the control gate 230, a portion of which penetrates the gate dielectric layer 220 and extends into the floating gate 210.

[0072] In some embodiments of this application, the floating gate connection structure 241 is made of the same material as the control gate 230. In some embodiments of this application, the floating gate connection structure 241 is made of a conductive material.

[0073] In some embodiments of this application, a portion of the floating gate connection structure 241 extends into the floating gate 210 to a depth of 80 to 120 angstroms. This depth should not be too great to avoid reducing the volume of the floating gate too much and affecting its performance.

[0074] exist Figure 1 In the semiconductor structure shown, the floating gate 110 is completely covered and shielded (and electrically isolated) by the gate dielectric layer 120 and the control gate 130. Therefore, the second contact structure 162 must penetrate the gate dielectric layer 120 and the control gate 130 to extend into the floating gate 110 in order to achieve electrical connection between the second contact structure 162 and the floating gate 110. However, in the technical solution of this application, to avoid the above situation, the gate dielectric layer is penetrated and connected to the floating gate through the floating gate connection structure 241. Thus, only the second contact structure needs to be connected to the floating gate connection structure 241 to indirectly achieve electrical connection between the second contact structure and the floating gate.

[0075] In some embodiments of this application, since the purpose of the floating gate connection structure 241 is to enable the second contact structure 262 and the floating gate 210 to be electrically connected, the floating gate connection structure 241 can be elongated or columnar, extending through the gate dielectric layer 220 and into a portion of the floating gate 210.

[0076] It should be noted that, for the sake of simplicity and convenience, the structures in the accompanying drawings are not drawn to actual scale. For example, although the widths of the control gate 230 and the floating gate connection structure 241 in the drawings are relatively close, in some embodiments of this application, the width ratio of the control gate 230 and the floating gate connection structure 241 is (6-15):1, such as 6:1, 8:1, 10:1, 12:1, or 15:1. Where process technology allows, the size of the control gate 230 is increased as much as possible to increase capacitance.

[0077] Continue to refer to Figure 13 As shown, the semiconductor structure further includes an isolation structure 240 located between the control gate 230 and the floating gate connection structure 241, for isolating the control gate 230 and the floating gate connection structure 241.

[0078] Since the floating gate connection structure 241 and the floating gate 210 are in contact connection, and in this device, the control gate 230 and the floating gate 210 need to work independently and cannot be electrically connected together, the isolation structure 240 is needed to isolate the control gate 230 and the floating gate connection structure 241.

[0079] In some embodiments of this application, the material of the isolation structure 240 is an insulating material, such as silicon oxide, silicon nitride, etc.

[0080] Continue to refer to Figure 13 As shown, the semiconductor structure further includes an interlayer dielectric layer 250 covering the semiconductor substrate 200, the control gate 230, the floating gate connection structure 241, and the isolation structure 210.

[0081] In some embodiments of this application, the material of the interlayer dielectric layer 250 includes silicon oxide.

[0082] Continue to refer to Figure 13 As shown, the semiconductor structure further includes a first contact structure 261, a second contact structure 262, and a third contact structure 263, which penetrate the interlayer dielectric layer 250 and are electrically connected to the control gate 230, the floating gate connection structure 241, and the active devices (e.g., source 281 and drain 282) in the semiconductor substrate 200, respectively. Specifically, the first contact structure 261 is electrically connected to the control gate 230; the second contact structure 262 is electrically connected to the floating gate connection structure 241 (further electrically connected to the floating gate 210 via the floating gate connection structure 241); and the third contact structure 263 is electrically connected to the source 281 and the drain 282.

[0083] In the technical solution of this application, the second contact structure 262 does not directly contact the floating gate 210, but is indirectly electrically connected to the floating gate 210 through the floating gate connection structure 241. Plasma will not accumulate at the corner of the floating gate 210, which can solve the problem of silicon burnout of capacitor devices.

[0084] In some embodiments of this application, the materials of the first contact structure 261, the second contact structure 262, and the third contact structure 263 include conductive materials such as copper and tungsten.

[0085] Continue to refer to Figure 13 As shown, an intermetallic dielectric layer 270 and a first metal layer 271, a second metal layer 272, and a third metal layer 273 are also formed on the surface of the intermetallic dielectric layer 250 and penetrate the intermetallic dielectric layer 270 and are electrically connected to the first contact structure 261, the second contact structure 262, and the third contact structure 263, respectively. Specifically, the first metal layer 271 is electrically connected to the first contact structure 261; the second metal layer 272 is electrically connected to the second contact structure 262; and the third metal layer 273 is electrically connected to the third contact structure 263.

[0086] This application provides a semiconductor structure and a method for forming the same, in which the third contact structure and the floating gate are not in direct contact, but are indirectly electrically connected through the floating gate connection structure, which can solve the problem of silicon burn-out in capacitor devices.

[0087] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0088] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0089] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" indicates the absence of intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," when used in this application, specify the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0090] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0091] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A semiconductor substrate is provided, on which a floating gate material layer and a gate dielectric material layer are sequentially formed; Etch the gate dielectric material layer to form a first opening in the floating gate material layer; A control gate material layer is formed in the first opening and on the surface of the gate dielectric material layer; The control gate material layer, the gate dielectric material layer, and the floating gate material layer located at the edge of the semiconductor substrate are etched to form a second opening, the remaining floating gate material layer is a floating gate, and the remaining gate dielectric material layer is a gate dielectric layer; Etching the remaining control gate material layer forms a third opening that isolates the control gate material layer, wherein the portion of the control gate material layer connected to the floating gate is a floating gate connection structure, and the portion of the control gate material layer not connected to the floating gate is a control gate. An isolation structure is formed in the third opening; An interlayer dielectric layer is formed in the second opening on the surface of the floating gate connection structure, the surface of the control gate, and the surface of the isolation structure. A first contact structure, a second contact structure, and a third contact structure are formed that penetrate the interlayer dielectric layer and are electrically connected to the control gate, the floating gate connection structure, and the active device in the semiconductor substrate, respectively.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The width ratio of the connection structure between the control gate and the floating gate is (6-15):

1.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method of etching the gate dielectric material layer to form a first opening in the floating gate material layer includes: A patterned photoresist layer is formed on the surface of the gate dielectric material layer, and the patterned photoresist layer defines the location of the first opening; The first opening is formed by etching the gate dielectric material layer using the patterned photoresist layer as a mask; Etch along the first opening into the floating gate material layer.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first opening is located at a depth of 80 to 120 angstroms in the floating gate material layer.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, Forming an isolation structure in the third opening and forming an interlayer dielectric layer in the second opening, on the surface of the floating gate connection structure, on the surface of the control gate, and on the surface of the isolation structure are the same steps.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The gate dielectric layer is a three-layer structure of silicon oxide-silicon nitride-silicon oxide.

7. A semiconductor structure, characterized in that, include: A semiconductor substrate, wherein a floating gate and a gate dielectric layer are sequentially formed on the semiconductor substrate; A control gate is located on the surface of the gate dielectric layer; A floating gate connection structure is located on both sides of the control gate, and a portion of the floating gate connection structure penetrates the gate dielectric layer and extends into the floating gate; An isolation structure is located between the control gate and the floating gate connection structure to isolate the control gate and the floating gate connection structure. An interlayer dielectric layer covers the semiconductor substrate, the control gate, the floating gate connection structure, and the isolation structure; The first contact structure, the second contact structure, and the third contact structure penetrate the interlayer dielectric layer and are respectively electrically connected to the control gate, the floating gate connection structure, and the active device in the semiconductor substrate.

8. The semiconductor structure as described in claim 7, characterized in that, The width ratio of the connection structure between the control gate and the floating gate is (6-15):

1.

9. The semiconductor structure as described in claim 7, characterized in that, A portion of the floating gate connection structure extends into the floating gate to a depth of 80 to 120 angstroms.

10. The semiconductor structure as claimed in claim 7, characterized in that, The gate dielectric layer is a three-layer structure of silicon oxide-silicon nitride-silicon oxide.

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