Ferroelectric memory and storage device

Abstract

A ferroelectric memory comprises at least one memory cell, each memory cell comprising: a first electrode (1), a second electrode (2), a third electrode (3), a ferroelectric layer (4), and a first semiconductor layer (10), a second semiconductor layer (20) and a third semiconductor layer (30) arranged in a stacked manner; wherein a PN junction is formed between the first semiconductor layer (10) and the second semiconductor layer (20); the first electrode (1) is arranged on a side of the first semiconductor layer (10) away from the second semiconductor layer (20); the third electrode (3) is arranged on a side of the third semiconductor layer (30) away from the second semiconductor layer (20); the ferroelectric layer (4) surrounds all or part of the side of the third semiconductor layer (30); and the second electrode (2) surrounds the ferroelectric layer (4). Thus, when data is subsequently read and written to the memory cell, the influence of the polarization of the ferroelectric layer (4) on the PN junction formed by the first semiconductor layer (10) and the second semiconductor layer (20) can be reduced, thereby facilitating the improvement of the durability of the ferroelectric memory.

Description

Technical Field

[0001] The present application relates to the technical field of data storage, and in particular to a ferroelectric memory and a storage device. Background Art

[0002] At present, dynamic random access memory (DRAM) has become an indispensable main memory for high-performance computing, and the market demand for DRAM capacity is growing exponentially every year. However, DRAM can only achieve 14nm node miniaturization in terms of process. For larger capacity storage requirements, it can only be achieved by stacking multiple DRAM chips, which will cause problems with the area, cost and power consumption of the entire memory. Therefore, ferroelectric random access memory (FRAM) was born. Ferroelectric random access memory can also be called ferroelectric memory. It is a kind of memory made by using the principle that the polarization direction of ferroelectric materials changes under the action of an electric field. It has the advantages of fast read and write speed, low power consumption and small area.

[0003] In the prior art, the storage unit in the ferroelectric memory is usually a ferroelectric field-effect transistor (FeFET) based on a metal-ferroelectrics-insulator-semiconductor (MFIS) structure. However, the ferroelectric memory based on the FeFET structure has defects at the interface between the ferroelectric layer and the insulating layer, which is easy to capture charges, resulting in poor durability of the ferroelectric memory. Summary of the invention

[0004] The present application provides a ferroelectric memory and a storage device, which are used to reduce interface defects in the ferroelectric memory and improve the durability of the ferroelectric memory.

[0005] In order to achieve the above objectives, this application adopts the following technical solutions:

[0006] In a first aspect, a ferroelectric memory is provided, the ferroelectric memory comprising at least one memory cell, each memory cell comprising: a first electrode, a second electrode, a third electrode, a ferroelectric layer, and a first semiconductor layer, a second semiconductor layer and a third semiconductor layer stacked, the semiconductor material of each semiconductor layer may be silicon or silicon germanium, etc.; wherein one of the first semiconductor layer and the second semiconductor layer is an N-type semiconductor and the other is a P-type semiconductor (for example, the first semiconductor layer is an N-type semiconductor and the second semiconductor layer is a P-type semiconductor; or the first semiconductor layer is a P-type semiconductor and the second semiconductor layer is an N-type semiconductor), so that a PN junction is formed between the first semiconductor layer and the second semiconductor layer; and In addition, a first electrode is arranged on a side of the first semiconductor layer away from the second semiconductor layer, and a third electrode is arranged on a side of the third semiconductor layer away from the second semiconductor layer. The electrode materials of the first electrode and the third electrode can be compounds of silicon and metal, such as titanium silicide, zirconium silicide, tantalum silicide and tungsten silicide. The ferroelectric layer surrounds all or part of the side surfaces of the third semiconductor layer. The side surfaces of the third semiconductor layer can refer to surfaces parallel to the depth direction (or axial direction) of the third semiconductor layer, or refer to the surroundings of the third semiconductor layer. The second electrode surrounds the ferroelectric layer. The electrode material of the second electrode can be a metal material, such as aluminum (Al), copper (Cu), tungsten (W) and tungsten nitride (WN).

[0007] In the ferroelectric memory provided by the above technical solution, each memory cell can be equivalent to a memory cell of a metal-ferroelectrics-semiconductor (MFS) structure controlled by the polarization of the ferroelectric layer. There is no interface between the ferroelectric layer and the insulating layer that is easy to capture charges in the memory cell, thereby reducing interface defects and improving the durability of the ferroelectric memory. At the same time, in each memory cell, the ferroelectric layer only surrounds all or part of the side surfaces of the third semiconductor layer, but does not surround the first semiconductor layer and the second semiconductor layer. In this way, when writing data to the memory cell later, the influence of the first electrode on the polarization state of the ferroelectric material can be reduced, thereby reducing the risk of miswriting of the ferroelectric memory.

[0008] In a possible implementation manner of the first aspect, the third semiconductor layer is an intrinsic semiconductor, for example, the third semiconductor layer is intrinsic Si.

[0009] In a possible implementation of the first aspect, when the second semiconductor layer is a P-type semiconductor, the third semiconductor layer is a P-type semiconductor; or, when the second semiconductor layer is an N-type semiconductor, the third semiconductor layer is an N-type semiconductor. In the above possible implementation, when the second semiconductor layer and the third semiconductor layer are both P-type semiconductors or N-type semiconductors, the second semiconductor layer and the third semiconductor layer can be manufactured in one step, thereby simplifying the manufacturing steps of the ferroelectric memory; in addition, the second semiconductor layer and the third semiconductor layer are both P-type semiconductors or N-type semiconductors, which also reduces the contact resistance of the third electrode; at the same time, the carriers originally distributed on the surface of the third semiconductor layer can be distributed in the body of the third semiconductor layer, thereby reducing the interaction between the carriers and the traps in the ferroelectric layer, and improving the durability of the ferroelectric memory.

[0010] In a possible implementation manner of the first aspect, the first electrode is a bottom electrode, the second electrode is a gate electrode, and the third electrode is a top electrode.

[0011] In a possible implementation of the first aspect, the ferroelectric layer is a ferroelectric material or an antiferroelectric material, for example, the ferroelectric material may be hafnium zirconate (HfZrO2), and the antiferroelectric material may be zirconate (ZrO2). In the above possible implementation, when the ferroelectric layer is a ferroelectric material or an antiferroelectric material, by changing the direction of the built-in electric field introduced into the ferroelectric material or the antiferroelectric material, a negative residual polarization state with different polarization strengths can be obtained, and a positive residual polarization state with different polarization strengths can also be obtained, so as to meet different design requirements and improve the design flexibility of the ferroelectric memory; in addition, when the ferroelectric layer is an antiferroelectric material, due to the high stability of the antiferroelectric material, the durability of the ferroelectric memory will be further improved.

[0012] In a possible implementation of the first aspect, when writing data to the storage unit, the absolute value of the voltage difference between the second electrode and the third electrode is set to a first voltage, the first voltage is greater than or equal to a specified voltage, and the specified voltage may refer to a critical voltage for reversing the polarization direction of the ferroelectric layer; when reading data from the storage unit, the voltage difference between the first electrode and the third electrode is set to a second voltage, and the second voltage is less than the specified voltage. In the above possible implementation, by applying different voltages to the first electrode, the second electrode and the third electrode, the storage unit can be read and written, and the reading and writing rate is relatively fast.

[0013] In a possible implementation of the first aspect, the ferroelectric memory includes a memory cell array of m rows and n columns, m first voltage lines, m second voltage lines and n third voltage lines, the memory cell array includes a plurality of memory cells, m and n are positive integers; wherein the first electrodes of the n memory cells belonging to the same row in the memory cell array are connected to one of the m first voltage lines, and the first electrodes of the memory cells in different rows are connected to different first voltage lines, so that the m rows are connected to the m first voltage lines; the second electrodes of the n memory cells belonging to the same row in the memory cell array are connected to one of the m second voltage lines, and the second electrodes of the memory cells in different rows are connected to different second voltage lines, so that the m rows are connected to the m second voltage lines; the third electrodes of the m memory cells belonging to the same column in the memory cell array are connected to one of the n third voltage lines, and the third electrodes of the memory cells in different columns are connected to different third voltage lines, so that the n columns are connected to the n third voltage lines. Optionally, the first voltage line is parallel to the second voltage line, and the third voltage line is perpendicular to both the first voltage line and the second voltage line. In the above possible implementations, the ferroelectric memory can realize a single storage cell area of ​​4F based on the MFS structure through the storage cell array. 2 , compared with the area of ​​8F of a single memory cell based on a capacitor structure in the prior art DRAM 2 In comparison, the area of ​​the ferroelectric memory can be greatly reduced.

[0014] In a possible implementation of the first aspect, the first voltage line is a source line SL, the second voltage line is a word line WL, and the third voltage line is a bit line BL, that is, in a memory cell array, the first electrodes of n memory cells belonging to the same row are connected to the same SL, the second electrodes of n memory cells belonging to the same row are connected to the same WL, and the third electrodes of m memory cells belonging to the same column are connected to the same BL.

[0015] In a possible implementation of the first aspect, when writing data to a memory cell in the memory cell array, the voltage of the first voltage line is set to a first voltage, and the first voltage is greater than or equal to a specified voltage. In the above possible implementation, setting the voltage of the first voltage line to the first voltage can ensure that all memory cells in the memory cell array are in a zero bias or reverse bias state to reduce leakage current when writing data.

[0016] In a possible implementation of the first aspect, when writing data in parallel to n memory cells included in the first row of the memory cell array, the voltage of the second voltage line connected to the n memory cells included in the first row is set to zero or the first voltage, and the voltage of the second voltage line connected to the memory cells included in the remaining rows of m rows except the first row is set to half of the first voltage, and the first row is any row of the m rows, and the first voltage is greater than or equal to the specified voltage. In the above possible implementation, the parallel writing of data to multiple memory cells included in the same row of the memory cell array can be realized, thereby greatly improving the read and write efficiency of the ferroelectric memory.

[0017] In a possible implementation of the first aspect, when writing data in parallel to n memory cells included in the first row of the memory cell array, the voltage of the second voltage line connected to the n memory cells included in the first row is set to zero or four-thirds of the first voltage, and the voltage of the second voltage line connected to the memory cells included in the remaining rows of m rows except the first row is set to two-thirds of the first voltage, and the first row is any row of the m rows, and the first voltage is greater than or equal to the specified voltage. In the above possible implementation, the parallel writing of data to multiple memory cells included in the same row of the memory cell array can be realized, thereby greatly improving the read and write efficiency of the ferroelectric memory.

[0018] In a possible implementation of the first aspect, when reading data from n memory cells included in the first row of the memory cell array, the voltage of the first voltage line connected to the n memory cells included in the first row is set to zero, the voltage of the first voltage line connected to the memory cells included in the remaining rows of m rows except the first row is set to a second voltage, the voltage of the second voltage line is set to zero, and the voltage of the third voltage line is set to a second voltage, and the second voltage is less than a specified voltage. In the above possible implementation, parallel reading of data from multiple memory cells included in the same row of the memory cell array can be realized, thereby greatly improving the read and write efficiency of the ferroelectric memory.

[0019] In a second aspect, a storage device is provided, which includes: a circuit board, and a ferroelectric memory connected to the circuit board, wherein the ferroelectric memory is a ferroelectric memory provided by the first aspect or any possible implementation of the first aspect.

[0020] In a third aspect, a storage device is provided, which includes a controller and a ferroelectric memory, wherein the controller is used to control the reading and writing of the ferroelectric memory, and the ferroelectric memory is a ferroelectric memory provided by the first aspect or any possible implementation of the first aspect.

[0021] In a fourth aspect, a non-transitory computer-readable storage medium is provided for use with a computer, the computer having software for designing integrated circuits, and one or more computer-readable data structures are stored on the computer-readable storage medium, the one or more computer-readable data structures including photomask data for manufacturing the ferroelectric memory provided by the first aspect or any possible implementation of the first aspect.

[0022] It can be understood that any of the storage devices provided above and the non-transitory computer-readable storage medium used with a computer, etc. contain the same or corresponding features of the ferroelectric memory provided above. Therefore, the beneficial effects that can be achieved can be referred to the beneficial effects in the corresponding integrated circuit provided above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of the structure of a storage device provided in an embodiment of the present application;

[0024] Figure 2 A schematic diagram of a ferroelectric memory provided in an embodiment of the present application;

[0025] Figure 3 A schematic diagram of a storage unit provided in an embodiment of the present application;

[0026] Figure 4 A cross-sectional view of a storage unit provided in an embodiment of the present application;

[0027] Figure 5 A cross-sectional view of another storage unit provided in an embodiment of the present application;

[0028] Figure 6 A cross-sectional view of another storage unit provided in an embodiment of the present application;

[0029] Figure 7 A schematic diagram of a read current provided in an embodiment of the present application;

[0030] Figure 8 A schematic diagram of another ferroelectric memory provided in an embodiment of the present application;

[0031] Fig. 9 A schematic diagram of another ferroelectric memory provided in an embodiment of the present application;

[0032] Fig.10 A schematic diagram of a PV curve provided in an embodiment of the present application;

[0033] Fig.11 A schematic diagram of another ferroelectric memory provided in an embodiment of the present application. DETAILED DESCRIPTION

[0034] The following will discuss the making and use of various embodiments in detail. However, it should be understood that many applicable inventive concepts provided by this application can be implemented in a variety of specific environments. The specific embodiments discussed are only illustrative of specific ways to implement and use this description and this technology, and do not limit the scope of this application.

[0035] Unless defined otherwise, all technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art.

[0036] Various circuits or other components may be described or referred to as being "configured to" perform one or more tasks. In this case, "configured to" is used to imply structure by indicating that the circuit / component includes structure (e.g., circuitry) that performs the one or more tasks during operation. Thus, even when the specified circuit / component is not currently operational (e.g., not turned on), the circuit / component may be referred to as being configured to perform the task. Circuits / components used with the phrase "configured to" include hardware, such as circuits that perform an operation, etc.

[0037] The technical scheme in the embodiment of the present application will be described below in conjunction with the accompanying drawings in the embodiment of the present application. In the present application, "at least one" refers to one or more, and "multiple" refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that there may be three relationships, for example, A and / or B, which can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or its similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can represent: a, b, c, a and b, a and c, b and c or a, b and c, where a, b and c can be single or multiple. In addition, in the embodiment of the present application, the words "first", "second" and the like do not limit the quantity and order.

[0038] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0039] The technical solution of the present application can be applied to various storage systems using ferroelectric memory, for example, the technical solution of the present application can be applied to a computer, and can also be applied to a storage system including a memory, or a storage system including a processor and a memory, wherein the processor can be a central processing unit (CPU), an artificial intelligence (AI) processor, a digital signal processor (digital signal processor), a neural network processor, etc. For example, Figure 1 A schematic diagram of a storage system provided in an embodiment of the present application, the storage system may include a ferroelectric memory; optionally, the storage system may also include a CPU, a cache, a controller, etc. The CPU, the cache, the controller, and the ferroelectric memory may be integrated together, and the ferroelectric memory may be coupled to the cache through the controller, and coupled to the CPU through the cache.

[0040] Figure 2 A structural schematic diagram of a ferroelectric memory provided in an embodiment of the present application, the ferroelectric memory includes a memory cell array of m rows and n columns, m first voltage lines, m second voltage lines and n third voltage lines, the memory cell array includes a plurality of memory cells, and m and n are positive integers. Figure 2 In the example, the values ​​of m and n are both equal to 3. In practical applications, the first voltage line can be a source line (SL), the second voltage line can be a word line (WL), and the third voltage line can be a bit line (BL). In the ferroelectric memory, n memory cells belonging to the same row can be connected to one SL among m SLs and one WL among m WLs, and memory cells in different rows can be connected to different SLs and WLs, and m memory cells belonging to the same column can be connected to one BL among m BLs, and memory cells in different columns can be connected to different BLs.

[0041] The following takes a memory cell in the memory cell array of the ferroelectric memory as an example to describe the structure of the memory cell in detail.

[0042] Figure 3 A schematic diagram of the structure of a storage unit provided in an embodiment of the present application is shown in FIG. Figure 3 (a) is a three-dimensional diagram of the storage unit. Figure 3 (b) in Figure 3 The stereogram shown in (a) is a stereogram after being cut vertically downward along the straight line HH'. Figure 3The memory cell includes: a first electrode 1, a second electrode 2, a third electrode 3, a ferroelectric layer 4, and a first semiconductor layer 10, a second semiconductor layer 20 and a third semiconductor layer 30 which are stacked.

[0043] Among them, one of the first semiconductor layer 10 and the second semiconductor layer 20 is an N-type semiconductor and the other is a P-type semiconductor, that is, a PN junction is formed between the first semiconductor layer 10 and the second semiconductor layer 20. For example, the first semiconductor layer 10 is an N-type semiconductor and the second semiconductor layer 20 is a P-type semiconductor; or, the first semiconductor layer 10 is a P-type semiconductor and the second semiconductor layer 20 is an N-type semiconductor. The semiconductor material in the first semiconductor layer 10 and the second semiconductor layer 20 can be silicon (Si) or silicon germanium (SiGe). Figure 3 In the description, an example is given in which the first semiconductor layer 10 is P-type Si and the second semiconductor layer 20 is N-type Si.

[0044] In addition, a first electrode 1 is disposed on a side of the first semiconductor layer 10 away from the second semiconductor layer 20, and the axial margin of the first electrode 1 may be equal to or less than the axial margin of the first semiconductor layer 10. A third electrode 3 is disposed on a side of the third semiconductor layer 30 away from the second semiconductor layer 20, and the axial margin of the third electrode 3 may be equal to or less than the axial margin of the third semiconductor layer 30. The electrode materials of the first electrode 1 and the third electrode 3 here may be compounds of silicon and metal, such as titanium silicide, zirconium silicide, tantalum silicide, and tungsten silicide.

[0045] Furthermore, the ferroelectric layer 4 surrounds all or part of the side surfaces of the third semiconductor layer 30, and the second electrode 2 surrounds the ferroelectric layer 4. Here, the side surfaces of the third semiconductor layer 30 may refer to surfaces parallel to the depth direction (or axial direction) of the third semiconductor layer 30, or may refer to the periphery of the third semiconductor layer 30. The ferroelectric layer 4 may surround all or part of the side surfaces of the third semiconductor layer 30. Figure 3 In the example, the ferroelectric layer 4 surrounds all sides of the third semiconductor layer 30. Figure 4 In the figure, the ferroelectric layer 4 surrounding the partial side of the third semiconductor layer 30 is used as an example for explanation. The ferroelectric layer 4 here can be a ferroelectric material or an antiferroelectric material. For example, the ferroelectric material can be hafnium zirconate (HfZrO2), and the antiferroelectric material can be zirconate (ZrO2). A film formed by a ferroelectric material can be called a ferroelectric film, and a film formed by an antiferroelectric material can be called an antiferroelectric film. In this application, the ferroelectric film and the antiferroelectric film can be collectively referred to as a ferroelectric layer (also referred to as a ferroelectric film). The electrode material of the second electrode 2 here can be a metal material, such as aluminum (Al), copper (Cu), tungsten (W) and tungsten nitride (WN).

[0046] In the ferroelectric memory provided by the embodiment of the present application, each memory cell can be equivalent to a memory cell of a metal-ferroelectric-semiconductor (MFS) structure controlled by the polarization of the ferroelectric layer 4. There is no interface between the ferroelectric layer and the insulating layer that is easy to capture charge in the memory cell, thereby reducing interface defects and improving the durability of the ferroelectric memory. At the same time, in each memory cell, the ferroelectric layer 4 only surrounds all or part of the side surfaces of the third semiconductor layer 30, but does not surround the first semiconductor layer 10 and the second semiconductor layer 20, so that when writing data to the memory cell later, the influence of the first electrode 1 on the polarization state of the ferroelectric material can be reduced, thereby reducing the risk of miswriting of the ferroelectric memory. In addition, when the ferroelectric layer 4 is a ferroelectric material or an antiferroelectric material, by changing the direction of the built-in electric field introduced into the ferroelectric material or the antiferroelectric material, a negative remanent polarization state with different polarization strengths can be obtained, and a positive remanent polarization state with different polarization strengths can also be obtained, so as to meet different design requirements and improve the design flexibility of the ferroelectric memory.

[0047] Optionally, the first semiconductor layer 10, the second semiconductor layer 20 and the third semiconductor layer 30 can be columnar, and the cross-section of the column can be any closed figure such as a circle, an ellipse or a polygon. For example, the polygon can be a triangle, a quadrilateral, a pentagon, a hexagon, etc., and the embodiment of the present application does not impose any specific restrictions on this. Figure 3 The columnar cross section is circular as an example for explanation.

[0048] In one embodiment, the third semiconductor layer 30 is an intrinsic semiconductor, for example Figure 3 As shown, the third semiconductor layer 30 is intrinsic Si. In another embodiment, when the second semiconductor layer 20 is a P-type semiconductor, the third semiconductor layer 30 is a P-type semiconductor, for example, the second semiconductor layer 20 and the third semiconductor layer 30 are both P-type Si; or, when the second semiconductor layer 20 is an N-type semiconductor, the third semiconductor layer 30 is an N-type semiconductor, for example, the second semiconductor layer 20 and the third semiconductor layer 30 are both N-type Si. When the second semiconductor layer 20 and the third semiconductor layer 30 are both P-type semiconductors or N-type semiconductors, the production of the second semiconductor layer 20 and the third semiconductor layer 30 can be achieved in one step, thereby simplifying the production steps of the ferroelectric memory. In addition, the second semiconductor layer 20 and the third semiconductor layer 30 are both P-type semiconductors or N-type semiconductors, which can also reduce the contact resistance of the third electrode 3; at the same time, the carriers originally distributed on the surface of the third semiconductor layer 30 can be distributed in the body of the third semiconductor layer 30, thereby reducing the interaction between the carriers and the traps in the ferroelectric layer 4, and improving the durability of the ferroelectric memory. For example, Figure 4In the description, an example is given in which the first semiconductor layer 10 is P-type Si, and the second semiconductor layer 20 and the third semiconductor layer 30 are both N-type Si. Figure 4 (a) is a three-dimensional diagram of the storage unit. Figure 4 (b) in Figure 4 The stereoscopic image shown in (a) is a stereoscopic image after being cut vertically downward along the straight line HH'.

[0049] In practical applications, the first electrode 1 may be a bottom electrode, the second electrode 2 may be a gate electrode, and the third electrode 3 may be a top electrode. By applying different voltages to the first electrode 1, the second electrode 2, and the third electrode 3, the storage unit can be read and written, that is, data can be written to or read from the storage unit. The voltages applied to the first electrode 1, the second electrode 2, and the third electrode 3 may be controlled by a controller.

[0050] like Figure 5 As shown, when writing data to the memory cell, a voltage can be applied between the second electrode 2 and the third electrode 3 to set the absolute value of the voltage difference between the second electrode 2 and the third electrode 3 (i.e., the absolute value of the difference between the two) to the first voltage V W , the first voltage V W Greater than or equal to a specified voltage, where the specified voltage may refer to a critical voltage that causes the polarization direction of the ferroelectric layer 4 to be reversed. Figure 5 for Figure 3 The memory cell shown in (a) is a cross-sectional view after being cut vertically downward along the straight line HH'.

[0051] Specifically, Figure 5 As shown in (a), when writing data "0" to the storage unit, the first electrode 1 and the third electrode 3 can be grounded, and a negative bias voltage -V can be applied to the second electrode 2. W , so that the voltage difference obtained by subtracting the voltage of the second electrode 2 from the voltage of the third electrode 3 is the first voltage V W At this time, the ferroelectric layer 4 is negatively polarized, a large amount of positive charges appear on the surface of the third semiconductor layer 30, and the contact barrier between the third semiconductor layer 30 and the ferroelectric layer 4 is reduced, so that the memory cell is written into a low resistance state, that is, the data "0" is written. Figure 5 As shown in (b), when writing data "1" to the storage unit, the first electrode 1 and the third electrode 3 can be grounded, and a positive bias voltage V can be applied to the second electrode 2. W , so that the voltage difference obtained by subtracting the voltage of the third electrode 3 from the voltage of the second electrode 2 is the first voltage V W At this time, the ferroelectric layer 4 is positively polarized, a large amount of negative charges appear on the surface of the third semiconductor layer 30, and the contact barrier between the third semiconductor layer 30 and the ferroelectric layer 4 increases, so that the storage unit is written to a high-resistance state, that is, data "1" is written. Figure 5 P in ferroelectric layer 4 represents the polarization direction.

[0052] It should be noted that in the embodiment of the present application, data "0" corresponds to a low-resistance state and data "1" corresponds to a high-resistance state. In actual applications, data "0" may also correspond to a high-resistance state and data "1" may correspond to a low-resistance state. The embodiment of the present application does not impose any restrictions on this.

[0053] like Figure 6 As shown, when reading data from the memory cell, a voltage may be applied between the first electrode 1 and the third electrode 3 to set the voltage difference between the first electrode 1 and the third electrode 3 to the second voltage V R , the second voltage V R Less than a specified voltage, where the specified voltage may refer to a critical voltage that causes the polarization direction of the ferroelectric layer 4 to be reversed. Figure 6 for Figure 3 The memory cell shown in (a) is a cross-sectional view after being cut vertically downward along the straight line HH'.

[0054] Specifically, when reading data from the storage unit, a second voltage V may be applied between the first electrode 1 and the third electrode 3. R , and read the current I of the third electrode 3 R ;like Figure 6 As shown in (a) in the figure, when the I R When the value of is greater than the threshold, it can be determined that the data in the storage unit is "0" (at this time, I R Marked as I R_0 ), this is because when the storage cell is written with data "0", the storage cell is in a low resistance state, so the read current is larger than the current when the data "1" is written; Figure 6 As shown in (b) in the figure, when the I R When the value of is less than the above threshold, it can be determined that the data in the storage unit is "1" (at this time, I R Marked as I R_1 ), this is because when the data "1" is written into the memory cell, the memory cell is in a high-resistance state, so the read current is smaller than the current when the data "0" is written. Figure 7 The current I read when writing data "0" and writing data "1" in the memory cell is shown in FIG. R A possible schematic diagram, specifically when the second voltage V R When the current is approximately in the range of [-2V, 0.4V], the current I R With the second voltage V R When the second voltage V R When the current is approximately in the range of [0.4V, 2V], the current I RWith the second voltage V R Increase with the increase of. Figure 7 When the second voltage V R When the value is about 1V, the data "0" corresponds to the read current I R_0 The value is approximately 10 -5 A, data "1" corresponds to the read current I R_1 The value is approximately 10 -12 A.

[0055] Further, in combination with the above description of the storage unit, the above Figure 2 The connection relationship between the memory cell array in the ferroelectric memory shown and the m first voltage lines, the m second voltage lines and the n third voltage lines is specifically described as follows.

[0056] Among them, the first electrodes 1 of n memory cells belonging to the same row in the memory cell array are connected to the same first voltage line, and the first electrodes 1 of memory cells in different rows are connected to different first voltage lines, so that m rows are connected to m first voltage lines correspondingly. The second electrodes of n memory cells belonging to the same row in the memory cell array are connected to the same second voltage line, and the second electrodes 2 of memory cells in different rows are connected to different second voltage lines, so that m rows are connected to m second voltage lines correspondingly. The third electrodes 3 of m memory cells belonging to the same column in the memory cell array are connected to the same third voltage line, and the third electrodes 3 of memory cells in different columns are connected to different third voltage lines, so that n columns are connected to n third voltage lines correspondingly. Optionally, the first voltage line is parallel to the second voltage line, and the third voltage line is perpendicular to both the first voltage line and the second voltage line. The above-mentioned ferroelectric memory can realize a single memory cell area of ​​4F based on the MFS structure through the memory cell array. 2 (feature size) is 8F, which is comparable to the area of ​​a single memory cell based on a capacitor structure in the prior art DRAM. 2 In comparison, the area of ​​the ferroelectric memory can be greatly reduced.

[0057] In practical applications, the first voltage line may be a source line (SL), the second voltage line may be a word line (WL), and the third voltage line may be a bit line (BL), that is, in a memory cell array, the first electrodes 1 of n memory cells belonging to the same row are connected to the same SL, the second electrodes 2 of the n memory cells belonging to the same row are connected to the same WL, and the third electrodes 3 of the m memory cells belonging to the same column are connected to the same BL.

[0058] for Figure 2The ferroelectric memory shown can realize reading and writing of the storage cells in the ferroelectric memory, that is, writing data to or reading data from the storage cells in the ferroelectric memory, by applying different voltages to m first voltage lines, m second voltage lines and n third voltage lines. The voltages applied to the m first voltage lines, m second voltage lines and n third voltage lines can be controlled by a controller. The following is explained by taking the first voltage line as SL, the second voltage line as WL, and the third voltage line as BL as an example, and the first voltage in the following text is greater than or equal to the specified voltage, and the second voltage is less than the specified voltage. The specified voltage here can refer to the critical voltage that reverses the polarization direction of the ferroelectric layer 4, and the first row in the memory cell array can refer to any row among the m rows. Figure 8 , Fig. 9 and Fig.11 The row with the five-pointed star indicates the first row.

[0059] Specifically, Figure 8 As shown, when writing data to a memory cell in the memory cell array, the voltages of the m SLs can be set to the first voltage V W , the first voltage V W The voltage is greater than or equal to the specified voltage, so that all the memory cells in the memory cell array are in a zero bias or reverse bias state to reduce the leakage current when writing data. At the same time, the writing of data "0" and "1" is realized by setting the voltage difference between the WL and BL connected to the memory cell in the memory cell array. For example, when the voltage difference between the WL and BL connected to a certain memory cell is set to a negative first voltage -V W , the memory cell is written as data "0"; when the voltage difference between WL and BL connected to a certain memory cell is set to the positive first voltage V W When the voltage difference between WL and BL connected to a certain storage cell is set to half of the first voltage 1 / 2V W , the state of the storage unit remains unchanged.

[0060] Or, if Figure 8 As shown, when writing data to the n memory cells in the first row of the memory cell array in parallel, the voltage of the WL connected to the n memory cells in the first row can be set to zero or the first voltage V W When the voltage of the WL corresponding to the first row is set to zero, if the voltage of a certain BL is set to zero, the storage unit connected to the BL is written as data "1". If the voltage of a certain BL is set to the first voltage V W , the state of the memory cell connected to the BL remains unchanged. When the voltage of the WL corresponding to the first row is set to the first voltage V WWhen the voltage of a BL is set to the first voltage V W , the memory cell connected to the BL is written as data "0", and if the voltage of a certain BL is set to zero, the state of the memory cell connected to the BL remains unchanged. In addition, the voltage of the WL connected to the memory cells included in the remaining rows of the m rows of the memory cell array except the first row can be set to half of the first voltage 1 / 2V W , that is, the unselected WL is connected to 1 / 2V W , so that the operating voltage of the unselected memory cell is 0, 1 / 2V W or -1 / 2V W . Figure 8 The described method of writing data may be referred to as the V / 2 method.

[0061] Or, if Fig. 9 As shown, when writing data to the n memory cells in the first row of the memory cell array in parallel, the voltage of the WL connected to the n memory cells in the first row can be set to zero or one-fourth of the first voltage 4 / 3V. W When the voltage of WL corresponding to the first row is set to 4 / 3V W When the voltage of a BL is set to one third of the first voltage 1 / 3V W , then the storage unit connected to the BL is written as data "1". If the voltage of a BL is set to the first voltage V W , the state of the storage unit connected to the BL remains unchanged. When the voltage of the WL corresponding to the first row is set to zero, if the voltage of a BL is set to the first voltage V W , then the storage unit connected to the BL is written as data "1", if the voltage of a BL is set to one-third of the first voltage 1 / 3V W , the state of the memory cell connected to the BL remains unchanged. In addition, the voltage of the WL connected to the memory cells included in the remaining rows of the m rows of the memory cell array except the first row can be set to two-thirds of the first voltage 2 / 3V W , that is, the unselected WL is connected to 2 / 3V W , so that the operating voltage of the unselected memory cell is 1 / 3V W or -1 / 3V W . Fig. 9 The described method of writing data may be referred to as the V / 3 method.

[0062] Similarly, according to the above Figure 8 or Fig. 9 The method for writing data described above can also be used to write data to m storage cells in a column of the storage cell array in parallel. The specific process is the same as that described above. Figure 8 or Fig. 9 The process is similar to that of the present application and will not be described in detail herein.

[0063] In the above-mentioned different data writing methods, when the ferroelectric layer 4 in the storage unit is a ferroelectric material, the relationship between the polarization intensity P of the ferroelectric layer 4 and the applied voltage V is as follows: Fig.10 As shown in (a) and (b) in FIG. 1 , the selected storage cell is at a negative first voltage -V W The data "0" is written into the selected memory cell when the external voltage is the positive first voltage V W When the ferroelectric layer 4 in the memory cell is an antiferroelectric material, the relationship between the polarization intensity P of the ferroelectric layer 4 and the applied voltage V is as follows: Fig.10 As shown in (c) and (d) in FIG. 1 , the selected storage cell is at a positive first voltage V when the external voltage V is applied. W The data "0" is written into the selected memory cell when the external voltage is a negative first voltage -V W When the selected memory cell is written with data “0”, the unselected memory cell retains the original data “0” or “1”. Fig.10 The external voltage V in may refer to the voltage applied between the second electrode 2 and the third electrode 3 .

[0064] Specifically, Fig.11 As shown, when data is read from the n memory cells included in the first row of the memory cell array, the voltage of the SL connected to the n memory cells included in the first row can be set to zero, and the voltage of the SL connected to the memory cells included in the remaining rows of the m rows of the memory cell array except the first row can be set to the second voltage V R , the voltages of all WLs are set to zero, and the voltages of all BLs are set to the second voltage V R At this time, the voltage difference between the first electrode 1 and the third electrode 3 of the n memory cells in the first row is set to V R , so that the current corresponding to the read data "0" or "1" is generated, and the voltage difference between the first electrode 1 and the third electrode 3 of the memory cells included in the remaining rows other than the first row is set to zero, so that no leakage current is generated.

[0065] In the above method for reading and writing the memory cells in the memory cell array, Figures 8 to 11 The described reading and writing method can realize parallel reading and writing of the same WL or the same BL in the memory cell array, that is, writing or reading data in parallel to multiple memory cells in the same row or column, thereby greatly improving the reading and writing efficiency of the ferroelectric memory.

[0066] Based on this, an embodiment of the present application also provides a storage device, which includes a circuit board and a ferroelectric memory connected to the circuit board, and the ferroelectric memory can be any of the ferroelectric memories provided above. Among them, the circuit board can be a printed circuit board (PCB), and of course the circuit board can also be a flexible circuit board (FPC), etc. This embodiment does not limit the circuit board. Optionally, the storage device is a different type of user equipment or terminal equipment such as a computer, a mobile phone, a tablet computer, a wearable device, and a vehicle-mounted device; the storage device can also be a network device such as a base station.

[0067] Optionally, the storage device further includes a packaging substrate, wherein the packaging substrate is fixed on a printed circuit board PCB via solder balls, and the ferroelectric memory is fixed on the packaging substrate via solder balls.

[0068] Based on this, an embodiment of the present application further provides a storage device, which includes a controller and a ferroelectric memory. The controller is used to control reading and writing in the ferroelectric memory. The ferroelectric memory can be any of the ferroelectric memories provided above.

[0069] It should be noted that for the relevant description of the three-dimensional ferroelectric memory, please refer to the above Figure 2-Figure 11 The description of ferroelectric memory in the embodiments of the present application will not be repeated here.

[0070] In another aspect of the present application, a non-transitory computer-readable storage medium is provided for use with a computer having software for designing integrated circuits, and one or more computer-readable data structures are stored on the computer-readable storage medium, wherein the one or more computer-readable data structures include photomask data for manufacturing any one of the ferroelectric memories provided above.

[0071] Finally, it should be noted that the above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A ferroelectric memory, characterized in that: The ferroelectric memory comprises at least one memory cell, each of which comprises: a first electrode, a second electrode, a third electrode, a ferroelectric layer, and a first semiconductor layer, a second semiconductor layer and a third semiconductor layer which are stacked; Among them, one of the first semiconductor layer and the second semiconductor layer is an N-type semiconductor, and the other is a P-type semiconductor, the first electrode is arranged on a side of the first semiconductor layer away from the second semiconductor layer, the third electrode is arranged on a side of the third semiconductor layer away from the second semiconductor layer, the ferroelectric layer surrounds all or part of the side surfaces of the third semiconductor layer, and the second electrode surrounds the ferroelectric layer.

2. The ferroelectric memory according to claim 1, characterized in that: The third semiconductor layer is an intrinsic semiconductor.

3. The ferroelectric memory according to claim 1, wherein: When the second semiconductor layer is a P-type semiconductor, the third semiconductor layer is a P-type semiconductor; or when the second semiconductor layer is an N-type semiconductor, the third semiconductor layer is an N-type semiconductor.

4. The ferroelectric memory according to claim 1, wherein: The first electrode is a bottom electrode, the second electrode is a gate electrode, and the third electrode is a top electrode.

5. The ferroelectric memory according to claim 1, characterized in that: The ferroelectric layer is a ferroelectric material or an antiferroelectric material.

6. The ferroelectric memory according to any one of claims 1 to 5, characterized in that: When writing data to the memory cell, the absolute value of the voltage difference between the second electrode and the third electrode is set to a first voltage, and the first voltage is greater than or equal to a specified voltage; When data is read from the memory cell, the voltage difference between the first electrode and the third electrode is set to a second voltage that is lower than the designated voltage.

7. The ferroelectric memory according to claim 1, characterized in that: The ferroelectric memory comprises a memory cell array of m rows and n columns, m source lines SL, m word lines WL and n bit lines BL, the memory cell array comprises a plurality of the memory cells, and m and n are positive integers; Among them, the first electrodes of the n memory cells belonging to the same row in the memory cell array are connected to one SL among the m SLs, the second electrodes of the n memory cells belonging to the same row in the memory cell array are connected to one WL among the m WLs, and the third electrodes of the m memory cells belonging to the same column in the memory cell array are connected to one BL among the n BLs.

8. The ferroelectric memory according to claim 7, characterized in that: The m SLs are parallel to the m WLs, and the n BLs are perpendicular to both the m SLs and the m WLs.

9. The ferroelectric memory according to claim 7, characterized in that: When writing data to a memory cell in the memory cell array, the voltage of the m SLs is set to a first voltage that is greater than or equal to a specified voltage.

10. The ferroelectric memory according to claim 7, characterized in that: When data are written in parallel to n memory cells included in the first row in the memory cell array, the voltage of the WL connected to the n memory cells included in the first row is set to zero or a first voltage, the voltage of the WL connected to the memory cells included in the remaining rows of the m rows except the first row is set to half of the first voltage, and the first row is any row of the m rows, and the first voltage is greater than or equal to a specified voltage.

11. The ferroelectric memory according to claim 7, characterized in that: When data are written in parallel to n memory cells included in the first row in the memory cell array, the voltage of the WL connected to the n memory cells included in the first row is set to zero or four-thirds of the first voltage, the voltage of the WL connected to the memory cells included in the remaining rows of the m rows except the first row is set to two-thirds of the first voltage, the first row is any row of the m rows, and the first voltage is greater than or equal to the specified voltage.

12. The ferroelectric memory according to any one of claims 7 to 11, characterized in that: When reading data to the n memory cells included in the first row in the memory cell array, the voltage of the SL connected to the n memory cells included in the first row is set to zero, the voltage of the SL connected to the memory cells included in the remaining rows of the m rows except the first row is set to a second voltage, the voltage of the WL is set to zero, and the voltage of the BL is set to the second voltage, and the second voltage is less than a specified voltage.

13. A storage device, characterized in that: The storage device comprises: a circuit board, and a ferroelectric memory connected to the circuit board, and the ferroelectric memory is the ferroelectric memory according to any one of claims 1-12.

14. A storage device, characterized in that: The storage device comprises a controller and a ferroelectric memory, wherein the controller is used to control the reading and writing of the ferroelectric memory, and the ferroelectric memory is the ferroelectric memory according to any one of claims 1 to 12.

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