Semiconductor device and method for manufacturing the same, and power conversion device

Abstract

In a semiconductor device (1), a first structure (5) having a first concavo-convex portion (6) and a second structure (7) having a second concavo-convex portion (8) covering the first structure (5) are formed in a bonding region (20) defined in a semiconductor substrate (3). A metal wiring (13) is bonded to the second concavo-convex portion (8) in the second structure (7). The depth of the concave portion in the second concavo-convex portion (8) is shallower than the depth of the concave portion in the first concavo-convex portion (6). An insulating member (11) defining the bonding region (20) is formed so as to reach the semiconductor substrate (3).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, a method for manufacturing the same, and a power conversion device. Background Art

[0002] In recent years, there is a demand for high current density in semiconductor devices for power. In order to achieve high current density, a semiconductor device that can withstand driving under high temperature conditions is required. In such a semiconductor device, it is recommended to use copper wiring (conducting wire) as a metal wiring connecting the semiconductor device to an external terminal.

[0003] Generally, in order to bond a metal wire having a diameter of about 100 μm to a semiconductor device, there is a method of bonding the metal wire by applying ultrasonic vibration energy to the metal wire. In this method, the energy of the ultrasonic wave when bonding a copper wire as the metal wire needs to be greater than the energy of the ultrasonic wave when bonding an aluminum wire.

[0004] Therefore, when bonding copper wires, a large load (energy load) acts on the semiconductor substrate itself on which semiconductor elements and the like are formed, and various measures have been taken in the semiconductor device to reduce the load (Patent Documents 1 and 2).

[0005] Patent Document 1: Japanese Patent Application Publication No. 2016-115700

[0006] Patent Document 2: Japanese Patent Application Laid-Open No. 02-025045 Summary of the invention

[0007] Problem that the invention aims to solve

[0008] In a semiconductor device, when bonding metal wiring including a copper wire, it is required to achieve good bonding while reducing the load acting on a semiconductor substrate and the like.

[0009] The present disclosure was completed under such development, one purpose of which is to provide a semiconductor device that reduces the load on a base including a semiconductor substrate during bonding of metal wiring, another purpose is to provide a method for manufacturing such a semiconductor device, and yet another purpose is to provide a power conversion device using such a semiconductor device.

[0010] Solutions for solving problems

[0011] The semiconductor device disclosed in the present invention comprises a semiconductor substrate, a bonding region, a first structure, a second structure and a metal wiring. A semiconductor element is formed on the semiconductor substrate. The bonding region is defined on the semiconductor substrate. The first structure has a first concave-convex portion formed in the bonding region. The second structure has a second concave-convex portion formed in a manner covering the first structure. The metal wiring is bonded to the second concave-convex portion in the second structure. The depth of the concave in the second concave-convex portion is shallower than the depth of the concave in the first concave-convex portion.

[0012] The manufacturing method of the semiconductor device involved in the present disclosure includes the following steps. A semiconductor element is formed on the main surface of a semiconductor substrate. A first structure having a first concave-convex portion is formed on the main surface of the semiconductor substrate. A second structure having a second concave-convex portion is formed in a manner covering the first structure. An insulating member is formed in a manner surrounding at least the first structure and the second structure, thereby defining a bonding area. A metal wiring is joined to the second structure in the bonding area. In the step of forming the first structure and the step of forming the second structure, the first structure and the second structure are formed in a manner such that the depth of the recess in the second concave-convex portion is shallower than the depth of the recess in the first concave-convex portion.

[0013] The power conversion device according to the present disclosure includes: a main conversion circuit having the above-mentioned semiconductor device and converting input power and outputting the converted power; and a control circuit outputting a control signal for controlling the main conversion circuit to the main conversion circuit.

[0014] Effects of the Invention

[0015] According to the semiconductor device involved in the present disclosure, a second structure having a second concave-convex portion is formed in a bonding region in a manner covering a first structure having a first concave-convex portion. The depth of the depression in the second concave-convex portion is shallower than the depth of the depression in the first concave-convex portion, and the metal wiring is bonded to the second concave-convex portion of the second structure. As a result, the load on the substrate when the metal wiring is bonded to the bonding region is reduced, and good bonding between the metal wiring and the bonding region is obtained.

[0016] According to the manufacturing method of the semiconductor device involved in the present disclosure, a first structure having a first concave-convex portion and a second structure having a second concave-convex portion are sequentially formed in a manner that the depth of the concave in the second concave-convex portion is shallower than the depth of the concave in the first concave-convex portion, and a bonding area is defined by an insulating member. The metal wiring is bonded to the second structure in the bonding area. As a result, the load on the substrate when the metal wiring is bonded to the bonding area is reduced, and the metal wiring can be well bonded to the bonding area.

[0017] According to the power conversion device according to the present disclosure, the main conversion circuit includes the semiconductor device described above and converts input power and outputs the converted power. This can improve the reliability of the power conversion device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a plan view showing a bonding region in the semiconductor device according to the first embodiment.

[0019] Figure 2 In this embodiment Figure 1 A cross-sectional view of the semiconductor device taken along the cross-sectional line II-II is shown.

[0020] Figure 3 It is a cross-sectional view showing one step of the method for manufacturing the semiconductor device in this embodiment.

[0021] Figure 4 This means that in this embodiment Figure 3 A cross-sectional view of a process performed after the process shown.

[0022] Figure 5 This means that in this embodiment Figure 4 A cross-sectional view of a process performed after the process shown.

[0023] Figure 6 This means that in this embodiment Figure 5 A cross-sectional view of a process performed after the process shown.

[0024] Figure 7 This means that in this embodiment Figure 6 A cross-sectional view of a process performed after the process shown.

[0025] Figure 8 This means that in this embodiment Figure 7 A cross-sectional view of a process performed after the process shown.

[0026] Fig. 9 This means that in this embodiment Figure 8 A cross-sectional view of a process performed after the process shown.

[0027] Fig.10 This means that in this embodiment Fig. 9 A cross-sectional view of a process performed after the process shown.

[0028] Fig.11 It is a cross-sectional view showing one step of a method for manufacturing a semiconductor device according to a first modification of the embodiment.

[0029] Fig.12 This means that in this embodiment Fig.11 A cross-sectional view of a process performed after the process shown.

[0030] Fig.13 This means that in this embodiment Fig.12 A cross-sectional view of a process performed after the process shown.

[0031] Fig.14 This means that in this embodiment Fig.13 A cross-sectional view of a process performed after the process shown.

[0032] Fig.15 This means that in this embodiment Fig.14 A cross-sectional view of a process performed after the process shown.

[0033] Fig.16 It is a first plan view showing a bonding region in a semiconductor device according to a second modification of the embodiment.

[0034] Fig.17 This is a second plan view showing a bonding region in the semiconductor device according to the second modification of the embodiment.

[0035] Fig.18 This is a third plan view showing a bonding region in the semiconductor device according to the second modification of the embodiment.

[0036] Fig.19 It is a cross-sectional view of a semiconductor device according to a third modified example of this embodiment.

[0037] Fig. 20 This is a cross-sectional view of a semiconductor device according to the second embodiment.

[0038] Fig.21 It is a cross-sectional view showing one step of the method for manufacturing the semiconductor device in this embodiment.

[0039] Fig. 22 This means that in this embodiment Fig.21 A cross-sectional view of a process performed after the process shown.

[0040] Fig.23 This means that in this embodiment Fig. 22 A cross-sectional view of a process performed after the process shown.

[0041] Fig.24 This means that in this embodiment Fig.23 A cross-sectional view of a process performed after the process shown.

[0042] Fig.25 This means that in this embodiment Fig.24A cross-sectional view of a process performed after the process shown.

[0043] Fig.26 This is a cross-sectional view of a semiconductor device according to a first example of the third embodiment.

[0044] Fig. 27 It is a cross-sectional view of a semiconductor device according to a second example of this embodiment.

[0045] Fig.28 This is a cross-sectional view of a semiconductor device according to a first example of the fourth embodiment.

[0046] Fig.29 It is a cross-sectional view of a semiconductor device according to a second example of this embodiment.

[0047] Fig.30 This is a block diagram of a power conversion device according to the fifth embodiment.

[0048] (Explanation of Reference Numerals)

[0049] 1: semiconductor device; 2: semiconductor element; 3: semiconductor substrate; 5, 5a, 5b: first structure; 6: first concavo-convex portion; 7, 7a, 7b: second structure; 8: second concavo-convex portion; 9, 9a, 9b: intermediate structure; 11: insulating member; 13, 13a, 13b: metal wiring; 20: bonding area; 21: first area; 23: second area; 25: one area; 51, 52, 53, 54: anti-etching agent; 55, 77: metal layer; 100: power supply; 200: power conversion device; 201: main conversion circuit; 202: semiconductor device; 203: control circuit; 300: load. DETAILED DESCRIPTION

[0050] Implementation method 1.

[0051] The semiconductor device according to Embodiment 1 is described. Figure 1 and Figure 2 As shown, in the semiconductor device 1, a bonding region 20 for bonding a metal wiring 13 is defined on one main surface of a semiconductor substrate 3 (semiconductor device) on which a semiconductor element 2 is formed. As the metal wiring 13, for example, a copper wiring (conducting wire) is connected.

[0052] As the semiconductor element 2, for example, an insulated gate bipolar transistor (IGBT: Insulated Gate Bipolar Transistor) or a field effect transistor (MOSFET: Metal Oxide Semiconductor Field Effect Transistor) is formed. As the semiconductor substrate 3, for example, a Si substrate or a SiC substrate is applied. As the semiconductor element 2, semiconductor elements other than IGBT and MOSFET can also be formed. As the semiconductor substrate 3, a GaN substrate can also be applied. The thickness of the chip as the semiconductor device 1 is set to about 50μm to 500μm, for example.

[0053] An electrode may also be formed on the other main surface (not shown) of the semiconductor substrate 3. As the material of the electrode, gold (Au), copper (Cu) or nickel (Ni) may be used, for example. A bonding layer, a barrier layer or an anti-oxidation layer may also be formed between the other main surface of the semiconductor substrate 3 and the electrode. As the material of the bonding layer, for example, gold (Au), titanium (Ti), titanium nitride (TiN) or tungsten (W) may be used. In addition, the electrode may also be a stacked structure of more than two layers. The thickness of the electrode is, for example, set to about 5 nm to 50 μm. For example, the electrode is formed by plating or sputtering.

[0054] The bonding region 20 is defined by the insulating member 11. A first region 21 and a second region 23 are defined in the bonding region 20. The first region 21 and the second region 23 are separated by the insulating member 11. The area of ​​the first region 21 is set larger than the area of ​​the second region 23. In addition, there is no particular limitation on the configuration structure, material, and shape of the insulating member 11 as long as the function as the semiconductor device is not impaired.

[0055] In the first region 21, a first structure 5a(5) having a first concavo-convex portion 6 and a second structure 7a(7) having a second concavo-convex portion 8 are formed. The second structure 7a(7) is formed so as to cover the first structure 5a(5). In the second region 23, a first structure 5b(5) having a first concavo-convex portion 6 and a second structure 7b(7) having a second concavo-convex portion 8 are formed. The second structure 7b(7) is formed so as to cover the first structure 5b(5).

[0056] The first structure 5 having the first concavo-convex portion 6 is arranged on the main surface of one side of the semiconductor substrate 3 in a manner such that a plurality of convex portions are separated from each other, for example, in an island shape. The first structure 5 may also be formed directly on the main surface of the semiconductor substrate 3. In addition, a layer for achieving adhesion or a layer for achieving electrical connection may be interposed between the first structure 5 and the main surface of the semiconductor substrate 3. As the material of such a layer, for example, titanium (Ti), tungsten (W), nickel (Ni) or an alloy mainly containing these metals is applied. In addition, as long as it is a material that can achieve adhesion or electrical connectivity, it is not limited to these materials.

[0057] The material of the first structure 5 may be, for example, metals such as aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), silicon (Si), or an oxide film, but is not limited to these materials as long as the function of the semiconductor device 1 is not impaired.

[0058] As an example, the first concavoconvex part 6 of the first structure 5 is formed in a dot-shaped convex part. The length (width) of one side of the convex part of the first concavoconvex part 6 is, for example, about 1 μm to 10 μm. The height of the convex part is, for example, about 0.5 μm to 5 μm. The distance between adjacent convex parts is, for example, about 0.5 μm to 5 μm.

[0059] The second structure 7 having the second concavoconvex portion 8 is formed by a metal layer 77. The second concavoconvex portion 8 is formed by forming the metal layer 77 so as to cover the first concavoconvex portion 6 of the first structure 5, for example, by reflecting the first concavoconvex portion 6 of the base in the metal layer 77. Therefore, the second concavoconvex portion 8 is also formed in a dot shape.

[0060] As the material of the second structure 7 (metal layer 77), for example, aluminum (Al), copper (Cu), nickel (Ni), cobalt (Co), chromium (Cr), etc. are applied. In addition, as the hardness of the second structure 7 (metal layer 77), the Vickers hardness is preferably 300 or more when measured by a Vickers hardness meter. If the Vickers hardness is 300 or more, it is possible to achieve good bonding while reducing the load acting during wire bonding. In addition, as long as the function of the semiconductor device 1 is not impaired, the material of the metal layer 77 is not limited to the above-mentioned materials.

[0061] In addition, an anti-oxidation layer (not shown) may be formed on the surface of the second structure 7 to suppress oxidation of the metal layer 77. As the anti-oxidation layer, gold (Au), silver (Ag), palladium (Pg) or an alloy layer of these metals may be applied. In addition, as the anti-oxidation layer, an organic protective film may also be applied.

[0062] The thickness of the second structure 7 is, for example, about 1 μm to 50 μm. The thickness of the second structure 7 corresponds to the distance between the upper end and the lower end of the second structure 7. The depth D2 of the depression of the second concavoconvex portion 8 of the second structure 7 is shallower than the depth D1 of the depression of the first concavoconvex portion 6 of the first structure 5 (see Figure 7 The depth of the depression of the second concavo-convex part 8 is preferably, for example, 5 μm or less.

[0063] The shape of the second concavoconvex portion 8 of the second structure 7 is different from the surface roughness of the metal layer 77. Relative to the average film thickness of the metal layer 77, the depth of the depression of the first concavoconvex portion 6 and the depth of the depression of the second concavoconvex portion 8 have a value greater than the surface roughness (Ra) of the metal layer 77.

[0064] As the metal wiring 13 bonded to the bonding area 20, for example, copper wiring is preferred. The copper wiring includes pure copper or copper alloy. In addition, as the metal wiring 13, it can also be a copper wiring coated with palladium (Pd), aluminum (Al), gold (Au) or silver (Ag) on ​​the outermost surface of the copper wiring. In addition, as the metal wiring 13, it is not limited to copper wiring, and for example, aluminum wiring can also be applied. In addition, as the metal wiring 13, for example, nickel wiring can also be applied.

[0065] The metal wiring 13 is preferably in the form of a wire. The thickness (φ) of the wire is, for example, about 100 μm to 500 μm. The metal wiring 13 may be in a plate-like shape or a foil-like shape, in addition to the wire.

[0066] For example, a copper wire is ultrasonically bonded to the bonding region 20 as the metal wiring 13. In the second structure 7, the concave region of the second concave-convex portion 8 at the portion to which the metal wiring 13 is bonded enters the portion where the metal wiring 13 is present in a manner of filling the concave region. In addition, as long as the contact area between the copper wire and the bonding region 20 can be ensured while reducing the load acting during wire bonding, the metal wiring 13 may be bonded in a manner that a cavity remains in the concave region of the second concave-convex portion 8.

[0067] The insulating member 11 is formed so as to cover the semiconductor substrate 3 on which the semiconductor element 2 is formed. The insulating member 11 is formed so as to reach the semiconductor substrate 3. The insulating member 11 defines the bonding region 20. In addition, the insulating member 11 defines the first region 21 and the second region 23. The area of ​​the second region 23 is set smaller than the area of ​​the first region 21.

[0068] The insulating member 11 is not particularly limited in shape, material, or form as long as the function as the semiconductor device is not impaired. For example, the insulating member 11 may be formed to reach the semiconductor substrate 3 or the second structural body 7. In addition, the insulating member 11 may be formed to reach the first structural body 5.

[0069] The first concavoconvex portion 6 of the first structure 5a and the second concavoconvex portion 8 of the second structure 7 are located in the first region 21 surrounded by the insulating member 11. The first concavoconvex portion 6 of the first structure 5b and the second concavoconvex portion 8 of the second structure 7 are located in the second region 23 surrounded by the insulating member 11. In addition, the first concavoconvex portion 6 and the second concavoconvex portion 8 may be formed in at least the second region 23 with a narrow area in the first region 21 and the second region 23.

[0070] When the first and second concavoconvex portions 6 and 8 are formed in both the first and second regions 21 and 23 , the first and second concavoconvex portions 6 and 8 may have the same or different shapes in the first and second regions 21 and 23 .

[0071] The convex parts of the first concavoconvex part 6 of the first structure 5 are formed, for example, periodically. The second structure 7 having the second concavoconvex part 8 is formed so as to cover the first structure 5. The second structure 7 may be formed so as to fill the space between the convex parts of the first concavoconvex part 6, or may be formed so as to leave a part of cavity between the convex parts.

[0072] In addition, the second concavoconvex portion 8 of the second structure 7 may be a concavoconvex shape that reflects the concavoconvex shape of the first concavoconvex portion 6 of the first structure 5, or may be a concavoconvex shape that is independent of the concavoconvex shape of the first concavoconvex portion 6 of the first structure 5. The depth of the depression of the second concavoconvex portion 8 of the second structure 7 is shallower than the depth of the depression of the first concavoconvex portion 6 of the first structure 5. The depth of the depression of the second concavoconvex portion 8 is preferably 80% or less of the depth of the depression of the first concavoconvex portion 6. The semiconductor device 1 according to the first embodiment is configured as described above.

[0073] Next, an example of a method for manufacturing the semiconductor device 1 is described. As manufacturing processes, there are generally three processes, namely, a first manufacturing process, a second manufacturing process, and a third manufacturing process. In the first manufacturing process, a first structure 5 having a first concavo-convex portion 6 is formed. In the second manufacturing process, a second structure 7 having a second concavo-convex portion 8 is formed. In the third manufacturing process, metal wiring is bonded.

[0074] First, the first manufacturing process is described. First, the semiconductor element 2 and the like are formed on the semiconductor substrate 3 (see Figure 3). Then, if Figure 3 As shown, a photoresist 51 is applied to cover the main surface of the semiconductor substrate 3 on which the semiconductor element 2 and the like are formed. There are positive resists and negative resists as the photoresist 51. As long as the first concavoconvex portion can be patterned as designed, both the positive resist and the negative resist can be used.

[0075] Next, the photoresist 51 is subjected to a photolithography process. A photomask corresponding to the pattern of the first structure is placed in an exposure device (not shown) and irradiated with ultraviolet light, thereby transferring the pattern of the photomask to the photoresist 51. The photoresist 51 irradiated with ultraviolet light is immersed in a developer to remove the uncured portion of the photoresist. Figure 4 As shown, a pattern of a photoresist 51 for forming a first structure is formed.

[0076] Then, if Figure 5 As shown, a metal layer 55 that becomes the first structure is formed in a manner that covers the pattern of the photoresist 51. As a method for forming the metal layer 55, there is, for example, a sputtering method that is one of the physical vapor deposition methods (PVD). The sputtering method includes a magnetron sputtering method, an evaporation method, an ion beam sputtering method, and the like. As long as the first concave-convex portion 6 can be formed, any sputtering method can be applied. In addition, regarding the conditions when the metal layer 55 is formed by the sputtering method (the type of power supply (DC type, AC type), power, heating, flow rate, auxiliary film formation, etc.), any conditions can be set as long as the first concave-convex portion 6 can be formed.

[0077] In addition to the sputtering method, there is also a plating method, for example. The plating method includes electroless plating and electrolytic plating. As for the type of plating method and the conditions for forming the metal layer 55 by the plating method, any plating method and conditions can be set as long as the first concavo-convex portion 6 can be formed.

[0078] In addition, when electrolytic plating is applied, a seed layer needs to be formed. In addition, a close-fitting film is required as needed. As a method for forming a seed layer and a close-fitting layer, there are, for example, a physical vapor growth method or a chemical vapor growth method (CVD: Chemical Vapor Deposition). As long as the first structure 5 can be formed, any method can be applied. From the perspective of the structure of the semiconductor device 1, etc., a sputtering method is preferably used as a method for forming a seed layer and a close-fitting layer.

[0079] When the first structure 5 is formed using an oxide film, a method for forming the oxide film includes a chemical vapor growth method. For example, a silicon oxide film can be formed using monosilane gas and oxygen.

[0080] Then, if Figure 6 As shown, the pattern of the photoresist 51 is removed. As a method for removing the photoresist 51, there is a wet etching process or a dry etching process. In order to remove the photoresist 51 while maintaining the shape of the first concavo-convex portion 6, it is desirable to selectively remove the photoresist 51 by wet etching. In addition, as an etching liquid, there is no particular limitation as long as it can remove the photoresist 51 while maintaining the shape of the first concavo-convex portion 6. In this way, the first manufacturing process is completed.

[0081] Next, the second manufacturing process is described. Figure 7 As shown, a metal layer 77 is formed in a manner covering the first structure 5. At this time, the thickness of the metal layer 77 is set to a thickness reflecting the shape of the substrate. Since the first structure 5 has a first concavo-convex portion 6, a second concavo-convex portion 8 reflecting the shape of the first concavo-convex portion 6 is formed in the metal layer 77 without additional processing. At this time, the depth D2 of the depression of the second concavo-convex portion 8 of the second structure 7 is formed shallower than the depth D1 of the depression of the first concavo-convex portion 6 of the first structure 5. In addition, the case where the shape of the substrate is not reflected in the metal layer 77, etc., will be described later as a modified example. In this way, the second manufacturing process is completed.

[0082] Next, the third manufacturing process is described. The bonding region 20 is subjected to a process for forming the insulating member 11. Figure 8 As shown in FIG. 1 , by subjecting the metal layer 77 and the like to photolithography and etching, the surface of the semiconductor substrate 3 in the region where the insulating member is to be disposed is exposed. Fig. 9 As shown, the insulating member 11 is formed by chemical vapor deposition, for example, so as to cover the semiconductor substrate 3. Then, a photolithography process is performed to form a pattern of the photoresist 52. The photoresist 52 is formed into a pattern that defines the bonding region 20 and separates the first region 21 from the second region 23.

[0083] Then, if Fig.10 As shown, the insulating member 11 is subjected to dry etching, for example, using the pattern of the photoresist 52 as an etching mask, thereby exposing the second structure 7. Thereafter, the photoresist 52 is removed. In this way, the insulating member 11 defining the bonding region 20 and defining the first region 21 and the second region 23 is patterned.

[0084] Next, the metal wiring 13 (13a, 13b) is bonded to the bonding region 20. The copper wire as the metal wiring 13a is bonded to the second structure 7a (7) in the first region 21 by ultrasonic bonding. Also, the copper wire as the metal wiring 13b is bonded to the second structure 7b (7) in the second region 23 by ultrasonic bonding. Figure 2As shown, the copper wire metal wiring 13a is bonded to the second structure 7a in the first region 21, and the copper wire metal wiring 13b is bonded to the second structure 7b in the second region 23. In this way, the third manufacturing step is completed, and the main part of the semiconductor device 1 is completed.

[0085] In the semiconductor device 1 described above, the copper wire as the metal wiring 13 is bonded to the second structure 7 having the second concavo-convex portion 8 formed in the bonding region 20. Therefore, when the copper wire is bonded to the second structure 7 by ultrasound, the energy of the ultrasound is dispersed by the second concavo-convex portion 8. Furthermore, the second structure 7 having the second concavo-convex portion 8 is stacked on the first structure 5 having the first concavo-convex portion 6. Thus, the energy of the ultrasound is effectively dispersed. In addition, the contact area between the copper wire and the second structure 7 (bonding region 20) is increased, and the friction force required for bonding the copper wire can be effectively obtained.

[0086] As a result, it is possible to bond copper wires that require greater ultrasonic energy than in the case of bonding aluminum wires without applying a large load to the bonding region 20 or the like.

[0087] Furthermore, the insulating member 11 defining the bonding region 20 is formed so as to reach the semiconductor substrate 3 , thereby also being able to suppress the influence of the ultrasonic wave from extending to the outside of the bonding region 20 .

[0088] In the past, in order to bond copper wires, there was a method of forming a copper film with a thickness of about 30 μm in advance in the bonding area (Patent Document 1). Compared with such a method, there is no need to form the copper film while managing the thickness of the copper film, which can reduce the time required for manufacturing. In addition, it can help reduce production costs.

[0089] In addition, there is a method in the past in which the bonding area for bonding the metal wire is set to a concave-convex shape (Patent Document 2). In such a method, when the depth of the concave portion is deep, it is difficult to fully ensure the contact area between the metal wire and the bonding area. Compared with this method, in the above-mentioned semiconductor device 1, by setting the depth of the concave portion of the second concave-convex portion 8 to, for example, 80% or less of the depth of the concave portion of the first concave-convex portion 6, the contact area between the copper wire as the metal wiring 13 and the second structure 7 (bonding area) can be reliably ensured. As a result, the copper wire can be firmly bonded to the bonding area 20.

[0090] Furthermore, in a general semiconductor device for electric power, the area of ​​the gate pad electrically connected to the gate electrode of an IGBT or the like is relatively small, and the surface of the gate pad is flat. In the semiconductor device 1 described above, the second region 23 having a small area among the first region 21 and the second region 23 in the bonding region 20 can be set as the gate pad, and the copper wire as the metal wiring 13 can be bonded to the second structure 7 in the second region 23. Thus, the copper wire bonding at the gate pad can be reliably performed, and the reliability of the semiconductor device 1 can be improved.

[0091] (First Modification)

[0092] Here, the metal layer 77 (see Figure 7 ) In the case where the second concavo-convex portion 8 is intentionally formed in the first structure 5. For example, when the shape of the substrate is not reflected in the metal layer 77, it is necessary to form the second concavo-convex portion 8 in the metal layer 77. In addition, sometimes the second concavo-convex portion 8 having a pattern different from the first concavo-convex portion 6 of the first structure 5 is formed in the metal layer 77.

[0093] like Fig.11 As shown in FIG. 5 , a metal layer 77 that becomes a second structure is formed so as to cover the first structure 5. Here, for the sake of explanation, it is assumed that the surface of the metal layer 77 is flat. Fig.12 As shown in FIG. 5 , a photoresist 53 is applied to cover the metal layer 77. Next, as shown in FIG. Fig.13 As shown, by performing photolithography, a pattern of a photoresist 53 for forming the second structure 7 having the second concavo-convex portion 8 is formed.

[0094] Then, if Fig.14 As shown, the metal layer 77 is subjected to dry etching, for example, using the pattern of the photoresist 53 as an etching mask, thereby forming the second structure 7 having the second concavo-convex portion 8. Fig.15 As shown, the photoresist 53 is removed. Figure 8 to Figure 10 The semiconductor device 1 having the metal wiring 13 bonded to the bonding region 20 is manufactured by the same process as shown in FIG. Figure 2 ).

[0095] In the semiconductor device 1 according to the first modification, when the shape of the base is not reflected in the metal layer 77, the second concavo-convex portion 8 can be formed in the metal layer 77, and the metal wiring 13 can be firmly bonded to the bonding region 20. In addition, the second concavo-convex portion 8 (second structure 7) having an appropriate depth and pattern corresponding to the bonding condition of the metal wiring 13 to the bonding region 20 can be formed. Thus, the metal wiring 13 can be bonded to the second structure 7 having the second concavo-convex portion 8 optimal for various bonding conditions.

[0096] (Second Modification)

[0097] In the semiconductor device 1 described above, the following case is described as an example: the first concavo-convex portion 6 is formed in a dot-shaped convex portion, and the second concavo-convex portion 8 is formed with a dot-shaped convex portion reflecting the dot-shaped first concavo-convex portion 6. Here, the change in the pattern of the convex or concave portion of the first concavo-convex portion 6 and the second concavo-convex portion 8 is described.

[0098] like Fig.16 As shown in FIG. 1 , the first concavoconvex portion 6 and the second concavoconvex portion 8 may also be, for example, stripe-shaped patterns. Fig.17 As shown in FIG. 1 , the first concavoconvex portion 6 and the second concavoconvex portion 8 may also be, for example, a meandering pattern. Fig.18 As shown, the first concavo-convex portion 6 and the second concavo-convex portion 8 may be, for example, a racetrack-shaped (elliptical) pattern.

[0099] (Third Modification)

[0100] Here, a semiconductor device in which an intermediate structure is interposed between the first structure 5 and the second structure 7 is described. The intermediate structure is formed to improve the adhesion between the first structure 5 and the second structure 7. In addition, the intermediate structure is formed to suppress the diffusion of the respective materials between the first structure 5 and the second structure 7.

[0101] like Fig.19 As shown, in the bonding region 20, the intermediate structure 9 is interposed between the first structure 5 and the second structure 7. In the first region 21, the intermediate structure 9a is interposed between the first structure 5a and the second structure 7a. In the second region 23, the intermediate structure 9b is interposed between the first structure 5b and the second structure 7b.

[0102] The intermediate structure 9 may be either a single layer or a multilayer. As the material of the intermediate structure 9, for example, there are aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), cobalt (Co), chromium (Cr) or titanium (Ti). In addition, as the material of the intermediate structure 9, there are alloys of these metals. As long as the material does not impair the function of the semiconductor device 1 and can seek electrical connection, improvement of tightness and suppression of diffusion, it is not limited to these materials. In addition, as the material of the intermediate structure 9, the properties such as density, surface roughness, and conductivity are not particularly limited.

[0103] Furthermore, the shape of the intermediate structure 9 is not particularly limited as long as the energy of the ultrasonic wave is effectively dispersed and the friction force required for joining the copper wires can be effectively obtained. For example, the concavo-convex shape may not be formed in the intermediate structure 9. In addition, the intermediate structure 9 may be formed in a manner that fills the space between the convex portions of the first concavo-convex portion 6, or may be formed in a manner that leaves a part of the cavity between the convex portions.

[0104] When the intermediate structure 9 is not provided with a concavo-convex shape, the second structure 7 is formed by the above-mentioned Figure 11 to Figure 15 The second structure 7 having the second concavo-convex portion 8 can be formed by the same steps as those shown.

[0105] In addition, when a concavo-convex shape is formed in the intermediate structure 9, the concavo-convex shape may be a concavo-convex shape reflecting the shape of the first concavo-convex portion 6 or a concavo-convex shape having a pattern different from the first concavo-convex portion 6. Furthermore, the depth of the concavo-convex shape of the intermediate structure 9 is not particularly limited.

[0106] When the intermediate structure 9 has a concavo-convex shape, when forming the second structure 7 , if the metal layer 77 can reflect the shape of the base, an additional step of forming the second concavo-convex portion 8 in the metal layer 77 is not required.

[0107] In the semiconductor device 1 according to the third modification, the intermediate structure 9 for improving adhesion is formed, so that the metal wiring 13 can be more firmly bonded to the bonding region 20 .

[0108] In addition, when the first area 21 in the bonding area 20 and the second area 23 with a smaller area are used as gate pads, the gate pad and the gate electrode (for example, IGBT) are electrically connected through other wiring (not shown), so an insulating film can be applied as the intermediate structure 9.

[0109] Implementation method 2.

[0110] In Embodiment 1, the case where the first structure 5 is arranged on the main surface of the semiconductor substrate 3 so that the plurality of protrusions are separated from each other is described. Here, an example of a semiconductor device including the continuous film-like first structure 5 is described.

[0111] like Fig. 20 As shown, a continuous film-like first structure 5 having a first concavo-convex portion 6 is formed in the bonding region 20 of the semiconductor device 1. The first structure 5 includes a portion extending in a film-like manner on the surface of the semiconductor substrate 3 and a portion protruding from the film-like portion. The height between the lower surface of the film-like portion and the upper surface of the protruding portion (the thickness of the first structure 5) is, for example, about 1 μm to 50 μm.

[0112] A first structure 5a having a first concavo-convex portion 6 and a second structure 7a having a second concavo-convex portion 8 are formed in the first region 21. The second structure 7a is formed so as to cover the film-like first structure 5a. A first structure 5b having a first concavo-convex portion 6 and a second structure 7b having a second concavo-convex portion 8 are formed in the second region 23. The second structure 7b is formed so as to cover the film-like first structure 5b.

[0113] In addition, regarding other structures, Figure 2 Since the structure of the semiconductor device 1 shown in the figures is the same as that in the figures, the same reference numerals are given to the same components, and the description thereof will not be repeated unless necessary.

[0114] Next, an example of a method for manufacturing the semiconductor device 1 is described. In particular, the first structure 5 can be manufactured by Figure 11 to Figure 15 The same process as shown in the figure is used to form the Fig.21 As shown in FIG. 1 , a metal layer 55 serving as a first structure is formed on one main surface of the semiconductor substrate 3. Fig. 22 As shown in FIG. 5 , a photoresist 54 is applied to cover the metal layer 55. Next, as shown in FIG. Fig.23 As shown, by performing photolithography, a pattern of a photoresist 54 for forming the first structure 5 having the first concavo-convex portion 6 is formed.

[0115] Then, if Fig.24 As shown, the metal layer 55 is subjected to, for example, dry etching using the pattern of the photoresist 54 as an etching mask, and the etching process is stopped before the surface of the semiconductor substrate 3 is exposed, thereby forming a continuous film-like first structure 5 having the first concavoconvex portion 6 .

[0116] Then, if Fig.25 As shown, the photoresist 54 is removed. Figure 7 to Figure 10 The semiconductor device 1 having the metal wiring 13 bonded to the bonding region 20 is manufactured by the same process as shown in FIG. Fig. 20 ).

[0117] In the semiconductor device 1, as described above, when the copper wire is ultrasonically bonded to the second structure 7, the energy of the ultrasonic wave is dispersed by the second concavoconvex portion 8. The second structure 7 having the second concavoconvex portion 8 is stacked on the first structure 5 having the first concavoconvex portion 6.

[0118] Furthermore, the first structure 5 having the first concavoconvex portion 6 is formed in a continuous film shape. This can prevent the energy of the ultrasonic wave accumulated in the concave portion of the first concavoconvex portion 6 from directly affecting the semiconductor substrate 3 (semiconductor device 1), thereby preventing the semiconductor device 1 from being damaged.

[0119] Implementation method 3.

[0120] Here, changes in the first structure 5 in the bonding region 20 will be described.

[0121] (first example)

[0122] like Fig.26 As shown, in the first region 21 in the bonding region 20, as the first structure 5, a first structure 5a is formed in which a plurality of convex portions of the first concavo-convex portion 6 are arranged on the main surface of the semiconductor substrate 3 in a manner that is separated from each other. On the other hand, in the second region 23 in the bonding region 20, as the first structure 5, a continuous film-like first structure 5b having the first concavo-convex portion 6 is formed.

[0123] In addition, regarding other structures, Figure 2 Since the structure of the semiconductor device 1 shown in the figures is the same as that in the figures, the same reference numerals are given to the same components, and the description thereof will not be repeated unless necessary.

[0124] (Second example)

[0125] like Fig. 27 As shown, in the first region 21 in the bonding region 20, a first film-like continuous structure 5a having a first concavo-convex portion 6 is formed as the first structure 5. On the other hand, in the second region 23 in the bonding region 20, a first structure 5b is formed as the first structure 5, which is arranged on the main surface of the semiconductor substrate 3 in a manner that a plurality of convex portions of the first concavo-convex portion 6 are separated from each other.

[0126] In addition, regarding other structures, Figure 2 Since the structure of the semiconductor device 1 shown in the figures is the same as that in the figures, the same reference numerals are given to the same components, and the description thereof will not be repeated unless necessary.

[0127] The semiconductor device 1 according to the first example or the semiconductor device 1 according to the second example is manufactured as follows. First, after forming the semiconductor element 2 and the like on the semiconductor substrate 3, a bonding region 20 is bonded to one of the first region 21 and the second region 23. Figure 3 to Figure 6 The first structure 5 having the first concavo-convex portion 6 in which a plurality of convex portions are separated from each other is formed in the same process as shown.

[0128] In the other of the first area 21 and the second area 23, Figure 21 to Figure 25 The first structure 5 having a continuous film shape and a first concavoconvex portion 6 is formed by the same process as shown in FIG. Figure 7 to Figure 10 The semiconductor device 1 according to the first example or the semiconductor device 1 according to the second example is completed by performing the same steps as those shown.

[0129] In the bonding region 20 of the semiconductor device 1 involved in the first example and the semiconductor device 1 involved in the second example described above, as the first structure 5, a first structure 5 having a first convex-concave portion 6 in which a plurality of convex portions are separated from each other and a continuous film-like first structure 5 having a first convex-concave portion 6 are mixed.

[0130] As described above, in the continuous film-like first structure 5 having the first concavoconvex portion 6, it is possible to suppress the energy of the ultrasonic wave accumulated in the concave portion of the first concavoconvex portion 6 from directly affecting the semiconductor substrate 3 (semiconductor device 1), compared with the first structure 5 having the first concavoconvex portion 6 in a manner in which the convex portions are separated from each other. As a result, the options (range) of the bonding conditions based on the energy of the ultrasonic wave when bonding the metal wiring 13 are increased, and a structural design that is more in line with the function of the semiconductor device can be performed.

[0131] Implementation method 4.

[0132] Here, a semiconductor device 1 including a bonding region 20 consisting of a single region as the bonding region 20 will be described.

[0133] (first example)

[0134] like Fig.28 As shown, the bonding region 20 is composed of one region 25. One region 25 is defined by the insulating member 11. In one region 25, a first structure 5 having a continuous film shape and a first concavo-convex portion 6 is formed as a first structure 5. A second structure 7 having a second concavo-convex portion 8 is formed so as to cover the first structure 5.

[0135] In addition, regarding other structures, Figure 2 Since the structure of the semiconductor device 1 shown in the figures is the same as that in the figures, the same reference numerals are given to the same components, and the description thereof will not be repeated unless necessary.

[0136] (Second example)

[0137] like Fig.29As shown, the bonding region 20 is composed of one region 25. One region 25 is defined by the insulating member 11. In one region 25, a first structure 5 is formed as a first structure 5 arranged on the main surface of the semiconductor substrate 3 in a manner that a plurality of convex portions of the first concavo-convex portion 6 are separated from each other. A second structure 7 having a second concavo-convex portion 8 is formed so as to cover the first structure 5.

[0138] In addition, regarding other structures, Figure 2 Since the structure of the semiconductor device 1 shown in the figures is the same as that in the figures, the same reference numerals are given to the same components, and the description thereof will not be repeated unless necessary.

[0139] In the semiconductor device 1 according to the first example and the semiconductor device 1 according to the second example described above, the following effects are obtained in addition to the effects described in the first embodiment and the like.

[0140] In each of the above-mentioned semiconductor devices 1, the bonding region 20 is not divided into a plurality of regions, but is formed by a single region 25. Thus, a bonding region can be formed on the surface of a semiconductor element such as a diode (chip) which generally does not require a plurality of electrode pads. As a result, the degree of freedom in the structural design of the semiconductor device 1 can be increased.

[0141] Implementation method 5.

[0142] Here, a power conversion device to which the semiconductor devices described in the above-mentioned Embodiments 1 to 4 are applied will be described. The present disclosure is not limited to a specific power conversion device, and the case where the present disclosure is applied to a three-phase inverter will be described below as Embodiment 5.

[0143] Fig.30 It is a block diagram showing the configuration of a power conversion system to which the power conversion device according to the present embodiment is applied. Fig.30 The power conversion system shown is composed of a power supply 100, a power conversion device 200, and a load 300. The power supply 100 is a DC power supply, and supplies DC power to the power conversion device 200. The power supply 100 can be composed of various power supplies, for example, a DC system, a solar cell, and a storage battery. In addition, it can also be composed of a rectifier circuit or an AC / DC converter connected to an AC system. In addition, the power supply 100 can also be composed of a DC / DC converter that converts the DC power output from the DC system into a specified power.

[0144] The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300, converts the DC power supplied from the power source 100 into AC power, and supplies the AC power to the load 300. Fig.30As shown, the power conversion device 200 includes: a main conversion circuit 201 that converts DC power into AC power and outputs the AC power; and a control circuit 203 that outputs a control signal for controlling the main conversion circuit 201 to the main conversion circuit 201 .

[0145] The load 300 is a three-phase motor driven by the AC power supplied from the power conversion device 200. The load 300 is not limited to a specific use, and is a motor mounted on various electrical devices, for example, used as a motor for hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioning equipment.

[0146] The following describes the details of the power conversion device 200. The main conversion circuit 201 includes a switching element and a freewheeling diode (not shown). The DC power supplied from the power supply 100 is converted into AC power and supplied to the load 300 by the switching action of the switching element. There are various structures for the specific circuit structure of the main conversion circuit 201. The main conversion circuit 201 involved in this embodiment is a 2-level three-phase full-bridge circuit, which can be composed of 6 switching elements and 6 freewheeling diodes connected in anti-parallel to each switching element.

[0147] At least one of the switching elements and the freewheeling diodes of the main conversion circuit 201 is a switching element or a freewheeling diode possessed by the semiconductor device 202 corresponding to the semiconductor device 1 involved in at least one of the above-mentioned embodiments 1 to 3. The six switching elements constitute the upper and lower arms connected in series every two switching elements, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full bridge circuit. Moreover, the output terminals of each upper and lower arm, that is, the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0148] In addition, the main conversion circuit 201 is provided with a driving circuit (not shown) for driving each switching element. The driving circuit may be built into the semiconductor device 202 or may be provided with the driving circuit separately from the semiconductor device 202. The driving circuit generates a driving signal for driving the switching element of the main conversion circuit 201 and supplies it to the control electrode of the switching element of the main conversion circuit 201. Specifically, according to the control signal from the control circuit 203 described later, a driving signal for turning on the switching element and a driving signal for turning off the switching element are output to the control electrode of each switching element. When the switching element is maintained in the on state, the driving signal is a voltage signal (on signal) above the threshold voltage of the switching element, and when the switching element is maintained in the off state, the driving signal is a voltage signal (off signal) below the threshold voltage of the switching element.

[0149] The control circuit 203 controls the switch elements of the main conversion circuit 201 so that the desired power is supplied to the load 300. Specifically, the time (on time) at which each switch element of the main conversion circuit 201 should be in the on state is calculated based on the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by PWM control that modulates the on time of the switch element according to the voltage to be output. In addition, a control instruction (control signal) is output to the drive circuit of the main conversion circuit 201 in such a manner that an on signal is output to the switch element that should be in the on state and an off signal is output to the switch element that should be in the off state at each time point. The drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switch element according to the control signal.

[0150] In the power conversion device 200 according to the present embodiment, the semiconductor device 1 according to the first to fourth embodiments is applied as the semiconductor device 202 constituting the main conversion circuit 201. Thus, copper wires or the like can be more firmly and well bonded to the bonding region 20 as the metal wiring 13. As a result, the reliability of the power conversion device 200 can be improved.

[0151] In this embodiment, an example of applying the present disclosure to a 2-level three-phase inverter is described, but the present disclosure is not limited thereto and can be applied to various power conversion devices. In this embodiment, a 2-level power conversion device is used, but a 3-level or multi-level power conversion device can also be used. When power is supplied to a single-phase load, the present disclosure can also be applied to a single-phase inverter. In addition, when power is supplied to a DC load, the present disclosure can also be applied to a DC / DC converter or an AC / DC converter.

[0152] In addition, the power conversion device to which the present invention is applied is not limited to the case where the above-mentioned load is an electric motor. For example, it can also be used as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker or a contactless power supply system, and can also be used as a power conditioner for a solar power generation system or a power storage system.

[0153] Furthermore, the semiconductor device 1 described in each embodiment can be combined in various ways as needed.

[0154] The embodiments disclosed this time are illustrative and are not limited thereto. The present disclosure is indicated by the claims rather than the above description, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0155] Industrial Applicability

[0156] The present disclosure is effectively used in a semiconductor device in which a metal wiring is bonded to a bonding region.

Claims

1. A semiconductor device comprising: A semiconductor substrate having a semiconductor element formed thereon; a bonding area defined on the semiconductor substrate; an insulating member formed in contact with the semiconductor substrate and defining the bonding region; A first structure having a first concave-convex portion formed in the bonding area; A second structure having a second concave-convex portion, the second structure being formed in a manner of covering the first structure; as well as a metal wiring connected to the second concave-convex portion of the second structure; The depth of the depression in the second concavo-convex portion is shallower than the depth of the depression in the first concavo-convex portion, The insulating member is formed so as to surround the first structure and the second structure.

2. A semiconductor device comprising: A semiconductor substrate having a semiconductor element formed thereon; a bonding area defined on the semiconductor substrate; A first structure having a first concave-convex portion formed in the bonding area; an intermediate structure formed on the first structure; A second structure having a second concavo-convex portion, the second structure being formed in a manner covering the first structure and the intermediate structure; as well as a metal wiring connected to the second concave-convex portion of the second structure; The depth of the recess in the second recessed and convex portion is shallower than the depth of the recess in the first recessed and convex portion.

3. The semiconductor device according to claim 1, wherein An intermediate structure is interposed between the first structure and the second structure.

4. The semiconductor device according to any one of claims 1 to 3, wherein: The first structure includes the first concavo-convex portion which is formed intermittently so that convex portions are separated from each other.

5. The semiconductor device according to any one of claims 1 to 3, wherein: The first structure includes the first concavoconvex portion formed in a continuous film shape.

6. The semiconductor device according to any one of claims 1 to 3, wherein: The bonding region is divided into a first region having a first area and a second region having a second area smaller than the first area.

7. The semiconductor device according to claim 6, wherein: The first structure and the second structure are arranged at least in the second region.

8. The semiconductor device according to any one of claims 1 to 3, wherein: The second structure is formed of a metal having a Vickers hardness of 300 or more.

9. The semiconductor device according to claim 8, wherein: The metals include nickel (Ni), cobalt (Co), and chromium (Cr).

10. The semiconductor device according to any one of claims 1 to 3, wherein The first structure includes an oxide.

11. The semiconductor device according to any one of claims 1 to 3, wherein: The metal wiring includes a copper wiring.

12. A method for manufacturing a semiconductor device, comprising the following steps: forming a semiconductor element on a main surface of a semiconductor substrate; forming a first structure having a first concavo-convex portion on the main surface of the semiconductor substrate; forming a second structure having a second concave-convex portion in a manner covering the first structure; forming an insulating member so as to surround at least the first structure and the second structure, thereby defining a bonding region; as well as bonding a metal wire to the second structure in the bonding region, In the step of forming the first structure and the step of forming the second structure, the first structure and the second structure are formed so that the depth of the recess in the second recessed and convex portion is shallower than the depth of the recess in the first recessed and convex portion.

13. The method for manufacturing a semiconductor device according to claim 12, wherein: The step of forming the first structure includes forming a first layer on the main surface of the semiconductor substrate, and processing the first layer to partially expose the main surface of the semiconductor substrate, thereby forming the discontinuous first concavoconvex portion in which convex portions are separated.

14. The method for manufacturing a semiconductor device according to claim 12, wherein: The step of forming the first structure includes forming a first layer on the main surface of the semiconductor substrate and processing the first layer until it reaches halfway on the main surface of the semiconductor substrate, thereby forming the first concavo-convex portion in a continuous film shape.

15. The method for manufacturing a semiconductor device according to any one of claims 12 to 14, wherein: The step of defining the bonding region includes the step of forming the insulating member so as to reach the main surface of the semiconductor substrate.

16. The method for manufacturing a semiconductor device according to any one of claims 12 to 14, wherein: The step of bonding the metal wiring to the second structure includes the step of bonding a copper wiring as the metal wiring.

17. A power conversion device comprising: A main conversion circuit, comprising the semiconductor device according to any one of claims 1 to 11, the main conversion circuit converting input power and outputting the converted power; and The control circuit outputs a control signal for controlling the main conversion circuit to the main conversion circuit.

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