Imaging device and electronic device

Abstract

[Problem] To provide an imaging device capable of coping with an increase in the number of analog-digital converters arranged in parallel while maintaining a chip size that is dominated by a contribution of a pixel chip in which pixels are arranged. [Solution] An imaging device according to the present disclosure has a stacked chip structure in which at least three semiconductor chips including a first layer semiconductor chip, a second layer semiconductor chip, and a third layer semiconductor chip are stacked. A pixel array unit including pixels arranged two-dimensionally in a matrix shape is formed on the first layer semiconductor chip. An analog circuit unit of an analog-digital conversion unit that converts an analog pixel signal read from each pixel of the pixel array unit through a signal line into a digital pixel signal is provided on one of the second layer semiconductor chip and the third layer semiconductor chip. A digital circuit unit of the analog-digital conversion unit is provided on the other of the second layer semiconductor chip and the third layer semiconductor chip.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to an imaging device and an electronic apparatus. BACKGROUND

[0002] The imaging device is provided with an analog-digital conversion unit that digitizes an analog pixel signal read from a pixel. The analog-digital conversion unit is a so-called column-parallel type analog-digital conversion unit that includes a plurality of analog-digital converters provided corresponding to a pixel column.

[0003] Further, in the imaging device, a stacked chip structure is employed in which a pixel array unit formed by arranging pixels is formed on a semiconductor chip of a first layer, an analog-digital conversion unit is formed on a semiconductor chip of a second layer, and the semiconductor chip of the first layer and the semiconductor chip of the second layer are stacked (for example, refer to Patent Literature 1). According to this stacked chip structure, since the semiconductor chip of the first layer only needs to have a size (area) sufficient to form the pixel array unit 11, it is possible to reduce the size of the semiconductor chip of the first layer and the size of the entire chip.

[0004] LIST OF CITATIONS

[0005] PATENT LITERATURE

[0006] Patent Literature 1: WO 2014 / 007004 A1 SUMMARY

[0007] PROBLEMS TO BE SOLVED BY THE INVENTION

[0008] In the conventional technology disclosed in Patent Literature 1, two systems or four systems of analog-digital converters are provided in parallel, and an analog pixel signal read in parallel from each pixel in two pixel rows or four pixel rows is processed in parallel by the two systems or four systems of analog-digital converters, so it is possible to reduce the read time of the pixel signal.

[0009] However, although the chip size is reduced by the stacked chip structure, in the case where the number of parallel analog-digital converters increases, the size of the semiconductor chip of the second layer and the size of the entire chip also increase.

[0010] An object of the present disclosure is to provide an imaging device that can cope with an increase in the number of parallel analog-digital converters while maintaining a chip size in which a pixel chip formed by arranging pixels is dominant, and an electronic apparatus having the same.

[0011] TECHNICAL SOLUTION TO THE PROBLEM

[0012] To achieve the above object, according to the present disclosure,

[0013] Provided is an imaging device having a stacked chip structure in which at least three semiconductor chips including a first layer semiconductor chip, a second layer semiconductor chip, and a third layer semiconductor chip are stacked, the imaging device including:

[0014] a pixel array unit in which pixels are arranged in a matrix in two dimensions, the pixel array unit being formed on the first layer semiconductor chip;

[0015] an analog circuit unit of an analog-digital conversion unit that converts an analog pixel signal read from each pixel of the pixel array unit through a signal line into a digital pixel signal, the analog circuit unit being provided on one of the second layer semiconductor chip and the third layer semiconductor chip; and

[0016] a digital circuit unit of the analog-digital conversion unit, the digital circuit unit being provided on the other of the second layer semiconductor chip and the third layer semiconductor chip.

[0017] Further, an electronic device of the present disclosure for achieving the above object includes the imaging device having the above configuration. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 is a block diagram schematically showing an outline of a system configuration of an imaging device to which a first embodiment of the technology according to the present disclosure is applied.

[0019] Figure 2 is a circuit diagram showing an example of a circuit configuration of a pixel.

[0020] Figure 3 is a block diagram schematically showing an example of a configuration of an analog-digital conversion unit.

[0021] Figure 4 is a circuit diagram showing a circuit configuration of a comparator according to Circuit Configuration Example 1.

[0022] Figure 5 is a circuit diagram showing a circuit configuration of a comparator according to Circuit Configuration Example 2.

[0023] Figure 6 is a circuit diagram showing a circuit configuration of a comparator according to Circuit Configuration Example 3.

[0024] Figure 7 is a circuit diagram showing a circuit configuration of a comparator according to Circuit Configuration Example 4.

[0025] Figure 8 is a schematic exploded perspective view showing a stacked chip structure of a CMOS image sensor according to the first embodiment.

[0026] Figure 9 is a circuit diagram showing a connection relationship of one pixel column when a plurality of systems of analog-digital converters are arranged in parallel and the number of rows read at the same time is increased.

[0027] Figure 10 is a block diagram schematically showing an outline of a system configuration of an imaging device to which a second embodiment of the technology according to the present disclosure is applied.

[0028] Figure 11 is a schematic exploded perspective view showing a stacked chip structure of a CMOS image sensor according to the second embodiment.

[0029] Figure 12A is an end face view of a cut portion of an example 1 of an electrical connection structure between semiconductor chips, Figure 12B is an end face view of a cut portion of an example 2 of an electrical connection structure between semiconductor chips.

[0030] Figure 13 is an explanatory view of a parasitic resistance and a parasitic capacitance of a signal line.

[0031] Figure 14 is an explanatory view of reduction of power consumption accompanying halving of a parasitic resistance and a parasitic capacitance of a signal line.

[0032] Figure 15 is a block diagram schematically showing an outline of a system configuration of an imaging device to which a third embodiment of the technology according to the present disclosure is applied.

[0033] Figure 16 is a schematic exploded perspective view showing a stacked chip structure of a CMOS image sensor according to the third embodiment.

[0034] Figure 17 is a schematic exploded perspective view showing a stacked chip structure of a CMOS image sensor according to a fourth embodiment.

[0035] Figure 18 is a schematic exploded perspective view showing a stacked chip structure of a CMOS image sensor according to a fifth embodiment.

[0036] Figure 19 is a schematic exploded perspective view showing a stacked chip structure of a CMOS image sensor according to a sixth embodiment.

[0037] Figure 20 is a schematic exploded perspective view showing a stacked chip structure of a CMOS image sensor according to a seventh embodiment.

[0038] Figure 21 is a schematic exploded perspective view showing a stacked chip structure of a CMOS image sensor according to an eighth embodiment.

[0039] Figure 22 is a diagram showing an application example of the technology according to the present disclosure.

[0040] Figure 23 is a block diagram schematically showing an outline of a configuration example of an imaging system that is an example of the electronic apparatus of the present disclosure.

[0041] Figure 24 is a block diagram schematically showing a configuration example of a vehicle control system that is an example of a mobile body control system to which the technology according to the present disclosure is applied.

[0042] Figure 25 is a diagram showing an example of a setting position of an imaging unit in a mobile body control system. DETAILED DESCRIPTION

[0043] Hereinafter, a mode for carrying out the technology according to the present disclosure (hereinafter referred to as "embodiment") will be explained in detail with reference to the drawings. The technology according to the present disclosure is not limited to the embodiment, and various numerical values and the like in the embodiment are examples. In the following explanation, the same elements or elements having the same function will use the same reference numerals, and the repeated explanation will be omitted. Note that the explanation will be given in the following order.

[0044] 1. General explanation of imaging apparatus and electronic apparatus of the present disclosure

[0045] 2. Imaging apparatus according to first embodiment

[0046] 2-1. Configuration example of CMOS image sensor

[0047] 2-2. Circuit configuration example of pixel

[0048] 2-3. Configuration example of analog-digital conversion unit

[0049] 2-4. Circuit configuration example of comparator

[0050] 2-4-1. Circuit configuration example 1

[0051] 2-4-2. Circuit configuration example 2

[0052] 2-4-3. Circuit configuration example 3

[0053] 2-4-4. Circuit configuration example 4

[0054] 2-5. Laminated chip structure

[0055] 3. Imaging apparatus according to second embodiment

[0056] 3-1. Configuration example of CMOS image sensor

[0057] 3-2. Layered chip structure

[0058] 3-3. Electrical connection structure between semiconductor chips

[0059] 3-3-1. Example 1 of electrical connection structure

[0060] 3-3-2. Example 2 of electrical connection structure

[0061] 4. Imaging device according to third embodiment

[0062] 4-1. Configuration example of CMOS image sensor

[0063] 4-2. Layered chip structure

[0064] 5. Imaging device according to fourth embodiment

[0065] 6. Imaging device according to fifth embodiment

[0066] 7. Imaging device according to sixth embodiment

[0067] 8. Imaging device according to seventh embodiment

[0068] 9. Imaging device according to eighth embodiment

[0069] 10. Modified example

[0070] 11. Application example

[0071] 12. Application example of technology according to present disclosure

[0072] 12-1. Electronic device (example of imaging system) of present disclosure

[0073] 12-2. Application example of mobile body

[0074] 13. Configuration that present disclosure can adopt

[0075] [General description of imaging device and electronic device of present disclosure]

[0076] In the imaging device and electronic device of the present disclosure, the analog-digital conversion unit can include a plurality of analog-digital converters provided corresponding to the pixel columns of the pixel array unit, and the analog-digital converter can include a comparator that compares the analog pixel signal with a reference signal of a ramp wave, and a counter that measures a time from a timing of generation of the reference signal to a timing at which the analog pixel signal and the reference signal of the ramp wave cross. Also, the comparator of the analog-digital conversion unit can be provided on one of the semiconductor chip of the second layer and the semiconductor chip of the third layer, and the counter of the analog-digital conversion unit can be provided on the other of the semiconductor chip of the second layer and the semiconductor chip of the third layer.

[0077] In the imaging device and the electronic device of the present disclosure including the above-described preferred configuration, the comparator of the A / D conversion unit and the load current source connected to the signal line can be provided on the semiconductor chip of the second layer, and the counter, the logic circuit unit, and the interface of the A / D conversion unit can be provided on the semiconductor chip of the third layer. Further, on the semiconductor chip of the third layer, in addition to the counter, the logic circuit unit, and the interface of the A / D conversion unit, a storage unit or an AI (artificial intelligence) circuit can be provided.

[0078] Further, the imaging device and the electronic device of the present disclosure including the above-described preferred configuration can include a semiconductor chip of a fourth layer. Further, on the semiconductor chip of the fourth layer, a storage unit or an AI circuit can be provided. Further, the size of the semiconductor chip of the fourth layer can be smaller than the size of the semiconductor chips of the other layers.

[0079] Further, in the imaging device and the electronic device of the present disclosure including the above-described preferred configuration, the counter, the logic circuit unit, and the interface of the A / D conversion unit can be provided on the semiconductor chip of the second layer, and the comparator of the A / D conversion unit and the load current source connected to the signal line can be provided on the semiconductor chip of the third layer.

[0080] Further, in the imaging device and the electronic device of the present disclosure including the above-described preferred configuration, the A / D conversion unit can include a plurality of systems of A / D conversion units including a first A / D conversion unit and a second A / D conversion unit that convert each analog pixel signal read in parallel from each pixel of a plurality of pixel rows of the pixel array unit into a digital pixel signal. Also, with respect to the signal line, in the length direction thereof, for each pixel column, corresponding to the plurality of systems of A / D conversion units, can be divided into a plurality of signal lines including a first signal line and a second signal line.

[0081] Further, in the imaging device and the electronic device of the present disclosure including the above-described preferred configuration, the first connection portion connecting the first signal line to the first A / D conversion unit and the second connection portion connecting the second signal line to the second A / D conversion unit can be provided close to each other within the region of the pixel array unit. Further, the first connection portion and the second connection portion can connect the semiconductor chip of the first layer and the semiconductor chip of the second layer by direct bonding using a Cu electrode.

[0082] <Imaging device according to the first embodiment>

[0083] As an imaging device to which the first embodiment of the technology according to the present disclosure is applied, a CMOS (complementary metal oxide semiconductor) image sensor, which is one type of X-Y address type imaging device, will be described as an example. The embodiments to be described later are also similarly applicable. The CMOS image sensor is an image sensor manufactured by applying or partially using a CMOS process.

[0084] [Configuration example of CMOS image sensor]

[0085] Figure 1 is a block diagram schematically showing an outline of a system configuration of a CMOS image sensor that is an example of an imaging device to which the first embodiment of the technology according to the present disclosure is applied.

[0086] The CMOS image sensor 1A according to the first embodiment has a configuration including a pixel array unit 11 and a peripheral circuit unit of the pixel array unit 11. The pixel array unit 11 has a configuration in which pixels (pixel circuits) 20 including light-receiving elements are two-dimensionally arranged in a row direction and a column direction, that is, two-dimensionally arranged in a matrix shape. Here, the row direction refers to an arrangement direction of the pixels 20 in a row, and the column direction refers to an arrangement direction of the pixels 20 in a column. The pixels 20 generate and accumulate photocharges corresponding to amounts of received light by performing photoelectric conversion.

[0087] The peripheral circuit unit of the pixel array unit 11 includes, for example, a row selection unit 12, a load current source unit 13, an analog-digital conversion unit 14, a logic circuit unit 15 as a signal processing unit, a timing control unit 16, and the like.

[0088] In the pixel array unit 11, for the matrix-shaped pixel array, a pixel control line 31 (311 to 31 m ) is wired in the row direction for each row of pixels. In addition, a signal line 32 (321 to 32 n ) is wired in the column direction for each column of pixels. The pixel control line 31 transmits a drive signal for driving at the time of reading a signal from the pixel 20. In Figure 1 , the pixel control line 31 is shown as one wire, but is not limited to one. One end of the pixel control line 31 is connected to an output terminal corresponding to each row of the row selection unit 12.

[0089] Hereinafter, each constituent element of the peripheral circuit unit of the pixel array unit 11, that is, the row selection unit 12, the load current source unit 13, the analog-digital conversion unit 14, the logic circuit unit 15, and the timing control unit 16 will be described.

[0090] The row selection unit 12 includes a shift register and an address decoder, and controls the scanning of pixel rows or the address of pixel rows when selecting each pixel 20 of the pixel array unit 11. Although the specific structure of the row selection unit 12 is not shown, the row selection unit 12 typically includes two scanning systems: a read scanning system and a scan output scanning system.

[0091] To read pixel signals from pixel 20, the read-scan system sequentially selects and scans pixels 20 of pixel array unit 11 row by row. The pixel signals read from pixel 20 are analog signals. The exit-scan system performs an exit scan on the read rows scanned by the read-scan system one time corresponding to the shutter speed, preceding the read-scan.

[0092] The scanning process, performed by the scanning system, removes unwanted charges from the photoelectric conversion units of pixels 20 in the read row, thereby resetting the photoelectric conversion units. Then, by removing (resetting) the unwanted charges using the scanning system, a so-called electronic shutter operation is performed. Here, the electronic shutter operation refers to the operation of discarding the photoelectric charge of the photoelectric conversion units and starting a new exposure (starting the accumulation of photoelectric charge).

[0093] The load current source unit 13 includes signal lines 321 to 32 for each pixel column. n Multiple connected load current sources I (reference) Figure 2 The set of signals. The load current source I can be, for example, a MOS field-effect transistor (FET), and is connected through signal lines 321 to 322. n Bias current is provided to each pixel 20 of the pixel row selectively scanned by the row selection unit 12.

[0094] The analog-to-digital conversion unit 14 includes a collection of multiple analog-to-digital converters configured corresponding to (e.g., for each pixel column) the pixel columns of the pixel array unit 11. The analog-to-digital conversion unit 14 converts signals for each pixel column via signal lines 321 to 322. n A column-parallel analog-to-digital converter that converts the output analog pixel signals into digital signals.

[0095] As the analog-to-digital converter in the analog-to-digital conversion unit 14, for example, a single-slope type analog-to-digital converter, which is an example of a reference signal comparison type analog-to-digital converter, can be used. However, the analog-to-digital converter is not limited to a single-slope type analog-to-digital converter, and successive approximation type analog-to-digital converters or delta-sigma modulation type (ΔΣ modulation type) analog-to-digital converters can also be used.

[0096] The logic circuit unit 15, which is a signal processing unit, reads the pixel signal digitized by the A / D conversion unit 14 and performs predetermined signal processing. Specifically, in the logic circuit unit 15, as the predetermined signal processing, for example, correction of a vertical line defect or a dot defect, or clamping of a signal, and digital signal processing such as parallel-serial conversion, compression, encoding, addition, averaging, and intermittent operation are performed. The logic circuit unit 15 outputs the generated image data as an output signal OUT of the CMOS image sensor 1A to a device of a later stage.

[0097] The timing control unit 16 generates various timing signals, clock signals, and control signals, and the like, based on a synchronization signal supplied from the outside. Also, the timing control unit 16 controls the driving of the row selection unit 12, the A / D conversion unit 14, the logic circuit unit 15, and the like, based on the generated signals.

[0098] [Example of circuit configuration of pixel]

[0099] Figure 2 is a circuit diagram showing an example of a circuit configuration of the pixel 20. The pixel 20 includes, for example, a photodiode 21 as a photoelectric conversion element which is a light-receiving element. In addition to the photodiode 21, the pixel 20 includes a transfer transistor 22, a reset transistor 23, an amplification transistor 24, and a selection transistor 25.

[0100] As the four transistors including the transfer transistor 22, the reset transistor 23, the amplification transistor 24, and the selection transistor 25, for example, N-channel MOS field effect transistors are used. However, the combination of the conductive types of the four transistors 22 to 25 exemplified here is merely an example, and the combination is not limited thereto.

[0101] For the pixel 20, as the plurality of pixel control lines 31 (311 to 31 m ) described above, a plurality of pixel control lines are commonly wired to each of the pixels 20 in the same pixel row. The plurality of pixel control lines are connected to the output terminals of the row selection unit 12 corresponding to each of the pixel rows in units of pixel rows. The row selection unit 12 outputs the transfer signal TRG, the reset signal RST, and the selection signal SEL to the plurality of pixel control lines as appropriate.

[0102] The photodiode 21 has an anode electrode connected to a low-potential side power supply (for example, a ground potential), photoelectrically converts received light into a light charge (here, a photoelectron) of an amount of charge corresponding to an amount of received light, and accumulates the light charge. The cathode electrode of the photodiode 21 is electrically connected to the gate electrode of the amplification transistor 24 via the transfer transistor 22. Here, the region electrically connected to the gate electrode of the amplification transistor 24 is a floating diffusion portion (floating diffusion region / impurity diffusion region) FD. The floating diffusion portion FD is a charge-voltage conversion unit that converts a charge into a voltage.

[0103] A high level (e.g., V) is provided from row selection unit 12 to the gate electrode of transmission transistor 22. DD The transmission signal TRG is at an effective level. The transmission transistor 22 turns on in response to the transmission signal TRG to transfer the photocharge converted by the photodiode 21 and accumulated in the photodiode 21 to the floating diffuser FD.

[0104] Reset transistor 23 is connected to the high-potential side power supply voltage V. DD Between the node and the floating diffuser FD. A high-level reset signal RST is provided from the row selection unit 12 to the gate electrode of the reset transistor 23. The reset transistor 23 turns on in response to the reset signal RST and discharges the charge of the floating diffuser FD to the voltage V. DD The node is used to reset the floating diffuser FD.

[0105] Amplifying transistor 24 has a gate electrode connected to the floating diffuser FD and a high-potential side power supply voltage V. DD The drain electrode is connected to the node. The amplifying transistor 24 serves as the input unit for a source follower that reads the signal obtained by photoelectric conversion in the photodiode 21. That is, the source electrode of the amplifying transistor 24 is connected to the signal line 32 via the select transistor 25. Moreover, the amplifying transistor 24 and the current source I connected to one end of the signal line 32 constitute a source follower that converts the voltage of the floating diffuser FD into the potential of the signal line 32.

[0106] The selection transistor 25 has a drain electrode connected to the source electrode of the amplifying transistor 24 and a source electrode connected to the signal line 32. A selection signal SEL, which is active high, is provided from the row selection unit 12 to the gate electrode of the selection transistor 25. The selection transistor 25 is turned on in response to the selection signal SEL, thereby transmitting the signal output from the amplifying transistor 24 to the signal line 32 when the pixel 20 is in the selected state.

[0107] Note that in the circuit example above, pixel 20 has been described as a four-Tr configuration comprising a transmission transistor 22, a reset transistor 23, an amplification transistor 24, and a selection transistor 25, i.e., four transistors (Tr). However, this disclosure is not limited thereto. For example, the selection transistor 25 may be omitted, and the amplification transistor 24 may have the function of the selection transistor 25, thereby providing a three-Tr configuration, or a configuration in which the number of transistors is increased to five or more Tr as needed may also be provided.

[0108] [Example of Analog-to-Digital Conversion Unit Construction]

[0109] Next, an example of the configuration of the analog-digital conversion unit 14 will be described. Here, a case where a single-slope type analog-digital converter is used as each analog-digital converter of the analog-digital conversion unit 14 will be described as an example.

[0110] Figure 3 An example of the configuration of the analog-digital conversion unit 14 is shown. In the CMOS image sensor 1A according to the first embodiment, the analog-digital conversion unit 14 includes a plurality of sets of single-slope type analog-digital converters provided corresponding to each column of pixels of the pixel array unit 11. Here, a single-slope type analog-digital converter 140 of the nth column will be described as an example.

[0111] The analog-digital converter 140 has a circuit configuration including a comparator 141 and a counter 142. Also, in the single-slope type analog-digital converter 140, a reference signal generated by the reference signal generation unit 17 is used. The reference signal generation unit 17 generates a reference signal V RAMP of a ramp (RAMP) wave whose level (voltage) monotonously decreases with the passage of time, and supplies this reference signal V RAMP as a reference signal to the comparator 141 provided for each column of pixels.

[0112] The comparator 141 uses the analog pixel signal V VSL read from the pixel 20 as a comparison input, uses the reference signal V RAMP of the ramp wave generated by the reference signal generation unit 17 as a reference input, and then compares these two signals. Also, for example, when the reference signal V RAMP is greater than the pixel signal V VSL , the output of the comparator 141 enters a first state (for example, a high level), and when the reference signal V RAMP is equal to or less than the pixel signal V VSL , the output enters a second state (for example, a low level). Thus, the comparator 141 outputs a pulse signal having a pulse width corresponding to the signal level (specifically, the magnitude of the signal level) of the pixel signal V VSL as a comparison result.

[0113] At the same time as the start time at which the reference signal V RAMP is supplied to the comparator 141, a clock signal CLK is supplied from the timing control unit 16 to the counter 142. Then, the counter 142 performs a counting operation in synchronization with the clock signal CLK to measure the period of the pulse width of the output pulse of the comparator 141, that is, the period from the start of the comparison operation to the end of the comparison operation. The count result (count value) from the counter 142 is supplied to the logic circuit unit 15 as a digital value obtained by digitizing the analog pixel signal V VSL .

[0114] As described above, the analog-digital conversion unit 14 including the set of single-slope type analog-digital converters 140 changes the size relationship between the reference signal V RAMP and the analog pixel signal V VSL output from the pixel 20 based on the reference signal of the ramp wave generated by the reference signal generation unit 17.

[0115] Note that, in the above example, as the analog-digital conversion unit 14, a configuration in which the analog-digital converters 140 are arranged in one-to-one correspondence with the pixel columns of the pixel array unit 11 has been exemplified, but a configuration in which the analog-digital converters 140 are provided in units of a plurality of pixel columns can also be used.

[0116] [Circuit configuration example of comparator]

[0117] As the comparator 141 of the analog-digital converter 140, a comparator having various configurations can be used. In the following, a specific circuit configuration example of a comparator that can be used as the comparator 141 of the analog-digital converter 140 will be described.

[0118] (Circuit configuration example 1)

[0119] Figure 4 is a circuit diagram showing the circuit configuration of the comparator according to circuit configuration example 1. The comparator 50A according to circuit configuration example 1 includes a differential amplifier 51, a first capacitance element C 11 , a second capacitance element C 12 , a first switching transistor NT 13 , and a second switching transistor NT 14 .

[0120] The first switching transistor NT 13 and the second switching transistor NT 14 are examples of switching elements. Here, for example, an N-channel MOS transistor is used as the first switching transistor NT 13 and the second switching transistor NT 14 , but a P-channel MOS transistor can also be used.

[0121] The differential amplifier 51 includes a first differential transistor NT 11 , a second differential transistor NT 12 , a current source I 11 , a first load transistor PT 11 , and a second load transistor PT 12 . Here, an N-channel MOS transistor is used as the first differential transistor NT 11 and the second differential transistor NT 12 , and a P-channel MOS transistor is used as the first load transistor PT 11 and the second load transistor PT12 .

[0122] In the differential amplifier 51, the first differential transistor NT 11 and the second differential transistor NT 12 are connected to each other at their respective sources to form a differential pair that operates differentially. A current source I 11 is connected between the common connection node of the sources of the first differential transistor NT 11 and the second differential transistor NT 12 and the ground GND. The first load transistor PT 11 has a diode connection configuration in which the gate electrode and the drain electrode are connected to each other, and the first load transistor PT 11 is connected in series with the first differential transistor NT 11 . That is, the respective drain electrodes of the first load transistor PT 11 and the first differential transistor NT 11 are connected to each other.

[0123] The second load transistor PT 12 is connected in series with the second differential transistor NT 12 . That is, the respective drain electrodes of the second load transistor PT 12 and the second differential transistor NT 12 are connected to each other. Also, the respective gate electrodes of the first load transistor PT 11 and the second load transistor PT 12 are connected to each other to constitute a current mirror circuit.

[0124] Further, the common connection node N 12 between the second differential transistor NT 12 and the second load transistor PT 11 serves as an output node of the differential amplifier 51, from which the output signal OUT is led out through the output terminal T 10 . The respective sources of the first load transistor PT 11 and the second load transistor PT 12 are connected to the node of the power supply voltage V DD .

[0125] The first capacitance element C 11 is connected between the input terminal T RAMP of the reference signal V 11 of the ramp wave and the gate electrode of the first differential transistor NT 11 , and serves as an input capacitor of the reference signal V RAMP . The second capacitance element C 12 is connected between the input terminal T VSL of the pixel signal V 12 and the gate electrode of the second differential transistor NT12 Between the gate electrodes, and used as the pixel signal V VSL The input capacitor.

[0126] First switching transistor NT 13 Connected to the first differential transistor NT 11 Between the gate and drain electrodes. The second switching transistor NT 14 Connected to the second differential transistor NT 12 Between the gate electrode and the drain electrode. The first switching transistor NT 13 Second switching transistor NT 14 By from Figure 1 The timing control unit 16 shown is connected via input terminal T 13 The input drive signal AZ is controlled to ON (conduct) / OFF (disconduct), thereby selectively performing automatic zeroing (initialization operation).

[0127] The comparator 50A according to the circuit construction example 1 described above is a known comparator with a differential amplifier construction. In the case of the comparator 50A according to circuit construction example 1, since it is necessary to ensure the input range corresponding to the signal quantity of pixel 20, it is necessary to adjust the power supply voltage V... DD Set it to a relatively high value (e.g., about 1.8V).

[0128] (Circuit Construction Example 2)

[0129] Figure 5 This is a circuit diagram illustrating the circuit construction of the comparator according to Circuit Construction Example 2. The comparator 50B according to Circuit Construction Example 2 includes a differential amplifier 51 and a first capacitor element C. 21 Second capacitor element C 22 Third capacitor element C 23 First switching transistor PT 23 Second switching transistor PT 24 .

[0130] First switching transistor PT 23 Second switching transistor PT 24 This is an example of an automatic zero-adjustment switch. Here, for example, a P-channel MOS transistor is used as the first switching transistor PT. 23 Second switching transistor PT 24 However, N-channel MOS transistors can also be used.

[0131] Differential amplifier 51 includes a first differential transistor PT 21 Second differential transistor PT 22 Current source I 21 First load transistor NT 21and a second load transistor NT 22 Here, a P-channel MOS transistor is used as the first differential transistor PT 21 and the second differential transistor PT 22 A N-channel MOS transistor is used as the first load transistor NT 21 and the second load transistor NT 22 Furthermore, these differential transistors and load transistors can also be composed of opposite channels (opposite conductivity types).

[0132] In the differential amplifier 51, the first differential transistor PT 21 and the second differential transistor PT 22 The respective source electrodes are connected to each other to form a differential pair that performs differential operation. A current source I 21 is connected between the source common connection node of the first differential transistor PT 21 and the second differential transistor PT 22 and the node of the power supply voltage V DD The first load transistor NT 21 has a diode connection configuration in which the gate electrode and the drain electrode are connected to each other, and the first load transistor NT 21 is connected in series with the first differential transistor PT 21 That is, the respective drain electrodes of the first load transistor NT 21 and the first differential transistor PT 21 are connected to each other.

[0133] The second load transistor NT 22 is connected in series with the second differential transistor PT 22 That is, the respective drain electrodes of the second load transistor NT 22 and the second differential transistor PT 22 are connected to each other. Furthermore, the respective gate electrodes of the first load transistor NT 21 and the second load transistor NT 22 are connected to each other to constitute a current mirror circuit.

[0134] In addition, the common connection node between the second differential transistor PT 22 and the second load transistor NT 22 serves as an output node of the differential amplifier 51, and an output signal OUT is led out from this output node through an output terminal T 20 The respective source electrodes of the first load transistor NT 21 and the second load transistor NT 22 are connected to a low-potential side power supply (for example, ground GND).

[0135] A first capacitance element C 21 is connected between the pixel signal VVSL input terminal T 21 and the gate electrode of the first differential transistor PT 21 and functions as an input capacitor of the pixel signal V VSL The second capacitive element C 22 is connected between the input terminal T RAMP of the reference signal V 22 of the ramp wave and the gate electrode of the first differential transistor PT 21 and functions as an input capacitor of the reference signal V RAMP Thus, the first differential transistor PT 21 uses as a gate input a signal obtained by synthesizing (adding) the pixel signal V 21 and the reference signal V 22 VSL RAMP

[0136] The first switch transistor PT 23 is connected between the gate electrode and the drain electrode of the first differential transistor PT 21 The second switch transistor PT 24 is connected between the gate electrode and the drain electrode of the second differential transistor PT 22 The first switch transistor PT 23 and the second switch transistor PT 24 are turned on / off controlled by a drive signal AZ input from the timing control unit 16 shown in Fig. Figure 1 via the input terminal T 23 so as to selectively perform auto-zero (initialization operation).

[0137] The third capacitive element C 23 is connected between the gate electrode of the second differential transistor PT 22 and the input terminal T 24 of a predetermined voltage REF. Thus, the second differential transistor PT 22 inputs as a gate the predetermined voltage REF supplied through the terminal T 23 via the third capacitive element C 24 . The predetermined voltage REF is an arbitrary constant voltage such as a power supply voltage V DD level or a ground (GND) level. Here, the predetermined voltage REF is set to the GND level.

[0138] According to the comparator 50B of the above-described circuit configuration example 2, since the input voltage of the differential amplifier 51 at the time of inversion of the output signal OUT of the differential amplifier 51 does not change with the signal amount of the pixel 20 and is constant, it is possible to reduce the power supply voltage V DD ​​​(For example, about 1.3 V). As a result, since it is possible to reduce the power consumption of the A / D conversion unit 14, it is possible to reduce the power consumption of the CMOS image sensor 1A.

[0139] (Circuit configuration example 3)

[0140] Figure 6 is a circuit diagram showing a circuit configuration of a comparator according to the circuit configuration example 3. The comparator 50C according to the circuit configuration example 3 includes a first capacitance element C 31 , a second capacitance element C 32 , an input transistor PT 31 , a switching transistor PT 32 , a first current source transistor NT 31 , and a second current source transistor NT 32 .

[0141] The switching transistor PT 32 is an example of an auto-zero switch. Here, for example, as the switching transistor PT 32 , a P-channel MOS transistor is used, but an N-channel MOS transistor can also be used. A predetermined bias voltage V 31 is applied to the gate electrode of the first current source transistor NT bias1 . A predetermined bias voltage V 32 is applied to the gate electrode of the second current source transistor NT bias2 .

[0142] The first current source transistor NT 31 , the input transistor PT 31 , and the second current source transistor NT 32 are connected in series between a node of the power supply voltage V DD and a low-potential side power supply (for example, ground GND) in this order. Also, a common connection node between the input transistor PT 31 and the second current source transistor NT 32 serves as an output node from which an output signal OUT is led through an output terminal T 30 .

[0143] The first capacitance element C 31 is connected between the input terminal T VSL of the pixel signal V 31 and the gate electrode of the input transistor PT 31 , and serves as an input capacitor of the pixel signal V VSL . The second capacitance element C 32 is connected between the input terminal T RAMP of the reference signal V 32 of the ramp wave and the gate electrode of the input transistor PT 31Between the gate electrodes, and used as a reference signal V RAMP The input capacitor. Therefore, the input transistor PT 31 Using the first capacitor element C 31 Second capacitor element C 32 pixel signal V VSL and reference signal V RAMP The signal obtained by synthesis (addition) is used as the gate input.

[0144] Switching transistor PT 32 Connected to the input transistor PT 31 Between the gate and drain electrodes of the switching transistor PT. 32 By from Figure 1 The timing control unit 16 shown is connected via input terminal T 33 The input drive signal AZ is used for on / off control, thereby selectively performing automatic zeroing (initialization operation).

[0145] The comparator 50C according to the circuit construction example 3 described above is a comparator obtained by simplifying the comparator 50B according to the circuit construction example 2, which has a differential amplifier structure, and is capable of controlling the current flowing through the second current source transistor NT. 32 The current is reduced to about half that of the comparator 50B according to circuit construction example 2. As a result, compared with the case of comparator 50B according to circuit construction example 2, the power consumption of analog-to-digital conversion unit 14 can be further reduced, thereby reducing the power consumption of CMOS image sensor 1A.

[0146] (Circuit Construction Example 4)

[0147] Figure 7 This is a circuit diagram illustrating the circuit construction of the comparator according to circuit construction example 4. The comparator 50D according to circuit construction example 4 includes a first capacitor element C. 41 Input transistor PT 41 Input-side load current source I 41 Second capacitor element C 42 Output transistor PT 42 Output side load current source I 42 and switching transistor PT 43 .

[0148] Input transistor PT 41 Includes a P-channel MOS transistor and an input transistor PT. 41 Connected to signal line 32 and input-side load current source I 41 Between. Specifically, the input transistor PT 41 The source electrode is connected to signal line 32, and the drain electrode is connected to the input-side load current source I.41 One end is connected. Therefore, the pixel signal V VSL The signal is input to the input transistor PT via signal line 32. 41 The source electrode.

[0149] Input-side load current source I 41 The other end is connected to the low-potential side power supply (e.g., ground GND). Input-side load current source I 41 Input transistor PT 41 The series connection circuit with signal line 32 provides a constant current I. d1 Input-side load current source I 41 You can use, for example, an N-channel MOS transistor.

[0150] First capacitor element C 41 The reference signal V connected to the ramp wave RAMP Input terminal T 41 and input transistor PT 41 Between the gate electrodes, and used as a reference signal V RAMP The input capacitor. Therefore, in the input transistor PT 41 In the middle, the pixel signal V is input to the source electrode through signal line 32. VSL And through the first capacitor element C 41 A reference signal V for inputting a ramp wave to the gate electrode. RAMP .

[0151] Input transistor PT 41 For the reference signal V input to the gate electrode RAMP and the pixel signal V input to the source electrode VSL The difference between them (i.e., the input transistor PT) 41 Gate-source voltage V gs The voltage is amplified, and the amplified difference is output as the drain voltage from the drain electrode. Note that at the input transistor PT... 41 In order to suppress the back-gate effect, it is desirable to short-circuit the back-gate electrode and the source electrode.

[0152] Switching transistor PT 43 It is connected to the input transistor PT 41 An example of an automatic zero-adjustment switch between the gate and drain electrodes. Here, for example, it is a switching transistor PT. 43 A P-channel MOS transistor can be used, but an N-channel MOS transistor can also be used. Switching transistor PT 43 By from Figure 1 The timing control unit 16 shown is connected via input terminal T 42 The input drive signal AZ is used for on / off control, thereby selectively performing automatic zeroing (initialization operation).

[0153] second capacitor element C 42 with the input transistor PT 41 is connected in parallel. Specifically, one end of the second capacitor element C 42 is connected to the source electrode of the input transistor PT 41 , and the other end of the second capacitor element C 42 is connected to the drain electrode of the input transistor PT 41 .

[0154] output transistor PT 42 includes, for example, a P-channel MOS transistor, and the output transistor PT 42 is connected between the signal line 32 and an output-side load current source I 42 . Specifically, the source electrode of the output transistor PT 42 is connected to the signal line 32, and the drain electrode is connected to one end of the output-side load current source I 42 . Thus, the pixel signal V VSL is input to the source electrode of the output transistor PT 42 through the signal line 32.

[0155] The other end of the output-side load current source I 42 is connected to a low-potential-side power supply (for example, ground GND). The output-side load current source I 42 provides a constant current I d2 to the series connection circuit of the output transistor PT 42 and the signal line 32. The output-side load current source I 42 may be provided using, for example, an N-channel MOS transistor or the like.

[0156] The gate electrode of the output transistor PT 42 is connected to the drain electrode of the input transistor PT 41 . Thus, the drain voltage of the input transistor PT 41 is input to the gate electrode of the output transistor PT 42 . In order to suppress the back gate effect, it is desirable to short-circuit the back gate electrode and the source electrode of the output transistor PT 42 .

[0157] The output transistor PT 42 outputs, from the drain electrode, a signal OUT through the output terminal T 40 , which indicates whether or not the voltage difference between the pixel signal V VSL input to the source electrode through the signal line 32 and the drain voltage of the input transistor PT 41 input to the gate electrode exceeds a predetermined threshold voltage.

[0158] Note that the circuit construction of comparator 50D according to circuit construction example 4 illustrated herein is an example, and this disclosure is not limited to this circuit construction. Specifically, in the input transistor PT 41 In the subsequent circuit construction, for example, it can be connected with the input transistor PT. 41 Parallel configuration suppresses input transistor PT 41 A clamped transistor with a reduced drain voltage when in the non-conducting state. Alternatively, it can be used with the input transistor PT. 41 The parallel configuration limits the input transistor PT independently of the potential of signal line 32. 41 The lower limit of the drain voltage of the clamped transistor.

[0159] The comparator 50D according to the circuit construction example 4 above has the following circuit construction: In the same simplified comparator as in circuit construction example 3, the load current source (corresponding to) connected to the signal line 32 is a load current source (corresponding to) Figure 2 The load current source I) in the circuit is shared as the load current source used in comparator 50D. In the case of comparator 50D according to circuit construction example 4, the power supply voltage V of comparator 50D is... DD The reduction in power consumption also enables the analog-to-digital conversion unit 14 to achieve low power consumption, thereby enabling the CMOS image sensor 1A to achieve low power consumption.

[0160] [Layered Chip Structure]

[0161] According to the first embodiment, the CMOS image sensor 1A has a stacked chip structure in which at least three semiconductor chips, such as a first-layer semiconductor chip, a second-layer semiconductor chip, and a third-layer semiconductor chip, are stacked. Figure 8 A schematic exploded perspective view of the stacked chip structure of the CMOS image sensor 1A according to the first embodiment is shown.

[0162] like Figure 8 As shown, the CMOS image sensor 1A according to the first embodiment has a stacked chip structure in which a first layer semiconductor chip 41, a second layer semiconductor chip 42 and a third layer semiconductor chip 43 are stacked.

[0163] Furthermore, a pixel array unit 11 is formed on the first-layer semiconductor chip 41, and the pixels 20 are arranged in a matrix-like two-dimensional arrangement in the pixel array unit 11. In addition, for example, pads 51 for external connection and power supply are provided at the left and right ends of the first-layer semiconductor chip 41.

[0164] An analog circuit unit of the A / D conversion unit 14, specifically, the comparator 141 of the A / D converter 140 is provided on the second layer semiconductor chip 42. A load current source unit 13 and a reference signal generation unit 17 are also provided on the second layer semiconductor chip 42. Note that, Figure 8 The arrangement of the load current source unit 13, the reference signal generation unit 17, and the comparator 141 on the second layer semiconductor chip 42 shown is an example, and is not limited to this arrangement example.

[0165] A digital circuit unit of the A / D conversion unit 14, specifically, the counter 142 of the A / D converter 140 is provided on the third layer semiconductor chip 43. A logic circuit unit 15 as a signal processing unit, the row selection unit 12, and an interface (I / F) 18 are also provided on the third layer semiconductor chip 43. Note that, Figure 8 The arrangement of the counter 142, the logic circuit unit 15, the row selection unit 12, and the interface 18 on the third layer semiconductor chip 43 shown is an example, and is not limited to this arrangement example.

[0166] For example, connection portions (VIA) 52, 53 that electrically connect the semiconductor chip 42 and the semiconductor chip 43 are provided on the left and right of the second layer semiconductor chip 42. Examples of the connection portions 52, 53 include through silicon vias (TSV) and metal-metal joints including Cu-Cu joints.

[0167] In the stacked chip structure described above, the signal line 32 (refer to Figure 1 ) that is wired for each pixel column in the pixel array unit 11 of the first layer semiconductor chip 41 and each load current source I (refer to Figure 2 ) of the load current source unit 13 provided on the second layer semiconductor chip 42 are electrically connected for each pixel column via the first layer connection portion 54 and the second layer connection portion 55. Further, the comparator 141 provided on the second layer semiconductor chip 42 and the counter 142 provided on the third layer semiconductor chip 43 are electrically connected for each pixel column via the second layer connection portion 56 and the third layer connection portion 57. Examples of the connection portion 54, the connection portion 55, the connection portion 56, and the connection portion 57 include through silicon vias (TSV) and metal-metal joints including Cu-Cu joints.

[0168] Note that in the example above, the analog circuit unit of the analog-to-digital converter 14 is formed in the second-layer semiconductor chip 42, and the digital circuit unit of the analog-to-digital converter 14 is formed in the third-layer semiconductor chip 43. However, the reverse configuration can also be used. That is, the digital circuit unit of the analog-to-digital converter 14 can be formed in the second-layer semiconductor chip 42, and the analog circuit unit of the analog-to-digital converter 14 can be formed in the third-layer semiconductor chip 43.

[0169] Furthermore, while the above example illustrates a three-layer stacked chip structure, the stacked chip structure is not limited to three layers and can also be four or more layers. In the case of a stacked structure with four or more layers, the analog circuit units and digital circuit units of the analog-to-digital conversion unit 14 can be distributed across the semiconductor chips of the second and subsequent layers.

[0170] As described above, in the CMOS image sensor 1A according to the first embodiment, the stacked chip structure has a stacked structure of three or more layers, and the analog circuit unit and digital circuit unit of the analog-to-digital conversion unit 14 are disposed (formed) on semiconductor chips of different layers, thereby enabling the following functions and effects to be achieved.

[0171] For example, such as Figure 9 As shown, when multiple systems (e.g., four systems) of analog-to-digital converters 140 are arranged in parallel for each pixel column and the number of rows read simultaneously is increased, in a two-layer stacked structure, the size of the semiconductor chip in the second layer and the overall chip size are increased by increasing the number of parallel analog-to-digital converters 140. On the other hand, by adopting a stacked structure of three or more layers and arranging the analog circuit units and digital circuit units of the analog-to-digital converter unit 14 on semiconductor chips in different layers, it is possible to increase the number of parallel analog-to-digital converters 140 while maintaining the chip size, which is mainly contributed by the semiconductor chip 41 in the first layer where the pixel array unit 11 is formed, thereby improving the frame rate.

[0172] Furthermore, according to the CMOS image sensor 1A of the first embodiment having a stacked chip structure of three or more layers, a process suitable for manufacturing pixels 20 can be applied to the first-layer semiconductor chip 41. In addition, in the above example, a low-cost process (e.g., 55nm process) suitable for manufacturing analog circuit units of the analog-to-digital converter unit 14 can be applied to the second-layer semiconductor chip 42, and a process suitable for manufacturing digital circuit units of the analog-to-digital converter unit 14 (e.g., 22nm process) can be applied to the third-layer semiconductor chip 43, thus optimizing characteristics and cost. In particular, advanced processes can be applied to the manufacturing of digital circuit units.

[0173] <Camera device according to the second embodiment>

[0174] Similar to the first embodiment, the imaging device employing the technology according to the present disclosure in the second embodiment includes a CMOS image sensor. Furthermore, the pixel array unit 11 is divided into multiple regions, such as two regions, in the column direction, and correspondingly, the signal line 32 is divided (e.g., two segments) into multiple signal lines in the length direction (column direction).

[0175] [Example of CMOS image sensor construction]

[0176] Figure 10 This is a block diagram schematically illustrating the outline of a system configuration of a CMOS image sensor, which is an example of a camera device applying the technology according to the second embodiment of this disclosure.

[0177] In the CMOS image sensor 1B according to the second embodiment, the pixel array units 11 arranged in a matrix of pixels 20 are, for example, divided into two regions 11A and 11B in the column direction. Correspondingly, the signal lines 32 are divided into first signal lines 32A (32A1 to 32A1) in the length direction (column direction) according to each pixel column. n ) and second signal line 32B (32B1~32B) n ).

[0178] Furthermore, two systems of load current source unit 13 and two systems of analog-to-digital converter unit 14 are provided corresponding to the two regions 11A and 11B of pixel array unit 11. Specifically, load current source unit 13A and analog-to-digital converter unit 14A are provided corresponding to region 11A of pixel array unit 11, and load current source unit 13B and analog-to-digital converter unit 14B are provided corresponding to region 11B of pixel array unit 11. For example, a logic circuit unit 15 serving as a signal processing unit is provided together for the two regions 11A and 11B of pixel array unit 11.

[0179] The circuit structure of each pixel 20 in the two regions 11A and 11B of the pixel array unit 11 and the structure of each analog-to-digital converter in the analog-to-digital conversion unit 14 are basically the same as those in the case of the CMOS image sensor 1A according to the first embodiment.

[0180] [Layered Chip Structure]

[0181] Figure 11 A schematic exploded perspective view of the stacked chip structure of the CMOS image sensor 1B according to the second embodiment is shown.

[0182] like Figure 11As illustrated, like the case of the CMOS image sensor 1A according to the first embodiment, the CMOS image sensor 1B according to the second embodiment also has a stacked chip structure in which at least three semiconductor chips such as the first layer's semiconductor chip 41, the second layer's semiconductor chip 42, and the third layer's semiconductor chip 43 are stacked.

[0183] Also, in the first layer's semiconductor chip 41, two regions 11A, 11B of the pixel array unit 11 in which the pixels 20 are two-dimensionally arranged in a matrix are sandwiched by connection portions (VIA) 54A, 54B for electrical connection with the second layer's semiconductor chip 42. Further, for example, pads 51 for external connection and power supply are provided at both ends of the first layer's semiconductor chip 41.

[0184] On the second layer's semiconductor chip 42, the analog circuit unit of the A / D conversion unit 14, specifically, the comparators 141A, 141B of the A / D converter 140 are provided. On the second layer's semiconductor chip 42, the load current source units 13A, 13B are also provided across the connection portions (VIA) 55A, 55B for electrical connection with the first layer's semiconductor chip 41.

[0185] Further, on the second layer's semiconductor chip 42, the reference signal generation unit 17 is preferably provided at a position at a distance from the comparators 141A, 141B. Here, the term "at a distance" means not only a case where the distance is strictly equal, but also a case where the distance is substantially equal, and various deviations due to design or manufacture are allowed.

[0186] Note that, Figure 11 The arrangement of the comparators 141A, 141B of the A / D converter 140, the load current source units 13A, 13B, and the reference signal generation unit 17 on the second layer's semiconductor chip 42 as illustrated is an example, and is not limited to this arrangement example.

[0187] On the third layer's semiconductor chip 43, the digital circuit unit of the A / D conversion unit 14, specifically, the counters 142A, 142B of the A / D converter 140 are provided. On the third layer's semiconductor chip 43, the logic circuit unit 15 as the signal processing unit, the row selection unit 12, and the interface (I / F) 18 are also provided.

[0188] Note that, Figure 11 The arrangement of the counters 142A, 142B of the A / D converter 140, the logic circuit unit 15, the row selection unit 12, and the interface 18 on the third layer's semiconductor chip 43 as illustrated is an example, and is not limited to this arrangement example.

[0189] In the stacked chip structure described above, the signal lines 32A, 32B wired in each pixel column in the two regions 11A, 11B of the semiconductor chip 41 of the first layer and the circuit units provided in the semiconductor chip 42 of the second layer corresponding to the two regions 11A, 11B are electrically connected in each pixel column through the connection portions 54A, 54B of the first layer and the connection portions 55A, 55B of the second layer.

[0190] More specifically, the first signal line 32A and each load current source I of the load current source unit 13A and the comparator 141A are electrically connected through the connection portion 54A of the first layer and the connection portion 55A of the second layer as the first connection portion. Further, the second signal line 32B, each load current source I of the load current source unit 13B, and the comparator 141B are electrically connected through the connection portion 54B of the first layer and the connection portion 55B of the second layer as the second connection portion.

[0191] Further, the comparators 141A, 141B provided in the semiconductor chip 42 of the second layer corresponding to the two regions 11A, 11B and the counters 142A, 142B provided on the semiconductor chip 43 of the third layer are electrically connected in each pixel column through the connection portions 56A, 56B of the second layer and the connection portions 57A, 57B of the third layer. Examples of the connection portions 54A, 54B, the connection portions 55A, 55B, the connection portions 56A, 56B, and the connection portions 57A, 57B include through silicon vias (TSVs) and metal-metal joints including Cu-Cu joints.

[0192] Note that, in the example described above, a case where the stacked chip structure is a three-layer stacked structure has been exemplified, but the stacked chip structure is not limited to a three-layer stacked structure and can be a four-layer or more stacked structure. In the case of a four-layer or more stacked structure, the analog circuit unit and the digital circuit unit of the A / D conversion unit 14 can be arranged dispersedly on the semiconductor chips of the second layer and subsequent layers.

[0193] [Electrical connection structure between semiconductor chips]

[0194] Next, the electrical connection structure between the semiconductor chip 41 of the first layer and the semiconductor chip 42 of the second layer and between the semiconductor chip 42 of the second layer and the semiconductor chip 43 of the third layer will be described.

[0195] (Electrical connection structure example 1)

[0196] Figure 12A An end surface view of the cut portion in the case of the electrical connection structure example 1 between semiconductor chips is shown. The electrical connection structure example 1 is an example in which a through silicon via (TSV) is used as an electrical connection portion between semiconductor chips. As shown in FIG. 17, the electrical connection structure example 1 includes a first connection portion 54A of the first layer and a second connection portion 55A of the second layer. The first connection portion 54A of the first layer and the second connection portion 55A of the second layer are electrically connected through the TSV 58A. Figure 12AAs shown, openings 61 for pads 51 for external connection or power supply are formed at both ends of the first layer semiconductor chip 41 in which the pixel array unit (pixel region) 11 is formed.

[0197] Further, in the electrical connection structure example 1, a through silicon via 62 is used as the electrical connection portion between the first layer semiconductor chip 41, the second layer semiconductor chip 42, and the third layer semiconductor chip 43. Further, the connection portions 54A (54B), 55A (55B) that electrically connect the first layer semiconductor chip 41 and the second layer semiconductor chip 42 are disposed close to the inside of the pixel array unit 11. As the connection portions 54A (54B), 55A (55B) in the pixel array unit 11, Cu-Cu bonding (direct bonding using a Cu electrode) is used.

[0198] (Electrical connection structure example 2)

[0199] Figure 12B An end surface view of the cut portion in the case of the electrical connection structure example 2 between the semiconductor chips is shown. In the electrical connection structure example 2, Cu-Cu bonding is used as the connection portions 54A (54B), 55A (55B) in the pixel array unit 11 between the first layer semiconductor chip 41 and the second layer semiconductor chip 42. For the connection portions outside the pixel array unit 11 between the second layer semiconductor chip 42 and the third layer semiconductor chip 43, a through silicon via 62 can be used, or Cu-Cu bonding can be used.

[0200] As described above, the CMOS image sensor 1B according to the second embodiment has a stacked chip structure with a stacked structure of three or more layers, and the analog circuit unit and the digital circuit unit of the analog-digital conversion unit 14 are disposed on the semiconductor chips of different layers, thereby being able to achieve the same effects and advantages as in the case of the CMOS image sensor 1A according to the first embodiment.

[0201] That is, it is possible to increase the number of parallel analog-digital converters 140 while maintaining the chip size in which the first layer semiconductor chip 41 in which the pixel array unit 11 is formed is mainly contributed, thereby being able to improve the frame rate. Further, it is possible to apply a process suitable for manufacturing the pixels 20 to the first layer semiconductor chip 41.

[0202] Further, in the case of the above example, it is possible to apply a low-cost process (for example, a 55 nm process) suitable for manufacturing the analog circuit unit of the analog-digital conversion unit 14 to the second layer semiconductor chip 42, and it is possible to apply a process (for example, a 22 nm process) suitable for manufacturing the digital circuit unit of the analog-digital conversion unit 14 to the third layer semiconductor chip 43, thereby being able to optimize the characteristics and the cost. In particular, it is possible to apply an advanced process to the manufacturing of the digital circuit unit.

[0203] Furthermore, in the CMOS image sensor 1B according to the second embodiment, the pixel array unit 11 is divided into multiple regions in the column direction, and correspondingly, the signal line 32 is divided into multiple signal lines in the length direction according to each pixel column. Therefore, the following functions and effects can be achieved.

[0204] like Figure 13 As shown, when the parasitic resistance of signal line 32 is R VSL The parasitic capacitance is C VSL The current flowing through the load current source I is I LM The transconductance of a MOS transistor is g. m At that time, the stabilization time of pixel P phase / D phase is changed from 1 / g m (∝1 / √I LM Parasitic resistance R VSL and parasitic capacitance C VSL Decision. By dividing signal line 32 into multiple signal lines, the parasitic resistance R of a single signal line can be reduced. VSL and parasitic capacitance C VSL For example, by splitting signal line 32 in two, the parasitic resistance R can be reduced. VSL and parasitic capacitance C VSL Halve.

[0205] Figure 14 This is a time series diagram for a horizontal time period (1H). The parasitic resistance R... VSL and parasitic capacitance C VSL By halving the time required, the settling time of the pixel P-phase / D-phase (the settling time of the signal line potential) can be shortened, thus reducing the time needed to read a line of pixel signals and increasing the frame rate. Furthermore, because the settling time can be shortened, such as... Figure 14 As shown, an idle period occurs within a horizontal time frame, thus power consumption can be reduced by stopping circuit operation during this idle period. Alternatively, without shortening the settling time, while maintaining the same horizontal time frame, the current I flowing through the load current source I can be increased. LM Reduce parasitic resistance R VSL and parasitic capacitance C VSL The amount reduced.

[0206] <Camera device according to the third embodiment>

[0207] The camera device according to the second embodiment has a structure in which the analog circuit unit of the analog-to-digital converter 14 is formed in the semiconductor chip 42 of the second layer, and the digital circuit unit of the analog-to-digital converter 14 is formed in the semiconductor chip 43 of the third layer. In contrast, the camera device according to the third embodiment has a structure in which the digital circuit unit of the analog-to-digital converter 14 is formed in the semiconductor chip 42 of the second layer, and the analog circuit unit of the analog-to-digital converter 14 is formed in the semiconductor chip 43 of the third layer.

[0208] [Example of CMOS image sensor construction]

[0209] Figure 15 This is a block diagram schematically illustrating the outline of a system configuration of a CMOS image sensor, which is an example of a camera device applying the technology according to the third embodiment of this disclosure.

[0210] The CMOS image sensor 1C according to the third embodiment is similar to that in the second embodiment in that the pixel array unit 11 is divided into two regions 11A and 11B in the column direction, and correspondingly, the signal line 32 is divided into first signal lines 32A (32A1 to 32A1) according to each pixel column. n ) and second signal line 32B (32B1~32B) n ).

[0211] Furthermore, corresponding to the two regions 11A and 11B of the pixel array unit 11, two systems of the load current source unit 13, two systems of the analog-to-digital converter unit 14, and two systems of the logic circuit unit 15 serving as signal processing units are provided. Specifically, the load current source unit 13A, the analog-to-digital converter unit 14A, and the logic circuit unit 15A are provided corresponding to region 11A of the pixel array unit 11, and the load current source unit 13B, the analog-to-digital converter unit 14B, and the logic circuit unit 15B are provided corresponding to region 11B of the pixel array unit 11.

[0212] The circuit structure of each pixel 20 in the two regions 11A and 11B of the pixel array unit 11 and the structure of each analog-to-digital converter in the analog-to-digital conversion unit 14 are basically the same as those in the case of the CMOS image sensor 1A according to the first embodiment.

[0213] [Layered Chip Structure]

[0214] Figure 16 A schematic exploded perspective view of the stacked chip structure of a CMOS image sensor 1C according to a third embodiment is shown.

[0215] like Figure 16As shown, like the case of the CMOS image sensor 1A according to the first embodiment, the CMOS image sensor 1C according to the third embodiment also has a stacked chip structure in which at least three semiconductor chips such as the semiconductor chip 41 of the first layer, the semiconductor chip 42 of the second layer, and the semiconductor chip 43 of the third layer are stacked.

[0216] Moreover, in the semiconductor chip 41 of the first layer, two regions 11A, 11B of the pixel array unit 11 in which the pixels 20 are two-dimensionally arranged in a matrix are sandwiched by connection portions (VIA) 54A, 54B for electrical connection with the semiconductor chip 42 of the second layer. In addition, for example, pads 51 for external connection and power supply are provided at both ends of the semiconductor chip 41 of the first layer.

[0217] On the semiconductor chip 42 of the second layer, the digital circuit unit of the A / D conversion unit 14, specifically, the counters 142A, 142B of the A / D converter 140 are provided. On the outside of the counters 142A, 142B, connection portions 56A, 56B for electrical connection with the semiconductor chip 43 of the third layer are provided.

[0218] On the semiconductor chip 42 of the second layer, in addition to the digital circuit unit of the A / D conversion unit 14, the logic circuit units 15A, 15B as signal processing units are provided. Between the logic circuit units 15A, 15B, connection portions 55A, 55B for relaying electrical connection between the semiconductor chip 41 of the first layer and the semiconductor chip 42 of the second layer are provided. On the semiconductor chip 42 of the second layer, an interface (I / F) 18 is also provided.

[0219] Note that, Figure 16 The arrangement of the counters 142A, 142B of the A / D converter 140, the logic circuit units 15A, 15B, and the interface 18 on the semiconductor chip 42 of the second layer shown is an example, and is not limited to this arrangement example.

[0220] On the semiconductor chip 43 of the third layer, the analog circuit unit of the A / D conversion unit 14, specifically, the comparators 141A, 141B of the A / D converter 140 are provided. On the outside of the comparators 141A, 141B, connection portions 57A, 57B for electrical connection with the semiconductor chip 42 of the second layer are provided.

[0221] On the semiconductor chip 43 of the third layer, in addition to the comparators 141A, 141B, load current source units 13A, 13B are provided which are electrically connected to the semiconductor chip 41 of the first layer via the connection portions 55A, 55B of the semiconductor chip 42 of the second layer and the connection portions (VIA) 58A, 58B. On the semiconductor chip 43 of the third layer, a row selection unit 12 is also provided. Further, on the semiconductor chip 43 of the third layer, it is preferable that the reference signal generation unit 17 is provided at a position which is equidistant from the comparators 141A, 141B and the like.

[0222] Note that, Figure 16 The arrangement of the comparators 141A, 141B, the load current source units 13A, 13B, the row selection unit 12, and the reference signal generation unit 17 of the analog-digital converter 140 on the semiconductor chip 43 of the third layer shown is an example, and is not limited to this arrangement example.

[0223] In the stacked chip structure described above, the signal lines 32A, 32B which are wired in each pixel column in the semiconductor chip 41 of the first layer and the load currents I of the load current source units 13A, 13B provided on the semiconductor chip 43 of the third layer are electrically connected in each pixel column via the connection portions 54A, 54B of the first layer, the connection portions 55A, 55B of the second layer, and the connection portions 58A, 58B of the third layer.

[0224] Further, the counters 142A, 142B provided on the semiconductor chip 42 of the second layer corresponding to the two regions 11A, 11B and the comparators 141A, 141B provided on the semiconductor chip 43 of the third layer are electrically connected in each pixel column via the connection portions 56A, 56B of the second layer and the connection portions 57A, 57B of the third layer. Examples of the connection portions 54A, 54B, the connection portions 55A, 55B, the connection portions 56A, 56B, the connection portions 57A, 57B, and the connection portions 58A, 58B include through silicon vias (TSVs) and metal-metal joints including Cu-Cu joints.

[0225] Note that, in the example described above, a case where the stacked chip structure is a three-layer stacked structure has been exemplified, but the stacked chip structure is not limited to a three-layer stacked structure, and can be a four-layer or more stacked structure. In the case of a four-layer or more stacked structure, it is possible to arrange the analog circuit units and the digital circuit units of the analog-digital conversion unit 14 dispersedly on the semiconductor chips of the second layer and subsequent layers.

[0226] As described above, in the CMOS image sensor 1C according to the third embodiment, the stacked chip structure has a stacked structure of three or more layers, and the analog circuit unit and the digital circuit unit of the A / D conversion unit 14 are formed on the semiconductor chips of different layers, and thus the same effects and advantages as in the case of the CMOS image sensor 1A according to the first embodiment can be achieved.

[0227] That is, it is possible to increase the number of parallel A / D converters 140 while maintaining the chip size mainly contributed by the first layer semiconductor chip 41 on which the pixel array unit 11 is formed, and thus it is possible to improve the frame rate. Further, it is possible to apply a process suitable for manufacturing the pixels 20 to the first layer semiconductor chip 41.

[0228] Further, in the case of the above example, it is possible to apply a process suitable for manufacturing the digital circuit unit of the A / D conversion unit 14 (for example, a 22 nm process) to the second layer semiconductor chip 42, and it is possible to apply a low-cost process suitable for manufacturing the analog circuit unit of the A / D conversion unit 14 (for example, a 55 nm process) to the third layer semiconductor chip 43, and thus it is possible to optimize the characteristics and the cost. In particular, it is possible to apply an advanced process to the manufacturing of the digital circuit unit.

[0229] Further, in the CMOS image sensor 1C according to the third embodiment, since the signal line 32 is divided into a plurality of signal lines in the length direction thereof, the same effects and advantages as in the case of the CMOS image sensor 1B according to the second embodiment can be achieved. That is, since it is possible to reduce the parasitic resistance R VSL and the parasitic capacitance C VSL of one signal line, it is possible to shorten the settling time of the signal line potential, and as a result, it is possible to shorten the time required to read the pixel signals of one row, and thus it is possible to improve the frame rate.

[0230] Further, since it is possible to shorten the settling time, a free time occurs within one horizontal period, and thus it is possible to reduce the power consumption by stopping the circuit operation during the free time. Alternatively, without shortening the settling time, it is possible to reduce the current I LM flowing through the load current source I by the same one horizontal period, and thus it is possible to reduce the parasitic resistance R VSL and the parasitic capacitance C VSL by the same amount.

[0231] Further, in the case of the CMOS image sensor 1C according to the third embodiment, since the interface 18 is provided in the semiconductor chip 42 of the second layer, compared to the case where the interface 18 is provided in the semiconductor chip 43 of the third layer, it is possible to reduce the parasitic resistance and parasitic capacitance related to the output of the interface 18. The output of the interface 18 is a high-speed signal, and it is important in design to reduce the parasitic resistance and parasitic capacitance of one layer.

[0232] <Camera according to fourth embodiment>

[0233] The fourth embodiment is a modification of the second embodiment, and is an example in which a storage region is secured in the semiconductor chip of the third layer.

[0234] Figure 17 A schematic exploded perspective view of a stacked chip structure of a CMOS image sensor that is an example of a camera according to the fourth embodiment of the technology according to the present disclosure is shown.

[0235] In the stacked chip structure in which at least three semiconductor chips such as the semiconductor chip 41 of the first layer, the semiconductor chip 42 of the second layer, and the semiconductor chip 43 of the third layer are stacked, the configurations of the semiconductor chip 41 of the first layer and the semiconductor chip 42 of the second layer are the same as in the case of the CMOS image sensor 1B according to the second embodiment.

[0236] The CMOS image sensor 1D according to the fourth embodiment has a configuration in which, on the semiconductor chip 43 of the third layer, in addition to the counters 142A, 142B that are digital circuit units of the analog-digital conversion unit 14, the logic circuit unit 15 that is a signal processing unit, the row selection unit 12, and the interface 18, a storage unit 71 is also provided. The storage unit 71 can be used, for example, to temporarily store data during desired signal processing in the logic circuit unit 15.

[0237] <Camera according to fifth embodiment>

[0238] The fifth embodiment is a modification of the fourth embodiment, and is an example in which an AI (Artificial Intelligence) region is secured in the semiconductor chip of the third layer instead of a storage region.

[0239] Figure 18 A schematic exploded perspective view of a stacked chip structure of a CMOS image sensor that is an example of a camera according to the fifth embodiment of the technology according to the present disclosure is shown.

[0240] In the stacked chip structure in which four semiconductor chips such as the first layer's semiconductor chip 41, the second layer's semiconductor chip 42, the third layer's semiconductor chip 43, and the fourth layer's semiconductor chip 44 are stacked, the first layer's semiconductor chip 41 and the second layer's semiconductor chip 42 have the same configuration as in the case of the CMOS image sensor 1B according to the second embodiment.

[0241] The CMOS image sensor 1E according to the fifth embodiment has a configuration in which, on the third layer's semiconductor chip 43, in addition to the counters 142A, 142B that are the digital circuit units of the analog-digital conversion units 14, the logic circuit unit 15 that is the signal processing unit, the row selection unit 12, and the interface 18, the AI circuit 72 is provided. The AI circuit 72 can be used for, for example, image processing and various settings of analog signals.

[0242] <Camera according to the sixth embodiment>

[0243] The sixth embodiment is a modification of the second embodiment, and is an example in which the stacked chip structure has a stacked structure of four layers.

[0244] Figure 19 A schematic exploded perspective view of a stacked chip structure of a CMOS image sensor that is an example of a camera according to the sixth embodiment of the technology according to the present disclosure is shown.

[0245] As Figure 19 shown, the CMOS image sensor 1F according to the sixth embodiment has a stacked chip structure in which four semiconductor chips such as the first layer's semiconductor chip 41, the second layer's semiconductor chip 42, the third layer's semiconductor chip 43, and the fourth layer's semiconductor chip 44 are stacked.

[0246] The first layer's semiconductor chip 41, the second layer's semiconductor chip 42, and the third layer's semiconductor chip 43 have the same configuration as in the case of the CMOS image sensor 1B according to the second embodiment. That is, in the first layer's semiconductor chip 41, two divided regions 11A, 11B of the pixel array unit 11 and the like are formed, and on the second layer's semiconductor chip 42, the comparators 141A, 141B of the analog-digital converter 140, the load current source units 13A, 13B, the reference signal generation unit 17, and the like are provided. The first layer's semiconductor chip 41 and the second layer's semiconductor chip 42 are electrically connected by the first layer's connection portions 54A, 54B and the second layer's connection portions 55A, 55B.

[0247] Counters 142A, 142B of an analog-digital converter 140, a logic circuit unit 15, and a row selection unit 12 are provided on the semiconductor chip 43 of the third layer. The comparators 141A, 141B on the semiconductor chip 42 of the second layer and the counters 142A, 142B on the semiconductor chip 43 of the third layer are electrically connected through the second-layer connection portions 56A, 56B and the third-layer connection portions 57A, 57B.

[0248] A storage unit 71 and an interface 18 are provided on the semiconductor chip 44 of the fourth layer. The semiconductor chip 43 of the third layer and the semiconductor chip 44 of the fourth layer are connected, for example, by CoW (chip on wafer). The logic circuit unit 15 on the semiconductor chip 43 of the third layer and the storage unit 71 on the semiconductor chip 44 of the fourth layer are electrically connected through the third-layer connection portion 63 and the fourth-layer connection portion 64. The storage unit 71 can be used, for example, to temporarily store data during desired signal processing in the logic circuit unit 15.

[0249] <Imaging device according to the seventh embodiment>

[0250] The seventh embodiment is a modification of the sixth embodiment, and is an example in which an AI region is secured in the semiconductor chip of the fourth layer instead of a storage region.

[0251] Figure 20 A schematic exploded perspective view of a stacked chip structure of a CMOS image sensor, which is an example of an imaging device to which the technology according to the present disclosure is applied, is shown.

[0252] As Figure 20 shown, similarly to the CMOS image sensor 1E according to the sixth embodiment, the CMOS image sensor 1G according to the seventh embodiment also has a stacked chip structure in which four semiconductor chips such as the semiconductor chip 41 of the first layer, the semiconductor chip 42 of the second layer, the semiconductor chip 43 of the third layer, and the semiconductor chip 44 of the fourth layer are stacked.

[0253] In the above-described stacked chip structure, the configurations of the semiconductor chip 41 of the first layer, the semiconductor chip 42 of the second layer, and the semiconductor chip 43 of the third layer are the same as in the case of the CMOS image sensor 1F according to the sixth embodiment. Also, instead of the storage unit 71, an AI circuit 72 is provided on the semiconductor chip 44 of the fourth layer. The semiconductor chip 43 of the third layer and the semiconductor chip 44 of the fourth layer are connected, for example, by CoW, and the logic circuit unit 15 on the semiconductor chip 43 of the third layer and the AI circuit 72 on the semiconductor chip 44 of the fourth layer are electrically connected through the third-layer connection portion 63 and the fourth-layer connection portion 64. The AI circuit 72 can be used, for example, for image processing and various settings for analog signals, and the like.

[0254] <Camera according to the eighth embodiment>

[0255] The eighth embodiment is a modification of the seventh embodiment, and is an example in which the size of the semiconductor chip of the fourth layer is made smaller than the sizes of the other semiconductor chips.

[0256] Figure 21 A schematic exploded perspective view of a stacked chip structure of a CMOS image sensor, which is an example of a camera to which the technology according to the present disclosure is applied, according to the eighth embodiment is shown.

[0257] As Figure 21 shown, the CMOS image sensor 1H according to the eighth embodiment also has a stacked chip structure in which four semiconductor chips, i.e., semiconductor chips such as the semiconductor chip 41 of the first layer, the semiconductor chip 42 of the second layer, the semiconductor chip 43 of the third layer, and the semiconductor chip 44 of the fourth layer, are stacked. However, the size of the semiconductor chip 44 of the fourth layer is made smaller than the sizes of the other semiconductor chips 41, 42, and 43.

[0258] The semiconductor chip 43 of the third layer and the semiconductor chip 44 of the fourth layer are connected, for example, by CoW, and the logic circuit unit 15 on the semiconductor chip 43 of the third layer and the AI circuit 72 on the semiconductor chip 44 of the fourth layer are electrically connected through the connection portion 63 of the third layer and the connection portion 64 of the fourth layer. The AI circuit 72 can be used, for example, for image processing and various settings for analog signals, and the like.

[0259] In the CMOS image sensor 1H according to the eighth embodiment having the above-described stacked chip structure, an advanced process (for example, a 12 nm process) can be applied to the semiconductor chip 44 of the fourth layer. Also, since the size of the semiconductor chip 44 of the fourth layer is made smaller than the sizes of the other semiconductor chips 41, 42, and 43, a large number of semiconductor chips 44 can be manufactured from one wafer, and thus a cost reduction can be achieved.

[0260] <Modification>

[0261] Although the technology according to the present disclosure has been described above based on the preferred embodiments, the technology according to the present disclosure is not limited to these embodiments. The configuration and structure of the camera described in the above embodiments are exemplary, and can be changed as appropriate.

[0262] <Application Example>

[0263] For example, as Figure 22 shown, the camera according to the above-described embodiments can be used for various devices that sense light such as visible light, infrared light, ultraviolet light, and X-rays. Specific examples of the various devices are listed below.

[0264] • An apparatus for photographing an image for appreciation, such as a digital camera or a portable apparatus having a camera function.

[0265] • An apparatus for transportation, such as a vehicle-mounted sensor that photographs an image of the front, rear, surroundings, and interior of a car, and the like, for safe driving such as automatic stop, recognition of the state of a driver, and the like, a monitoring camera that monitors a traveling vehicle and a road, and a distance measuring sensor that measures the distance between vehicles, and the like.

[0266] • An apparatus for a household electric appliance such as a television, a refrigerator, and an air conditioner, for photographing an image of a user's gesture and performing an operation of the device according to the gesture.

[0267] • An apparatus for medical care or health care, such as an endoscope, or a device that performs angiography by receiving infrared light, and the like.

[0268] • An apparatus for security, such as a monitoring camera for preventing crime, or a camera for personal authentication, and the like.

[0269] • An apparatus for beauty, such as a skin measuring instrument that photographs a skin, or a microscope that photographs a scalp.

[0270] • An apparatus for sports, such as a sports camera or a wearable camera for sports and the like.

[0271] • An apparatus for agriculture, such as a camera for monitoring the state of a field and a crop.

[0272]

[0273] The technology according to the present disclosure can be applied to various products. Hereinafter, a more specific application example will be described.

[0274] [Electronic device of the present disclosure]

[0275] Here, a case where the present disclosure is applied to an electronic device such as a camera system such as a digital camera or a video camera, a mobile terminal device (for example, a mobile phone) having a camera function, or a copying machine using a camera apparatus as an image reading unit will be described.

[0276] (Example of camera system)

[0277] Figure 23 is a block diagram showing a configuration example of a camera system that is an example of the electronic device of the present disclosure.

[0278] As Figure 23 ​As shown, the imaging system 100 according to the present example includes an imaging optical system 101 including a lens group or the like, an imaging unit 102, a DSP (digital signal processor) circuit 103, a frame memory 104, a display device 105, a recording device 106, an operation system 107, and a power supply system 108, and the like. Also, the DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, the operation system 107, and the power supply system 108 are connected to each other through a bus 109.

[0279] The imaging optical system 101 acquires incident light (image light) from a subject, and images the incident light on an imaging surface of the imaging unit 102. The imaging unit 102 converts, for each pixel, an amount of light of the incident light imaged on the imaging surface by the optical system 101 into an electric signal, and outputs the electric signal as a pixel signal. The DSP circuit 103 performs general camera signal processing such as white balance processing, demosaicing processing, and gamma correction processing, and the like.

[0280] The frame memory 104 is appropriately used to store data in the process of signal processing by the DSP circuit 103. The display device 105 includes a panel-type display device such as a liquid crystal display device or an organic EL (Electro Luminescence) display device, and the display device 105 displays a moving image or a still image captured by the imaging unit 102. The recording device 106 records a moving image or a still image captured by the imaging unit 102 on a recording medium such as a portable semiconductor memory, an optical disk, or a hard disk drive (HDD).

[0281] The operation system 107 issues operation instructions for various functions of the imaging device 100 under the operation of a user. The power supply system 108 appropriately supplies various power supplies used as operation power for the DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, and the operation system 107 to these supply targets.

[0282] In the imaging system 100 having the above-described configuration, as the imaging unit 102, the imaging device according to each of the above-described embodiments can be used. According to the imaging device, it is possible to increase the number of parallel analog-digital converters while maintaining the chip size mainly contributed by the pixel chip formed by arranging the pixels, and thus it is possible to improve the frame rate.

[0283] [Application Example of Mobile Body]

[0284] The technology according to the present disclosure (this technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented as an imaging device mounted on any of the following types of mobile bodies, such as a car, an electric car, a hybrid car, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, a construction machine, or an agricultural machine (tractor).

[0285] Figure 24 is a block diagram showing an example of a schematic configuration of a vehicle control system as an example of a mobile body control system to which the technology according to the present disclosure can be applied.

[0286] The vehicle control system 12000 includes a plurality of electronic control units connected to one another through a communication network 12001. In Figure 24 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, a vehicle exterior information detection unit 12030, a vehicle interior information detection unit 12040, and an integrated control unit 12050. Further, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound image output unit 12052, and a vehicle-mounted network interface (I / F) 12053 are shown.

[0287] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle in accordance with various programs. For example, the drive system control unit 12010 functions as a control device for each of devices such as a drive force generation device such as an internal combustion engine or a drive motor, which generates the drive force of the vehicle; a drive force transmission mechanism that transmits the drive force to wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a brake device that generates the braking force of the vehicle.

[0288] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body in accordance with various programs. For example, the body system control unit 12020 functions as a control device for each of devices such as a keyless entry system; a smart key system; a power window device; and various lamps such as a headlamp, a tail lamp, a brake lamp, a signal lamp, or a fog lamp. In this case, radio waves transmitted from a portable device that substitutes for a key or signals of various switches can be input to the body system control unit 12020. The body system control unit 12020 receives the input of these radio waves or signals, and controls the door lock device, the power window device, the lamps, and the like of the vehicle.

[0289] The vehicle exterior information detection unit 12030 detects information outside the vehicle on which the vehicle control system 12000 is mounted. For example, a camera unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to capture an image of the outside of the vehicle, and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can perform object detection processing or distance detection processing on a pedestrian, a vehicle, an obstacle, a sign, or a letter on a road surface, and the like.

[0290] The camera unit 12031 is an optical sensor that receives light and outputs an electric signal corresponding to the amount of received light. The camera unit 12031 can output the electric signal as an image, or can output the electric signal as ranging information. Furthermore, the light received by the camera unit 12031 can be visible light or non-visible light such as infrared rays.

[0291] The vehicle interior information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 for detecting the state of the driver is connected to the vehicle interior information detection unit 12040. For example, the driver state detection unit 12041 includes a camera that captures an image of the driver, and based on detection information input from the driver state detection unit 12041, the vehicle interior information detection unit 12040 can calculate the degree of fatigue or the degree of concentration of the driver, or can determine whether the driver is dozing off.

[0292] Based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, the microcomputer 12051 can calculate a control target value of the driving force generation device, the steering mechanism, or the brake device, and can output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control for the purpose of realizing an advanced driver assistance system (ADAS) function including collision avoidance or impact mitigation of the vehicle, following travel based on an inter-vehicle distance, vehicle speed maintenance travel, vehicle collision warning, or lane departure warning of the vehicle, and the like.

[0293] Furthermore, the microcomputer 12051 can control the driving force generation device, the steering mechanism, or the brake device, and the like, based on the information around the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, thereby performing cooperative control for the purpose of autonomous driving of the vehicle without relying on the operation of the driver, or the like.

[0294] Further, the microcomputer 12051 can output a control command to the body system control unit 12020 on the basis of information outside the vehicle acquired by the outside information detecting unit 12030. For example, the microcomputer 12051 can control a headlamp in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside information detecting unit 12030, thereby performing cooperative control for anti-dazzling, such as switching a high beam to a low beam.

[0295] The sound image output unit 12052 transmits an output signal of at least one of a sound or an image to an output device capable of visually or aurally notifying a passenger on board or outside the vehicle of information. In Figure 24 Examples of the output device are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 can include at least one of an on-board display or a head-up display, for example.

[0296] Figure 25 FIG. 12 is a view showing an example of a mounting position of the imaging unit 12031.

[0297] In Figure 25 The vehicle 12100 includes imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.

[0298] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as a front nose, a rearview mirror, a rear bumper, a rear door, and an upper portion of a windshield inside a cabin of the vehicle 12100, for example. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper portion of the windshield inside the cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the rearview mirror mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or the rear door mainly acquires an image of the rear of the vehicle 12100. The front images acquired by the imaging units 12101 and 12105 are mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, a traffic signal, a traffic sign, or a lane, for example.

[0299] Note that Figure 25Examples of the imaging ranges of the imaging units 12101 to 12104 are shown. The imaging range 12111 represents the imaging range of the imaging unit 12101 provided to the front nose, the imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging units 12102 and 12103 provided to the side mirrors, and the imaging range 12114 represents the imaging range of the imaging unit 12104 provided to the rear bumper or the rear door. For example, an overhead image of the vehicle 12100 viewed from above is obtained by superimposing image data acquired by the imaging units 12101 to 12104.

[0300] At least one of the imaging units 12101 to 12104 can have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 can be a stereo camera including a plurality of imaging elements, or can be an imaging element having pixels for phase difference detection.

[0301] For example, the microcomputer 12051 can obtain distances to each three-dimensional object within the imaging ranges 12111 to 12114 and changes in the distances over time (relative speeds with respect to the vehicle 12100) on the basis of the distance information obtained from the imaging units 12101 to 12104, and thereby extract a three-dimensional object that is traveling in almost the same direction as the vehicle 12100 at a predetermined speed (for example, greater than or equal to 0 km / h), particularly a three-dimensional object closest on the travel road of the vehicle 12100, as a preceding vehicle. Further, the microcomputer 12051 can set a vehicle-to-vehicle distance to be ensured behind the preceding vehicle in advance, and can perform automatic brake control (including follow-up stop control) and automatic acceleration control (including follow-up start control), and the like. As described above, it is possible to perform cooperative control for the purpose of automatic driving or the like in which the vehicle autonomously travels without depending on the operation of the driver.

[0302] For example, on the basis of the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can classify three-dimensional object data on three-dimensional objects into a two-wheeled vehicle, a normal vehicle, a large vehicle, a pedestrian, and other three-dimensional objects such as a utility pole, extract the three-dimensional object data, and automatically avoid obstacles using the three-dimensional object data. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually recognized by the driver of the vehicle 12100 and obstacles that are difficult to be visually recognized. Also, the microcomputer 12051 determines a collision risk indicating a risk of collision with each obstacle, and when the collision risk is equal to or higher than a set value and a collision is likely to occur, the microcomputer 12051 can output a warning to the driver through the audio speaker 12061 or the display unit 12062, or perform forced deceleration or avoidance steering through the drive system control unit 12010, and thereby perform driving assistance for avoiding a collision.

[0303] At least one of the imaging units 12101 to 12104 can be an infrared camera for detecting infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not the pedestrian is present in an image captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points in an image captured by the imaging units 12101 to 12104 as an infrared camera, and determining whether or not an object represented by a series of the feature points is a pedestrian by performing pattern matching processing. When the microcomputer 12051 determines that a pedestrian is present in an image captured by the imaging units 12101 to 12104 and recognizes the pedestrian, the sound image output unit 12052 controls the display unit 12062 so that a square contour line for emphasis is superimposed and displayed on the recognized pedestrian. In addition, the sound image output unit 12052 can control the display unit 12062 so that an icon or the like representing the pedestrian is displayed at a desired position.

[0304] An example of a vehicle control system to which the technology according to the present disclosure is applicable has been described above. The technology according to the present disclosure is applicable, for example, to the imaging unit 12031 and the like in the above-described configuration. Moreover, by applying the technology according to the present disclosure to the imaging unit 12031 and the like, it is possible to increase the number of parallel analog-digital converters while maintaining the chip size that is dominated by the contribution of the pixel chip formed by arranging pixels, and thus it is possible to improve the frame rate.

[0305] <Configuration to which the present disclosure is applicable>

[0306] Note that the present disclosure can also have the following configuration.

[0307] <<A. Imaging device>>

[0308] [A-01]

[0309] An imaging device having a stacked chip structure in which at least three semiconductor chips including a first layer semiconductor chip, a second layer semiconductor chip, and a third layer semiconductor chip are stacked, the imaging device including:

[0310] a pixel array unit in which pixels are two-dimensionally arranged in a matrix, and the pixel array unit is formed on the first layer semiconductor chip;

[0311] an analog circuit unit of an analog-digital conversion unit that converts an analog pixel signal read from each pixel of the pixel array unit through a signal line into a digital pixel signal, and the analog circuit unit is provided on one of the second layer semiconductor chip and the third layer semiconductor chip; and

[0312] a digital circuit unit of the analog-digital conversion unit is provided on the other of the second-layer semiconductor chip and the third-layer semiconductor chip.

[0313] [A-02]

[0314] The image pickup device according to the above [A-01], wherein

[0315] the analog-digital conversion unit includes a plurality of analog-digital converters provided corresponding to the pixel columns of the pixel array unit,

[0316] the analog-digital converter includes:

[0317] a comparator that compares the analog pixel signal with a reference signal of a ramp wave, and

[0318] a counter that measures a time from a timing of generation of the reference signal to a timing at which the analog pixel signal crosses the reference signal of the ramp wave,

[0319] the comparator of the analog-digital conversion unit is provided on one of the second-layer semiconductor chip and the third-layer semiconductor chip, and

[0320] the counter of the analog-digital conversion unit is provided on the other of the second-layer semiconductor chip and the third-layer semiconductor chip.

[0321] [A-03]

[0322] The image pickup device according to the above [A-02], wherein

[0323] the comparator of the analog-digital conversion unit and a load current source connected to the signal line are provided on the second-layer semiconductor chip, and

[0324] the counter of the analog-digital conversion unit, the logic circuit unit, and the interface are provided on the third-layer semiconductor chip.

[0325] [A-04]

[0326] The image pickup device according to the above [A-03], wherein

[0327] a storage unit is further provided on the third-layer semiconductor chip in addition to the counter of the analog-digital conversion unit, the logic circuit unit, and the interface.

[0328] [A-05]

[0329] The image pickup device according to the above [A-03], wherein

[0330] an AI circuit is further provided on the third-layer semiconductor chip in addition to the counter of the analog-digital conversion unit, the logic circuit unit, and the interface.

[0331] [A-06]

[0332] The imaging device according to the above [A-03], further comprising:

[0333] The semiconductor chip of the fourth layer, wherein

[0334] The storage unit is provided on the semiconductor chip of the fourth layer.

[0335] [A-07]

[0336] The imaging device according to the above [A-03], further comprising:

[0337] The semiconductor chip of the fourth layer, wherein

[0338] The AI circuit is provided on the semiconductor chip of the fourth layer.

[0339] [A-08]

[0340] The imaging device according to the above [A-07], wherein

[0341] The semiconductor chip of the fourth layer is smaller in size than the semiconductor chips of the other layers.

[0342] [A-09]

[0343] The imaging device according to the above [A-02], wherein

[0344] The counter of the analog-digital conversion unit, the logic circuit unit, and the interface are provided on the semiconductor chip of the second layer, and

[0345] The comparator of the analog-digital conversion unit and the load current source connected to the AND signal line are provided on the semiconductor chip of the third layer.

[0346] [A-10]

[0347] The imaging device according to any one of the above [A-01] to the above [A-09], wherein

[0348] The analog-digital conversion unit includes a plurality of system analog-digital conversion units including a first analog-digital conversion unit and a second analog-digital conversion unit that convert each of analog pixel signals read in parallel from each pixel in a plurality of pixel rows of the pixel array unit into a digital pixel signal.

[0349] [A-11]

[0350] The imaging device according to the above [A-10], wherein

[0351] The signal line is divided into a plurality of signal lines including a first signal line and a second signal line, with respect to each pixel column, in a length direction of the signal line, corresponding to a plurality of systems of analog-digital conversion units.

[0352] [A-12]

[0353] The imaging device according to [A-11] above, wherein

[0354] The first connection portion connecting the first signal line and the first analog-digital conversion unit and the second connection portion connecting the second signal line and the second analog-digital conversion unit are disposed close to each other within a region of the pixel array unit.

[0355] [A-13]

[0356] The imaging device according to [A-12] above, wherein

[0357] The first connection portion and the second connection portion connect the semiconductor chip of the first layer and the semiconductor chip of the second layer by direct bonding using a Cu electrode.

[0358] <<B. Electronic device>>

[0359] [B-01]

[0360] An electronic device including:

[0361] An imaging device having a stacked chip structure in which at least three semiconductor chips including a semiconductor chip of a first layer, a semiconductor chip of a second layer, and a semiconductor chip of a third layer are stacked, the imaging device including:

[0362] a pixel array unit in which pixels are arranged in a matrix shape two-dimensionally and formed on the semiconductor chip of the first layer;

[0363] an analog circuit unit of an analog-digital conversion unit that converts an analog pixel signal read from each pixel of the pixel array unit through a signal line into a digital pixel signal, and that is provided on one of the semiconductor chip of the second layer and the semiconductor chip of the third layer; and

[0364] a digital circuit unit of the analog-digital conversion unit that is provided on the other of the semiconductor chip of the second layer and the semiconductor chip of the third layer.

[0365] [B-02]

[0366] The electronic device according to [B-01] above, wherein

[0367] The analog-digital conversion unit includes a plurality of analog-digital converters provided corresponding to the pixel columns of the pixel array unit,

[0368] The analog-digital converter includes:

[0369] a comparator that compares the analog pixel signal with a reference signal of a ramp wave; and

[0370] a counter that measures a time from a timing of generation of the reference signal to a timing at which the analog pixel signal crosses the reference signal of the ramp wave,

[0371] The comparator of the analog-digital conversion unit is provided on one of the semiconductor chips of the second layer and the semiconductor chips of the third layer, and

[0372] The counter of the analog-digital conversion unit is provided on the other of the semiconductor chips of the second layer and the semiconductor chips of the third layer.

[0373] [B-03]

[0374] The electronic device according to the above [B-02], wherein

[0375] The comparator of the analog-digital conversion unit and a load current source connected to the signal line are provided on the semiconductor chip of the second layer, and

[0376] The counter of the analog-digital conversion unit, the logic circuit unit, and the interface are provided on the semiconductor chip of the third layer.

[0377] [B-04]

[0378] The electronic device according to the above [B-03], wherein

[0379] The storage unit is further provided on the semiconductor chip of the third layer in addition to the counter of the analog-digital conversion unit, the logic circuit unit, and the interface.

[0380] [B-05]

[0381] The electronic device according to the above [B-03], wherein

[0382] The AI circuit is further provided on the semiconductor chip of the third layer in addition to the counter of the analog-digital conversion unit, the logic circuit unit, and the interface.

[0383] [B-06]

[0384] The electronic device according to the above [B-03], further comprising:

[0385] a fourth layer of semiconductor chips, wherein

[0386] The storage unit is provided on the semiconductor chip of the fourth layer.

[0387] [B-07]

[0388] The electronic device according to the above [B-03], further comprising:

[0389] The semiconductor chip of the fourth layer is smaller in size than the semiconductor chips of the other layers.

[0390] The AI circuit is provided on the semiconductor chip of the fourth layer.

[0391] [B-08]

[0392] The electronic device according to the above [B-07], wherein:

[0393] The semiconductor chip of the fourth layer is smaller in size than the semiconductor chips of the other layers.

[0394] [B-09]

[0395] The electronic device according to the above [B-02], wherein:

[0396] The counter of the analog-digital conversion unit, the logic circuit unit, and the interface are provided on the semiconductor chip of the second layer, and

[0397] The comparator of the analog-digital conversion unit and the load current source connected to the AND signal line are provided on the semiconductor chip of the third layer.

[0398] [B-10]

[0399] The electronic device according to any one of the above [B-01] to the above [B-09], wherein:

[0400] The analog-digital conversion unit includes a plurality of system analog-digital conversion units including a first analog-digital conversion unit and a second analog-digital conversion unit that convert each of analog pixel signals read in parallel from each pixel in a plurality of pixel rows of the pixel array unit into a digital pixel signal.

[0401] [B-11]

[0402] The electronic device according to the above [B-10], wherein:

[0403] The signal line is divided into a plurality of signal lines including a first signal line and a second signal line, in correspondence with the plurality of system analog-digital conversion units, for each pixel column in a length direction thereof.

[0404] [B-12]

[0405] The electronic device according to the above [B-11], wherein:

[0406] The first connection portion connecting the first signal line and the first analog-digital conversion unit and the second connection portion connecting the second signal line and the second analog-digital conversion unit are arranged close to each other in the region of the pixel array unit.

[0407] [B-13]

[0408] The electronic device according to the above [B-12], wherein

[0409] The first connection portion and the second connection portion connect the semiconductor chip of the first layer and the semiconductor chip of the second layer by direct bonding using a Cu electrode.

[0410] List of Reference Signs

[0411] 1A CMOS image sensor of first embodiment

[0412] 1B CMOS image sensor according to second embodiment

[0413] 1C CMOS image sensor of third embodiment

[0414] 1D CMOS image sensor according to fourth embodiment

[0415] 1E CMOS image sensor of fifth embodiment

[0416] 1F CMOS image sensor according to sixth embodiment

[0417] 1G CMOS image sensor of seventh embodiment

[0418] 1H CMOS image sensor according to eighth embodiment

[0419] 11 Pixel array unit

[0420] 12 Row selection unit

[0421] 13 Load current source unit

[0422] 14 Analog-digital conversion unit

[0423] 15 Logic circuit unit (signal processing unit)

[0424] 16 Timing control unit

[0425] 17 Reference signal generation unit

[0426] 20 Pixel (pixel circuit)

[0427] 21 Photodiode

[0428] 22 Transfer transistor

[0429] 23 Reset transistor

[0430] 24 amplification transistor

[0431] 25 selection transistor

[0432] 31 (31 1 ~ 31 m ) pixel control line

[0433] 32 (32 1 ~ 32 n ) signal line

[0434] 41 first layer semiconductor chip

[0435] 42 second layer semiconductor chip

[0436] 43 third layer semiconductor chip

[0437] 44 fourth layer semiconductor chip

[0438] 71 storage unit

[0439] 72 AI circuit

[0440] 140 analog-digital converter

[0441] 141 comparator

[0442] 142 counter

Claims

1. An imaging device having a stacked chip structure in which at least four semiconductor chips of a first layer of semiconductor chips, a second layer of semiconductor chips, a third layer of semiconductor chips, and a fourth layer of semiconductor chips are stacked, the imaging device comprising: a pixel array unit in which pixels are arranged in a matrix shape in two dimensions, and the pixel array unit is formed on the semiconductor chip of the first layer; an analog circuit unit of an analog-digital conversion unit that converts an analog pixel signal read from each pixel of the pixel array unit through a signal line into a digital pixel signal, and the analog circuit unit is provided on one of the semiconductor chip of the second layer and the semiconductor chip of the third layer; and a digital circuit unit of the analog-digital conversion unit that is provided on the other of the semiconductor chip of the second layer and the semiconductor chip of the third layer, wherein the semiconductor chip of the first layer, the semiconductor chip of the second layer, and the semiconductor chip of the third layer have the same size, and the semiconductor chip of the fourth layer has a size smaller than the size of the semiconductor chip of the first layer, the semiconductor chip of the second layer, and the semiconductor chip of the third layer.

2. The imaging device according to claim 1, wherein the analog-digital conversion unit includes a plurality of analog-digital converters provided corresponding to pixel columns of the pixel array unit, the analog-digital converter includes: a comparator that compares the analog pixel signal with a reference signal of a ramp wave; and a counter that measures a time from a timing of generation of the reference signal to a timing at which the analog pixel signal crosses the reference signal of the ramp wave, the comparator of the analog-digital conversion unit is provided on one of the semiconductor chip of the second layer and the semiconductor chip of the third layer, and the counter of the analog-digital conversion unit is provided on the other of the semiconductor chip of the second layer and the semiconductor chip of the third layer.

3. The imaging device according to claim 2, wherein the comparator of the analog-digital conversion unit and a load current source connected to the signal line are provided on the semiconductor chip of the second layer, and the counter of the analog-digital conversion unit, a logic circuit unit, and an interface are provided on the semiconductor chip of the third layer.

4. The imaging device according to claim 3, wherein a storage unit is provided on the semiconductor chip of the third layer in addition to the counter of the analog-digital conversion unit, the logic circuit unit, and the interface.

5. The imaging device according to claim 3, wherein an AI circuit is provided on the semiconductor chip of the third layer in addition to the counter of the analog-digital conversion unit, the logic circuit unit, and the interface.

6. The imaging device according to claim 3, wherein a storage unit is provided on the semiconductor chip of the fourth layer. ​ 7. The imaging device according to claim 3, wherein an AI circuit is provided on the semiconductor chip of the fourth layer.

8. The imaging device according to claim 2, wherein the counter, a logic circuit unit, and an interface of the A / D conversion unit are provided on the semiconductor chip of the second layer, and the comparator of the A / D conversion unit and a load current source connected to the signal line are provided on the semiconductor chip of the third layer.

9. The imaging device according to any one of claims 1 to 8, wherein the A / D conversion unit includes a plurality of system A / D conversion units including a first A / D conversion unit and a second A / D conversion unit that convert each of analog pixel signals read in parallel from each pixel in a plurality of pixel rows of the pixel array unit into a digital pixel signal.

10. The imaging device according to claim 9, wherein the signal line is divided into a plurality of signal lines including a first signal line and a second signal line with respect to each pixel column in the length direction thereof corresponding to the plurality of system A / D conversion units.

11. The imaging device according to claim 10, wherein a first connection portion connecting the first signal line and the first A / D conversion unit and a second connection portion connecting the second signal line and the second A / D conversion unit are provided close to each other in a region of the pixel array unit.

12. The imaging device according to claim 11, wherein the first connection portion and the second connection portion connect the semiconductor chip of the first layer and the semiconductor chip of the second layer by direct bonding using a Cu electrode.

13. An electronic device including the imaging device according to any one of claims 1 to 12.

Images