Semiconductor package device and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor package device and a manufacturing method thereof. By stacking each wafer package structure along a direction perpendicular to the first substrate, i.e. each wafer package structure is arranged vertically to the substrate, and the electrical path length between each wafer package structure and the first substrate is relatively consistent, the problem of inconsistent electrical path length in the PoP in the prior art can be solved. In addition, each wafer package structure can dissipate heat through the first substrate, which can alleviate the heat accumulation problem of the intermediate wafer package structure in the prior art.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor packaging technology, and more specifically to semiconductor packaging apparatus and manufacturing methods thereof. Background Technology

[0002] In the current PoP (Package on Package) structure, as the number of packaging layers in the PoP increases, the following problems may occur:

[0003] First, there's the issue of inconsistent electrical path lengths. That is, the electrical path length from the bottom to the substrate differs depending on the vertical position of the package structure. The farther the package structure is from the substrate, the longer the electrical path to the substrate, resulting in longer signal transmission time. Consequently, the topmost package structure, furthest from the substrate, may experience significant signal delay issues.

[0004] Secondly, there is the problem of uneven heat dissipation (or heat accumulation). That is, the topmost packaging structure, which is farthest from the substrate, mainly relies on air for heat dissipation, while the bottommost packaging structure, which is closest to the substrate, dissipates heat through the substrate. However, the packaging structures in the middle layers cannot dissipate heat through air and the substrate, resulting in poor heat dissipation and heat accumulation. Summary of the Invention

[0005] This disclosure presents a semiconductor packaging apparatus and a method for manufacturing the same.

[0006] In a first aspect, this disclosure provides a semiconductor packaging apparatus, comprising:

[0007] First substrate;

[0008] A wafer module is disposed on the first substrate, wherein the wafer module includes at least two wafer packaging structures disposed side by side on the first substrate, the wafer packaging structure includes a first metal layer, a second substrate and a second metal layer disposed perpendicular to the first substrate in sequence, the second substrate being electrically connected to the first substrate, and in the wafer module, the first metal layer of one wafer packaging structure is contacted and bonded to the second metal layer of the other wafer packaging structure.

[0009] In some alternative embodiments, the wafer packaging structure further includes a wafer and a first packaging material disposed perpendicular to the first substrate, the first packaging material covering the wafer, the wafer being disposed between the second substrate and the second metal layer, and the wafer being electrically connected to the second substrate.

[0010] In some optional embodiments, the semiconductor packaging device further includes:

[0011] A second packaging material surrounds the wafer module, and the first metal layer, the second substrate, and the second metal layer in the wafer packaging structure are exposed from the upper surface of the second packaging material.

[0012] In some optional embodiments, the semiconductor packaging device further includes:

[0013] A redistribution layer is disposed on the lower surface of the wafer module, and the second substrate is electrically connected to the first substrate through the redistribution layer.

[0014] In some optional embodiments, the semiconductor packaging device further includes:

[0015] A first solder bump is disposed between the first substrate and the redistribution layer, and is electrically connected to the redistribution layer and the first substrate, respectively.

[0016] In some optional embodiments, the semiconductor packaging device further includes:

[0017] The second solder bump is disposed between the first substrate and the second substrate, and is electrically connected to the first substrate and the second substrate respectively.

[0018] In some optional embodiments, the semiconductor packaging device further includes:

[0019] A first metal heat dissipation layer is disposed on each of the first metal layer and the second metal layer exposed on the outer surface of the wafer module.

[0020] In some optional embodiments, the second solder bump includes a nickel layer and a tin-silver layer disposed sequentially from the second substrate toward the first substrate, and the first metal heat dissipation layer includes a nickel layer and a tin-silver layer disposed sequentially from the outer surface of the wafer module.

[0021] In some optional embodiments, the semiconductor packaging device further includes:

[0022] A bottom filler is disposed between the wafer module and the first substrate.

[0023] In some alternative embodiments, the underfill and the second encapsulation material are filled between two adjacent wafer package structures in the wafer module.

[0024] In some alternative embodiments, the underfill extends to the sidewall of the wafer module.

[0025] In some optional embodiments, the semiconductor packaging device further includes:

[0026] A support colloid is disposed between the bottom edge of the wafer module and the first substrate, and the bottom filler covers the support colloid.

[0027] In some alternative implementations, in the wafer module, the first metal layer in one wafer package structure is bonded to the second metal layer in the other wafer package structure.

[0028] In some optional embodiments, the semiconductor packaging device further includes:

[0029] Solder is disposed on the upper surface of the first substrate;

[0030] A solder pad is disposed between the first substrate and the second substrate, and is electrically connected to the second substrate and the solder, respectively.

[0031] In some optional embodiments, the semiconductor packaging device further includes:

[0032] A second metal heat dissipation layer is disposed on the outer surface of the first metal layer and the second metal layer exposed on the wafer module.

[0033] In some optional embodiments, the bonding pad includes a nickel layer and a gold layer disposed sequentially from the second substrate toward the first substrate, and the second metal heat dissipation layer includes a nickel layer and a gold layer disposed sequentially from the outer surface of the wafer module.

[0034] In some optional embodiments, the semiconductor packaging device further includes:

[0035] A functional element is disposed on the wafer package structure, and the functional element is electrically connected to the second substrate.

[0036] In some alternative implementations, the functional element includes at least one of the following: a passive element, a power management integrated circuit (PMIC).

[0037] In some optional embodiments, the semiconductor packaging device further includes:

[0038] A second wiring layer is disposed between the functional element and the second substrate, and the functional element is electrically connected to the second substrate through the second wiring layer.

[0039] Secondly, this disclosure provides a method for manufacturing a semiconductor packaging device, comprising:

[0040] A first substrate and a wafer module are provided, wherein the wafer module includes at least two wafer packaging structures stacked in parallel from bottom to top, and the wafer packaging structure includes a first metal layer, a second substrate, a wafer, a first packaging material and a second metal layer arranged sequentially from bottom to top, the wafer being electrically connected to the second substrate, and the first packaging material covering the wafer;

[0041] The wafer module is electrically connected to the first substrate, such that each of the second substrates is electrically connected to the first substrate.

[0042] In some optional implementations, the method further includes:

[0043] An underfill is filled between the wafer module and the first substrate.

[0044] In some alternative embodiments, prior to electrically connecting the wafer module to the first substrate, the method further includes:

[0045] A support colloid is disposed between the bottom edge of the wafer module and the first substrate.

[0046] In some alternative implementations, the wafer module is obtained through the following steps:

[0047] Provide at least two wafer packaging structure strips, wherein the wafer packaging structure strip is a strip-shaped structure composed of at least two wafer packaging structures arranged horizontally side by side;

[0048] The at least two wafer packaging structure strips are stacked together from bottom to top by metal-to-metal bonding;

[0049] Cut along a direction perpendicular to the wafer packaging structure strip to obtain individual wafer modules.

[0050] In some alternative embodiments, electrically connecting the wafer module to the first substrate such that each of the second substrates is electrically connected to the first substrate includes:

[0051] The wafer module is rotated 90 degrees and then molded to obtain a second packaging material covering the first surface of the wafer module. The first surface is perpendicular to the wafer and the second substrate in the wafer packaging structure.

[0052] The first surface is ground to expose the second substrate in each of the said wafer package structures;

[0053] A redistribution layer is formed on the first surface;

[0054] A first solder bump is formed on the redistribution layer;

[0055] The wafer module is electrically connected to the first substrate by flip-chip bonding, so that the first solder bumps are electrically connected to the redistribution layer and the first substrate respectively.

[0056] In some alternative embodiments, electrically connecting the wafer module to the first substrate such that each of the second substrates is electrically connected to the first substrate includes:

[0057] A nickel layer and a tin-silver layer are sequentially deposited on the surface of the wafer module using chemical plating to form at least two second solder bumps and a first metal heat dissipation layer. Each second solder bump is electrically connected to the corresponding second substrate, and the first metal heat dissipation layer is disposed on each first metal layer and the second metal layer exposed on the outer surface of the wafer module.

[0058] The wafer module is electrically connected to the first substrate by flip-chip bonding, so that the second solder bump is electrically connected to the first substrate.

[0059] In some alternative embodiments, solder is disposed on the upper surface of the first substrate; and

[0060] The step of electrically connecting the wafer module to the first substrate, such that each of the second substrates is electrically connected to the first substrate, includes:

[0061] A nickel layer and a gold layer are sequentially deposited on the surface of the wafer module using chemical plating to form at least two bonding pads and a second metal heat dissipation layer. Each bonding pad is electrically connected to the corresponding second substrate, and the second metal heat dissipation layer is disposed on each of the first metal layer and the second metal layer exposed on the outer surface of the wafer module.

[0062] The wafer module is electrically connected to the first substrate by thermal compression bonding, so that each of the second substrates is electrically connected to the first substrate.

[0063] To address the issues of inconsistent electrical path lengths and uneven heat dissipation in existing Point of Packaging (PoP) technologies, the semiconductor packaging apparatus and manufacturing method disclosed herein utilize a stacking design where each wafer packaging structure is stacked parallel to the first substrate, i.e., each wafer packaging structure is positioned perpendicular to the substrate. This results in relatively consistent electrical path lengths between each wafer packaging structure and the first substrate, thus resolving the problem of inconsistent electrical path lengths in existing PoP technologies. Furthermore, each wafer packaging structure can dissipate heat through the first substrate, mitigating the heat accumulation problem in intermediate layer wafer packaging structures in existing technologies. Attached Figure Description

[0064] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0065] Figure 1A , 1B 1C, 1D, 1E and 1F are schematic diagrams of longitudinal cross-sectional structures of one embodiment of the semiconductor packaging apparatus 1a, 1b, 1c, 1d, 1e and 1f according to the present disclosure;

[0066] Figure 2A , 2B 2C, 2D-1, 2E-1, 2F-1 and 2G-1 are schematic diagrams of longitudinal cross-sectional structures of semiconductor packaging devices 2a, 2b, 2c, 2d-1, 2e-1, 2f-1 and 2g-1 manufactured at various stages according to the semiconductor packaging device 1a of this disclosure.

[0067] Figure 2A , 2B 2C, 2D-2, 2E-2, 2F-2 and 2G-2 are schematic diagrams of longitudinal cross-sectional structures of semiconductor packaging devices 2a, 2b, 2c, 2d-2, 2e-2, 2f-2 and 2g-2 manufactured at various stages according to the semiconductor packaging device 1b of this disclosure;

[0068] Figure 2A , 2B 2C, 2D-3, 2E-3, 2F-3 and 2G-3 are schematic diagrams of longitudinal cross-sectional structures of semiconductor packaging devices 2a, 2b, 2c, 2d-3, 2e-3, 2f-3 and 2g-3 manufactured at various stages according to the semiconductor packaging device 1d of this disclosure.

[0069] Symbol explanation:

[0070] 11-First substrate; 12-Wafer module; 12a-First surface; 121-Wafer packaging structure; 1211-First metal layer; 1212-Second substrate; 1213-Wafer; 1214-First packaging material; 1215-Second metal layer; 13-Second packaging material; 14-Pads disposed on the lower surface of the first redistribution layer; 15-First solder bump; 16-Second solder bump; 161-Nickel layer of the second solder bump; 162-Ni layer of the second solder bump 17-First metal heat dissipation layer; 171-Nickel layer of the first metal heat dissipation layer; 172-Tin-silver layer of the first metal heat dissipation layer; 18-Underfiller; 19-Supporting colloid; 20-Solder; 21-Pad; 211-Nickel layer of the pad; 212-Gold layer of the pad; 22-Second metal heat dissipation layer; 221-Nickel layer of the second metal heat dissipation layer; 222-Gold layer of the second metal heat dissipation layer; 23-Wafer packaging structure strip; 24-Solder bump under the first substrate. Detailed Implementation

[0071] The specific embodiments of the present invention will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by the present invention and the resulting technical effects from the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0072] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and to facilitate understanding and reading of the invention. They are not intended to limit the scope of the invention and therefore have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and objectives of the invention, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity and not intended to limit the scope of the invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the invention's implementation.

[0073] It should also be noted that the longitudinal section corresponding to the embodiments of this disclosure can be the section corresponding to the front view direction, the transverse section can be the section corresponding to the right view direction, and the horizontal section can be the section corresponding to the top view direction.

[0074] Furthermore, the embodiments and features described herein can be combined with each other, unless otherwise specified. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0075] refer to Figure 1A , Figure 1A A longitudinal cross-sectional structural schematic diagram of an embodiment 1a of a semiconductor packaging device according to the present disclosure is shown.

[0076] like Figure 1A As shown, the semiconductor packaging device 1a includes a first substrate 11 and a wafer module 12. Wherein:

[0077] The chip module 12 is disposed on the first substrate 11.

[0078] Here, the chip module 12 may include at least two chip package structures 121 disposed side by side on the first substrate 11 (e.g., Figure 1AThe diagram shows three chip package structures 121. Each chip package structure 121 includes a first metal layer 1211, a second substrate 1212, and a second metal layer 1215, which are sequentially disposed perpendicular to the first substrate 11. In the chip package structure 121, the second substrate 1212 is electrically connected to the first substrate 11, and a first encapsulation material 1214 covers the chip 1213. From the above electrical connection relationship, it can be seen that the chip 1213 is electrically connected to the first substrate 11 through the second substrate 1212. That is, the chip 1213 in each chip package structure 121 can be electrically connected to the first substrate 11, thereby achieving electrical connection with other external components through the first substrate 11.

[0079] In some alternative embodiments, the wafer package structure 121 may further include a wafer 1213 disposed perpendicular to the first substrate 11 and a first package material 1214, the first package material 1214 covering the wafer 1213, the wafer 1213 being disposed between the second substrate 1212 and the second metal layer 1215, and the wafer 1213 being electrically connected to the second substrate 1212.

[0080] In some alternative implementations, optionally, such as Figure 1A As shown, the semiconductor packaging device 1a may further include a second packaging material 13, which surrounds the wafer module 12, and the first metal layer 1211, the second substrate 1212, and the second metal layer 1215 in each wafer package structure 121 are exposed from the upper surface of the second packaging material 13. Thus, the second packaging material 13 can provide protection for the wafer module 12, and each wafer package structure 121 can also achieve electrical connection between the second substrate 1212 exposed from the upper surface of the second packaging material 13 and the external environment. Furthermore, since the first metal layer 1211 and the second metal layer 1215 are exposed from the upper surface of the second packaging material 13, the good heat dissipation performance of the metal allows for better heat dissipation from the wafer package structure 121.

[0081] Here, the first substrate 11 and the second substrate 1212 can be various types of substrates, and this disclosure does not specifically limit them.

[0082] The first substrate 11 and the second substrate 1212 may include organic and / or inorganic materials, wherein the organic materials may be, for example, polyamide (PA), polyimide (PI), epoxy resin, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, prepreg or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), etc., while the inorganic materials may be, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc.

[0083] The first substrate 11 can also be, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber-based copper foil laminate, etc.

[0084] The first substrate 11 and the second substrate 1212 may further include interconnect structures, such as conductive traces, conductive vias, etc. Here, the conductive vias may be through-holes, buried vias, or blind vias, and the through-holes, buried vias, or blind vias may be filled with conductive materials such as metals or metal alloys. Here, the metal may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or alloys thereof.

[0085] Optionally, such as Figure 1A As shown, the lower surface of the first substrate 11 may also be provided with a first substrate solder bump 24, which is used to realize the electrical connection between the first substrate 11 and the outside world, thereby realizing the electrical connection between each chip packaging structure 121 in the chip module 12 and the outside world.

[0086] The first metal layer 1211 and the second metal layer 1215 can be various metals with good heat dissipation and / or good conductivity to improve the heat dissipation and electrical signal connection of the wafer package structure 121. For example, the first metal layer 1211 and the second metal layer 1215 can be gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu) or alloys thereof.

[0087] The wafer 1213 can be any type of bare die (i.e., die), and this disclosure does not specifically limit it. For example, the wafer 1213 can be a logic chip, a memory chip, a micro-electro-mechanical system (MEMS) chip, a radio frequency chip, etc.

[0088] The first encapsulation material 1214 and the second encapsulation material 13 can be formed from various molding compounds. For example, molding compounds may include epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc.

[0089] The technical effects that the semiconductor packaging device 1a provided in the above embodiments of this disclosure can achieve include, but are not limited to: by designing the stacking of each wafer packaging structure to be stacked along the direction perpendicular to the first substrate, that is, each wafer packaging structure is set perpendicular to the substrate, the electrical path length between each wafer packaging structure and the first substrate is relatively consistent, which can solve the problem of inconsistent electrical path length in the prior art in PoP; in addition, each wafer packaging structure can dissipate heat through the first substrate, which can alleviate the problem of heat accumulation in the intermediate layer wafer packaging structure in the prior art.

[0090] In some alternative embodiments, the semiconductor packaging device 1a may further include: functional elements ( Figure 1A (Not shown in the image). Functional elements may be disposed on the wafer package structure 121 (e.g., ...). Figure 1A (As shown in the dashed rectangle), the functional element is electrically connected to the second substrate 1212. Optionally, the functional element may include at least one of the following: a passive element, a power management integrated circuit.

[0091] In some alternative embodiments, the semiconductor packaging device 1a may further include a second wiring layer ( Figure 1A (Not shown in the diagram), a second redistribution layer is disposed between the functional element and the second substrate 1212, and the functional element can be electrically connected to the second substrate 1212 through the second redistribution layer. That is, the number of available I / Os in the upward direction of the second substrate 1212 can be increased through the second redistribution layer.

[0092] In some optional embodiments, a first redistribution layer may also be provided on the lower surface of the wafer module 12 in the semiconductor packaging device 1a. Figure 1A (Not shown in the image). For example... Figure 1AThe pad 14 shown can be a pad disposed on the lower surface of the first rewiring layer. Thus, the second substrate 1212 in each wafer package structure 121 of the wafer module 12 can be electrically connected to the first substrate 11 through the first rewiring layer. That is, the lines of the second substrate 1212 can be fanned out through the first rewiring layer disposed on the lower surface of the wafer module 12 to increase the number of available I / Os in the downward direction of the second substrate 1212.

[0093] Here, the first and second redistribution layers can be redistribution layers composed of conductive and dielectric materials. It should be noted that the fabrication process can employ currently known or future-developed redistribution layer formation technologies, and this disclosure does not specifically limit this. For example, redistribution layers can be formed using methods including, but not limited to, photolithography, electroplating, and electroless plating. Here, the dielectric material can include organic and / or inorganic materials. Organic materials can be, for example, polyamide (PA), polyimide (PI), epoxy resin, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, also known as prepreg or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), etc., while inorganic materials can be, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc. The conductive material may include a seed layer and a metal layer. Here, the seed layer may be, for example, titanium (Ti), tungsten (W), nickel (Ni), etc., while the metal layer may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or alloys thereof.

[0094] In some alternative implementations, such as Figure 1A As shown, the semiconductor packaging device 1a may further include a first solder bump 15. The first solder bump 15 is disposed between the first substrate 11 and the first redistribution layer, and electrically connects the first redistribution layer and the first substrate 11 respectively. That is, the first redistribution layer is bonded and electrically connected to the first substrate 11 through the first solder bump 15.

[0095] The first solder bump 15 may be composed of various materials that have a welding function, such as at least one of the following: tin, lead, indium, silver, etc.

[0096] In some alternative implementations, such as Figure 1AAs shown, the semiconductor packaging device 1a may further include an underfill 18. The underfill 18 is disposed between the wafer module 12 and the first substrate 11. The underfill 18 can be used to protect the bottom of the wafer module 12 and fill the gap between the bottom of the wafer module 12 and the first substrate, thereby achieving the purpose of reinforcement. The underfill 18 may be, for example, capillary underfill (CUF), molded underfill (MUF), non-conductive paste (NCP), etc.

[0097] In some alternative implementations, such as Figure 1A As shown, in the chip module 12, the first metal layer 1211 of one adjacent chip package structure 121 contacts and is bonded to the second metal layer 1215 of the other chip package structure 121. That is, one chip package structure 121 in the chip module 12 is bonded to the other chip package structure 121 by a metal-to-metal bonding method. Compared with the stacked packaging structure of the prior art, the two outermost chip package structures 121 of the chip module 12 can exchange heat with the outside world through the first metal layer 1211 and the second metal layer 1215 respectively, and can also exchange heat through the first substrate 11. Since metal has a better heat dissipation effect, the first metal layer 1211 and the second metal layer 1215 provide a better heat dissipation effect, thus improving the heat dissipation effect of the two outermost chip package structures 121. In addition to heat exchange through the first substrate 11, the chip packaging structure 121 of the intermediate layer of the chip module 12 can also exchange heat through the first metal layer and the second metal layer bonded on both sides. Compared with the stacked packaging structure of the intermediate layer in the prior art, which cannot dissipate heat through air and substrate, the heat dissipation effect is further improved.

[0098] The following is for reference. Figure 1B , Figure 1B This is a longitudinal cross-sectional structural schematic diagram of an embodiment 1b of the semiconductor packaging apparatus according to the present disclosure. Figure 1B The semiconductor packaging device 1b shown is similar to Figure 1A The semiconductor packaging device 1a shown differs in that, in addition to the first substrate 11, the wafer module 12, and the second packaging material 13, the semiconductor packaging device 1b also includes a second solder bump 16. The second solder bump 16 is disposed between the first substrate 11 and the second substrate 1212, and the second solder bump 16 is electrically connected to both the first substrate 11 and the second substrate 1212. That is, relative to... Figure 1AIn the semiconductor packaging device 1a and semiconductor packaging device 1b shown, the second substrate 1212 is not bonded to the first substrate 11 through a redistribution layer, but through a second solder bump 16.

[0099] In some alternative implementations, such as Figure 1B As shown, the semiconductor packaging apparatus 1b may further include a first metal heat dissipation layer 17. The first metal heat dissipation layer 17 is disposed in each wafer packaging structure 121 where the first metal layer 1211 and the second metal layer 1215 are exposed on the outer surface of the wafer module 12. Here, the first metal heat dissipation layer 17 is used to protect the portions of the first metal layer 1211 and the second metal layer 1215 exposed on the outer surface of the wafer module 12 and to achieve good heat dissipation.

[0100] In some optional embodiments, the second solder bump 16 may include a nickel layer 161 and a tin-silver layer 162 sequentially disposed from the second substrate 1212 toward the first substrate 11. The nickel layer 161 serves to prevent the tin-silver layer 162 from eroding into the second substrate 1212, while simultaneously increasing the adhesion between the tin-silver layer 162 and the second substrate 1212. The tin-silver layer 162 can then bond the second substrate 1212 to the first substrate 11 after heating. The first metal heat dissipation layer 17 may include a nickel layer 171 and a tin-silver layer 172 sequentially disposed on the outer surface of the wafer module 12. The nickel layer 171 serves to prevent the tin-silver layer 172 from eroding into the first metal layer 1211 or the second metal layer 1215, while simultaneously increasing the adhesion between the tin-silver layer 172 and the first metal layer 1211 or the second metal layer 1215.

[0101] The following is for reference. Figure 1C , Figure 1C This is a longitudinal cross-sectional structural schematic diagram of an embodiment 1c of the semiconductor packaging apparatus according to the present disclosure. Figure 1C The semiconductor packaging device 1b shown is similar to Figure 1BThe semiconductor packaging device 1b shown differs in that, in the direction perpendicular to the first substrate 11, the lengths of the first metal layer 1211 and the second metal layer 1215 in the semiconductor packaging device 1c are shorter than the length of the second substrate 1212, and the first metal layer 1211 and the second metal layer 1215 are recessed relative to the second substrate 1212. This is because, in practice, the second solder bump 16 and the first metal heat dissipation layer 17 are often fabricated simultaneously. If the first metal layer 1211 and the second metal layer 1215 are recessed relative to the second substrate 1212 in the direction perpendicular to the first substrate 11, then during the formation of the second solder bump 16 on the second substrate 1212 and the formation of the first metal heat dissipation layer 17 on the first metal layer 1211 and the second metal layer 1215 using chemical plating, the first metal heat dissipation layer 17 will also be recessed relative to the second solder bump 16. This makes it easier for the second solder bump 16 to contact the upper surface of the first substrate 11 when it is subsequently bonded to the first substrate 11, thereby improving the bonding success rate.

[0102] The following is for reference. Figure 1D , Figure 1D This is a longitudinal cross-sectional structural schematic diagram of an embodiment 1d of the semiconductor packaging apparatus according to the present disclosure. Figure 1D The semiconductor packaging device 1d shown is similar to Figure 1A The semiconductor packaging device 1a shown differs in that, in addition to a first substrate 11, a wafer module 12, and a second packaging material 13, the semiconductor packaging device 1d also includes solder 20 and bonding pads 21. Solder 20 is disposed on the upper surface of the first substrate 11. Bonding pads 21 are disposed between the first substrate 11 and the second substrate 1212, and are electrically connected to both the second substrate 1212 and the solder 20. That is, relative to… Figure 1A In the semiconductor packaging apparatus 1a and semiconductor packaging apparatus 1c shown, the second substrate 1212 is not bonded to the first substrate 11 through a redistribution layer, but through solder 20 and pad 21.

[0103] In some alternative implementations, such as Figure 1E As shown, the semiconductor packaging apparatus 1b may further include a second metal heat dissipation layer 22. The second metal heat dissipation layer 22 is disposed in each wafer packaging structure 121 where the first metal layer 1211 and the second metal layer 1215 are exposed on the outer surface of the wafer module 12. Here, the second metal heat dissipation layer 22 is used to protect the portions of the first metal layer 1211 and the second metal layer 1215 exposed on the outer surface of the wafer module 12 and to achieve good heat dissipation.

[0104] In some optional embodiments, the bonding pad 20 may include a nickel layer 211 and a gold layer 212 sequentially disposed from the second substrate 1212 toward the first substrate 11. The nickel layer 211 serves to prevent the gold layer 212 from eroding into the second substrate 1212, while simultaneously increasing the adhesion between the gold layer 212 and the second substrate 1212. The gold layer 212 can then be heated to bond the second substrate 1212 to the first substrate 11 via solder 20. The second metal heat dissipation layer 22 may include a nickel layer 221 and a gold layer 222 sequentially disposed on the outer surface of the wafer module 12. The nickel layer 221 serves to prevent the gold layer 222 from eroding into the first metal layer 1211 or the second metal layer 1215, while simultaneously increasing the adhesion between the gold layer 222 and the first metal layer 1211 or the second metal layer 1215.

[0105] The following is for reference. Figure 1E , Figure 1E This is a longitudinal cross-sectional structural schematic diagram of an embodiment 1e of the semiconductor packaging apparatus according to the present disclosure. Figure 1E The semiconductor packaging device 1e shown is similar to Figure 1B The semiconductor packaging device 1b shown differs in that, in the direction perpendicular to the first substrate 11, the lengths of the first metal layer 1211 and the second metal layer 1215 in the semiconductor packaging device 1e are shorter than the length of the second substrate 1212, and the first metal layer 1211 and the second metal layer 1215 are recessed relative to the second substrate 1212. This is because, in practice, solder pads 20 and a second metal heat dissipation layer 22 are often fabricated simultaneously. If the first metal layer 1211 and the second metal layer 1215 are recessed relative to the second substrate 1212 in the direction perpendicular to the first substrate 11, then during the formation of solder pads 20 on the second substrate 1212 and the formation of the second metal heat dissipation layer 22 on the first metal layer 1211 and the second metal layer 1215, respectively, the first metal heat dissipation layer 17 will also be recessed relative to the second solder bump 16. This is more conducive to the solder 20 making it easier to contact the upper surface of the first substrate 11 when it is subsequently bonded to the first substrate 11, thereby improving the bonding success rate.

[0106] In some alternative implementations, such as Figure 1C and Figure 1EAs shown, the semiconductor packaging devices 1c and 1e may further include a support colloid 19. The support colloid 19 is disposed between the bottom edge of the wafer module 12 and the first substrate 11, and the underfill 18 covers the support colloid 19. The support colloid 19 can be various adhesive colloids. For example, it can be a non-conductive film (NCF). During the manufacturing process, the support colloid can be placed on the first substrate 11 before the wafer module 12 is bonded to the first substrate 11. Due to the colloidal properties of the support colloid 19, it will deform during the heating process of bonding the wafer module 12 to the first substrate, thereby enabling the second substrate 1212 in the wafer module 12 to be electrically connected to the first substrate 11. The underfill 18 is then placed after the wafer module 12 is bonded to the first substrate 11 to protect the bottom of the wafer module 12.

[0107] The following is for reference. Figure 1F , Figure 1F This is a longitudinal cross-sectional structural schematic diagram of an embodiment 1f of the semiconductor packaging apparatus according to the present disclosure. Figure 1F The semiconductor packaging device 1f shown is similar to Figure 1A The semiconductor packaging device 1a shown differs in that: a bottom filler 18 and a second packaging material 13 are filled between two adjacent wafer packaging structures 121 in the wafer module 12. Relative to Figure 1A The semiconductor packaging device 1a shown is Figure 1F In the semiconductor packaging apparatus 1f shown, each wafer package structure 121 can be individually bonded to the first substrate 11 during the manufacturing process, with bonding occurring independently between them. After each wafer package structure 121 is bonded to the first substrate 11, an underfill 18 is filled between the wafer module 12 and the first substrate 11 to protect the bottom of the wafer module 12. The underfill 18 then fills between adjacent wafer package structures 121 due to capillary action. After filling with the underfill 18, molding is performed to form the second package material 13.

[0108] In some alternative implementations, such as Figure 1F As shown, the bottom filler 18 can be extended and disposed on the sidewall of the wafer module 12.

[0109] Figure 2A , 2B Figures 2A, 2B, 2C, 2D-1, 2E-1, 2F-1, and 2G-1 are longitudinal cross-sectional structural schematic diagrams of semiconductor packaging devices 2a, 2b, 2c, 2d-1, 2e-1, 2f-1, and 2g-1 manufactured at various stages according to the semiconductor packaging device 1a of this disclosure. The figures have been simplified for better understanding of various aspects of this disclosure.

[0110] refer to Figure 2A Provide at least two chip packaging structure strips 23.

[0111] Figure 2A The diagram schematically illustrates one of the wafer package structure strips 23. The wafer package structure strip 23 is a strip-shaped structure composed of at least two horizontally arranged wafer package structures 121.

[0112] The wafer packaging structure 121 may include a first metal layer 1211, a second substrate 1212, a wafer 1213, a first packaging material 1214 and a second metal layer 1215 arranged sequentially from bottom to top. The wafer 1213 is electrically connected to the second substrate 1212, and the first packaging material 1214 covers the wafer 1213.

[0113] refer to Figure 2B At least two wafer package structure strips 23 are stacked together from bottom to top using metal-to-metal bonding. Then, along a direction perpendicular to the wafer package structure strips 23 (e.g., Figure 2B (As shown by the bold black dashed line in the middle) is cut to obtain individual chip modules 12. For example... Figure 2C As shown, Figure 2C Only one chip module 12 is shown as an example.

[0114] refer to Figure 2D-1 The wafer module 12 is rotated 90 degrees and then molded to obtain a second packaging material 13 covering the first surface 12a of the wafer module 12. The first surface 12a is perpendicular to the wafer 1213 and the second substrate 1212 in the wafer packaging structure 121.

[0115] refer to Figure 2E-1 For each encapsulated wafer module 12, the first surface 12a is ground to expose the second substrate 1212 in each wafer package structure 121, a redistribution layer 14 is formed on the first surface 12a, and a first solder bump 15 is formed on the redistribution layer 14.

[0116] refer to Figure 2F-1 Cut along the direction extending from the second substrate 1212 to obtain each wafer module 12.

[0117] Figure 2F-1 Only one of the chip modules 12 is shown as an example.

[0118] refer to Figure 2G-1 The wafer module 12 is electrically connected to the first substrate 11 via flip chip bonding (FCB), so that the first solder bumps 15 are electrically connected to the redistribution layer 14 and the first substrate 11 respectively. Then, an underfill 18 is filled between the wafer module 12 and the first substrate 11. This results in... Figure 1AThe semiconductor packaging device 1a shown.

[0119] Figure 2A , 2B Figures 2A, 2B, 2C, 2D-2, 2E-2, 2F-2, and 2G-2 are longitudinal cross-sectional structural schematic diagrams of semiconductor packaging devices 2A, 2B, 2C, 2D-2, 2E-2, 2F-2, and 2G-2 manufactured at various stages according to the semiconductor packaging device 1b of this disclosure. The figures have been simplified for better understanding of various aspects of this disclosure.

[0120] It should be noted that, Figure 2A , Figure 2B and Figure 2C As already mentioned above, it will not be repeated here.

[0121] The following is for reference. Figure 2D-2 A nickel layer and a tin-silver layer are sequentially deposited on the surface of the chip module 12 using a chemical plating method to form at least two second solder bumps 16 and a first metal heat dissipation layer 17.

[0122] Each second solder bump 16 is electrically connected to the corresponding second substrate 1212, and the first metal heat dissipation layer 17 is disposed on each first metal layer 1211 and the second metal layer 1215 and exposed on the outer surface of the wafer module 121.

[0123] refer to Figure 2E-2 The wafer module 12 is electrically connected to the first substrate 11 by flip-chip bonding, so that the second solder bump 16 is electrically connected to the first substrate 11.

[0124] refer to Figure 2F-2 A bottom filler 18 is filled between the bottom of the wafer module 12 and the first substrate 11.

[0125] refer to Figure 2G-2 The wafer module 12 is molded to form a second package material 13 that covers the wafer module 12, thereby obtaining a product that can achieve the following: Figure 1B The semiconductor packaging device 1b shown.

[0126] Figure 2A , 2B Figures 2A, 2B, 2C, 2D-3, 2E-3, 2F-3, and 2G-3 are longitudinal cross-sectional structural schematic diagrams of semiconductor packaging devices 2A, 2B, 2C, 2D-3, 2E-3, 2F-3, and 2G-3 manufactured at various stages according to the semiconductor packaging device 1d of this disclosure. The figures have been simplified for better understanding of various aspects of this disclosure.

[0127] It should be noted that, Figure 2A , Figure 2B and Figure 2CAs described above, it will not be repeated here. It should be noted that solder 20 may be provided on the upper surface of the first substrate 11.

[0128] The following is for reference. Figure 2D-3 A nickel layer and a gold layer are sequentially deposited on the surface of the wafer module 12 by chemical plating to form at least two solder pads 21 and a second metal heat dissipation layer 22. Each solder pad 21 is electrically connected to the corresponding second substrate 1212. The second metal heat dissipation layer 22 is disposed on each first metal layer 1211 and second metal layer 1215 and exposed on the outer surface of the wafer module 12.

[0129] refer to Figure 2E-3 The wafer module 12 is electrically connected to the first substrate 11 by thermal compression bonding (TCB), so that each second substrate 1212 is electrically connected to the first substrate 11 by pads 21 and solder 20.

[0130] refer to Figure 2F-3 A bottom filler 18 is filled between the bottom of the wafer module 12 and the first substrate 11.

[0131] refer to Figure 2G-3 The wafer module 12 is molded to form a second package material 13 that covers the wafer module 12, thereby obtaining a product that can achieve the following: Figure 1C The semiconductor packaging device 1c shown.

[0132] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual implementation due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and illustrations should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit this disclosure.

Claims

1. A semiconductor packaging device, comprising: First substrate; A wafer module is disposed on a first substrate, wherein the wafer module includes at least two wafer packaging structures disposed side by side on the first substrate, each wafer packaging structure is stacked along a direction parallel to the first substrate, each wafer packaging structure is disposed perpendicular to the substrate, and the electrical path length between each wafer packaging structure and the first substrate is relatively consistent. The wafer packaging structure includes a first metal layer, a second substrate, and a second metal layer arranged in sequence perpendicular to the first substrate. The second substrate is electrically connected to the first substrate. In the wafer module, the first metal layer of one wafer packaging structure is contacted and bonded to the second metal layer of the other wafer packaging structure.

2. The semiconductor packaging apparatus according to claim 1, wherein, The semiconductor packaging apparatus further includes: A first wiring layer is disposed on the lower surface of the wafer module, and the second substrate is electrically connected to the first substrate through the first wiring layer.

3. The semiconductor packaging apparatus according to claim 1, wherein, The semiconductor packaging apparatus further includes: The second solder bump is disposed between the first substrate and the second substrate, and is electrically connected to the first substrate and the second substrate respectively; A first metal heat dissipation layer is disposed on each of the first metal layer and the second metal layer exposed on the outer surface of the wafer module.

4. The semiconductor packaging apparatus according to claim 3, wherein, The second solder bump includes a nickel layer and a tin-silver layer sequentially disposed from the second substrate toward the first substrate, and the first metal heat dissipation layer includes a nickel layer and a tin-silver layer sequentially disposed from the outer surface of the wafer module.

5. The semiconductor packaging apparatus according to claim 1, wherein, The semiconductor packaging apparatus further includes: A bottom filler is disposed between the wafer module and the first substrate; A support colloid is disposed between the bottom edge of the wafer module and the first substrate, and the bottom filler covers the support colloid.

6. The semiconductor packaging apparatus according to claim 1, wherein, The semiconductor packaging apparatus further includes: Solder is disposed on the upper surface of the first substrate; A solder pad is disposed between the first substrate and the second substrate, and is electrically connected to the second substrate and the solder, respectively; A second metal heat dissipation layer is disposed on the outer surface of the first metal layer and the second metal layer exposed on the wafer module.

7. The semiconductor packaging apparatus according to claim 6, wherein, The bonding pad includes a nickel layer and a gold layer sequentially disposed from the second substrate toward the first substrate, and the second metal heat dissipation layer includes a nickel layer and a gold layer sequentially disposed from the outer surface of the wafer module.

8. The semiconductor packaging apparatus according to claim 1, wherein, The semiconductor packaging apparatus further includes: A functional element is disposed on the wafer package structure, and the functional element is electrically connected to the second substrate.

9. The semiconductor packaging apparatus according to claim 8, wherein, The functional components include at least one of the following: passive components and power management integrated circuits.

10. The semiconductor packaging apparatus according to claim 8, wherein, The semiconductor packaging apparatus further includes: A second wiring layer is disposed between the functional element and the second substrate, and the functional element is electrically connected to the second substrate through the second wiring layer.

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