Static random access memory and forming method thereof

Abstract

A static random access memory (SRAM) and its formation method are disclosed, comprising a substrate; a plurality of SRAM cells on the substrate, each SRAM cell including a plurality of channel layers, a plurality of gate structures, and a plurality of source / drain doped layers; a first dielectric layer on the substrate; a first conductive structure electrically connected to a portion of the gate structures and a portion of the source / drain doped layers; and a shared conductive structure including a second conductive structure and a shared conductive layer on the second conductive structure, wherein the top surface of the shared conductive structure is lower than the top surface of the first conductive structure. Because the top surface of the shared conductive structure is lower than the top surface of the first conductive structure, a larger formation space is provided for the subsequently formed power conductive layer, thereby increasing the process window of the power conductive layer, reducing the contact resistance between the power conductive layer and the subsequently formed second pull-up conductive layer, and effectively improving the performance of the SRAM.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a static random access memory and a method for forming the same. Background Technology

[0002] With the continuous development of digital integrated circuits, on-chip integrated memory has become an important component of digital systems. Static Random Access Memory (SRAM) has become an indispensable part of on-chip memory due to its advantages of low power consumption and high speed.

[0003] A basic static random access memory (SRAM) typically includes six transistors: two pull-up transistors (PU), two pull-down transistors (PD), and two pass-gate transistors (PG). SRAM operates continuously as long as a power supply is provided, storing data without requiring any update operations. Compared to dynamic random access memory (DRAM) circuits, it does not need to be refreshed and recharged periodically to prevent data loss; therefore, SRAM circuits offer higher performance and lower power consumption.

[0004] However, existing static random access memory still has many problems. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a static random access memory and a method for forming the same, which can effectively improve the performance of static random access memory.

[0006] To address the aforementioned problems, the present invention provides a static random access memory (SRAM), comprising: a substrate; a plurality of SRAM cells located on the substrate, each SRAM cell including a plurality of channel layers, a plurality of gate structures, and a plurality of source / drain doped layers; a first dielectric layer located on the substrate, the first dielectric layer covering the SRAM cells and exposing the top surfaces of the plurality of gate structures in the SRAM cells; a first conductive structure electrically connected to a portion of the gate structures and a portion of the source / drain doped layers; a shared conductive structure including a second conductive structure and a shared conductive layer located on the second conductive structure, the second conductive structure being electrically connected to a portion of the gate structures and a portion of the source / drain doped layers, the top surface of the shared conductive structure being lower than the top surface of the first conductive structure; and a second dielectric layer located on the first dielectric layer, the second dielectric layer covering the first conductive structure and the shared conductive structure.

[0007] Optionally, the static random access memory unit includes: a first transfer transistor, a first pull-up transistor, and a first pull-down transistor.

[0008] Optionally, the plurality of channel layers include: a first transmission channel layer, a first pull-up channel layer, and a first pull-down channel layer; the plurality of gate structures include: a first transmission gate, a first pull-up gate, and a first pull-down gate; the plurality of source / drain doped layers include: a first transmission source / drain doped layer, a first pull-up source / drain doped layer, and a first pull-down source / drain doped layer.

[0009] Optionally, the first transmission transistor includes: a first transmission channel layer, a first transmission gate structure spanning the first transmission channel layer, and first transmission source / drain doped layers located on both sides of the first transmission gate, wherein the first transmission source / drain doped layers are located within the first transmission channel layer; the first pull-up transistor includes: a first pull-up channel layer, a first pull-up gate structure spanning the first pull-up channel layer, and first pull-up source / drain doped layers located on both sides of the first pull-up gate, wherein the first pull-up source / drain doped layers are located within the first pull-up channel layer; the first pull-down transistor includes: a first pull-down channel layer, a first pull-down gate structure spanning the first pull-down channel layer, and first pull-down source / drain doped layers located on both sides of the first pull-down gate, wherein the first pull-down source / drain doped layers are located within the first pull-down channel layer.

[0010] Optionally, the first conductive structure includes: a first conductive layer on the first transmission gate, a conductive plug on the first transmission source / drain doped layer, and a second conductive layer on the conductive plug, wherein the top surface of the first conductive layer is flush with the top surface of the second conductive layer.

[0011] Optionally, the second conductive structure includes: a first pull-up conductive layer located on the first pull-up gate, a pull-down conductive plug located on the first pull-down source / drain doped layer, the shared conductive layer being located on the first pull-up conductive layer and the pull-down conductive plug, and the top surface of the shared conductive layer being lower than the top surface of the first transport conductive layer and the top surface of the second transport conductive layer.

[0012] Optionally, it may also include a cover layer located on the shared conductive structure, the top surface of the cover layer being flush with the top surface of the second dielectric layer.

[0013] Optionally, some of the channel layers further include: a second pull-up channel layer; some of the gate structures further include: a second pull-up gate; and some of the source / drain doped layers further include: a first pull-up source / drain doped layer.

[0014] Optionally, the static random access memory cell further includes: a second pull-up transistor, the second pull-up transistor including: a second pull-up channel layer, a second pull-up gate spanning the second pull-up channel layer, and a second pull-up source / drain doped layer located on both sides of the second pull-up gate, the second pull-up source / drain doped layer being located within the second pull-up channel layer.

[0015] Optionally, it further includes: a third conductive structure located on the second pull-up transistor, the third conductive structure being located within the second dielectric layer, and the top surface of the third conductive structure being flush with the top surface of the first conductive structure.

[0016] Optionally, the third conductive structure includes: a pull-up conductive plug located on the second pull-up source / drain doped layer, and a second pull-up conductive layer located on the pull-up conductive plug, wherein the top surface of the second pull-up conductive layer is flush with the top surface of the first transport conductive layer and the top surface of the second transport conductive layer.

[0017] Optionally, it further includes: a third dielectric layer and a fourth conductive structure, wherein the third dielectric layer is located on the second dielectric layer, the fourth conductive structure is located within the third dielectric layer, and the fourth conductive structure is electrically connected to the first conductive structure and the third conductive structure, respectively.

[0018] Optionally, the fourth conductive structure includes: a word line layer electrically connected to the first transmission conductive layer; a bit line layer electrically connected to the second transmission conductive layer; and a power conductive layer extending along the first direction and electrically connected to the second pull-up conductive layer.

[0019] Accordingly, the present invention also provides a method for forming a static random access memory (SRAM), comprising: providing a substrate; forming a plurality of SRAM cells and a first dielectric layer on the substrate, wherein the SRAM cells include a plurality of channel layers, a plurality of gate structures, and a plurality of source / drain doped layers, the first dielectric layer covering the SRAM cells, and exposing the top surfaces of the plurality of gate structures in the SRAM cells; forming a second dielectric layer, a first conductive structure, and a shared conductive structure, wherein the first conductive structure is electrically connected to a portion of the gate structures and a portion of the source / drain doped layers, the shared conductive structure includes a second conductive structure and a shared conductive layer located on the second conductive structure, the second conductive structure being electrically connected to a portion of the gate structures and a portion of the source / drain doped layers, the top surface of the shared conductive structure being lower than the top surface of the first conductive structure, the second dielectric layer being located on the first dielectric layer, and the second dielectric layer covering the first conductive structure and the shared conductive structure.

[0020] Optionally, the static random access memory unit includes: a first transfer transistor, a first pull-up transistor, and a first pull-down transistor.

[0021] Optionally, the plurality of channel layers include: a first transmission channel layer, a first pull-up channel layer, and a first pull-down channel layer; the plurality of gate structures include: a first transmission gate, a first pull-up gate, and a first pull-down gate; the plurality of source / drain doped layers include: a first transmission source / drain doped layer, a first pull-up source / drain doped layer, and a first pull-down source / drain doped layer.

[0022] Optionally, the first transmission transistor includes: a first transmission channel layer, a first transmission gate structure spanning the first transmission channel layer, and first transmission source / drain doped layers located on both sides of the first transmission gate, wherein the first transmission source / drain doped layers are located within the first transmission channel layer; the first pull-up transistor includes: a first pull-up channel layer, a first pull-up gate structure spanning the first pull-up channel layer, and first pull-up source / drain doped layers located on both sides of the first pull-up gate, wherein the first pull-up source / drain doped layers are located within the first pull-up channel layer; the first pull-down transistor includes: a first pull-down channel layer, a first pull-down gate structure spanning the first pull-down channel layer, and first pull-down source / drain doped layers located on both sides of the first pull-down gate, wherein the first pull-down source / drain doped layers are located within the first pull-down channel layer.

[0023] Optionally, the first conductive structure includes: a first conductive layer on the first transmission gate, a conductive plug on the first transmission source / drain doped layer, and a second conductive layer on the conductive plug, wherein the top surface of the first conductive layer is flush with the top surface of the second conductive layer.

[0024] Optionally, the second conductive structure includes: a first pull-up conductive layer located on the first pull-up gate, a pull-down conductive plug located on the first pull-down source / drain doped layer, the shared conductive layer being located on the first pull-up conductive layer and the pull-down conductive plug, and the top surface of the shared conductive layer being lower than the top surface of the first transport conductive layer and the top surface of the second transport conductive layer.

[0025] Optionally, the method for forming the shared conductive structure includes: forming a first pull-up conductive layer in the second dielectric layer, the first pull-up conductive layer being in contact with the first pull-up gate; forming a pull-down conductive plug in the second dielectric layer, the pull-down conductive plug being in contact with the first pull-down source / drain doped layer; forming an initial shared conductive layer in the second dielectric layer, the initial shared conductive layer being in contact with the first pull-up conductive layer and the pull-down conductive plug respectively, and the top surface of the initial shared conductive layer being flush with the top surface of the first transport conductive layer and the top surface of the second transport conductive layer; etching back the initial shared conductive layer to form the shared conductive layer, the top surface of the shared conductive layer being lower than the top surface of the first transport conductive layer and the top surface of the second transport conductive layer.

[0026] Optionally, after forming the shared conductive layer, the method further includes forming a capping layer on the shared conductive structure, wherein the top surface of the capping layer is flush with the top surface of the second dielectric layer.

[0027] Optionally, some of the channel layers further include: a second pull-up channel layer; some of the gate structures further include: a second pull-up gate; and some of the source / drain doped layers further include: a first pull-up source / drain doped layer.

[0028] Optionally, the static random access memory cell further includes: a second pull-up transistor, the second pull-up transistor including: a second pull-up channel layer, a second pull-up gate spanning the second pull-up channel layer, and a second pull-up source / drain doped layer located on both sides of the second pull-up gate, the second pull-up source / drain doped layer being located within the second pull-up channel layer.

[0029] Optionally, the process of forming the first conductive structure and the shared conductive structure further includes: forming a third conductive structure on the second pull-up transistor, the third conductive structure being located within the second dielectric layer, and the top surface of the third conductive structure being flush with the top surface of the first conductive structure.

[0030] Optionally, the third conductive structure includes: a pull-up conductive plug located on the second pull-up source / drain doped layer, and a second pull-up conductive layer located on the pull-up conductive plug, wherein the top surface of the second pull-up conductive layer is flush with the top surface of the first transport conductive layer and the top surface of the second transport conductive layer.

[0031] Optionally, after forming the first conductive structure and the shared conductive structure, the method further includes: forming a third dielectric layer and a fourth conductive structure, wherein the third dielectric layer is located on the second dielectric layer, the fourth conductive structure is located within the third dielectric layer, and the fourth conductive structure is electrically connected to the first conductive structure and the third conductive structure, respectively.

[0032] Optionally, the fourth conductive structure includes: a word line layer electrically connected to the first transmission conductive layer; a bit line layer electrically connected to the second transmission conductive layer; and a power conductive layer extending along the first direction and electrically connected to the second pull-up conductive layer.

[0033] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0034] The static random access memory (SRAM) of this invention includes: a first conductive structure electrically connected to a portion of the gate structure and a portion of the source / drain doped layers; and a shared conductive structure comprising a second conductive structure and a shared conductive layer located on the second conductive structure, wherein the second conductive structure is electrically connected to a portion of the gate structure and a portion of the source / drain doped layers, and the top surface of the shared conductive structure is lower than the top surface of the first conductive structure. Because the top surface of the shared conductive structure is lower than the top surface of the first conductive structure, the power conductive layer has a larger formation space, thereby increasing the process window of the power conductive layer, reducing the contact resistance between the power conductive layer and the second pull-up conductive layer, and effectively improving the performance of the SRAM.

[0035] In the method for forming a static random access memory (SRAM) according to the present invention, a first conductive structure and a shared conductive structure are formed. The first conductive structure is electrically connected to a portion of the gate structure and a portion of the source / drain doped layers. The shared conductive structure includes a second conductive structure and a shared conductive layer located on the second conductive structure. The second conductive structure is electrically connected to a portion of the gate structure and a portion of the source / drain doped layers. The top surface of the shared conductive structure is lower than the top surface of the first conductive structure. Because the top surface of the shared conductive structure is lower than the top surface of the first conductive structure, a larger formation space is provided for the subsequently formed power conductive layer, thereby increasing the process window of the power conductive layer, reducing the contact resistance between the power conductive layer and the subsequently formed second pull-up conductive layer, and effectively improving the performance of the SRAM. Attached Figure Description

[0036] Figures 1 to 2 This is a schematic diagram of a static random access memory (SRAM).

[0037] Figures 3 to 15 This is a schematic diagram of the structure of each step in the method for forming a static random access memory according to an embodiment of the present invention. Detailed Implementation

[0038] As described in the background section, existing static random access memories still have many problems. These will be explained in detail below with reference to the accompanying drawings.

[0039] Please refer to Figure 1 and Figure 2 , Figure 1 This is a top view of a static random access memory (SRAM). Figure 2 yes Figure 1A cross-sectional schematic diagram along line AA, omitting the substrate, the first pull-up transistor, and the second pull-up transistor, includes: a substrate 100; a first transmission transistor PG1, a first pull-up transistor PU1, and a first pull-down transistor PD1 located on the substrate 100; a first conductive structure (not shown), which is electrically connected to the first transmission transistor PG1; and a second conductive structure 101, which is electrically connected to the first pull-up transistor PU1 and the first pull-down transistor PD1, respectively, with the top surface of the second conductive structure 101 flush with the top surface of the first conductive structure.

[0040] In this embodiment, the first transmission transistor PG1 includes: a first transmission gate and a first transmission source / drain doped layer (not shown) located on both sides of the first transmission gate; the first pull-up transistor PU1 includes: a first pull-up gate and a first pull-up source / drain doped layer (not shown) located on both sides of the first pull-up gate; the first pull-down transistor PD1 includes: a first pull-down gate and a first pull-down source / drain doped layer (not shown) located on both sides of the first pull-down gate.

[0041] The first conductive structure includes: a first conductive layer on the first transmission gate, a conductive plug on the first transmission source / drain doped layer, and a second conductive layer on the conductive plug, wherein the top surface of the first conductive layer is flush with the top surface of the second conductive layer.

[0042] The second conductive structure 101 includes: a first pull-up conductive layer 101a located on the first pull-up gate, a pull-down conductive plug 101b located on the first pull-down source / drain doped layer, and a shared conductive layer 101c located on the first pull-up conductive layer and the pull-down conductive plug, wherein the top surface of the shared conductive layer 101c is flush with the top surface of the first transmission conductive layer and the top surface of the second transmission conductive layer.

[0043] Please continue to refer to this. Figure 1 and Figure 2 It also includes: a second pull-up transistor PU2 located on the substrate 100; and a third conductive structure 102 located on the second pull-up transistor PU2, wherein the top surface of the third conductive structure 102 is flush with the top surface of the first conductive structure.

[0044] In this embodiment, the second pull-up transistor PU2 includes a second pull-up gate and a second pull-up source / drain doped layer (not shown) located on both sides of the second pull-up gate; the third conductive structure 102 includes: a pull-up conductive plug 102a located on the second pull-up source / drain doped layer, and a second pull-up conductive layer 102b located on the pull-up conductive plug, wherein the top surface of the second pull-up conductive layer 102b is flush with the top surface of the first transmission conductive layer and the top surface of the second transmission conductive layer.

[0045] Please continue to refer to this. Figure 1 and Figure 2 It also includes a power conductive layer 103, which is electrically connected to the second pull-up conductive layer 102b.

[0046] In this embodiment, according to circuit design requirements, the power conductive layer 103 must not be short-circuited with the shared conductive layer 101c. However, since the top surface of the shared conductive layer 101c is flush with the top surfaces of the first and second transmission conductive layers, to avoid a short circuit between the power conductive layer 103 and the shared conductive layer 101c, the design size of the power conductive layer 103 needs to be reduced. This results in a smaller volume of the power conductive layer 103, an increased contact resistance between the power conductive layer 103 and the second pull-up conductive layer 102b, and a smaller process window for the power conductive layer 103, thereby reducing the performance of the static random access memory.

[0047] Based on this, the present invention provides a static random access memory and a method for forming the same. By lowering the top surface of the shared conductive structure below the top surface of the first conductive structure, the power conductive layer formed subsequently has a larger formation space, thereby increasing the process window of the power conductive layer, reducing the contact resistance between the power conductive layer and the second pull-up conductive layer, and effectively improving the performance of the static random access memory.

[0048] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0049] Figures 3 to 15 This is a schematic diagram of the formation process of a static random access memory according to an embodiment of the present invention.

[0050] Please refer to Figure 3 Provides a base.

[0051] In this embodiment, the substrate 200 is made of silicon; in other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0052] In this embodiment, after providing the substrate 200, a plurality of static random access memory (SRAM) cells and a first dielectric layer are formed on the substrate 200. Each SRAM cell includes a plurality of channel layers, a plurality of gate structures, and a plurality of source / drain doped layers. The first dielectric layer covers the SRAM cells and exposes the top surfaces of the gate structures within the SRAM cells. For a detailed formation process, please refer to [reference needed]. Figures 4 to 9 .

[0053] In this embodiment, the plurality of channel layers include: a first transmission channel layer, a first pull-up channel layer, a first pull-down channel layer, a second transmission channel layer, a second pull-up channel layer, and a second pull-down channel layer; the plurality of gate structures include: a first transmission gate, a first pull-up gate, a first pull-down gate, a second transmission gate, a second pull-up gate, and a second pull-down gate; the plurality of source / drain doped layers include: a first transmission source / drain doped layer, a first pull-up source / drain doped layer, a first pull-down source / drain doped layer, a second transmission source / drain doped layer, a second pull-up source / drain doped layer, and a second pull-down source / drain doped layer.

[0054] Please refer to Figures 4 to 6 , Figure 4 This is a 3D diagram of a static random access memory (SRAM). Figure 5 yes Figure 4 Top view, Figure 6 yes Figure 5 A schematic diagram of the cross-section along the BB line shows that a first transmission channel layer, a first pull-up channel layer, a first pull-down channel layer, a second transmission channel layer, a second pull-up channel layer, and a second pull-down channel layer (not shown) are formed on the substrate 200.

[0055] In this embodiment, the first transmission channel layer, the first pull-up channel layer, the first pull-down channel layer, the second transmission channel layer, the second pull-up channel layer, and the first pull-down channel layer extend along the first direction X.

[0056] In this embodiment, the first transmission channel layer, the first pull-up channel layer, the first pull-down channel layer, the second transmission channel layer, the second pull-up channel layer, and the first pull-down channel layer are made of silicon. In other embodiments, the materials of the first transmission channel layer, the first pull-up channel layer, the first pull-down channel layer, the second transmission channel layer, the second pull-up channel layer, and the first pull-down channel layer may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0057] In this embodiment, the first transmission channel layer, the first pull-up channel layer, the first pull-down channel layer, the second transmission channel layer, the second pull-up channel layer, and the first pull-down channel layer adopt a fin structure; in other embodiments, the first transmission channel layer, the first pull-up channel layer, the first pull-down channel layer, the second transmission channel layer, the second pull-up channel layer, and the first pull-down channel layer may also adopt a GAA structure or a nanosheet structure.

[0058] Please refer to Figure 7 , Figure 7 and Figure 6 The view orientation is consistent, and an isolation layer 201 is formed on the substrate.

[0059] In this embodiment, the isolation layer covers part of the sidewalls of the first transmission channel layer, the first pull-up channel layer, the first pull-down channel layer, the second transmission channel layer, the second pull-up channel layer, and the first pull-down channel layer, and the top surface of the isolation layer is lower than the top surfaces of the first transmission channel layer, the first pull-up channel layer, the first pull-down channel layer, the second transmission channel layer, the second pull-up channel layer, and the first pull-down channel layer.

[0060] In this embodiment, the material of the isolation layer is silicon oxide.

[0061] Please refer to Figure 8 and Figure 9 , Figure 8 This is a top view of a static random access memory (SRAM) omitting the first media layer. Figure 9 yes Figure 8 A schematic cross-sectional view along the CC line shows that a first dielectric layer 202 and a plurality of static random access memory (SRAM) cells are formed on the substrate 200. The first dielectric layer 202 covers the SRAM cells and exposes the top surface of a plurality of gate structures in the SRAM cells.

[0062] In this embodiment, the static random access memory unit includes: a first transfer transistor PG1, a first pull-up transistor PU1, a first pull-down transistor PD1, a second transfer transistor PG2, a second pull-up transistor PU2, and a second pull-down transistor PD2.

[0063] In this embodiment, the first transmission transistor PG1 includes: a first transmission channel layer, a first transmission gate structure spanning the first transmission channel layer, and a first transmission source / drain doped layer located on both sides of the first transmission gate, wherein the first transmission source / drain doped layer is located within the first transmission channel layer.

[0064] In this embodiment, the first pull-up transistor PU2 includes: a first pull-up channel layer, a first pull-up gate structure spanning the first pull-up channel layer, and a first pull-up source / drain doped layer located on both sides of the first pull-up gate, wherein the first pull-up source / drain doped layer is located within the first pull-up channel layer.

[0065] In this embodiment, the first pull-down transistor PD1 includes: a first pull-down channel layer, a first pull-down gate structure spanning the first pull-down channel layer, and a first pull-down source / drain doped layer located on both sides of the first pull-down gate, wherein the first pull-down source / drain doped layer is located within the first pull-down channel layer.

[0066] In this embodiment, the first dielectric layer 202 is made of silicon oxide; in other embodiments, the first dielectric layer may also be made of a low-k dielectric material (referring to a dielectric material with a relative permittivity of less than 3.9) or an ultra-low-k dielectric material (referring to a dielectric material with a relative permittivity of less than 2.5).

[0067] Please refer to Figures 10 to 12 , Figure 9 This is a top view of a static random access memory (SRAM) omitting the first media layer, the second media layer, and the overlay layer. Figure 11 yes Figure 10 A cross-sectional view along the DD line, omitting the first transmission transistor. Figure 12 yes Figure 10 A cross-sectional view along the EE line, omitting the first and second pull-up transistors, shows a second dielectric layer 209, a first conductive structure, and a shared conductive structure. The first conductive structure is electrically connected to a portion of the gate structure and a portion of the source / drain doped layers. The shared conductive structure includes a second conductive structure and a shared conductive layer 208 located on the second conductive structure. The second conductive structure is electrically connected to a portion of the gate structure and a portion of the source / drain doped layers. The top surface of the shared conductive structure is lower than the top surface of the first conductive structure. The second dielectric layer is located on the first dielectric layer 202 and covers the first conductive structure and the shared conductive structure.

[0068] In this embodiment, the first conductive structure includes: a first conductive layer 203 located on the first transmission gate, a conductive plug 204 located on the first transmission source / drain doped layer, and a second conductive layer 205 located on the conductive plug 204, wherein the top surface of the first conductive layer 203 is flush with the top surface of the second conductive layer 205.

[0069] In this embodiment, the second conductive structure includes: a first pull-up conductive layer 206 located on the first pull-up gate, a pull-down conductive plug 207 located on the first pull-down source / drain doped layer, a shared conductive layer 208 located on the first pull-up conductive layer 206 and the pull-down conductive plug 207, and the top surface of the shared conductive layer 208 being lower than the top surface of the first transmission conductive layer 203 and the top surface of the second transmission conductive layer 205.

[0070] In this embodiment, the method for forming the shared conductive structure includes: forming a first pull-up conductive layer 206 in the second dielectric layer 209, the first pull-up conductive layer 206 being in contact with the first pull-up gate; forming a pull-down conductive plug 207 in the second dielectric layer 209, the pull-down conductive plug 207 being in contact with the first pull-down source / drain doped layer; forming an initial shared conductive layer (not shown) in the second dielectric layer 209, the initial shared conductive layer being in contact with the first pull-up conductive layer 206 and the pull-down conductive plug 207 respectively, and the top surface of the initial shared conductive layer being flush with the top surface of the first transmission conductive layer 203 and the top surface of the second transmission conductive layer 205; etching back the initial shared conductive layer to form the shared conductive layer 208, the top surface of the shared conductive layer 208 being lower than the top surface of the first transmission conductive layer 203 and the top surface of the second transmission conductive layer 205.

[0071] In this embodiment, after forming the shared conductive layer 208, the method further includes forming a cover layer 210 on the shared conductive layer 208, wherein the top surface of the cover layer 210 is flush with the top surface of the second dielectric layer 209.

[0072] In this embodiment, the process of forming the first conductive structure and the shared conductive structure further includes: forming a third conductive structure on the second pull-up transistor PU2, wherein the third conductive structure is located within the second dielectric layer 209, and the top surface of the third conductive structure is flush with the top surface of the first conductive structure.

[0073] In this embodiment, the third conductive structure includes: a pull-up conductive plug 211 located on the second pull-up source / drain doped layer, and a second pull-up conductive layer 212 located on the pull-up conductive plug 211, wherein the top surface of the second pull-up conductive layer 212 is flush with the top surface of the first transport conductive layer 203 and the top surface of the second transport conductive layer 205.

[0074] In this embodiment, a first conductive structure and a shared conductive structure are formed. The first conductive structure is electrically connected to a portion of the gate structure and a portion of the source / drain doped layers. The shared conductive structure includes a second conductive structure and a shared conductive layer located on the second conductive structure. The second conductive structure is electrically connected to a portion of the gate structure and a portion of the source / drain doped layers. The top surface of the shared conductive structure is lower than the top surface of the first conductive structure. Because the top surface of the shared conductive structure is lower than the top surface of the first conductive structure, a larger formation space is provided for the subsequently formed power conductive layer, thereby increasing the process window of the power conductive layer, reducing the contact resistance between the power conductive layer and the subsequently formed second pull-up conductive layer, and effectively improving the performance of the static random access memory.

[0075] Please refer to Figures 13 to 15 , Figure 13 This is a top view of a static random access memory (SRAM) omitting the first, second, and third media layers. Figure 14 yes Figure 13 A cross-sectional view along the FF line, omitting the first transfer transistor. Figure 15 yes Figure 13 A cross-sectional view along the GG line, omitting the first and second pull-up transistors, shows that after the first conductive structure and the shared conductive structure are formed, a third dielectric layer 213 and a fourth conductive structure are formed. The third dielectric layer 213 is located on the second dielectric layer 209, and the fourth conductive structure is located within the third dielectric layer 213. The fourth conductive structure is electrically connected to both the first conductive structure and the third conductive structure.

[0076] In this embodiment, the fourth conductive structure includes: a word line layer 214, which is electrically connected to the first transmission conductive layer 203; a bit line layer 215, which is electrically connected to the second transmission conductive layer 205; and a power conductive layer 216, which extends along the first direction X and is electrically connected to the second pull-up conductive layer 212.

[0077] In this embodiment, since the top surface of the shared conductive structure is lower than the top surface of the first conductive structure, the power conductive layer 216 has a larger formation space. The size of the power conductive layer 16 in the first direction X can be equal to the size of the first pull-up channel layer in the first direction, thereby increasing the process window of the power conductive layer 216, reducing the contact resistance between the power conductive layer 16 and the subsequently formed second pull-up conductive layer 212, and effectively improving the performance of the static random access memory.

[0078] Accordingly, embodiments of the present invention also provide a static random access memory (SRAM), please refer to [link to previous document]. Figures 13 to 15 The system includes: a substrate 200; a plurality of static random access memory (SRAM) cells located on the substrate 200, each SRAM cell including a plurality of channel layers, a plurality of gate structures, and a plurality of source / drain doped layers; a first dielectric layer 202 located on the substrate 200, the first dielectric layer 202 covering the SRAM cells and exposing the top surfaces of the plurality of gate structures in the SRAM cells; a first conductive structure electrically connected to a portion of the gate structures and a portion of the source / drain doped layers; a shared conductive structure including a second conductive structure and a shared conductive layer 208 located on the second conductive structure, the second conductive structure being electrically connected to a portion of the gate structures and a portion of the source / drain doped layers, the top surface of the shared conductive structure being lower than the top surface of the first conductive structure; and a second dielectric layer 209 located on the first dielectric layer 202, the second dielectric layer 209 covering the first conductive structure and the shared conductive structure.

[0079] In this embodiment, since the top surface of the shared conductive structure is lower than the top surface of the first conductive structure, the power conductive layer 216 has a larger forming space, thereby increasing the process window of the power conductive layer 216, reducing the contact resistance between the power conductive layer 216 and the second pull-up conductive layer 212, and effectively improving the performance of the static random access memory.

[0080] In this embodiment, the static random access memory unit includes: a first transfer transistor PG1, a first pull-up transistor PU1, and a first pull-down transistor PD1.

[0081] In this embodiment, the plurality of channel layers include: a first transmission channel layer, a first pull-up channel layer, and a first pull-down channel layer; the plurality of gate structures include: a first transmission gate, a first pull-up gate, and a first pull-down gate; the plurality of source / drain doped layers include: a first transmission source / drain doped layer, a first pull-up source / drain doped layer, and a first pull-down source / drain doped layer.

[0082] In this embodiment, the first transmission transistor PG1 includes: a first transmission channel layer, a first transmission gate structure spanning the first transmission channel layer, and first transmission source / drain doped layers located on both sides of the first transmission gate, wherein the first transmission source / drain doped layers are located within the first transmission channel layer; the first pull-up transistor PU1 includes: a first pull-up channel layer, a first pull-up gate structure spanning the first pull-up channel layer, and first pull-up source / drain doped layers located on both sides of the first pull-up gate, wherein the first pull-up source / drain doped layers are located within the first pull-up channel layer; the first pull-down transistor PD1 includes: a first pull-down channel layer, a first pull-down gate structure spanning the first pull-down channel layer, and first pull-down source / drain doped layers located on both sides of the first pull-down gate, wherein the first pull-down source / drain doped layers are located within the first pull-down channel layer.

[0083] In this embodiment, the first conductive structure includes: a first conductive layer 203 located on the first transmission gate, a conductive plug 204 located on the first transmission source / drain doped layer, and a second conductive layer 205 located on the conductive plug 204, wherein the top surface of the first conductive layer 203 is flush with the top surface of the second conductive layer 205.

[0084] In this embodiment, the second conductive structure includes: a first pull-up conductive layer 206 located on the first pull-up gate, a pull-down conductive plug 207 located on the first pull-down source / drain doped layer, a shared conductive layer 208 located on the first pull-up conductive layer 206 and the pull-down conductive plug 207, and the top surface of the shared conductive layer 208 being lower than the top surface of the first transmission conductive layer 203 and the top surface of the second transmission conductive layer 205.

[0085] In this embodiment, it further includes a cover layer 210 located on the shared conductive structure, the top surface of the cover layer 210 being flush with the top surface of the second dielectric layer 209.

[0086] In this embodiment, the plurality of channel layers further include: a second pull-up channel layer; the plurality of gate structures further include: a second pull-up gate; and the plurality of source / drain doped layers further include: a first pull-up source / drain doped layer.

[0087] In this embodiment, the static random access memory cell further includes a second pull-up transistor PU2, which includes a second pull-up channel layer, a second pull-up gate spanning the second pull-up channel layer, and a second pull-up source / drain doped layer located on both sides of the second pull-up gate. The second pull-up source / drain doped layer is located within the second pull-up channel layer.

[0088] In this embodiment, it further includes a third conductive structure located on the second pull-up transistor PU2, the third conductive structure being located within the second dielectric layer 209, and the top surface of the third conductive structure being flush with the top surface of the first conductive structure.

[0089] In this embodiment, the third conductive structure includes: a pull-up conductive plug 211 located on the second pull-up source / drain doped layer, and a second pull-up conductive layer 212 located on the pull-up conductive plug 211, wherein the top surface of the second pull-up conductive layer 212 is flush with the top surface of the first transport conductive layer 203 and the top surface of the second transport conductive layer 205.

[0090] In this embodiment, it further includes a third dielectric layer 213 and a fourth conductive structure. The third dielectric layer 213 is located on the second dielectric layer 209, and the fourth conductive structure is located within the third dielectric layer 213. The fourth conductive structure is electrically connected to the first conductive structure and the third conductive structure, respectively.

[0091] In this embodiment, the fourth conductive structure includes: a word line layer 214, which is electrically connected to the first transmission conductive layer 203; a bit line layer 215, which is electrically connected to the second transmission conductive layer 205; and a power conductive layer 216, which extends along the first direction X and is electrically connected to the second pull-up conductive layer 212.

[0092] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A static random access memory, characterized in that, include: Base; A plurality of static random access memory cells are located on the substrate, wherein the static random access memory cells include a plurality of channel layers, a plurality of gate structures and a plurality of source and drain doped layers; A first dielectric layer is located on the substrate, the first dielectric layer covers the static random access memory cell, and exposes the top surface of a plurality of gate structures in the static random access memory cell; A first conductive structure is electrically connected to a portion of the gate structure and a portion of the source / drain doped layers; A shared conductive structure includes a second conductive structure and a shared conductive layer located on the second conductive structure. The second conductive structure is electrically connected to a portion of the gate structure and a portion of the source / drain doped layers. The top surface of the shared conductive structure is lower than the top surface of the first conductive structure. A second dielectric layer is located on the first dielectric layer, and the second dielectric layer covers the first conductive structure and the shared conductive structure; wherein... The static random access memory unit includes: a first transfer transistor, a first pull-up transistor, and a first pull-down transistor; The plurality of channel layers include: a first transport channel layer, a first pull-up channel layer, and a first pull-down channel layer; the plurality of gate structures include: a first transport gate, a first pull-up gate, and a first pull-down gate; the plurality of source / drain doped layers include: a first transport source / drain doped layer, a first pull-up source / drain doped layer, and a first pull-down source / drain doped layer; The first transmission transistor includes: a first transmission channel layer, a first transmission gate structure spanning the first transmission channel layer, and first transmission source / drain doped layers located on both sides of the first transmission gate, wherein the first transmission source / drain doped layers are located within the first transmission channel layer; the first pull-up transistor includes: a first pull-up channel layer, a first pull-up gate structure spanning the first pull-up channel layer, and first pull-up source / drain doped layers located on both sides of the first pull-up gate, wherein the first pull-up source / drain doped layers are located within the first pull-up channel layer; the first pull-down transistor includes: a first pull-down channel layer, a first pull-down gate structure spanning the first pull-down channel layer, and first pull-down source / drain doped layers located on both sides of the first pull-down gate, wherein the first pull-down source / drain doped layers are located within the first pull-down channel layer; The first conductive structure includes: a first conductive layer on the first transmission gate, a conductive plug on the first transmission source / drain doped layer, and a second conductive layer on the conductive plug, wherein the top surface of the first conductive layer is flush with the top surface of the second conductive layer.

2. The static random access memory as described in claim 1, characterized in that, The second conductive structure includes: a first pull-up conductive layer located on a first pull-up gate, a pull-down conductive plug located on a first pull-down source / drain doped layer, a shared conductive layer located on the first pull-up conductive layer and the pull-down conductive plug, and the top surface of the shared conductive layer being lower than the top surface of the first transmission conductive layer and the top surface of the second transmission conductive layer.

3. The static random access memory as described in claim 1, characterized in that, Also includes: A cover layer is located on the shared conductive structure, the top surface of which is flush with the top surface of the second dielectric layer.

4. The static random access memory as described in claim 1, characterized in that, The channel layers further include: a second pull-up channel layer; the gate structures further include: a second pull-up gate; the source / drain doped layers further include: a first pull-up source / drain doped layer.

5. The static random access memory as described in claim 4, characterized in that, The static random access memory cell further includes a second pull-up transistor, which includes a second pull-up channel layer, a second pull-up gate spanning the second pull-up channel layer, and a second pull-up source / drain doped layer located on both sides of the second pull-up gate, wherein the second pull-up source / drain doped layer is located within the second pull-up channel layer.

6. The static random access memory as described in claim 5, characterized in that, Also includes: A third conductive structure is located on the second pull-up transistor, the third conductive structure is located within the second dielectric layer, and the top surface of the third conductive structure is flush with the top surface of the first conductive structure.

7. The static random access memory as described in claim 6, characterized in that, The third conductive structure includes: a pull-up conductive plug located on the second pull-up source / drain doped layer, and a second pull-up conductive layer located on the pull-up conductive plug, wherein the top surface of the second pull-up conductive layer is flush with the top surface of the first transport conductive layer and the top surface of the second transport conductive layer.

8. The static random access memory as described in claim 7, characterized in that, Also includes: A third dielectric layer and a fourth conductive structure, wherein the third dielectric layer is located on the second dielectric layer, the fourth conductive structure is located within the third dielectric layer, and the fourth conductive structure is electrically connected to the first conductive structure and the third conductive structure, respectively.

9. The static random access memory as described in claim 8, characterized in that, The fourth conductive structure includes: a word line layer electrically connected to the first transmission conductive layer; a bit line layer electrically connected to the second transmission conductive layer; and a power conductive layer extending along a first direction and electrically connected to the second pull-up conductive layer.

10. A method for forming a static random access memory, characterized in that, include: Provide a base; A plurality of static random access memory cells and a first dielectric layer are formed on the substrate. The static random access memory cells include a plurality of channel layers, a plurality of gate structures and a plurality of source and drain doped layers. The first dielectric layer covers the static random access memory cells and exposes the top surfaces of a plurality of gate structures in the static random access memory cells. A second dielectric layer, a first conductive structure, and a shared conductive structure are formed. The first conductive structure is electrically connected to a portion of the gate structure and a portion of the source / drain doped layers. The shared conductive structure includes a second conductive structure and a shared conductive layer located on the second conductive structure. The second conductive structure is electrically connected to a portion of the gate structure and a portion of the source / drain doped layers. The top surface of the shared conductive structure is lower than the top surface of the first conductive structure. The second dielectric layer is located on the first dielectric layer and covers the first conductive structure and the shared conductive structure. The static random access memory unit includes: a first transfer transistor, a first pull-up transistor, and a first pull-down transistor; The plurality of channel layers include: a first transport channel layer, a first pull-up channel layer, and a first pull-down channel layer; the plurality of gate structures include: a first transport gate, a first pull-up gate, and a first pull-down gate; the plurality of source / drain doped layers include: a first transport source / drain doped layer, a first pull-up source / drain doped layer, and a first pull-down source / drain doped layer; The first transmission transistor includes: a first transmission channel layer, a first transmission gate structure spanning the first transmission channel layer, and first transmission source / drain doped layers located on both sides of the first transmission gate, wherein the first transmission source / drain doped layers are located within the first transmission channel layer; the first pull-up transistor includes: a first pull-up channel layer, a first pull-up gate structure spanning the first pull-up channel layer, and first pull-up source / drain doped layers located on both sides of the first pull-up gate, wherein the first pull-up source / drain doped layers are located within the first pull-up channel layer; the first pull-down transistor includes: a first pull-down channel layer, a first pull-down gate structure spanning the first pull-down channel layer, and first pull-down source / drain doped layers located on both sides of the first pull-down gate, wherein the first pull-down source / drain doped layers are located within the first pull-down channel layer; The first conductive structure includes: a first conductive layer on the first transmission gate, a conductive plug on the first transmission source / drain doped layer, and a second conductive layer on the conductive plug, wherein the top surface of the first conductive layer is flush with the top surface of the second conductive layer.

11. The method for forming a static random access memory as described in claim 10, characterized in that, The second conductive structure includes: a first pull-up conductive layer located on a first pull-up gate, a pull-down conductive plug located on a first pull-down source / drain doped layer, a shared conductive layer located on the first pull-up conductive layer and the pull-down conductive plug, and the top surface of the shared conductive layer being lower than the top surface of the first transmission conductive layer and the top surface of the second transmission conductive layer.

12. The method for forming a static random access memory as described in claim 11, characterized in that, The method for forming the shared conductive structure includes: forming a first pull-up conductive layer in the second dielectric layer, the first pull-up conductive layer being in contact with the first pull-up gate; forming a pull-down conductive plug in the second dielectric layer, the pull-down conductive plug being in contact with the first pull-down source / drain doped layer; forming an initial shared conductive layer in the second dielectric layer, the initial shared conductive layer being in contact with the first pull-up conductive layer and the pull-down conductive plug respectively, and the top surface of the initial shared conductive layer being flush with the top surface of the first transport conductive layer and the top surface of the second transport conductive layer; etching back the initial shared conductive layer to form the shared conductive layer, the top surface of the shared conductive layer being lower than the top surface of the first transport conductive layer and the top surface of the second transport conductive layer.

13. The method for forming a static random access memory as described in claim 10, characterized in that, After forming the shared conductive layer, the method further includes forming a capping layer on the shared conductive structure, wherein the top surface of the capping layer is flush with the top surface of the second dielectric layer.

14. The method for forming a static random access memory as described in claim 10, characterized in that, The channel layers further include: a second pull-up channel layer; the gate structures further include: a second pull-up gate; the source / drain doped layers further include: a first pull-up source / drain doped layer.

15. The method for forming a static random access memory as described in claim 14, characterized in that, The static random access memory cell further includes a second pull-up transistor, which includes a second pull-up channel layer, a second pull-up gate spanning the second pull-up channel layer, and a second pull-up source / drain doped layer located on both sides of the second pull-up gate, wherein the second pull-up source / drain doped layer is located within the second pull-up channel layer.

16. The method for forming a static random access memory as described in claim 15, characterized in that, In the process of forming the first conductive structure and the shared conductive structure, the method further includes: forming a third conductive structure on the second pull-up transistor, the third conductive structure being located within the second dielectric layer, and the top surface of the third conductive structure being flush with the top surface of the first conductive structure.

17. The method for forming a static random access memory as described in claim 16, characterized in that, The third conductive structure includes: a pull-up conductive plug located on the second pull-up source / drain doped layer, and a second pull-up conductive layer located on the pull-up conductive plug, wherein the top surface of the second pull-up conductive layer is flush with the top surface of the first transport conductive layer and the top surface of the second transport conductive layer.

18. The method for forming a static random access memory as described in claim 17, characterized in that, After forming the first conductive structure and the shared conductive structure, the method further includes: forming a third dielectric layer and a fourth conductive structure, wherein the third dielectric layer is located on the second dielectric layer, the fourth conductive structure is located within the third dielectric layer, and the fourth conductive structure is electrically connected to the first conductive structure and the third conductive structure, respectively.

19. The method for forming a static random access memory as described in claim 18, characterized in that, The fourth conductive structure includes: a word line layer electrically connected to the first transmission conductive layer; a bit line layer electrically connected to the second transmission conductive layer; and a power conductive layer extending along a first direction and electrically connected to the second pull-up conductive layer.

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