Semiconductor Structure and Method of Manufacturing the Same

Abstract

An embodiment of the present invention provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate and a memory cell located on the substrate. The memory cell includes a first dielectric layer and a metal bit line located within the first dielectric layer; a semiconductor channel is located on a partial surface of the metal bit line; a word line is disposed to surround a partial area of the semiconductor channel; a second dielectric layer is located between the metal bit line and the word line and on a side of the word line away from the substrate; a first lower electrode layer and a second lower electrode layer are stacked on a top surface of the semiconductor channel away from the metal bit line, and the first lower electrode layer is in contact with the top surface of the semiconductor channel; an upper electrode layer is located on the top surface of the second lower electrode layer and surrounds the first lower electrode layer and the second lower electrode layer; a capacitive dielectric layer is located between the upper electrode layer and the first lower electrode layer and also between the upper electrode layer and the second lower electrode layer. The embodiment of the present invention is beneficial to improving the integration density of the semiconductor structure while increasing the capacitance and improving the capacitance size accuracy.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor technology, and in particular, to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] With the increasing demand for high performance and low cost of semiconductor devices, the demand for high integration density and high storage capacity of semiconductor devices also increases.

[0003] However, with the increase in the integration density of semiconductor devices, while increasing the capacitance of capacitors in semiconductor devices, the aspect ratio of the capacitors is also getting higher and higher. Due to the limitations of process equipment and the size of semiconductor devices, the dimensional accuracy of forming capacitors with a high aspect ratio is not high, which affects the electrical performance of the capacitors.

[0004] Therefore, while increasing the integration density of the semiconductor structure, it is necessary to design a semiconductor device that can not only increase the capacitance but also improve the dimensional accuracy of the capacitor. Summary of the Invention

[0005] Embodiments of the present invention provide a semiconductor structure and a manufacturing method thereof, which are beneficial to increasing the capacitance and improving the dimensional accuracy of the capacitor while increasing the integration density of the semiconductor structure.

[0006] To solve the above problems, embodiments of the present invention provide a semiconductor structure, including: a substrate and a storage unit located on the substrate, the storage unit including: a first dielectric layer and a metal bit line located in the first dielectric layer, and the first dielectric layer exposes the surface of the metal bit line; a semiconductor channel, the semiconductor channel is located on a part of the surface of the metal bit line, and the bottom surface of the semiconductor channel facing the metal bit line is electrically connected to the metal bit line; a word line, the word line is disposed around a part of the region of the semiconductor channel; a second dielectric layer, the second dielectric layer is located between the metal bit line and the word line, and is also located on the side of the word line away from the substrate; a first lower electrode layer and a second lower electrode layer stacked on the top surface of the semiconductor channel away from the metal bit line, the first lower electrode layer is in contact with the top surface of the semiconductor channel; an upper electrode layer, the upper electrode layer is located on the top surface of the second lower electrode layer, and surrounds the first lower electrode layer and the second lower electrode layer; a capacitor dielectric layer, the capacitor dielectric layer is located between the upper electrode layer and the first lower electrode layer, and is also located between the upper electrode layer and the second lower electrode layer.

[0007] Accordingly, an embodiment of the present invention further provides a method for manufacturing a semiconductor structure, including: providing a substrate; forming a memory cell on the substrate, and the process steps of forming the memory cell include: providing a first dielectric layer and a metal bit line located in the first dielectric layer, and the first dielectric layer exposes the surface of the metal bit line; forming a semiconductor channel, the semiconductor channel is located on a partial surface of the metal bit line, and the bottom surface of the semiconductor channel facing the metal bit line is electrically connected to the metal bit line; forming a word line, the word line is disposed to surround a partial area of the semiconductor channel; forming a second dielectric layer, the second dielectric layer is located between the metal bit line and the word line, and is also located on a side of the word line away from the substrate; forming a first lower electrode layer, the first lower electrode layer is in contact with the top surface of the semiconductor channel; forming a second lower electrode layer, the second lower electrode layer is located on the top surface of the first lower electrode layer; forming an upper electrode layer, the upper electrode layer is located on the top surface of the second lower electrode layer, and is formed to surround the first lower electrode layer and the second lower electrode layer; forming a capacitor dielectric layer, the capacitor dielectric layer is located between the upper electrode layer and the first lower electrode layer, and is also located between the upper electrode layer and the second lower electrode layer.

[0008] The technical solution provided by the embodiment of the present invention has the following advantages:

[0009] In the above technical solution, the lower electrode layer of the capacitor in the semiconductor structure is composed of a first lower electrode layer and a second lower electrode layer stacked, which is beneficial to increasing the overall height of the lower electrode layer of the capacitor to increase the aspect ratio of the capacitor, thereby increasing the facing area between the upper electrode layer and the lower electrode layer in the capacitor to increase the capacitance of the capacitor. Further, the channel region of the semiconductor channel is vertically disposed on the surface of the metal bit line, that is, the extending direction of the channel region is perpendicular to the surface of the metal bit line. Without reducing the size of the semiconductor channel, it is beneficial to save the layout space of the semiconductor channel in the direction parallel to the surface of the metal bit line (usually the horizontal direction), thereby increasing the integration density of the semiconductor structure in the horizontal direction.

[0010] In addition, the orthographic projection of the bottom surface of the second lower electrode layer on the substrate is located within the orthographic projection of the top surface of the first lower electrode layer on the substrate, so that the second lower electrode layer is aligned with the first lower electrode layer, that is, it is ensured that the bottom surface of the second lower electrode layer is in complete contact with the top surface of the first lower electrode layer, avoiding misalignment between the bottom surface of the second lower electrode layer and the top surface of the first lower electrode layer. Thus, while increasing the capacitance, the dimensional accuracy of the capacitor is improved to improve the formation quality of the capacitor and ensure that the capacitor has good electrical performance.

[0011] In addition, the capacitive dielectric layer covers the top and side surfaces of the second lower electrode layer, and also covers the side surface of the first lower electrode layer and the top surface of the first lower electrode layer exposed by the second lower electrode layer, preventing the upper electrode layer from contacting the first lower electrode layer through the top surface of the first lower electrode layer exposed by the second lower electrode layer, so as to further ensure that the capacitor has good electrical performance.

[0012] In addition, the semiconductor channel is used to form the channel of the junctionless transistor. The junctionless transistor has no PN junction, has a simple manufacturing process and excellent performance, enhances the reliability of the device, especially the hot carrier injection effect and noise tolerance, and is conducive to further improving the electrical performance of the semiconductor structure. Brief Description of the Drawings

[0013] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. Unless otherwise stated, the figures in the drawings do not constitute a proportional limitation.

[0014] Figure 1 It is a schematic cross-sectional structure diagram corresponding to the semiconductor structure provided by an embodiment of the present invention;

[0015] Figures 2 to 6 It is five schematic cross-sectional structure diagrams of the structure jointly formed by the first lower electrode layer, the second lower electrode layer and the capacitive dielectric layer in the semiconductor structure provided by an embodiment of the present invention;

[0016] Figures 7 to 22 It is a schematic cross-sectional structure diagram corresponding to each step in the manufacturing method of the semiconductor structure provided by another embodiment of the present invention. Detailed Description of the Embodiments

[0017] As can be seen from the background art, in the prior art, while improving the integration density of semiconductor devices, the capacitance and dimensional accuracy of the capacitors in the semiconductor structure need to be improved.

[0018] To solve the above problems, an embodiment of the present invention provides a semiconductor structure and a manufacturing method thereof. In the semiconductor structure, the channel region of the semiconductor channel is vertically disposed on the surface of the metal bit line, such that the semiconductor structure includes a vertical Gate-All-Around (GAA) transistor, which is beneficial to saving the layout space of the semiconductor channel in the direction parallel to the surface of the metal bit line (usually the horizontal direction), thereby improving the integration density of the semiconductor structure in the horizontal direction. In addition, by changing the structure of the lower electrode layer in the capacitor, specifically, the lower electrode layer is composed of a stacked first lower electrode layer and a second lower electrode layer, which is beneficial to increasing the overall height of the lower electrode layer of the capacitor, so as to increase the aspect ratio of the capacitor, thereby increasing the facing area between the upper electrode layer and the lower electrode layer of the capacitor, and increasing the capacitance of the capacitor. Moreover, the orthographic projection of the bottom surface of the second lower electrode layer on the substrate is located within the orthographic projection of the top surface of the first lower electrode layer on the substrate, such that the second lower electrode layer is aligned with the first lower electrode layer, that is, it is ensured that the bottom surface of the second lower electrode layer is in complete contact with the top surface of the first lower electrode layer, avoiding misalignment between the bottom surface of the second lower electrode layer and the top surface of the first lower electrode layer, thereby improving the dimensional accuracy of the capacitor while increasing the capacitance of the capacitor, improving the formation quality of the capacitor, and ensuring that the capacitor has good electrical properties. Further, the capacitor dielectric layer also covers the top surface of the first lower electrode layer exposed by the second lower electrode layer, avoiding contact between the upper electrode layer and the top surface of the first lower electrode layer exposed by the second lower electrode layer, so as to further ensure that the capacitor has good electrical properties.

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will elaborate on each embodiment of the present invention with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present invention, many technical details are presented for the readers to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0020] An embodiment of the present invention provides a semiconductor structure, and the following will detail the semiconductor structure provided by an embodiment of the present invention with reference to the accompanying drawings. Figure 1 It is a schematic cross-sectional structure diagram corresponding to the semiconductor structure provided by an embodiment of the present invention. Figures 2 to 6 It is five schematic cross-sectional structure diagrams of the structure jointly formed by the first lower electrode layer, the second lower electrode layer, and the capacitor dielectric layer in the semiconductor structure provided by an embodiment of the present invention.

[0021] Reference Figures 1 to 6, the semiconductor structure includes: a substrate 110 and a memory cell 100 located on the substrate 110. The memory cell 100 includes: a first dielectric layer 103 and a metal bit line 101 located within the first dielectric layer 103, and the first dielectric layer 103 exposes the surface of the metal bit line 101; a semiconductor channel 102, the semiconductor channel 102 is located on a partial surface of the metal bit line 101, and the bottom surface of the semiconductor channel 102 facing the metal bit line 101 is electrically connected to the metal bit line 101; a word line 104, the word line 104 is disposed around a partial area of the semiconductor channel 102; a second dielectric layer 105, the second dielectric layer 105 is located between the metal bit line 101 and the word line 104, and is also located on the side of the word line 104 away from the substrate 110; a first lower electrode layer 116 and a second lower electrode layer 126 stacked on the top surface of the semiconductor channel 102 away from the metal bit line 101, the first lower electrode layer 116 is in contact with the top surface of the semiconductor channel 102; an upper electrode layer 146, the upper electrode layer 146 is located on the top surface of the second lower electrode layer 126, and surrounds the first lower electrode layer 116 and the second lower electrode layer 126; a capacitive dielectric layer 136, the capacitive dielectric layer 136 is located between the upper electrode layer 146 and the first lower electrode layer 116, and is also located between the upper electrode layer 146 and the second lower electrode layer 126.

[0022] Specifically, the orthographic projection of the bottom surface of the second lower electrode layer 126 on the substrate 110 is located within the orthographic projection of the top surface of the first lower electrode layer 116 on the substrate 110; the capacitive dielectric layer 136 covers the top surface and the side surface of the second lower electrode layer 126, and also covers the side surface of the first lower electrode layer 116 and the top surface of the first lower electrode layer 116 exposed by the second lower electrode layer 126.

[0023] In the direction from the substrate 110 pointing to the metal bit line 101, the semiconductor channel 102 includes a first doped region I, a channel region II, and a second doped region III arranged in sequence. The first doped region I is electrically connected to the metal bit line 101; the word line 104 is disposed around the channel region II; the first lower electrode layer 116 is in contact with the side of the second doped region III away from the channel region II.

[0024] Since the semiconductor structure includes vertical Gate-All-Around (GAA) transistors and the metal bit line 101 is located between the substrate 110 and the Gate-All-Around transistors, a 3D (3 Dimensions) stacked memory device can be formed, which is beneficial to improving the integration density of the semiconductor structure. In addition, the capacitor in the semiconductor structure is composed of a first lower electrode layer 116, a second lower electrode layer 126, a capacitor dielectric layer 136, and an upper electrode layer 146. Among them, the lower electrode layer of the capacitor is formed by stacking the first lower electrode layer 116 and the second lower electrode layer 126. On the one hand, in the direction perpendicular to the surface of the substrate 110, when preparing a lower electrode layer with a relatively high height, the first lower electrode layer 116 and the second lower electrode layer 126 with relatively low heights can be formed step by step. Since the heights of the first lower electrode layer 116 and the second lower electrode layer 126 are relatively low, it is beneficial to avoid the inclination or collapse of the first lower electrode layer 116 and the second lower electrode layer 126, improve the overall stability of the lower electrode layer, and form a capacitor with a large aspect ratio and a large capacitance. On the other hand, the positive projection of the bottom surface of the second lower electrode layer 126 on the substrate 110 is located within the positive projection of the top surface of the first lower electrode layer 116 on the substrate, so that the second lower electrode layer 126 is aligned with the first lower electrode layer 116, that is, the misalignment between the bottom surface of the second lower electrode layer 126 and the top surface of the first lower electrode layer 116 is avoided. Thus, while increasing the capacitance, the dimensional accuracy of the capacitor is improved to improve the formation quality of the capacitor and ensure that the capacitor has good electrical properties.

[0025] The following will be combined with Figure 1 to describe the semiconductor structure in more detail.

[0026] In this embodiment, the substrate 110 can be a logic circuit structure layer and has several logic circuits.

[0027] The first dielectric layer 103 can include: an interlayer dielectric layer 120, the interlayer dielectric layer 120 is located on the surface of the substrate 110, and the metal bit line 101 is located on a part of the surface of the interlayer dielectric layer 120 away from the substrate 110; an isolation layer 130, the isolation layer 130 is located on the surface of the interlayer dielectric layer 120 exposed by the metal bit line 101 and covers the sidewall of the metal bit line 101.

[0028] Specifically, the logic circuit structure layer can be a stacked structure. On a part of the surface of the interlayer dielectric layer 120 away from the logic circuit structure layer, there can be multiple metal bit lines 101 arranged at intervals, and each metal bit line 101 can be in electrical contact with at least one first doped region I. Figure 1Taking the example that each metal bit line 101 is in contact with two first doped regions I, the number of first doped regions I in electrical connection with each metal bit line 101 can be reasonably set according to actual electrical requirements. The top surface of the metal bit line 101 can be flush with the top surface of the isolation layer 130, which is beneficial to providing good support for other structures located on the top surfaces of the metal bit line 101 and the isolation layer 130.

[0029] The interlayer dielectric layer 120 is used to insulate the logic circuit structure layer and the metal bit line 101, and the interlayer dielectric layer 120 is beneficial to preventing leakage between adjacent metal bit lines 101. Among them, the material of the interlayer dielectric layer 120 includes at least one of silicon oxide, silicon nitride, silicon carbonitride or silicon carbonitrogen oxide.

[0030] The isolation layer 130 is located between adjacent metal bit lines 101 and is used to insulate adjacent metal bit lines 101. Among them, the material of the isolation layer 130 includes at least one of silicon oxide, silicon nitride, silicon carbonitride or silicon carbonitrogen oxide.

[0031] In this embodiment, the interlayer dielectric layer 120 and the isolation layer 130 are an integral structure, thereby improving the interface state defects between the interlayer dielectric layer 120 and the isolation layer 130 and improving the performance of the semiconductor structure. Moreover, the material of the interlayer dielectric layer 120 is the same as that of the isolation layer 130. In this way, it is beneficial to reduce the manufacturing process steps of the semiconductor structure, reduce the manufacturing cost and complexity of the semiconductor structure. In other embodiments, the interlayer dielectric layer and the isolation layer can be a layered structure, and the materials of the interlayer dielectric layer and the isolation layer can be different.

[0032] The material of the metal bit line 101 is metal. The advantages of such a setting include: on the one hand, the resistivity of the metal bit line 101 made of metal material is generally small, which is beneficial to reducing the resistance of the metal bit line 101, improving the transmission rate of electrical signals in the metal bit line 101, reducing the parasitic capacitance of the metal bit line 101, and reducing the thermal loss to reduce the power consumption; on the other hand, the semiconductor structure can also include a circuit structure, and the circuit structure has a metal conductive layer for realizing electrical connection, such as the M0 layer, M1 layer, M2 layer, etc. commonly referred to by those skilled in the art. The process steps of the metal conductive layer can be utilized to fabricate the metal bit line 101 while forming the metal conductive layer. In this way, the manufacturing process steps of the semiconductor structure can be saved, and the cost of the semiconductor structure can be reduced.

[0033] The material of the metal bit line 101 can be a single metal, a metal compound or an alloy. Among them, the single metal can be copper, aluminum, tungsten, gold or silver, etc.; the metal compound can be tantalum nitride or titanium nitride; the alloy can be an alloy material composed of at least two of copper, aluminum, tungsten, gold or silver. In addition, the material of the metal bit line 101 can also be at least one of nickel, cobalt or platinum.

[0034] In some embodiments, the material of the metal bit line 101 is copper.

[0035] The semiconductor structure may include a plurality of metal bit lines 101 arranged at intervals, and each metal bit line 101 extends in a first direction; each metal bit line 101 may be electrically connected to at least two semiconductor channels 102.

[0036] The material of the semiconductor channel 102 includes at least one of IGZO (Indium Gallium Zinc Oxide), IWO (Indium Tungsten Oxide), or ITO (Indium Tin Oxide). When the semiconductor channel 102 is composed of the above materials, it is beneficial to improve the carrier mobility of the semiconductor channel 102, thereby facilitating the more efficient transmission of electrical signals by the semiconductor channel 102.

[0037] In one example, the material of the semiconductor channel 102 is IGZO. The carrier mobility of IGZO is 20 to 50 times that of polysilicon, which is beneficial to improving the carrier mobility of the channel region II in the semiconductor channel 102, thereby facilitating the reduction of the leakage current when the semiconductor structure operates, reducing the power consumption of the semiconductor structure, and improving the working efficiency of the semiconductor structure. In addition, the retention time of the memory cell configured with the fully surrounding gate transistor composed of the IGZO semiconductor channel 102 can exceed 400 s, which is beneficial to reducing the refresh rate and power consumption of the memory.

[0038] In this embodiment, the semiconductor channel 102 is a cylindrical structure, and the side surface of the semiconductor channel 102 is a smoothly transitioning surface, which is beneficial to avoiding the phenomena of tip discharge or leakage in the semiconductor channel 102 and further improving the electrical performance of the semiconductor structure. It should be noted that in other embodiments, the semiconductor channel may also be an elliptical cylindrical structure, a square cylindrical structure, or other irregular structures. It can be understood that when the semiconductor channel structure is a square cylindrical structure, the corner formed by the adjacent side surfaces of the side wall of the square cylindrical structure can be a rounded corner, which can also avoid the tip discharge problem. The square cylindrical structure can be a cube cylindrical structure or a cuboid cylindrical structure.

[0039] The first doped region I forms one of the source or drain of the transistor device, and the second doped region III forms the other of the source or drain of the transistor device. The semiconductor elements in the first doped region I, the channel region II, and the second doped region III are the same, that is, the first doped region I, the channel region II, and the second doped region III are an integral structure, which is beneficial to improving the interface state defects between the first doped region I and the channel region II, and improving the interface state defects between the channel region II and the second doped region III, so as to improve the performance of the semiconductor structure. It can be understood that in other embodiments, the semiconductor channel can also be a three-layer structure, and each layer structure serves as the first doped region, the channel region, and the third doped region respectively.

[0040] Among them, the first doped region I may include: a first metal semiconductor layer 112, the first metal semiconductor layer 112 is in contact with the metal bit line 101, and the resistivity of the first metal semiconductor layer 112 is less than the resistivity of the first doped region I outside the first metal semiconductor layer 112. In this way, it is beneficial to reduce the resistivity of the first doped region I, and the first metal semiconductor layer 112 and the first doped region I outside the first metal semiconductor layer 112 form an ohmic contact, avoiding the Schottky barrier contact formed by the direct contact between the metal bit line 101 and the semiconductor material. The ohmic contact is beneficial to reducing the contact resistance between the first doped region I and the metal bit line 101, thereby reducing the energy consumption during the operation of the semiconductor structure, and improving the RC delay effect to improve the electrical performance of the semiconductor structure. It can be understood that in other embodiments, the semiconductor material of the first doped region can also be directly in contact with the metal bit line, that is, the first doped region does not include the first metal semiconductor layer.

[0041] Specifically, the metal element in the first metal semiconductor layer 112 includes at least one of cobalt, nickel, or platinum. Taking the material of the semiconductor channel 102 as IGZO as an example, correspondingly, the material of the first metal semiconductor layer 112 can be nickel-containing IGZO, cobalt-containing IGZO, cobalt-nickel-containing IGZO, or platinum-containing IGZO, etc. In addition, the first metal semiconductor layer 112 can also be doped with nitrogen element.

[0042] The semiconductor element in the first metal semiconductor layer 112 is the same as the semiconductor element in the first doping region I outside the first metal semiconductor layer 112. That is, the first doping region I is an integral structure as a whole, and then the first metal semiconductor layer 112 is a part of the first doping region I, which is beneficial to improving the interface state defects between the first metal semiconductor layer 112 and the first doping region I outside the first metal semiconductor layer 112, and improving the performance of the semiconductor structure. It should be noted that in other embodiments, the semiconductor element in the first metal semiconductor layer may also be different from the semiconductor element in the first doping region outside the first metal semiconductor layer. For example, the semiconductor element in the first metal semiconductor layer may be silicon or germanium. Correspondingly, the first doping region is a double-layer structure including the first metal semiconductor layer.

[0043] In some embodiments, the semiconductor channel 102 is in contact with the metal bit line 101, that is, the first doping region I is located on the surface of the metal bit line 101. Further, the semiconductor structure may further include: a metal layer 108, the metal layer 108 is located on the surface of the metal bit line 101 not covered by the semiconductor channel 102, and the metal layer 108 is composed of the metal element in the first metal semiconductor layer 112. It can be understood that the metal layer 108 is formed simultaneously in the process of forming the first metal semiconductor layer 112, and the material of the metal layer 108 may be at least one of cobalt, nickel or platinum.

[0044] In addition, in some other embodiments, the material of the metal bit line 101 is at least one of nickel, cobalt or platinum. Then, correspondingly, in the manufacturing process of the semiconductor structure, a part of the metal bit line 101 in contact with the first doping region I reacts with the first doping region I to form the first metal semiconductor layer 112. In this way, the metal bit line 101 and the first metal semiconductor layer 112 are an integral structure, which is beneficial to further reducing the contact resistance between the metal bit line 101 and the first metal semiconductor layer 112. That is, the metal bit line 101 can provide the metal element for forming the first metal semiconductor layer 112.

[0045] The second doping region III may include: a second metal semiconductor layer 122, the second metal semiconductor layer 122 is in contact with the lower electrode layer 116, and the resistivity of the material of the second metal semiconductor layer 122 is less than the resistivity of the second doping region III outside the second metal semiconductor layer 122. In this way, it is beneficial to reduce the resistivity of the second doping region III; and an ohmic contact is formed between the second metal semiconductor layer 122 and the capacitor structure, which is beneficial to reducing the contact resistance between the second doping region III and the capacitor structure, thereby reducing the energy consumption when the semiconductor structure works and improving the electrical performance of the semiconductor structure.

[0046] The metal element in the second metal semiconductor layer 122 includes at least one of cobalt, nickel, or platinum. In this embodiment, the metal element in the first metal semiconductor layer 112 may be the same as the metal element in the second metal semiconductor layer 122. In other embodiments, the metal element in the first metal semiconductor layer may also be different from the metal element in the second metal semiconductor layer.

[0047] In addition, the semiconductor element in the second metal semiconductor layer 122 is the same as the semiconductor element in the second doping region III outside the second metal semiconductor layer 122. That is, the second doping region III is an integral structure as a whole, and the second metal semiconductor layer 122 is a part of the second doping region III, which is beneficial to improving the interface state defects between the second metal semiconductor layer 122 and the second doping region III outside the second metal semiconductor layer 122 and improving the performance of the semiconductor structure. It should be noted that in other embodiments, the semiconductor element in the second metal semiconductor layer may also be different from the semiconductor element in the second doping region outside the second metal semiconductor layer. For example, the semiconductor element in the second metal semiconductor layer may be silicon or germanium. Correspondingly, the second doping region is a double-layer structure including the second metal semiconductor layer.

[0048] Taking the semiconductor element as silicon as an example, the second metal semiconductor layer 122 includes at least one of cobalt silicide, nickel silicide, or platinum silicide. In addition, the second metal semiconductor layer 122 may also be doped with a nitrogen element.

[0049] In the extending direction of the metal bit line 101, when the width of the semiconductor channel 102 is within the nanoscale range, when the semiconductor channel 102 is used to form the channel of a junctionless transistor, it is beneficial to form a nanoscale junctionless transistor channel, that is, the types of doping ions in the first doping region I, the channel region II, and the second doping region III are the same. For example, the doping ions are all N-type ions or all P-type ions. Further, the doping ions in the first doping region I, the channel region II, and the second doping region III can be the same. Herein, "junctionless" means without a PN junction, that is, there is no PN junction in the transistor formed by the semiconductor channel 102. The advantages include: on the one hand, there is no need for additional doping of the first doping region I and the second doping region III, thus avoiding the problem that the doping process of the first doping region I and the second doping region III is difficult to control. Especially as the transistor size is further reduced, if the first doping region I and the second doping region III are additionally doped, the doping concentration is more difficult to control; on the other hand, since the device is a junctionless transistor, it is beneficial to avoid the phenomenon of making a super-steep PN junction by using a super-steep source-drain concentration gradient doping process within the nanoscale range. Therefore, problems such as threshold voltage drift and increased leakage current caused by doping abruptness can be avoided, and it is also beneficial to suppress the short-channel effect and still work within the scale of a few nanometers. Thus, it helps to further improve the integration density and electrical performance of the semiconductor structure. It can be understood that the additional doping here refers to the doping carried out to make the types of doping ions in the first doping region I and the second doping region III different from those in the channel region.

[0050] Further, the concentrations of the doping ions in the first doping region I and the second doping region III can both be greater than the doping concentration of the doping ions in the channel region II. The doping ions are N-type ions or P-type ions. Specifically, the N-type ions are at least one of arsenic ions, phosphorus ions, or antimony ions; the P-type ions are at least one of boron ions, indium ions, or gallium ions.

[0051] The word line 104 includes a gate dielectric layer 114, and the gate dielectric layer 114 can surround the entire sidewall surface of the semiconductor channel 102. Thus, it is beneficial to avoid leakage of the semiconductor channel 102 and improve the electrical performance of the GAA transistor.

[0052] In other embodiments, the gate dielectric layer may only cover the sidewall surfaces of the semiconductor channels in the channel region, or the gate dielectric layer covers the sidewall surfaces of the semiconductor channels in the channel region and the first doped region, or the gate dielectric layer covers the sidewall surfaces of the semiconductor channels in the channel region and the second doped region. When the gate dielectric layer is disposed around the second doped region, that is, on the sidewall surfaces of the semiconductor channels in the second doped region, the gate dielectric layer can protect the surface of the second doped region and avoid process damage to the surface of the second doped region during the manufacturing process, thereby facilitating further improvement of the electrical performance of the semiconductor structure.

[0053] The word line 104 further includes a gate conductive layer 124. The gate conductive layer 124 is disposed around a partial region of the semiconductor channel 102, and the gate dielectric layer 14 is located between the semiconductor channel 102 and the gate conductive layer 124.

[0054] Specifically, the gate conductive layer 124 is disposed around the channel region II and on the sidewall surfaces of the corresponding gate dielectric layer 114 in the channel region II.

[0055] Wherein, the material of the gate dielectric layer 114 includes at least one of silicon oxide, silicon nitride or silicon oxynitride, and the material of the gate conductive layer 124 includes at least one of polysilicon, titanium nitride, tantalum nitride, copper, tungsten or aluminum.

[0056] In this embodiment, the semiconductor structure may include a plurality of word lines 104 arranged at intervals, and each word line 104 extends in a second direction different from the first direction. For example, the first direction may be perpendicular to the second direction. In addition, for each word line 104, each word line 104 may be disposed around the channel region II of at least one semiconductor channel 102. Figure 1 Taking the example that each word line 104 surrounds 2 semiconductor channels 102, the number of semiconductor channels 102 surrounded by each word line 104 can be reasonably set according to actual electrical requirements.

[0057] The second dielectric layer 105 is used to isolate the metal layer 108 and the word line 104 to isolate the metal bit line 101 from the word line 104, and is also used to isolate adjacent word lines 104 and adjacent metal layers 108. That is to say, the second dielectric layer 105 is located between the metal layer 108 and the word line 104, and is also located in the intervals between adjacent word lines 104 and in the intervals between adjacent metal layers 108.

[0058] The second dielectric layer 105 may include: a third dielectric layer 115, which is located between the metal layer 108 and the word line 104 and in the space between adjacent metal layers 108, so as to insulate between the metal layer 108 and the word line 104, prevent electrical interference between the metal layer 108 and the word line 104, and further prevent electrical interference between the metal bit line 101 and the word line 104; a fourth dielectric layer 125, which is located between adjacent word lines 104 and in contact with the third dielectric layer 115, for insulating between adjacent word lines 104 and preventing electrical interference between adjacent word lines 104; the fourth dielectric layer 125 is also located on the surface of the word line 104 away from the substrate 110, for supporting other conductive structures located on the surface of the fourth dielectric layer 125 away from the substrate 110 and achieving insulation between the word line 104 and other conductive structures.

[0059] The top surface of the fourth dielectric layer 125 may be flush with the top surface of the second doped region III, which is beneficial to providing good support for other structures located on the top surfaces of the fourth dielectric layer 125 and the second doped region III.

[0060] In this embodiment, the materials of the third dielectric layer 115 and the fourth dielectric layer 125 are the same, and may both be at least one of silicon oxide, silicon nitride, silicon carbonitride, or silicon oxynitride. In other embodiments, the materials of the third dielectric layer and the fourth dielectric layer may also be different.

[0061] It can be understood that in other embodiments, the second dielectric layer may also be other stacked film layer structures, and the specific structure of the stacked film layer structure is related to the manufacturing process steps, as long as the second dielectric layer can achieve the isolation purpose.

[0062] The capacitor includes: a first lower electrode layer 116, a second lower electrode layer 126, a capacitor dielectric layer 136, and an upper electrode layer 146. The following will be combined with Figures 1 to 6 to introduce the capacitor in detail.

[0063] In this embodiment, the first lower electrode layer 116 and the second lower electrode layer 126 form the lower electrode layer of the capacitor. Each word line 104 extends in the second direction. Figure 1 Taking as an example that each word line 104 surrounds 2 semiconductor channels 102, and the first lower electrode layer 116 and the second lower electrode layer 126 also extend in the second direction. Specifically, each lower electrode layer corresponds to a word line 104, that is, each lower electrode layer is in contact with the side of each second doped region III of the semiconductor channels 102 surrounded by the word line 104 corresponding to this lower electrode layer and away from the channel region II. Figure 1 Taking as an example that each lower electrode layer is in contact with the top surfaces of the second doped regions III of 2 semiconductor channels 102.

[0064] In some examples, in the direction perpendicular to the surface of the substrate 110, the thickness of the first lower electrode layer 116 can be greater than the thickness of the second lower electrode layer 126; in other examples, in the direction perpendicular to the surface of the substrate 110, the thickness of the first lower electrode layer 116 can also be less than or equal to the thickness of the second lower electrode layer 126. In addition, the material of the first lower electrode layer 116 can be the same as the material of the second lower electrode layer 126. And since the first lower electrode layer 116 and the second lower electrode layer 126 are fabricated step by step, the materials of the first lower electrode layer 116 and the second lower electrode layer 126 can also be different.

[0065] In addition, the upper electrode layer 146 also extends along the second direction. The upper electrode layer 146 corresponds to the lower electrode layer one by one, and the orthographic projection of the upper electrode layer 146 on the substrate 110 covers the orthographic projection of the lower electrode layer on the substrate 110, and the orthographic projection of the lower electrode layer on the substrate 110 covers the orthographic projection of the word line 104 on the substrate 110.

[0066] In other embodiments, each lower electrode layer can also only be in contact with one side of the second doped region away from the channel region. The upper electrode layer can correspond to the lower electrode layer one by one or one upper electrode layer corresponds to multiple lower electrode layers; or one lower electrode layer can be in contact with one side of multiple second doped regions away from the channel region, and the upper electrode layer can only correspond to one semiconductor channel, that is, one lower electrode layer corresponds to multiple upper electrode layers, so that the upper electrode layers in adjacent capacitors can be connected to different potentials or the lower electrode layers can be connected to different potentials, which is beneficial to realizing diversified control of adjacent capacitors.

[0067] The lower electrode layer is composed of a first lower electrode layer 116 and a second lower electrode layer 126 stacked, which is beneficial to increasing the overall height of the lower electrode layer to increase the capacitance of the capacitor. At the same time, in the way of forming the first lower electrode layer 116 and the second lower electrode layer 126 with lower heights step by step, the inclination or collapse of the first lower electrode layer 116 and the second lower electrode layer 126 is avoided, and the overall stability of the lower electrode layer is improved. The orthographic projection of the bottom surface of the second lower electrode layer 126 on the substrate 110 is located within the orthographic projection of the top surface of the first lower electrode layer 116 on the substrate 110, ensuring that the bottom surface of the second lower electrode layer 126 is in full contact with the top surface of the first lower electrode layer 116, avoiding misalignment between the bottom surface of the second lower electrode layer 126 and the top surface of the first lower electrode layer 116, and improving the dimensional accuracy of the capacitor.

[0068] In some examples, in the extending direction of the metal bit line 101, the bottom width of the first lower electrode layer 116 is less than the maximum width of the semiconductor channel 102. In other embodiments, the bottom width of the first lower electrode layer can be greater than or equal to the maximum width of the semiconductor channel.

[0069] Reference Figures 1 to 4, the first lower electrode layer 116 includes: a first lower conductive column 113, the first lower conductive column 113 is in contact with the second doped region III; a first lower conductive block 123, one end of the first lower conductive block 123 is in contact with the first lower conductive column 113, and the other end is in contact with the second lower electrode layer 126. The second lower electrode layer 126 includes: a second lower conductive column 133, the second lower conductive column 133 is in contact with the first lower conductive block 123; a second lower conductive block 143, one end of the second lower conductive block 143 is in contact with the second lower conductive column 133, and the other end is in contact with the capacitive dielectric layer 136. In some examples, the first lower conductive column 113 covers the entire top surface of the second doped region III, and in the direction away from the substrate 110, the cross-sectional area of the first lower conductive column 113 gradually increases in the direction parallel to the surface of the substrate 110, and the positive projection of the top surface of the first lower conductive column 113 on the substrate 110 coincides with the positive projection of the bottom surface of the first lower conductive block 123 on the substrate 110. While ensuring the maximum contact area between the second doped region III and the first lower electrode layer 116, it is beneficial to increase the volume of the first lower electrode layer 116 to reduce the resistance of the first lower electrode layer 116 itself, thereby facilitating the reduction of the contact resistance between the second doped region III and the first lower electrode layer 116.

[0070] In the direction away from the substrate 110, the cross-sectional area of the second lower conductive column 133 gradually increases in the direction parallel to the surface of the substrate 110, and the positive projection of the bottom surface of the second lower conductive column 133 on the substrate 110 is located within the positive projection of the bottom surface of the first lower conductive block 123 on the substrate 110. This is beneficial for increasing the volume of the second lower electrode layer 126 while avoiding misalignment between the bottom surface of the second lower electrode layer 126 and the top surface of the first lower electrode layer 116, so as to reduce the resistance of the second lower electrode layer 126 itself, thereby facilitating the reduction of the contact resistance between the second lower electrode layer 126 and the first lower electrode layer 116. In addition, the positive projection of the top surface of the second lower conductive column 133 on the substrate 110 coincides with the positive projection of the bottom surface of the second lower conductive block 143 on the substrate 110.

[0071] In other embodiments, the positive projection of the top surface of the first lower conductive column on the substrate may cover the positive projection of the bottom surface of the first lower conductive block on the substrate, and the positive projection of the top surface of the second lower conductive column on the substrate may cover the positive projection of the bottom surface of the second lower conductive block on the substrate.

[0072] In this embodiment, the first lower conductive column 113 and the first lower conductive block 123 are of an integral structure, and the second lower conductive column 133 and the second lower conductive block 143 are of an integral structure, thereby improving the interfacial state defects between the first lower conductive column 113 and the first lower conductive block 123, and the interfacial state defects between the second lower conductive column 133 and the second lower conductive block 143, so as to improve the performance of the semiconductor structure. Moreover, the materials of the first lower conductive column 113, the first lower conductive block 123, the second lower conductive column 133, and the second lower conductive block 143 can be the same. In this way, it is beneficial to reduce the manufacturing process steps of the semiconductor structure, and lower the manufacturing cost and complexity of the semiconductor structure. Among them, the materials of the first lower conductive column 113, the first lower conductive block 123, the second lower conductive column 133, and the second lower conductive block 143 can all be at least one of platinum nickel, titanium, tantalum, cobalt, polysilicon, copper, tungsten, tantalum nitride, titanium nitride, or ruthenium.

[0073] In other embodiments, the first lower conductive column and the first lower conductive block may not be of an integral structure, and the second lower conductive column and the second lower conductive block may not be of an integral structure, that is, the materials of the first lower conductive column, the first lower conductive block, the second lower conductive column, and the second lower conductive block may also be different.

[0074] In other embodiments, referring to Figure 5 , the cross-sectional shapes of both the first lower electrode layer 116 and the second lower electrode layer 126 can be rectangular; referring to Figure 6 , the cross-sectional shapes of both the first lower electrode layer 116 and the second lower electrode layer 126 can be inverted trapezoidal.

[0075] Referring to Figures 2 to 6 , the capacitive dielectric layer 136 includes: a first capacitive dielectric layer 156 that covers the side surface of the first lower electrode layer 116; a second capacitive dielectric layer 166 that covers the top surface of the first lower electrode layer 116 exposed by the second lower electrode layer 126; and a third capacitive dielectric layer 176 that covers the top surface and the side surface of the second lower electrode layer 126.

[0076] The first capacitive dielectric layer 156, the second capacitive dielectric layer 166, and the third capacitive dielectric layer 176 jointly cover the surfaces of the first lower electrode layer 116 and the second lower electrode layer 126 to isolate the upper electrode layer 146 from the first lower electrode layer 116 and the second lower electrode layer 126. In addition, the second capacitive dielectric layer 166 covers the top surface of the first lower electrode layer 116 exposed by the second lower electrode layer 126 to prevent the upper electrode layer 146 from contacting the first lower electrode layer 116 through the top surface of the first lower electrode layer 116 exposed by the second lower electrode layer 126, so as to further ensure that the capacitor has good electrical performance.

[0077] Further, the capacitive dielectric layer 136 may further include: a fourth capacitive dielectric layer 186, which is connected to the bottom surface of the first capacitive dielectric layer 156 and extends in a direction away from the axis perpendicular to the surface of the substrate 110 of the first lower electrode layer 116; the upper electrode layer 146 (refer to Figure 1 ) is also located on the surface of the fourth capacitive dielectric layer 186. In some examples, along the extending direction of the metal bit line 101, when the bottom surface width of the first lower electrode layer 116 is smaller than the maximum width of the semiconductor channel 102, a part of the top surface of the second doped region III is exposed by the first lower electrode layer 116. The fourth capacitive dielectric layer 186 is connected to the bottom surface of the first capacitive dielectric layer 156 and extends in a direction away from the axis perpendicular to the surface of the substrate 110 of the first lower electrode layer 116. In this way, it is beneficial to isolate the upper electrode layer 146 and the second doped region III through the fourth dielectric layer 186 to ensure good electrical performance of the semiconductor structure.

[0078] In this embodiment, the fourth capacitive dielectric layer 186 and the first capacitive dielectric layer 156 are of an integrally formed structure, which is beneficial to improving the interface state defects between the fourth capacitive dielectric layer 186 and the first capacitive dielectric layer 156, enhancing the overall isolation effect between the fourth capacitive dielectric layer 186 and the first capacitive dielectric layer 156, and the materials of the fourth capacitive dielectric layer 186 and the first capacitive dielectric layer 156 are the same. In this way, it is beneficial to reduce the manufacturing process steps of the semiconductor structure, and lower the manufacturing cost and complexity of the semiconductor structure. In other embodiments, the fourth capacitive dielectric layer and the first capacitive dielectric layer may be a layered structure, and the materials of the fourth capacitive dielectric layer and the first capacitive dielectric layer may be different.

[0079] In some embodiments, refer to Figure 2 , the top surface of the first lower electrode layer 116 exposed by the second lower electrode layer 126 has the first capacitive dielectric layer 156, and the second capacitive dielectric layer 166 is located on the top surface of the first capacitive dielectric layer 156 to cover the top surface of the first lower electrode layer 116 exposed by the second lower electrode layer 126. In addition, the second capacitive dielectric layer 166 also extends in a direction away from the axis perpendicular to the surface of the substrate 110 of the second lower electrode layer 126 to further enhance the isolation effect between the upper electrode layer 146 and the top surface of the first lower electrode layer 116.

[0080] In other embodiments, refer to Figure 3 , the second capacitive dielectric layer 166 is in contact with the top surface of the first lower electrode layer 116 exposed by the second lower electrode layer 126 and extends in a direction away from the axis perpendicular to the surface of the substrate 110 of the second lower electrode layer 126 to isolate the upper electrode layer 146 and the top surface of the first lower electrode layer 116.

[0081] The second capacitor dielectric layer 166 and the third capacitor dielectric layer 176 can be an integrally formed structure, which is beneficial to improving the interface state defects between the second capacitor dielectric layer 166 and the third capacitor dielectric layer 176, enhancing the overall isolation effect of the second capacitor dielectric layer 166 and the third capacitor dielectric layer 176, and the materials of the second capacitor dielectric layer 166 and the third capacitor dielectric layer 176 are the same. Thus, it is beneficial to reduce the manufacturing process steps of the semiconductor structure, and lower the manufacturing cost and complexity of the semiconductor structure. In other embodiments, the second capacitor dielectric layer and the third capacitor dielectric layer can be a layered structure, and the materials of the second capacitor dielectric layer and the third capacitor dielectric layer can be different.

[0082] In still other examples, referring to Figures 4 to 6 , the top surface of the first lower electrode layer 116 exposed by the second lower electrode layer 126 has a first capacitor dielectric layer 156, and the first capacitor dielectric layer 156 and the second capacitor dielectric layer 166 are an integrally formed structure, which is beneficial to improving the interface state defects between the first capacitor dielectric layer 156 and the second capacitor dielectric layer 166, enhancing the overall isolation effect of the first capacitor dielectric layer 156 and the second capacitor dielectric layer 166, and the materials of the first capacitor dielectric layer 156 and the second capacitor dielectric layer 166 are the same. Thus, it is beneficial to reduce the manufacturing process steps of the semiconductor structure, and lower the manufacturing cost and complexity of the semiconductor structure. In other embodiments, the first capacitor dielectric layer and the second capacitor dielectric layer can be a layered structure, and the materials of the first capacitor dielectric layer and the second capacitor dielectric layer can be different.

[0083] It should be noted that Figures 2 to 6 in, the structure in the dashed box a except the first lower electrode layer 116 is the fourth capacitor dielectric layer 186, and the structure in the dashed box b except the second lower electrode layer 126 is the second capacitor dielectric layer 166.

[0084] In this embodiment, the relative dielectric constant of the material of the capacitor dielectric layer 136 is greater than that of the material of the second dielectric layer 105, which is beneficial to further enhancing the isolation effect between the first lower electrode layer 116 and the second lower electrode layer 126 and the upper electrode layer 146, and improving the electrical performance of the capacitor in the semiconductor structure.

[0085] Among them, the materials of the first capacitor dielectric layer 156, the second capacitor dielectric layer 166, the third capacitor dielectric layer 176, and the fourth capacitor dielectric layer 186 all include high dielectric constant materials such as silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide, or barium strontium titanate.

[0086] It should be noted that Figures 2 to 6The second capacitive dielectric layers 166 between adjacent capacitors are spaced apart from each other. For example, in fact, the second capacitive dielectric layers 166 between adjacent capacitors can be in contact and connected to each other. The fourth capacitive dielectric layers 186 between adjacent capacitors are spaced apart from each other. For example, in fact, the fourth capacitive dielectric layers 186 between adjacent capacitors can be in contact and connected to each other.

[0087] Continuing to refer to Figure 1 , the upper electrode layer 146 includes: a first upper electrode layer 196, the first upper electrode layer 196 surrounds the first lower electrode layer 116 and is located on the side surface of the first capacitive dielectric layer 156; a second upper electrode layer 106, the second upper electrode layer 106 surrounds the second lower electrode layer 116, is located on the surface of the third capacitive dielectric layer 176, and the bottom surface of the second upper electrode layer 106 is in contact with the top surface of the first upper electrode layer 196.

[0088] The material of the first upper electrode layer 196 and the material of the second upper electrode layer 106 can both be at least one of platinum nickel, titanium, tantalum, cobalt, polysilicon, copper, tungsten, tantalum nitride, titanium nitride or ruthenium. In other embodiments, the material of the first upper electrode layer and the material of the second upper electrode layer can also be different.

[0089] In this embodiment, the material of the entire lower electrode layer 116 and the material of the entire upper electrode layer 136 can be the same. In other embodiments, the material of the lower electrode layer and the material of the upper electrode layer can also be different.

[0090] In some embodiments, the semiconductor structure may include 2 memory cells 100 stacked on the substrate 110. Figure 1 Taking 2 memory cells 100 stacked on the substrate 110 as an example, the number of memory cells 100 stacked on the substrate 110 can be reasonably set according to actual electrical requirements. Since multiple memory cells 100 can be stacked on the same substrate 110, increasing the size in the thickness direction of the semiconductor structure can increase the array density of the semiconductor structure, improve the storage performance of the semiconductor structure, and reduce the planar size of the semiconductor structure to achieve the purpose of 3D stacking. It can be understood that the array density refers to the density of the memory cells 100 within the semiconductor structure.

[0091] Further, the semiconductor structure further includes: an insulating layer 107, the insulating layer 107 is located on the surface of the second dielectric layer 105, and the capacitor formed by the first lower electrode layer 116, the second lower electrode layer 126, the capacitive dielectric layer 136 and the upper electrode layer 146 is located within the insulating layer 107. The insulating layer 107 is used to support the capacitor to prevent the capacitor from collapsing, and is also used to isolate the upper electrode layers 146 of adjacent capacitors 106.

[0092] In this embodiment, the insulating layer 107 has a stacked film layer structure and includes a first insulating layer 117 and a second insulating layer 127. The first insulating layer 117 is located between adjacent first upper electrode layers 196 and is used to achieve electrical insulation between adjacent first upper electrode layers 196; the second insulating layer 127 is located between adjacent second upper electrode layers 106 and covers the upper surface of the first insulating layer 117, and is used to achieve electrical insulation between adjacent second upper electrode layers 106.

[0093] Wherein, the materials of the first insulating layer 117 and the second insulating layer 127 are the same, and can be at least one of silicon nitride, silicon oxynitride, silicon carbon oxynitride or silicon oxide. In other embodiments, the materials of the first insulating layer and the second insulating layer may also be different.

[0094] In summary, the channel region II of the semiconductor channel 102 is vertically disposed on the metal bit line 101, so that a GAA transistor is formed in the semiconductor structure, and thus a 3D stacked memory device can be formed, which is beneficial to improving the integration density of the semiconductor structure. At the same time, the lower electrode layer of the capacitor in the semiconductor structure is composed of a first lower electrode layer 116 and a second lower electrode layer 126 stacked, which is beneficial to increasing the overall height of the lower electrode layer of the capacitor to increase the capacitance of the capacitor. Moreover, the orthographic projection of the bottom surface of the second lower electrode layer 126 on the substrate 110 is located within the orthographic projection of the top surface of the first lower electrode layer 116 on the substrate 110, so that the second lower electrode layer 126 is aligned with the first lower electrode layer 116, avoiding misalignment between the bottom surface of the second lower electrode layer 126 and the top surface of the first lower electrode layer 116. Therefore, while increasing the capacitance, the dimensional accuracy of the capacitor is improved to improve the formation quality of the capacitor and ensure that the capacitor has good electrical performance.

[0095] In addition, the semiconductor structure provided in this embodiment can be applied to 4F 2The memory, where F is the feature size. The memory can be a RRAM (Static Random Access Memory), MRAM (Magnetoresistive Random Access Memory), or PCRAM (Phase Change Random Access Memory), DRAM (Dynamic Random Access Memory) memory, or SRAM (SRAM, Static Random Access Memory) memory. It can also be applied to in-memory computing (IMC, In Memory Computing), which allows users to store data in the memory and process information at a faster speed. In a specific embodiment, the memory can be a DRAM memory. In the above embodiment, the metal bit line 101 mentioned is the bit line of the DRAM memory, the word line 104 is the word line of the DRAM memory, and the capacitive structure is the storage capacitor of the DRAM memory.

[0096] Correspondingly, another embodiment of the present invention provides a manufacturing method of a semiconductor structure, which can be used to form the above semiconductor structure.

[0097] Figures 7 to 22 FIG. is a schematic structural diagram corresponding to each step in the manufacturing method of the semiconductor structure provided by another embodiment of the present invention. Hereinafter, the manufacturing method of the semiconductor structure provided in this embodiment will be described in detail with reference to the accompanying drawings. For the same or corresponding parts as those in the above embodiment, no detailed description will be given hereinafter.

[0098] Referring to Figures 7 to 22 , a substrate 110 is provided, and a memory cell 100 is formed on the substrate 110. Specifically, forming the memory cell 100 includes the following steps:

[0099] Referring to Figure 7 , the substrate 110 can be a logic circuit structure layer. A first dielectric layer 120 and a metal bit line 101 located within the first dielectric layer 120 are provided, and the first dielectric layer 120 exposes the surface of the metal bit line 101.

[0100] Specifically, a surface interlayer dielectric layer 120 covering the entire surface of the logic circuit structure layer is formed to protect the logic circuit structure layer and prevent electrical interference between the logic circuit structure layer and the metal bit line 101 formed on the interlayer dielectric layer 120 subsequently.

[0101] A plurality of mutually discrete metal bit lines 101 are formed on the surface of the interlayer dielectric layer 120, and the part of the surface of the metal bit line 101 that exposes the interlayer dielectric layer 120; an isolation layer 130 is formed. The isolation layer 130 is located on the surface of the interlayer dielectric layer 120 exposed by the metal bit line 101 and covers the sidewalls of the metal bit line 101.

[0102] For the material of the metal bit line 101, reference can be made to the corresponding description in the foregoing embodiments, and details are not described herein again.

[0103] It can be understood that in other embodiments, an initial dielectric layer may also be provided on the surface of the logic circuit structure layer; the initial dielectric layer is patterned to form a plurality of mutually discrete trenches therein, and the initial dielectric layer located below the trenches serves as an interlayer dielectric layer, and the initial dielectric layer located between adjacent trenches serves as an isolation layer. In this way, the isolation layer and the initial dielectric layer are an integral structure; then, a metal bit line filling the trenches is formed.

[0104] Reference Figure 8 , a first metal layer 118 is formed on the surface of the metal bit line 101.

[0105] The first metal layer 118 is used to react with the region of the semiconductor channel to be formed later that is close to the metal bit line 101, and provides metal elements for the subsequent formation of the first metal-semiconductor layer, so as to reduce the resistivity of the semiconductor channel. Among them, the material of the first metal layer 118 includes at least one of cobalt, nickel or platinum.

[0106] In this embodiment, the first metal layer 118 covers the entire surface of the metal bit line 101, which can avoid etching damage to the metal bit line 101 caused by the process of etching the first metal layer 118. In other embodiments, the first metal layer may also be located only on a part of the surface of the metal bit line, and the position of the first metal layer corresponds to the position of the semiconductor channel to be formed later.

[0107] In other embodiments, a first metal layer may not be formed on the surface of the metal bit line, and a semiconductor channel may be directly formed on a part of the surface of the metal bit line later. In addition, in some embodiments, the material of the metal bit line is at least one of nickel, cobalt or platinum, that is, the metal bit line can provide metal elements for the subsequent formation of the first metal-semiconductor layer, and thus there is no need to form a first metal layer on the surface of the metal bit line.

[0108] Reference Figure 9 and Figure 10 , a semiconductor channel 102 is formed. The semiconductor channel 102 is located on a part of the surface of the metal bit line 101, and the bottom surface of the semiconductor channel 102 facing the metal bit line 101 is electrically connected to the metal bit line 101. In this embodiment, the semiconductor channel 102 is in contact with the first metal layer 118; in other embodiments, the semiconductor channel may be directly in contact with the metal bit line.

[0109] Specifically, the process steps for forming the semiconductor channel 102 include the following steps:

[0110] Reference Figure 9, an initial channel layer 132 is formed, and the initial channel layer 132 is located on the metal bit line 101 and on the substrate 110.

[0111] In some embodiments, there is an isolation layer 130 between adjacent metal bit lines 101, and the initial channel layer 132 covers the surface of the isolation layer 130.

[0112] In this embodiment, a first metal layer 118 is formed on the surface of the metal bit line 101, and the initial channel layer 132 covers the surface of the first metal layer 118. In other embodiments, the initial channel layer may directly cover the surface of the metal bit line.

[0113] Specifically, the method for forming the initial channel layer 132 includes chemical vapor deposition, physical vapor deposition, atomic layer deposition, or metal organic chemical vapor deposition. Among them, the material of the initial channel layer 132 is IGZO, IWO, or ITO.

[0114] Continue to refer to Figure 9 , and a patterned mask layer 109 is formed on the surface of the initial channel layer 132.

[0115] The mask layer 109 is used to define the position and size of the subsequently formed semiconductor channel 102. The material of the mask layer 109 can be silicon nitride, silicon carbonitride, or silicon carbonitride oxide. In other embodiments, the material of the mask layer can also be photoresist.

[0116] Refer to Figure 10 , and using the mask layer 109 as a mask, the initial channel layer 132 (refer to Figure 8 ) is patterned to form the semiconductor channel 102.

[0117] In the direction from the substrate 110 to the metal bit line 101, the semiconductor channel 102 includes a first doped region I, a channel region II, and a second doped region III arranged in sequence.

[0118] Among them, the first doped region I, the channel region II, and the second doped region III in the semiconductor channel 102 are doped with the same type of doping ions, so the semiconductor channel 102 can be used to form the channel of a junctionless transistor, avoiding problems such as threshold voltage drift and increased leakage current caused by doping abruptness, and also being beneficial to suppressing the short channel effect.

[0119] It can be understood that before patterning, the initial channel layer 132 can be pre-doped, and the doping treatment can dope N-type ions or P-type ions; it can also be doped after patterning the initial channel layer 132 to form a semiconductor channel 102 with a suitable ion distribution.

[0120] In this embodiment, the semiconductor channel 102 can be subjected to corner-rounding treatment through thermal oxidation, etching, and / or hydrogen annealing treatment to form a semiconductor channel 102 with a cylindrical structure, which is beneficial to avoiding the phenomena of tip discharge or leakage in the semiconductor channel 102 when the semiconductor structure is working.

[0121] Referring to Figure 11 , a gate dielectric layer 114 is formed on the entire sidewall of the semiconductor channel 102. The gate dielectric layer 114 exposes the surface of the first metal layer 118 except directly below the semiconductor channel 102. The gate dielectric layer 114 is used to protect the semiconductor channel 102 during subsequent annealing treatment and prevent the material of the semiconductor channel 102 from reacting with the metal material in the subsequent process.

[0122] In this embodiment, the gate dielectric layer 114 is also located at the end face of the second doped region III away from the substrate 110. In the subsequent step of forming the fourth dielectric layer, the gate dielectric layer 114 located at the end face of the second doped region III away from the substrate 110 is removed together, which facilitates the formation of a metal layer on the end face of the second doped region III away from the substrate 110. In other embodiments, the gate dielectric layer covering the end face of the second doped region can be removed through an etching process.

[0123] In other embodiments, the gate dielectric layer can be formed only on the sidewall surface of the semiconductor channel in the channel region, or on the sidewall surfaces of the semiconductor channels in the channel region and the first doped region, or on the sidewall surfaces of the semiconductor channels in the channel region and the second doped region.

[0124] Continuing to refer to Figure 11 , a third dielectric layer 115 is formed. The third dielectric layer 115 is located on the surface of the first metal layer 118 away from the substrate 110 and in the space between adjacent first metal layers 118.

[0125] Specifically, the third dielectric layer 115 is located on the surface of the isolation layer 130 and on the sidewall surface of the gate dielectric layer 114 corresponding to the first doped region I (refer to Figure 9 ), and is used to isolate the first metal layer 118 from the word line formed subsequently. The third dielectric layer 115 is a whole film layer structure and is used to prevent electrical interference between the first metal layer 118 and the metal bit line 101 and the word line formed subsequently.

[0126] The step of forming the third dielectric layer 115 includes: forming an initial first dielectric layer on the surface of the metal bit line 101 away from the substrate 110; performing a planarization treatment and a back etching on the initial first dielectric layer to a preset thickness to form the third dielectric layer 115.

[0127] Referring to Figure 12 , in the channel region II (refer to Figure 10)An initial gate conductive layer 134 is formed on the sidewall surface of the corresponding gate dielectric layer 114, and the initial gate conductive layer 134 surrounds the channel region II. The initial gate conductive layer 134 is a whole-film layer structure.

[0128] Specifically, the method of forming the initial gate conductive layer 134 includes chemical vapor deposition, physical vapor deposition, atomic layer deposition, or metal organic chemical vapor deposition. In addition, through planarization and etching of the initial gate conductive layer 134, the initial gate conductive layer 134 is located on the sidewall surface of the gate dielectric layer 114 corresponding to the channel region II.

[0129] Reference Figure 13 , pattern the initial gate conductive layer 134 (reference Figure 12 ), to form spaced-apart gate conductive layers 124, such that the gate conductive layers 124 of different semiconductor channels 102 located on the same metal bit line 101 can be connected to different potentials, thereby facilitating the realization of diversified control of the semiconductor channels. Among them, the method of patterning includes photolithography.

[0130] For each gate dielectric layer 114, each gate dielectric layer 114 can be disposed around the channel region II of at least one semiconductor channel 102. Figure 13 In

[0131] as an example, each gate dielectric layer 114 surrounds 2 semiconductor channels 102. The number of semiconductor channels 102 surrounded by each gate dielectric layer 114 can be reasonably set according to actual electrical requirements.

[0132] Reference Figure 14 , form a fourth dielectric layer 125. The fourth dielectric layer 125 is located in the space between adjacent gate conductive layers 124, for preventing electrical interference between adjacent gate conductive layers 124, and the fourth dielectric layer 125 is also located on the surface of the gate conductive layer 124 away from the substrate 110, for supporting other conductive structures formed on the surface of the fourth dielectric layer 125 away from the substrate 110, and for realizing insulation between the gate conductive layer 124 and other conductive structures.

[0133] In addition, after forming the fourth dielectric layer 125, planarize the fourth dielectric layer 125, and remove the gate dielectric layer 114 on the end face of the mask layer 109 away from the substrate 110, such that the fourth dielectric layer 125 exposes the mask layer 109 on the end face of the second doped region III away from the substrate 110.

[0134] In this embodiment, the third dielectric layer 115 and the fourth dielectric layer 125 together form the second dielectric layer 105. The second dielectric layer 105 is located between the metal bit line 101 and the word line 104, and is also located on the side of the word line 104 away from the substrate 110. Moreover, the third dielectric layer 115 and the fourth dielectric layer 125 are made of the same material. In this way, it is beneficial to reduce the types of materials required for the manufacturing process of the semiconductor structure, and reduce the manufacturing cost and complexity of the semiconductor structure. In addition, the top surface of the mask layer 109 is also exposed by the second dielectric layer 105.

[0135] Reference Figures 14 to 15 , remove the mask layer 109 to expose the top surface of the second doped region III (Reference Figure 10 ), and form a second metal layer on the exposed top surface of the second doped region III.

[0136] The second metal layer is used to react with the second doped region III to provide metal elements for the subsequent formation of the second metal semiconductor layer 122, so as to reduce the resistivity of the semiconductor channel 102. Among them, the material of the second metal layer includes at least one of cobalt, nickel, or platinum.

[0137] The manufacturing method may further include: performing a first annealing process, in which the first metal layer 118 reacts with the first doped region I to convert a partial thickness of the first doped region I facing the metal bit line 101 into the first metal semiconductor layer 112, and the resistivity of the material of the first metal semiconductor layer 112 is less than the resistivity of the material of the first doped region I outside the first metal semiconductor layer 112.

[0138] Among them, the first metal layer 118 that reacts with the first doped region I becomes a part of the first doped region I, and the first metal layer 118 that does not react with the first doped region I serves as the metal layer 108. It can be understood that a partial thickness of the first metal layer 118 may remain between the metal bit line 101 and the first metal semiconductor layer 112, and this remaining first metal layer 118 serves as the metal layer 108, that is, the metal layer 108 can be located on the surface of the metal bit line 101 outside the first metal semiconductor layer 112, and can also be located between the first metal semiconductor layer 112 and the metal bit line 101.

[0139] In this embodiment, while performing the first annealing process, a second annealing process is performed, in which the second metal layer reacts with the second doped region III to convert an exposed partial thickness of the second doped region III into the second metal semiconductor layer 122, and the resistivity of the material of the second metal semiconductor layer 122 is less than the resistivity of the second doped region III outside the second metal semiconductor layer 122.

[0140] Specifically, rapid thermal annealing is used for the annealing treatment. The process parameters of the rapid thermal annealing include: annealing the semiconductor structure in an N2 atmosphere, with the annealing temperature ranging from 600 °C to 850 °C and the annealing duration ranging from 10 seconds to 60 seconds. Since the annealing temperature is moderate, it is beneficial for the first metal layer 118 to fully react with the first doped region I and for the second metal layer to fully react with the second doped region III, so as to form the first metal-semiconductor layer 112 and the second metal-semiconductor layer 122 with relatively low resistivity. In addition, due to the moderate annealing temperature, it is beneficial to prevent the metal elements in the first metal layer 118 and the second metal layer from diffusing into the channel region II. Moreover, annealing in an N2 atmosphere is beneficial to prevent the first metal layer 118, the second metal layer, and the semiconductor channel 102 from being oxidized.

[0141] In this embodiment, the first annealing treatment and the second annealing treatment are carried out simultaneously, which is beneficial to simplifying the manufacturing process steps of the semiconductor structure. In other embodiments, after forming the semiconductor channel on the first metal layer, the first annealing treatment can be carried out; after forming the second metal layer on the second doped region, the second annealing treatment is carried out.

[0142] In addition, in other embodiments, before forming the semiconductor channel, a first semiconductor layer can also be formed on the surface of the first metal layer. The material of the first semiconductor layer is silicon or germanium, and during the first annealing treatment, the first semiconductor layer reacts with the first metal layer to form the first metal-semiconductor layer; before forming the second metal layer, a second semiconductor layer is formed on the top surface of the second doped region. The material of the second semiconductor layer is silicon or germanium, and during the second annealing treatment, the second semiconductor layer reacts with the second metal layer to form the second metal-semiconductor layer.

[0143] Reference Figures 16 to 22 , a first lower electrode layer 116 is formed, and the first lower electrode layer 116 is in contact with the top surface of the semiconductor channel 102; a second lower electrode layer 126 is formed, and the second lower electrode layer 126 is located on the top surface of the first lower electrode layer 116; an upper electrode layer 146 is formed, and the upper electrode layer 146 is located on the top surface of the second lower electrode layer 126 and surrounds the first lower electrode layer 116 and the second lower electrode layer 126; a capacitive dielectric layer 136 is formed, and the capacitive dielectric layer 136 is located between the upper electrode layer 146 and the first lower electrode layer 116 and is also located between the upper electrode layer 146 and the second lower electrode layer 126;.

[0144] Specifically, the orthographic projection of the bottom surface of the second lower electrode layer 126 on the substrate 110 is located within the orthographic projection of the top surface of the first lower electrode layer 126 on the substrate 110; the capacitive dielectric layer 136 covers the top surface and the side surface of the second lower electrode layer 126, and also covers the side surface of the first lower electrode layer 116 and the exposed top surface of the first lower electrode layer 116 of the second lower electrode layer 126.

[0145] Specifically, forming the first lower electrode layer 116, the second lower electrode layer 126, the capacitive dielectric layer 136, and the upper electrode layer 146 includes the following steps:

[0146] Reference Figure 16 , forming the first lower electrode layer 116, the top surface of the first lower electrode layer 116 includes a central region c and a peripheral region d surrounding the central region c.

[0147] Specifically, a sacrificial layer 137 is formed on a side of the second doped region III away from the channel region II, and a first through hole e penetrating the sacrificial layer 137 and exposing the second doped region III is formed in the sacrificial layer 137; the first lower electrode layer 116 filling the first through hole e is formed.

[0148] The first through hole e includes a first trench and a second trench that are connected and communicated, and the first trench exposes the surface of the second doped region III.

[0149] Specifically, the steps of forming the first trench and the second trench may include: forming an initial sacrificial layer on the surface of the second dielectric layer 105; forming a patterned mask layer on the surface of the initial sacrificial layer; using the patterned mask layer as a mask to etch a part of the thickness of the initial sacrificial layer to form the second trench; in the region corresponding to the second trench, etching the part of the initial sacrificial layer exposed by the second trench until the surface of the second doped region III is exposed, to form a first trench with a gradually increasing cross-sectional area in a direction parallel to the surface of the 110 substrate.

[0150] In other embodiments, the cross-sectional shape of the first through hole e may also be rectangular or trapezoidal in reverse.

[0151] In this embodiment, each word line 104 extends along the second direction, each word line 104 surrounds 2 semiconductor channels 102, and the first trench and the second trench also extend along the second direction. Specifically, the first through hole e formed by the first trench and the second trench corresponds to the word line 104, that is, each first through hole e exposes one side of each second doped region III away from the channel region II surrounded by the word line 104 corresponding to the first through hole e. Figure 16 Taking the top surface of the second doped region III of 2 semiconductor channels 102 exposed by each first through hole e as an example.

[0152] In other embodiments, each first through hole may also only expose one side of a second doped region away from the channel region.

[0153] Reference Figure 17 , forming the first capacitive dielectric film 119, the first capacitive dielectric film 119 covers the top surface and the side surface of the first lower electrode layer 116.

[0154] In some embodiments, the process steps for forming the first capacitive dielectric film 119 include: removing the sacrificial layer 137 to form a continuous first initial capacitive dielectric film over the entire surface, and the first initial capacitive dielectric film also covers the top surface and the side surfaces of the first lower electrode layer 116, that is, the first initial capacitive dielectric film also covers the exposed fourth dielectric layer 125, the gate dielectric layer 114, and the top surface of the second doped region III (refer to Figure 10 ).

[0155] Pattern the first initial capacitive dielectric film to form the first capacitive dielectric film 119 and the fourth capacitive dielectric layer 186. The fourth capacitive dielectric layer 186 is connected to the bottom surface of the first capacitive dielectric film 119 and extends in a direction away from the axis perpendicular to the surface of the substrate 110 of the first lower electrode layer 116.

[0156] Since the second lower electrode layer 126 will be formed subsequently, in the direction perpendicular to the surface of the substrate 110, the aspect ratio of the first lower electrode layer 116 itself can be smaller to improve the structural stability of the first lower electrode layer 116 itself. When forming other film layers and etching other film layers subsequently, the first lower electrode layer 116 is not likely to tilt or collapse, thereby improving the overall stability of the semiconductor structure.

[0157] In other embodiments, refer to Figure 18 , before forming the first lower electrode layer 116, it further includes: forming the fourth capacitive dielectric layer 186 on the second dielectric layer 105, and the fourth capacitive dielectric layer 186 has an opening penetrating through the fourth capacitive dielectric layer 186, and the opening exposes at least part of the top surface of the second doped region III (refer to Figure 10 ); in the process steps for forming the first lower electrode layer 116, the first lower electrode layer 116 fills the opening; and forming the first capacitive dielectric film 119 covering the top surface and the side surfaces of the first lower electrode layer 116.

[0158] In other embodiments, a third through hole can be formed that penetrates the sacrificial layer and exposes at least the entire top surface of the second doped region; form an initial first capacitive dielectric layer on the sidewalls and the bottom of the third through hole; remove the initial first capacitive dielectric layer located at the bottom of the third through hole, and the remaining first capacitive dielectric layer serves as the first capacitive dielectric film, and the first capacitive dielectric film encloses a fourth through hole; form a first lower electrode layer filling the fourth through hole, that is, the top surface of the first lower electrode layer does not have a second capacitive dielectric layer, and the remaining sacrificial layer serves as the first insulating layer.

[0159] Refer to Figure 17 and Figure 18 , form a first insulating layer 117 covering the first capacitive dielectric film 119, and the first insulating layer 117 exposes the top surface of the first capacitive dielectric film 119.

[0160] In this embodiment, the fourth capacitor dielectric layers 186 between adjacent capacitors are spaced apart from each other, that is, there is a first insulating layer 117 between adjacent fourth capacitor dielectric layers 186. In other embodiments, after forming a continuous first initial capacitor dielectric film over the entire surface, the first initial capacitor dielectric film may not be patterned, that is, the first initial capacitor dielectric film includes a first capacitor dielectric layer and a fourth capacitor dielectric layer, and the fourth capacitor dielectric layers of adjacent capacitors are in contact with each other.

[0161] Referring to Figure 19 , a first upper electrode layer 196 is formed. The first upper electrode layer 196 surrounds the first lower electrode layer 116, and the first capacitor dielectric film 119 is located between the first upper electrode layer 196 and the first lower electrode layer 116.

[0162] Specifically, the first insulating layer 117 is patterned to form a second via hole f surrounding the first lower electrode layer 116, and the side surface of the first capacitor dielectric film 119 is exposed through the second via hole f; the first upper electrode layer 196 is formed to fill the second via hole f.

[0163] With reference to Figure 19 and Figure 20 , the first capacitor dielectric film 119 located in the central region c (refer to Figure 16 ) is removed to expose the top surface of the first lower electrode layer 116 in the central region c.

[0164] Referring to Figures 20 to 22 , a second lower electrode layer 126 is formed. The second lower electrode layer 126 is in contact with the top surface of the first lower electrode layer 116 in the central region c (refer to Figure 16 ); a third capacitor dielectric layer 176 is formed to cover the top surface and the side surface of the second lower electrode layer 126.

[0165] In some embodiments, referring to Figure 21 , the first capacitor dielectric film 119 on the side surface of the first lower electrode layer 116 serves as the first capacitor dielectric layer 156, and the remaining first capacitor dielectric film 119 on the top surface of the first lower electrode layer 116 serves as the second capacitor dielectric layer 166, that is, the first capacitor dielectric layer 156 and the second capacitor dielectric layer 166 are integrally formed structures.

[0166] Specifically, referring to Figure 20 , a support layer 147 is formed on the surface jointly constituted by the top surface of the first insulating layer 117, the top surface of the first upper electrode layer 196, the top surface of the second capacitor dielectric layer 166, and the top surface of the first lower electrode 116; a through hole is formed through the support layer 147 to expose the central region c of the first lower electrode 116 (refer to Figure 16The fifth through hole g of ( ) is such that since the orthographic projection of the fifth through hole g on the substrate 110 is located within the orthographic projection of the top surface of the first lower electrode layer 116 on the substrate 110, the orthographic projection of the bottom surface of the second lower electrode layer 126 formed subsequently in the fifth through hole g on the substrate 110 is located within the orthographic projection of the top surface of the first lower electrode layer 116 on the substrate 110. This is beneficial for improving the alignment accuracy between the second lower electrode layer 126 and the first lower electrode layer 116, avoiding misalignment between the second lower electrode layer 126 and the top surface of the first lower electrode layer 116, thereby improving the dimensional accuracy of the finally formed capacitor, improving the formation quality of the capacitor, and ensuring that the capacitor has good electrical properties.

[0167] Among them, the method steps for forming the fifth through hole g are the same as those for forming the first through hole e, and will not be elaborated here.

[0168] Reference Figure 21 , a third capacitor dielectric layer 176 is formed on the exposed surface of the second lower electrode layer 126.

[0169] Specifically, the support layer 147 (reference Figure 20 ) is removed to form a continuous third initial capacitor dielectric film over the entire surface. That is, the third initial capacitor dielectric film not only covers the exposed surface of the second lower electrode layer 126, but also covers the surface jointly formed by the top surface of the first insulating layer 117, the top surface of the first upper electrode layer 196, and the top surface of the second capacitor dielectric layer 166; the third initial capacitor dielectric film is patterned, and only the third initial capacitor dielectric film located on the sidewall and top surface of the second lower electrode layer 126 is retained as the third capacitor dielectric layer 176.

[0170] In some other embodiments, reference Figure 22 , the remaining first capacitor dielectric film 119 located on the side and top surfaces of the first lower electrode layer 116 is all used as the first capacitor dielectric layer 156.

[0171] Specifically, the method steps for forming the second lower electrode layer 126 and the third initial capacitor dielectric film are the same as those in the above embodiments, and will not be elaborated here.

[0172] When patterning the third initial capacitor dielectric film, not only the third initial capacitor dielectric film located on the sidewall and top surface of the second lower electrode layer 126 is retained as the third capacitor dielectric layer 176, but also the third initial capacitor dielectric film located on the top surface of the first capacitor dielectric layer 156 and part of the top surface of the first upper electrode layer 196 is retained as the second capacitor dielectric layer 166. That is, the second capacitor dielectric layer 166 and the third capacitor dielectric layer 176 are an integrally formed structure, and the second capacitor dielectric layer 166 extends in a direction perpendicular to the axis of the substrate 110 surface away from the second lower electrode layer 126. In this way, it is beneficial to strengthen the insulation effect between the subsequently formed second upper electrode layer 106 and the first lower electrode layer 116.

[0173] In other embodiments, when the top surface of the first lower electrode layer does not have the second capacitive dielectric layer, before forming the second lower electrode layer, at least a second capacitive dielectric layer film can be formed as the second capacitive dielectric layer in the peripheral region of the top surface of the first lower electrode layer, and then the second lower electrode layer can be formed. Alternatively, when forming the third capacitive dielectric layer 176, the third initial capacitive dielectric film is not patterned. Alternatively, when forming the third capacitive dielectric layer 176, at least the third initial capacitive dielectric film located on the sidewalls and the top surface of the second lower electrode layer 126 and the peripheral region of the top surface of the first lower electrode layer is retained.

[0174] It should be noted that Figure 22 in the example where the second capacitive dielectric layers 166 between adjacent capacitors are spaced apart from each other, that is, there is a second insulating layer 127 between adjacent second capacitive dielectric layers 166. In fact, the second capacitive dielectric layers 166 of adjacent capacitors can be in contact and connected to each other.

[0175] Further, referring to Figure 21 and Figure 22 a second insulating layer 127 covering the third capacitive dielectric layer 176 is formed; the second insulating layer 127 is patterned to form a sixth through hole surrounding the second lower electrode layer 126, and the sixth through hole exposes the side surface and the top surface of the third capacitive dielectric layer 176 and exposes the top surface of the first upper electrode layer 196; a second upper electrode layer 106 filling the sixth through hole is formed.

[0176] The first insulating layer 117 and the second insulating layer 127 together constitute the insulating layer 107. The first insulating layer 117 is located between adjacent first upper electrode layers 196 and is used to achieve electrical insulation between adjacent first upper electrode layers 196; the second insulating layer 127 is located between adjacent second upper electrode layers 106 and covers the upper surface of the first insulating layer 117 and is used to achieve electrical insulation between adjacent second upper electrode layers 106.

[0177] Among them, the first upper electrode layer 196 and the second upper electrode layer 106 together constitute the upper electrode layer 146; the first capacitive dielectric layer 156, the second capacitive dielectric layer 166, the third capacitive dielectric layer 176 and the fourth capacitive dielectric layer 186 together constitute the capacitive dielectric layer 136; the first lower electrode layer 116, the second lower electrode layer 126, the capacitive dielectric layer 136 and the upper electrode layer 146 together constitute a capacitor in the semiconductor structure.

[0178] Further, referring to Figure 1 after forming a storage unit 100, the next storage unit 100 can be formed on the side of the storage unit 100 away from the substrate 100.

[0179] In summary, by forming the lower electrode layer of the capacitor step by step, that is, forming the first lower electrode layer 116 and the second lower electrode layer 126 step by step, it is beneficial to improve the aspect ratio of the capacitor while improving the stability of the structure of the lower electrode layer itself, so as to increase the capacitance of the capacitor. In addition, by making the orthographic projection of the bottom surface of the second lower electrode layer 126 on the substrate 110 located within the orthographic projection of the top surface of the first lower electrode layer 116 on the substrate 110, the misalignment between the bottom surface of the second lower electrode layer and the top surface of the first lower electrode layer is avoided, thereby improving the dimensional accuracy of the capacitor while increasing the capacitance, so as to ensure that the capacitor has good electrical performance.

[0180] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present invention, and in practical applications, various changes can be made in form and details without departing from the spirit and scope of the present invention. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate and a storage unit located on the substrate, the storage unit comprising: A first dielectric layer and a metal bit line located within the first dielectric layer, and the first dielectric layer exposes the surface of the metal bit line; A semiconductor channel, the semiconductor channel is located on a partial surface of the metal bit line, and the bottom surface of the semiconductor channel facing the metal bit line is electrically connected to the metal bit line; A word line, the word line is disposed to surround a partial region of the semiconductor channel; A second dielectric layer, the second dielectric layer is located between the metal bit line and the word line, and is also located on a side of the word line away from the substrate; A first lower electrode layer and a second lower electrode layer stacked on a top surface of the semiconductor channel away from the metal bit line, and the first lower electrode layer is in contact with the top surface of the semiconductor channel; An upper electrode layer, the upper electrode layer is located on the top surface of the second lower electrode layer, and surrounds the first lower electrode layer and the second lower electrode layer; A capacitive dielectric layer, the capacitive dielectric layer is located between the upper electrode layer and the first lower electrode layer, and is also located between the upper electrode layer and the second lower electrode layer; The first lower electrode layer, the second lower electrode layer, the capacitive dielectric layer and the upper electrode layer form a capacitor, and the semiconductor structure includes a plurality of such capacitors in a direction in which the metal bit line extends, and the upper electrode layers of adjacent capacitors are isolated from each other.

2. The semiconductor structure according to claim 1, wherein, A positive projection of a bottom surface of the second lower electrode layer on the substrate is located within a positive projection of a top surface of the first lower electrode layer on the substrate.

3. The semiconductor structure according to claim 1, characterized in that, The capacitive dielectric layer covers the top surface and side surfaces of the second lower electrode layer, and also covers the side surfaces of the first lower electrode layer and the top surface of the first lower electrode layer exposed by the second lower electrode layer.

4. The semiconductor structure according to claim 1, wherein The capacitive dielectric layer comprises: A first capacitive dielectric layer, the first capacitive dielectric layer covers the side surface of the first lower electrode layer; A second capacitive dielectric layer, the second capacitive dielectric layer covers the top surface of the first lower electrode layer exposed by the second lower electrode layer; A third capacitive dielectric layer, the third capacitive dielectric layer covers the top surface and side surfaces of the second lower electrode layer.

5. The semiconductor structure according to claim 4, wherein The first capacitive dielectric layer and the second capacitive dielectric layer are an integrally formed structure.

6. The semiconductor structure according to claim 4, wherein The capacitive dielectric layer further comprises: a fourth capacitive dielectric layer, the fourth capacitive dielectric layer is connected to a bottom surface of the first capacitive dielectric layer and extends in a direction away from an axis of the first lower electrode layer perpendicular to the surface of the substrate; The upper electrode layer is also located on the surface of the fourth capacitive dielectric layer.

7. The semiconductor structure according to claim 6, wherein, The fourth capacitive dielectric layer and the first capacitive dielectric layer are an integrally formed structure.

8. The semiconductor structure according to claim 4, wherein The second capacitive dielectric layer is also located on the top surface of the first capacitive dielectric layer and extends in a direction away from an axis of the second lower electrode layer perpendicular to the surface of the substrate.

9. The semiconductor structure according to claim 4, wherein The upper electrode layer comprises: A first upper electrode layer, the first upper electrode layer surrounds the first lower electrode layer and is located on the side surface of the first capacitive dielectric layer; A second upper electrode layer, the second upper electrode layer surrounds the second lower electrode layer, is located on the surface of the third capacitive dielectric layer, and a bottom surface of the second upper electrode layer is in contact with a top surface of the first upper electrode layer.

10. The semiconductor structure according to claim 1, wherein, The relative dielectric constant of the material of the capacitive dielectric layer is greater than that of the material of the second dielectric layer.

11. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure includes at least two of the memory cells stacked on the substrate.

12. The semiconductor structure according to claim 1, wherein, The material of the semiconductor channel includes at least one or more of IGZO, IWO, or ITO; the semiconductor channel forms the channel of the junctionless transistor.

13. The semiconductor structure according to claim 1, wherein In the direction from the substrate towards the metal bit line, the semiconductor channel includes a first doped region, a channel region, and a second doped region arranged in sequence; the first doped region is electrically connected to the metal bit line; the word line surrounds the channel region; the first lower electrode layer is in contact with a side of the second doped region away from the channel region.

14. The semiconductor structure according to claim 1, wherein The word line includes: A gate dielectric layer that surrounds the entire sidewall surface of the semiconductor channel; A gate conductive layer that surrounds a partial region of the semiconductor channel, and the gate dielectric layer is located between the semiconductor channel and the gate conductive layer.

15. A method for manufacturing a semiconductor structure, characterized in that, Comprising: Providing a substrate; Forming a memory cell on the substrate, and the process steps for forming the memory cell include: Providing a first dielectric layer and a metal bit line located within the first dielectric layer, and the first dielectric layer exposes the surface of the metal bit line; Forming a semiconductor channel that is located on a partial surface of the metal bit line, and a bottom surface of the semiconductor channel facing the metal bit line is electrically connected to the metal bit line; Forming a word line that surrounds a partial region of the semiconductor channel; Forming a second dielectric layer that is located between the metal bit line and the word line, and is also located on a side of the word line away from the substrate; Forming a first lower electrode layer that is in contact with the top surface of the semiconductor channel; Forming a second lower electrode layer that is located on the top surface of the first lower electrode layer; Forming an upper electrode layer that is located on the top surface of the second lower electrode layer and surrounds the first lower electrode layer and the second lower electrode layer; Forming a capacitive dielectric layer that is located between the upper electrode layer and the first lower electrode layer, and is also located between the upper electrode layer and the second lower electrode layer; The process steps for forming the first lower electrode layer, the second lower electrode layer, the capacitive dielectric layer, and the upper electrode layer include: Forming the first lower electrode layer, and the top surface of the first lower electrode layer includes a central region and a peripheral region surrounding the central region; Forming a first capacitive dielectric film that covers the top surface and the side surface of the first lower electrode layer; Forming a first upper electrode layer that surrounds the first lower electrode layer, and the first capacitive dielectric film is located between the first upper electrode layer and the first lower electrode layer; Removing the first capacitive dielectric film located in the central region to expose the top surface of the first lower electrode layer in the central region, the first capacitive dielectric film located on the side surface of the first lower electrode layer serves as the first capacitive dielectric layer, and the remaining first capacitive dielectric film located on the top surface of the first lower electrode layer serves as the second capacitive dielectric layer; Form a second lower electrode layer, and the top surface of the second lower electrode layer is in contact with the top surface of the first lower electrode layer in the central region; Form a third capacitive dielectric layer, and the third capacitive dielectric layer covers the top surface and the side surface of the second lower electrode layer.

16. The manufacturing method according to claim 15, characterized in that, The process steps for forming the first capacitive dielectric film include: Form a continuous first initial capacitive dielectric film over the entire surface, and the first initial capacitive dielectric film also covers the top surface and the side surface of the first lower electrode layer; Pattern the first initial capacitive dielectric film to form the first capacitive dielectric film and a fourth capacitive dielectric layer, and the fourth capacitive dielectric layer is connected to the bottom surface of the first capacitive dielectric film and extends in a direction away from the axis perpendicular to the substrate surface of the first lower electrode layer.

17. The manufacturing method according to claim 15, characterized in that, In the direction from the substrate towards the metal bit line, the semiconductor channel includes a first doped region, a channel region, and a second doped region arranged in sequence; The process steps for forming the first lower electrode layer, the first capacitive dielectric film, and the first upper electrode layer include: Form a sacrificial layer on one side of the second doped region away from the channel region, and the sacrificial layer has a first through hole that penetrates the sacrificial layer and exposes the second doped region; Form the first lower electrode layer that fills the first through hole; Remove the sacrificial layer and form the first capacitive dielectric film; Form a first insulating layer that covers the first capacitive dielectric film, and the first insulating layer exposes the top surface of the first capacitive dielectric film; Pattern the first insulating layer to form a second through hole that surrounds the first lower electrode layer, and the second through hole exposes the side surface of the first capacitive dielectric film; Form the first upper electrode layer that fills the second through hole.

18. The manufacturing method according to claim 15, characterized in that, Before forming the first lower electrode layer, it further includes: forming a fourth capacitive dielectric layer on the second dielectric layer, and the fourth capacitive dielectric layer has an opening that penetrates the fourth capacitive dielectric layer; in the process steps for forming the first lower electrode layer, the first lower electrode layer fills the opening.

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