Capacitor structure, method for forming the same, and memory

Abstract

The present application discloses a capacitor structure, a forming method thereof, and a memory. The method includes: providing a substrate; stacking an electrode support structure on the substrate, the electrode support structure at least including a first support layer at the top, forming capacitor holes at intervals within the electrode support structure, the capacitor holes extending upward in a direction perpendicular to the surface of the substrate; forming electrode posts within the capacitor holes and an electrode layer extending from the electrode posts to the upper surface of the first support layer; removing the electrode layer; removing the first support layer; forming a dielectric layer on the top of the electrode support structure, the dielectric layer covering the tops of the electrode posts, and the outer peripheral walls of the tops of the electrode posts being connected to the dielectric layer. By covering the tops of the electrode posts with the dielectric layer, there is no gap between the dielectric layer and the outer peripheral walls of the electrode posts, and the dielectric layer can completely fix the tops of the electrode posts, preventing the electrode posts from tilting and deforming, and making it difficult for the electrode posts to fall off.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits and the manufacturing of electronic components, and particularly relates to a capacitor structure, a method for forming the same, and a memory. Background Art

[0002] A memory is a memory component used to store programs and various data information. According to the usage type of the memory, it can be divided into a read-only memory and a random access memory. A memory generally includes a capacitor and a transistor connected to the capacitor. The capacitor is used to store the charge representing the stored information, and the transistor is a switch that controls the inflow and release of the charge of the capacitor.

[0003] With the continuous reduction of the memory process node, in the prior art, when manufacturing an advanced dynamic random access memory (DRAM), the capacitor lower electrode formed in the capacitor hole is likely to fall off. Summary of the Invention

[0004] To solve the above problems, a first aspect of the present application provides a method for forming a capacitor structure, including: providing a substrate; stacking an electrode support structure on the substrate, the electrode support structure at least including a first support layer at the top, forming capacitor holes at intervals within the electrode support structure, the capacitor holes extending upward in a direction perpendicular to the surface of the substrate; forming electrode columns within the capacitor holes and an electrode layer extending from the electrode columns to the upper surface of the first support layer; removing the electrode layer; removing the first support layer; forming a dielectric layer on the top of the electrode support structure, the dielectric layer covering the top of the electrode columns, and the outer peripheral wall of the top of the electrode columns being connected to the dielectric layer.

[0005] Optionally, after forming the dielectric layer on the top of the electrode support structure, it further includes: forming a trench in the dielectric layer, the trench exposing the surface of the electrode support structure, the trench being located between two adjacent electrode columns; and / or the trench being located on one side of the electrode column.

[0006] Optionally, stacking the electrode support structure on the substrate includes sequentially stacking a third support layer, a second silicon oxide layer, a second support layer, and a first silicon oxide layer from bottom to top on the substrate, and the first silicon oxide layer is formed between the first support layer and the second support layer.

[0007] Optionally, after forming the trench in the dielectric layer, it further includes: removing the first silicon oxide layer.

[0008] Optionally, removing the first support layer includes: an oxide layer is formed between the first support layer and the electrode columns, and by using a wet etching process, the first support layer and the oxide layer are removed simultaneously; the etching solution of the wet etching process includes hot phosphoric acid.

[0009] Optionally, after removing the electrode layer, the top of the electrode post forms a shrinkage from bottom to top within the first support layer, and after removing the first support layer, the dielectric layer gradually redeposits and grows upward on the first silicon oxide layer until it fills the position of the original electrode layer.

[0010] Optionally, the dielectric layer is formed by at least one of chemical vapor deposition, physical vapor deposition, and atomic layer deposition.

[0011] Optionally, a capacitor contact is formed at the bottom of the capacitor via, and the electrode post is formed on the capacitor contact.

[0012] Optionally, the material of the electrode post includes titanium nitride.

[0013] Optionally, the material of the dielectric layer includes silicon nitride or silicon carbonitride.

[0014] Optionally, the first etching rate of the hot phosphoric acid on the first support layer and its oxide layer is greater than the second etching rate of the hot phosphoric acid on the first silicon oxide layer and the electrode post, and the ratio of the first etching rate to the second etching rate is greater than 50:1.

[0015] The second aspect of the present application provides a capacitor structure, which is prepared by using the formation method of any one of the above capacitor structures.

[0016] In an exemplary embodiment of the present application, the capacitor structure includes: a substrate; an electrode support structure disposed on the substrate, capacitor vias are formed at intervals within the electrode support structure, and the capacitor vias extend upward in a direction perpendicular to the surface of the substrate; an electrode post disposed within the capacitor vias, and the electrode post exposes the electrode support structure; a dielectric layer covering the top of the electrode post, and the outer peripheral wall of the top of the electrode post is connected to the dielectric layer.

[0017] Optionally, the dielectric layer is provided with grooves, the grooves expose the surface of the electrode support structure, the grooves are located between two adjacent electrode posts; and / or the grooves are located on one side of the electrode post.

[0018] Optionally, the electrode support structure includes a third support layer, a second silicon oxide layer, and a second support layer that are sequentially stacked from bottom to top on the substrate.

[0019] The third aspect of the present application provides a memory, and the memory includes the above capacitor structure.

[0020] The above technical solutions of the present application have the following beneficial technical effects:

[0021] In the embodiments of the present application, by removing the first support layer and its oxide layer, where the oxide layer is the oxide layer of silicon carbonitride, and then forming a dielectric layer on the top of the electrode support structure, the dielectric layer can closely cover the top of the electrode column. The top of the electrode column is located within the dielectric layer, and there is no gap between the outer peripheral wall of the electrode column and the dielectric layer. In this way, the dielectric layer can completely fix the top of the electrode column, prevent the electrode column from tilting and deforming, and make it difficult for the electrode column to fall off, thereby improving the yield of the capacitor structure. Description of the Drawings

[0022] Figure 1 is a schematic structural diagram of a capacitor structure in the prior art;

[0023] Figure 1a is a schematic structural diagram of a capacitor structure in the related art;

[0024] Figures 2 - 9 is a schematic structural diagram corresponding to each step in the method for forming a capacitor structure provided by the embodiments of the present application;

[0025] Figure 10 is a flowchart of a method for forming a capacitor structure according to an embodiment of the present application;

[0026] Figure 11 is a flowchart of a method for forming a capacitor structure according to another embodiment of the present application;

[0027] Reference Signs:

[0028] 11 - Capacitor Hole; 12 - Capacitor Contact; 13 - Electrode Column; 14 - Groove;

[0029] 101 - First Support Layer; 102 - First Silicon Oxide Layer; 103 - Second Support Layer; 104 - Second Silicon Oxide Layer; 105 - Third Support Layer; 106 - Electrode Layer; 107 - Oxide Layer; 108 - Dielectric Layer; 109 - Mask Layer; 110 - Fourth Support Layer. Detailed Embodiments

[0030] To make the objectives, technical solutions, and advantages of the present application clearer and more understandable, the present application will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings. It should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present application. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present application.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present application belongs. The terms used in the specification of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0032] It will be appreciated that the terms "first", "second", etc. used in the present application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of the present application, the first resistor may be referred to as the second resistor, and similarly, the second resistor may be referred to as the first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0033] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising", "including" or "having", etc. specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the related listed items.

[0034] As can be seen from the background art, in the prior art during the production and manufacturing of advanced dynamic random access memories (DRAMs), the capacitor lower electrode formed in the capacitor hole is likely to fall off.

[0035] Figure 1 is a schematic structural diagram of a capacitor structure in the prior art, referring to Figure 1 , there is a gap between the outer peripheral wall of the top of the electrode column 13 and the first support layer 101. The first support layer 101 cannot fix the electrode column 13, which easily causes the electrode column 13 to tilt and deform and fall off from the surface of the first support layer 101.

[0036] To solve the above technical problems, a first aspect of the present application provides a method for forming a capacitor structure, in which an electrode column 13 and an electrode layer 106 extending from the electrode column 13 to the upper surface of the first support layer 101 are formed in a capacitor hole 11; the electrode layer 106 is removed; the first support layer 101 is removed; a dielectric layer 108 is formed on the top of the electrode support structure, the dielectric layer 108 covers the top of the electrode column 13, and the outer peripheral wall of the top of the electrode column 13 is connected to the dielectric layer 108. There is no gap between the dielectric layer 108 and the outer peripheral wall of the electrode column 13. The dielectric layer 108 can completely fix the top of the electrode column 13, and the electrode column 13 is in close contact with the dielectric layer 108, which can prevent the electrode column 13 from tilting and deforming, so that the electrode column 13 is not likely to fall off.

[0037] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following will elaborate on each embodiment of the present application with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present application, many technical details are provided to help readers better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0038] Figure 10 It is a flowchart of a method for forming a capacitor structure according to an embodiment of the present application. Refer to Figure 10 , in some embodiments of the present application, a method for forming a capacitor structure is provided, which may include the following steps:

[0039] S10. Provide a substrate. The substrate is a metal silicide.

[0040] S20. Stack an electrode support structure on the substrate. The electrode support structure at least includes a first support layer 101 at the top. Capacitor holes 11 are formed at intervals within the electrode support structure, and the capacitor holes 11 extend upward in a direction perpendicular to the surface of the substrate. The first support layer 101 is silicon nitride or silicon carbonitride. During the formation of the capacitor holes 11, an oxide layer 107 is easily formed on the sidewalls of the first support layer 101 exposed to the capacitor holes 11, and this oxide layer 107 is the oxide layer 107 of silicon carbonitride.

[0041] S30. Form electrode posts 13 and an electrode layer 106 extending from the electrode posts 13 to the upper surface of the first support layer 101 within the capacitor holes 11. The electrode posts 13 are formed in the capacitor holes 11 by a deposition process, and an electrode layer 106 extending from the electrode posts 13 to the upper surface of the first support layer 101 is formed. The electrode layer 106 is formed on the upper surface of the first support layer 101. The materials of the electrode posts 13 and the electrode layer 106 include titanium nitride, etc.

[0042] S40. Remove the electrode layer 106. The top electrode layer 106 can be removed by an etch-back process. At this time, due to the internal stress contraction of the electrode posts 13, a trapezoidal morphology appears on the outer peripheral wall at the top of the electrode posts 13, that is, the electrode posts 13 gradually contract upward in a direction perpendicular to the first silicon oxide layer 102. Therefore, the outer peripheral wall of the electrode posts 13 is separated from the oxide layer 107 within the first support layer 101.

[0043] S50. Remove the first support layer 101. The first support layer 101 and its oxide layer 107 can be removed by using a wet etching process. The etching solution selected in this wet etching process includes hot phosphoric acid, which can completely remove the oxide layer 107 generated when the capacitor holes 11 are formed on the first support layer 101. At this time, the stress at the top of the electrode column 13 is completely released, enabling the electrode column 13 to have better close contact with the subsequent formed dielectric layer 108 wrapping its surface, and fully realizing the support stability of the dielectric layer 108 for the electrode column 13.

[0044] S60. Form a dielectric layer 108 on the top of the electrode support structure. The dielectric layer 108 covers the top of the electrode column 13, and the outer peripheral wall of the top of the electrode column 13 is connected to the dielectric layer 108. The dielectric layer 108 is redeposited on the first silicon oxide layer 102. The material of the dielectric layer 108 includes silicon carbonitride. The dielectric layer 108 is gradually redeposited and grown upward on the first silicon oxide layer 102 until the dielectric layer 108 is deposited and grown to the position of the original electrode layer 106. The dielectric layer 108 covers the top of the electrode column 13, which can fix the electrode column 13 to prevent the electrode column 13 from tilting and detaching from the dielectric layer 108; moreover, the surface of the dielectric layer 108 in contact with the electrode column 13 is not prone to form an oxide layer 107 of silicon carbonitride, and the stress of the electrode column 13 is completely released, so the electrode column 13 is not prone to falling off. In some embodiments, at least one of chemical vapor deposition, physical vapor deposition, and atomic layer deposition is used to form the dielectric layer 108.

[0045] The method for forming the capacitor structure provided by the embodiment of the present invention is simple and easy to operate, and can also make there be no gap between the dielectric layer 108 and the outer peripheral wall of the electrode column 13. The dielectric layer 108 can completely fix the top of the electrode column 13. The electrode column 13 is in close contact with the dielectric layer 108, which can prevent the electrode column 13 from tilting and deforming, and make the electrode column 13 not prone to falling off.

[0046] Figure 11 It is a flowchart of the method for forming the capacitor structure of another embodiment of the present application. Refer to Figure 11 , in another embodiment of the present application, a method for forming a capacitor structure is provided. After step S60, the following steps may further be included:

[0047] S70. Form a trench 14 in the dielectric layer 108. The trench 14 exposes the surface of the electrode support structure. The trench 14 is located between two adjacent electrode columns 13; and / or the trench 14 is located on one side of the electrode column 13. Before forming the trench 14 in the dielectric layer 108, a mask layer 109 may be formed on the top of the dielectric layer 108, and the trench 14 is formed by opening holes in the dielectric layer 108 using the photolithographic imaging process of grid holes.

[0048] S80. Remove the first silicon oxide layer 102. The first silicon oxide layer 102 can be removed by a wet etching process. In some embodiments, the materials of the first silicon oxide layer 102, the second support layer 103, and the dielectric layer 108 are different, and their etching rates in the same etching solution are different. Specifically, in the same etching solution, the etching rate of the first silicon oxide layer 102 is much greater than that of the second support layer 103 and the dielectric layer 108, so as to ensure that when the first silicon oxide layer 102 is completely removed, the second support layer 103 and the dielectric layer 108 can be completely retained, or nearly completely retained. Accordingly, the etching solution selected in the wet etching process can be an acidic solution.

[0049] Figures 2 - 9 Structural schematic diagrams corresponding to the steps in the method for forming a capacitor structure provided by the embodiments of the present application. The following will be combined with Figures 2 - 9 to elaborate on the steps of the embodiments of the present application in detail.

[0050] Refer to Figure 2 , provide a substrate (not shown in the figure), form an electrode support structure on the substrate. The electrode support structure includes a third support layer 105, a second silicon oxide layer 104, a second support layer 103, a first silicon oxide layer 102, and a first support layer 101 that are stacked in sequence from bottom to top along the longitudinal direction. Capacitor holes 11 are formed at intervals thereon along the longitudinal direction. It can be understood that the third support layer 105 is formed on the substrate. The materials of the first support layer 101, the second support layer 103, and the third support layer 105 include silicon nitride or silicon carbonitride; the material of the second silicon oxide layer 104 includes borophosphosilicate glass (BPSG); the material of the first silicon oxide layer 102 includes tetraethyl orthosilicate (TEOS). A capacitor contact 12 is formed at the bottom of the capacitor hole 11, and the material of the capacitor contact 12 includes conductive materials such as tungsten or titanium. During the formation of the capacitor hole 11, an oxide layer 107 is easily formed on the sidewall of the first support layer 101 exposed to the capacitor hole 11, and the oxide layer 107 is an oxide layer 107 of silicon carbonitride.

[0051] Refer to Figure 3 , in the capacitor hole 11, form an electrode column 13 by a deposition process, and form an electrode layer 106 extending from the electrode column 13 to the upper surface of the first support layer 101. The electrode layer 106 is formed on the upper surface of the first support layer 101, and the materials of the electrode column 13 and the electrode layer 106 include titanium nitride, etc.

[0052] Refer to Figure 4, the top electrode layer 106 is removed using a back-etching process. At this time, due to the internal stress contraction of the electrode post 13, a trapezoidal morphology appears on the outer peripheral wall of the top of the electrode post 13, that is, the electrode post 13 gradually contracts upward in a direction perpendicular to the first silicon oxide layer 102. Therefore, there is a detachment between the outer peripheral wall of the electrode post 13 and the oxide layer 107 within the first support layer 101.

[0053] Based on what is shown in the reference Figure 4 , usually, referring to Figure 1a , silicon carbonitride is directly deposited on the first support layer 101 to form the fourth support layer 110. The thickness of the fourth support layer 110 is the same as the thickness of the original electrode layer 106. The electrode post 13 is detached from the oxide layer 107 on its outer peripheral wall within the first support layer 101. If the oxide layer 107 is removed, the gap between the outer peripheral wall of the electrode post 13 and the first support layer 101 becomes larger. Therefore, the first support layer 101 cannot fix it, easily leading to the phenomenon that the electrode post 13 tilts, deforms, and falls off. If a groove 14 is opened between two adjacent electrode posts 13, referring to Figure 1 , when the outer peripheral wall of the electrode post 13 is not fixed by the first support layer 101, the electrode post 13 will tilt and deform, and even two adjacent electrode posts 13 will come into contact with each other.

[0054] Referring to Figure 5 , using a wet etching process, the first support layer 101 and its oxide layer 107 are removed. The etching solution selected in this wet etching process includes hot phosphoric acid, which can completely remove the oxide layer 107 generated when the capacitor hole 11 is formed on the first support layer 101. At this time, the stress at the top of the electrode post 13 is completely released, enabling the electrode post 13 to have a better tight contact area with the subsequent formed dielectric layer 108 wrapping its surface, and fully realizing the support stability of the dielectric layer 108 for the electrode post 13.

[0055] Specifically, the material of the first support layer 101 includes silicon nitride or silicon carbonitride, the material of the electrode post 13 includes titanium nitride, and the material of the first silicon oxide layer 102 includes tetraethyl orthosilicate (TEOS); in some embodiments, since the materials of the first support layer 101, the electrode post 13, and the first silicon oxide layer 102 are different, and their etching rates in the same etching solution are different. Accordingly, the etching solution selected in this wet etching process can be hot phosphoric acid. The etching rate of hot phosphoric acid for the first support layer 101 and its oxide layer 107 is much greater than the etching rate for the first silicon oxide layer 102 and the electrode post 13, and the etching rate ratio is greater than 50:1, to ensure that when the first support layer 101 and its oxide layer 107 are completely removed, the first silicon oxide layer 102 and the electrode post 13 can be completely retained, or nearly completely retained.

[0056] Referring to Figure 6, a dielectric layer 108 is redeposited on the first silicon oxide layer 102, and the material of the dielectric layer 108 includes silicon carbonitride. The dielectric layer 108 is gradually redeposited and grown upward on the first silicon oxide layer 102 until the dielectric layer 108 is deposited and grown to the position of the original electrode layer 106. The dielectric layer 108 covers the top of the electrode post 13, which can fix the electrode post 13 to prevent the inclination and detachment of the electrode post 13 from the dielectric layer 108; moreover, the surface of the dielectric layer 108 in contact with the electrode post 13 is not prone to form an oxide layer 107 of silicon carbonitride, and the stress of the electrode post 13 is completely released, and the electrode post 13 is not prone to fall off. In some embodiments, at least one of chemical vapor deposition, physical vapor deposition, and atomic layer deposition is used to form the dielectric layer 108.

[0057] Reference Figure 7 , a mask layer 109 is formed on the top of the dielectric layer 108, and trenches 14 are formed by opening holes in the dielectric layer 108 using a lithographic imaging process with grid holes. In an exemplary embodiment, a mask layer 109 is first formed on the upper surface of the dielectric layer 108, and then the mask layer 109 is patterned. The pattern formed by the patterned mask layer 109 coincides with the projection of the trench 14 on the upper surface of the dielectric layer 108. In this way, by etching the dielectric layer 108 downward in a direction perpendicular to the surface of the dielectric layer 108 through the exposed upper surface of the dielectric layer 108, trenches 14 can be formed in the dielectric layer 108.

[0058] Reference Figure 8 , the trenches 14 formed in the dielectric layer 108 can be located between two adjacent electrode posts 13, and / or the trenches 14 can be located on one side of the electrode post 13.

[0059] Reference Figure 9 , the first silicon oxide layer 102 is removed by a wet etching process. In some embodiments, the materials of the first silicon oxide layer 102, the second support layer 103, and the dielectric layer 108 are different, and their etching rates in the same etching solution are different. Specifically, in the same etching solution, the etching rate of the first silicon oxide layer 102 is much greater than the etching rates of the second support layer 103 and the dielectric layer 108, so as to ensure that when the first silicon oxide layer 102 is completely removed, the second support layer 103 and the dielectric layer 108 can be completely retained or nearly completely retained. Accordingly, the etching solution selected in the wet etching process can be an acidic solution.

[0060] In some embodiments, the materials of the second support layer 103 and the dielectric layer 108 include silicon nitride, and the etching solution includes a hydrofluoric acid solution. The first silicon oxide layer 102 is doped with boron or phosphorus to ensure the uniformity of critical dimensions and improve the etching rate of the first silicon oxide layer 102 during wet etching.

[0061] The second aspect of the present application provides a capacitive structure, which is prepared by the method in the above embodiment.

[0062] In an embodiment of the present application, with reference to Figure 9 , the capacitive structure includes a substrate (not shown in the figure); an electrode support structure disposed on the substrate, in which capacitive holes 11 are formed at intervals, and the capacitive holes 11 extend upward in a direction perpendicular to the surface of the substrate; an electrode column 13 disposed in the capacitive holes 11, and the electrode column 13 exposes the electrode support structure; a dielectric layer 108 covering the top of the electrode column 13, and the outer peripheral wall of the top of the electrode column 13 is connected to the dielectric layer 108. The electrode support structure is disposed on the upper surface of the substrate, and a capacitive contact 12 is provided at the bottom of the capacitive hole 11. The material of the capacitive contact 12 includes conductive materials such as tungsten or titanium. The bottom of the electrode column 13 is connected to the capacitive contact 12. The material of the electrode column 13 includes titanium nitride, etc.; the material of the dielectric layer 108 includes silicon carbonitride. There is no gap between the dielectric layer 108 and the outer peripheral wall of the electrode column 13. The dielectric layer 108 can completely fix the top of the electrode column 13. The electrode column 13 is in close contact with the dielectric layer 108, which can prevent the electrode column 13 from tilting and deforming, so that the electrode column 13 is not likely to fall off.

[0063] In some embodiments, the dielectric layer 108 is provided with a groove 14, the groove 14 exposes the surface of the electrode support structure, and the groove 14 is located between two adjacent electrode columns 13; and / or the groove 14 is located on one side of the electrode column 13. The groove 14 exposes the upper surface of the second support layer 103.

[0064] In some embodiments, the electrode support structure includes a third support layer 105, a second silicon oxide layer 104, and a second support layer 103 that are sequentially stacked on the substrate from bottom to top. The materials of the second support layer 103 and the third support layer 105 include silicon nitride or silicon carbonitride; the material of the second silicon oxide layer 104 includes borophosphosilicate glass (BPSG).

[0065] The third aspect of the present application provides a memory, and the memory includes the above capacitive structure.

[0066] In an embodiment of the present application, by removing the first support layer and its oxide layer, the oxide layer is an oxide layer of silicon carbonitride, and then forming a dielectric layer on the top of the electrode support structure. The dielectric layer can cover the top of the electrode column, so that there is no gap between the dielectric layer and the outer peripheral wall of the electrode column. The dielectric layer can completely fix the top of the electrode column, prevent the electrode column from tilting and deforming, make the electrode column not likely to fall off, and improve the yield of the capacitive structure.

[0067] It should be understood that the above specific embodiments of the present application are only used for exemplary illustration or explanation of the principles of the present application, and do not constitute a limitation to the present application. Therefore, any modifications, equivalent replacements, improvements, etc. made without departing from the spirit and scope of the present application shall be included within the protection scope of the present application. In addition, the appended claims of the present application are intended to cover all variations and modifications that fall within the scope and boundaries of the appended claims, or equivalent forms of such scope and boundaries.

Claims

1. A method for forming a capacitor structure, characterized in that Comprising: Providing a substrate; Stacking an electrode support structure on the substrate, the electrode support structure at least including a first support layer at the top, forming capacitor holes at intervals within the electrode support structure, and the capacitor holes extending upward in a direction perpendicular to the surface of the substrate; Forming electrode posts within the capacitor holes and an electrode layer extending from the electrode posts to the upper surface of the first support layer; Removing the electrode layer; Removing the first support layer; Forming a dielectric layer on the top of the electrode support structure, the dielectric layer covering the top of the electrode posts, and the outer peripheral wall of the top of the electrode posts being connected to the dielectric layer; Wherein, removing the first support layer includes: An oxide layer is formed between the first support layer and the electrode posts, and using a wet etching process, the first support layer and the oxide layer are removed simultaneously; The etching solution for the wet etching process includes hot phosphoric acid.

2. The method for forming a capacitive structure according to claim 1, wherein After forming the dielectric layer on the top of the electrode support structure, further including: Forming trenches in the dielectric layer, the trenches exposing the surface of the electrode support structure, and the trenches being located between two adjacent electrode posts; And / or the trenches are located on one side of the electrode posts.

3. The method for forming the capacitive structure according to claim 2, wherein Stacking an electrode support structure on the substrate includes sequentially stacking a third support layer, a second silicon oxide layer, a second support layer, and a first silicon oxide layer from bottom to top on the substrate, and the first silicon oxide layer is formed between the first support layer and the second support layer.

4. The method for forming the capacitive structure according to claim 3, wherein, After forming trenches in the dielectric layer, further including: Removing the first silicon oxide layer.

5. The method for forming the capacitive structure according to claim 3, wherein After removing the electrode layer, a contraction from bottom to top is formed at the top of the electrode posts within the first support layer, and after removing the first support layer, the dielectric layer gradually redeposits and grows upward on the first silicon oxide layer until it fills the original position of the electrode layer.

6. The method for forming a capacitive structure according to claim 1, wherein The dielectric layer is formed by at least one of chemical vapor deposition, physical vapor deposition, and atomic layer deposition.

7. The method for forming a capacitive structure according to claim 1, wherein A capacitor contact is formed at the bottom of the capacitor hole, and the electrode posts are formed on the capacitor contact.

8. The method for forming the capacitance structure according to claim 1, wherein, The material of the electrode posts includes titanium nitride.

9. The method for forming a capacitor structure according to claim 1, wherein, The material of the dielectric layer includes silicon nitride or silicon carbonitride.

10. The method for forming a capacitive structure according to claim 1, wherein, The first etching rate of the hot phosphoric acid for the first support layer and its oxide layer is greater than the second etching rate of the hot phosphoric acid for the first silicon oxide layer and the electrode posts, and the ratio of the first etching rate to the second etching rate is greater than 50:

1.

11. A capacitive structure, characterized in that, Prepared by using the method for forming a capacitor structure according to any one of claims 1 - 10.

12. The capacitive structure according to claim 11, wherein Comprising: A substrate; An electrode support structure, which is disposed on the substrate, and capacitor holes are formed at intervals within the electrode support structure, and the capacitor holes extend upward in a direction perpendicular to the surface of the substrate; Electrode posts, which are disposed within the capacitor holes, and the electrode posts expose the electrode support structure; A dielectric layer, which covers the top of the electrode posts, and the outer peripheral wall of the top of the electrode posts is connected to the dielectric layer.

13. The capacitive structure according to claim 12, wherein, The dielectric layer is provided with trenches, the trenches exposing the surface of the electrode support structure, and the trenches are located between two adjacent electrode posts; And / or the trenches are located on one side of the electrode posts.

14. The capacitive structure according to claim 12, wherein The electrode support structure includes a third support layer, a second silicon oxide layer, and a second support layer that are sequentially stacked from bottom to top on the substrate.

15. A memory, characterized in that, It includes the capacitor structure according to any one of claims 11-14.

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