In-memory computing circuit and method and resistive change memory

Abstract

The application provides an in-memory computing circuit and method and a resistance change type memory, the first transistor and the second transistor in the jth memory cell adopt a common gate and common source connection mode, so that the i bit line, the i complementary bit line and the i source line share charges, compared with the existing current convergence-based computing mode, the application provides no direct current in the computing process, solves the problem of excessive current convergence in the prior art, and reduces the power consumption of the in-memory computing circuit. The voltage on the i source line connected with the i voltage reading circuit is the result of the input value of the word line minus the positive and negative product of the memory cell, without the need to set more reading structures, thereby saving the occupied area and delay overhead of the in-memory computing circuit. Due to the connection mode of the memory cell and the bit line, the source line and the complementary bit line, the in-memory computing process is essentially equivalent to the calculation of a differential signal, thereby being able to suppress the influence of non-ideal factors such as process fluctuation on the calculation accuracy.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of resistive random access memory (RRAM) technology, and more particularly to an in-memory computing circuit and method and a resistive random access memory. BACKGROUND

[0002] By effectively reducing the power consumption and delay caused by frequent access, in-memory computing technology based on new non-volatile memory is expected to greatly improve the computing efficiency and computing power, thereby providing hardware support for data-centric computing tasks represented by artificial intelligence. Among them, resistive random access memory (RRAM) has shown great potential in operating power consumption, integration density and process compatibility. New non-volatile memory represented by resistive random access memory (RRAM) has the characteristics of low power consumption, small delay, high density and high process compatibility. The non-volatile in-memory computing technology based thereon can effectively reduce the data movement between the processor and the memory and between the memory levels (non-volatile storage to memory), thereby greatly reducing the power consumption and delay caused thereby, thereby breaking through the bottleneck caused by the memory wall. The existing in-memory computing technology needs to be improved. SUMMARY

[0003] Therefore, the present application provides an in-memory computing circuit and method and a resistive random access memory, which effectively solves the technical problems existing in the prior art, reduces the power consumption of the in-memory computing circuit, saves the occupied area and delay overhead of the in-memory computing circuit, and can inhibit the influence of non-ideal factors such as process fluctuation on the computing accuracy.

[0004] To achieve the above object, the technical scheme provided by the present application is as follows:

[0005] An in-memory computing circuit, comprising: a first bit line to an Mth bit line, a first complementary bit line to an Mth complementary bit line, a first source line to an Mth source line, a first voltage reading circuit to an Mth voltage reading circuit and a first word line to an Nth word line, M and N are both integers greater than 0;

[0006] A first storage unit to an Nth storage unit is connected between the ith bit line and the ith complementary bit line, the jth storage unit comprises a first resistive random access memory (RRAM), a second resistive random access memory (RRAM), a first transistor and a second transistor, the first end of the first resistive random access memory (RRAM) is connected with the ith bit line, the second end of the first resistive random access memory (RRAM) is connected with the first end of the first transistor, the second end of the first transistor is connected with the ith source line, and the gate of the first transistor is connected with the jth word line; the first end of the second resistive random access memory (RRAM) is connected with the ith complementary bit line, the second end of the second resistive random access memory (RRAM) is connected with the first end of the second transistor, the second end of the second transistor is connected with the ith source line, and the gate of the second transistor is connected with the jth word line, i is a positive integer less than or equal to M, and j is a positive integer less than or equal to N;

[0007] Furthermore, the i-th source line is connected to the i-th voltage reading circuit; wherein, the i-th bit line is connected to a first voltage signal, the i-th complementary bit line is connected to a second voltage signal, and the i-th source line is connected to a third voltage signal.

[0008] Optionally, the first voltage signal is a high-level signal, and the voltage value is Vh.

[0009] Optionally, the second voltage signal is a low-level signal, and the voltage value is Vl.

[0010] Optionally, the voltage value of the third voltage signal is V. MID = (Vh + Vl) / 2.

[0011] Optionally, the first transistor and the second transistor are N-type transistors.

[0012] Optionally, the i-th voltage reading circuit is an i-th analog-to-digital converter.

[0013] Accordingly, the present invention also provides an in-memory computing method, employing the aforementioned in-memory computing circuit, the method comprising:

[0014] The i-th bit line, the i-th complementary bit line, and the i-th source line are pre-charged, wherein the i-th bit line is connected to a first voltage signal, the i-th complementary bit line is connected to a second voltage signal, and the i-th source line is connected to a third voltage signal.

[0015] Optionally, after the pre-charge, the following is included:

[0016] Based on the input data, multiple preset word lines from the first word line to the Nth word line are selected to be turned on, and the i-th voltage reading circuit reads the transient voltage change of the i-th source line.

[0017] Accordingly, the present invention also provides a resistive variable memory, which includes the above-described in-memory computing circuit.

[0018] Compared with the prior art, the technical solution provided by the present invention has at least the following advantages:

[0019] This invention provides an in-memory computing circuit and method, and a resistive inverter memory, comprising: a first bit line to the Mth bit line, a first complementary bit line to the Mth complementary bit line, a first source line to the Mth source line, a first voltage readout circuit to the Mth voltage readout circuit, and a first word line to the Nth word line, where M and N are both integers greater than 0; a first memory cell to the Nth memory cell are connected between the i-th bit line and the i-th complementary bit line, the j-th memory cell including a first resistive inverter, a second resistive inverter, a first transistor, and a second transistor, the first terminal of the first resistive inverter being connected to the i-th bit line, the second terminal of the first resistive inverter being connected to the first terminal of the first transistor, and the first transistor... The second terminal of the body transistor is connected to the i-th source line, and the gate of the first transistor is connected to the j-th word line; the first terminal of the second resistive inverter is connected to the i-th complementary bit line, the second terminal of the second resistive inverter is connected to the first terminal of the second transistor, the second terminal of the second transistor is connected to the i-th source line, and the gate of the second transistor is connected to the j-th word line, where i is a positive integer less than or equal to M, and j is a positive integer less than or equal to N; and the i-th source line is connected to the i-th voltage reading circuit; wherein the i-th bit line is connected to a first voltage signal, the i-th complementary bit line is connected to a second voltage signal, and the i-th source line is connected to a third voltage signal.

[0020] As can be seen from the above, in the technical solution provided by the present invention, the first transistor and the second transistor in the j-th memory cell adopt a common gate and common source connection, so that the i-th bit line, the i-th complementary bit line and the i-th source line share charge. Compared with the existing calculation method based on current convergence, the present invention provides a calculation process without DC current, which solves the problem of excessive current convergence in the prior art and reduces the power consumption of the in-memory calculation circuit.

[0021] Furthermore, in the technical solution provided by the present invention, the voltage on the i-th source line connected to the i-th voltage reading circuit is the result of subtracting the positive and negative products of the word line input value and the storage of the storage unit. This eliminates the need for additional reading structures, saving the area occupied by the in-memory calculation circuit and the delay overhead.

[0022] Furthermore, the technical solution provided by this invention, due to the connection method between the storage unit and the bit line, source line and complementary bit line, makes the in-memory calculation process essentially equivalent to the calculation of differential signals, thereby suppressing the impact of non-ideal factors such as process fluctuations on the calculation accuracy. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of an in-memory computing circuit provided in an embodiment of the present invention;

[0025] Figure 2 A simulation data graph provided for an embodiment of the present invention;

[0026] Figure 3 This is a schematic diagram of another in-memory computing circuit provided in an embodiment of the present invention;

[0027] Figure 4 This is a flowchart of an in-memory computation method provided in an embodiment of the present invention. Detailed Implementation

[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] As described in the background section, by effectively reducing the power consumption and latency caused by frequent memory accesses, in-memory computing technology based on novel non-volatile memory is expected to significantly improve computing energy efficiency and computing power, thereby providing hardware support for data-centric computing tasks such as artificial intelligence. Among these, resistive random access memory (RRAM) has shown great potential in terms of operating power consumption, integration density, and process compatibility. Novel non-volatile memories, represented by RRAM, exhibit low power consumption, low latency, high density, and high process compatibility. Based on RRAM, non-volatile in-memory computing technology can effectively reduce data movement between the processor and memory, and between memory levels (non-volatile memory to main memory), thereby significantly reducing the resulting power consumption and latency, and breaking through the bottleneck caused by the memory wall. Existing in-memory computing technologies need further improvement.

[0030] Based on this, embodiments of the present invention provide an in-memory computing circuit and method and a resistive variable memory, which effectively solves the technical problems existing in the prior art, reduces the power consumption of the in-memory computing circuit, saves the occupied area and delay overhead of the in-memory computing circuit, and can suppress the impact of non-ideal factors such as process fluctuations on the calculation accuracy.

[0031] To achieve the above objectives, the technical solutions provided by the embodiments of the present invention are as follows, in detail... Figures 1 to 4 The technical solutions provided in the embodiments of the present invention will be described in detail.

[0032] Example 1

[0033] refer to Figure 1 The diagram shown is a schematic diagram of an in-memory computing circuit provided in an embodiment of the present invention. The in-memory computing circuit includes: first bit line BL1 to the Mth bit line BLm, first complementary bit line BLB1 to the Mth complementary bit line BLBm, first source line SL1 to the Mth source line SLm, first voltage read circuit 101 to the Mth voltage read circuit 10m, and first word line WL1 to the Nth word line WLn, where M and N are both integers greater than 0.

[0034] A first memory cell to a Nth memory cell are connected between the i-th bit line BLi and the i-th complementary bit line BLBi. The j-th memory cell 20 includes a first resistive inverter 211, a second resistive inverter 221, a first transistor 212, and a second transistor 222. The first terminal of the first resistive inverter 211 is connected to the i-th bit line BLi, the second terminal of the first resistive inverter 211 is connected to the first terminal of the first transistor 212, the second terminal of the first transistor 212 is connected to the i-th source line SLi, and the gate of the first transistor 212 is connected to the j-th word line WLj. The first terminal of the second resistive inverter 221 is connected to the i-th complementary bit line BLBi, the second terminal of the second resistive inverter 221 is connected to the first terminal of the second transistor 222, the second terminal of the second transistor 222 is connected to the i-th source line SLi, and the gate of the second transistor 222 is connected to the j-th word line WLj. i is a positive integer less than or equal to M, and j is a positive integer less than or equal to N.

[0035] Furthermore, the i-th source line SLi is connected to the i-th voltage reading circuit 10i; wherein, during the pre-charging phase, the i-th bit line BLi is connected to the first voltage signal, the i-th complementary bit line BLBi is connected to the second voltage signal, and the i-th source line SLi is connected to the third voltage signal.

[0036] It is understood that in the technical solution provided by the embodiments of the present invention, the first transistor and the second transistor in the j-th memory cell adopt a common gate and common source connection, so that the i-th bit line, the i-th complementary bit line and the i-th source line share charge. Compared with the existing calculation method based on current convergence, the embodiments of the present invention provide that there is no DC current during the calculation process, which solves the problem of excessive current convergence in the prior art and reduces the power consumption of the in-memory calculation circuit.

[0037] Furthermore, in the technical solution provided by the embodiments of the present invention, the voltage on the i-th source line connected to the i-th voltage reading circuit is the result of subtracting the positive and negative products of the word line input value and the stored value of the storage unit. There is no need to set up more reading structures, which saves the area occupied by the in-memory calculation circuit and the delay overhead.

[0038] Furthermore, the technical solution provided by the embodiments of the present invention, due to the connection method between the storage unit and the bit line, source line and complementary bit line, makes the in-memory calculation process essentially equivalent to the calculation of differential signals, thereby suppressing the impact of non-ideal factors such as process fluctuations on the calculation accuracy.

[0039] The in-memory computing circuit provided in this embodiment of the invention operates in two stages: a pre-charging stage and an evaluation stage. In the pre-charging stage, all word lines are turned off, and the voltage terminals connected to the bit lines, complementary bit lines, and source lines are connected for pre-charging (after being disconnected, their respective connected capacitors maintain their potential). Specifically, a first voltage signal is input to the i-th bit line to charge it to the corresponding voltage, a second voltage signal is input to the i-th complementary bit line to charge it to the corresponding voltage, and a third voltage signal is input to the i-th source line to charge it to the corresponding voltage. The first voltage signal provided in this embodiment of the invention is a high-level signal with a voltage value of Vh. The second voltage signal is a low-level signal with a voltage value of Vl. The third voltage signal has a voltage value of Vh. MID = (Vh + Vl) / 2.

[0040] The evaluation phase then begins, disconnecting the paths between the voltage terminal and the bit lines, complementary bit lines, and source lines. Multiple preset word lines are then activated based on the input data. Subsequently, the total resistance R of all the first resistors connected in parallel between the i-th bit line and the i-th source line is calculated. LTOT The total resistance R of all second resistors connected in parallel between the i-th complementary bit line and the i-th source line. RTOT The relative magnitudes of R and R determine whether to perform transient charging or transient discharging on the i-th source line, thus determining whether the transient voltage on the i-th source line increases or decreases; for example, when R... LTOT Less than R RTOT When the charging speed of the i-th bit line to the i-th source line is faster than the discharging speed of the i-th complementary bit line to the i-th source line, the transient voltage on the i-th source line increases; while when R LTOT Greater than R RTOT At this time, the charging speed of the i-th bit line to the i-th source line is slower than the discharging speed of the i-th complementary bit line to the i-th source line, resulting in a decrease in the transient voltage on the i-th source line. At this point, the transient voltage change of the i-th source line is read by the i-th voltage reading circuit, yielding the result of subtracting the positive and negative products of the input value of the i-th word line and the stored value of the corresponding connected memory unit. The output of the i-th voltage reading circuit can be a digital signal, and this invention does not impose specific limitations on this.

[0041] It is understood that the technical solution provided in this embodiment of the invention is based on the charge sharing design of the i-th bit line, the i-th complementary bit line, and the i-th source line to obtain the in-memory computing circuit. At the i-th source line, the gates of the first transistor and the second transistor in the j-th memory cell share a j-th word line, and the second terminals of the first transistor and the second transistor are both connected to the same i-th source line. The first resistive inverter is denoted as R. L And let the second resistor be denoted as R. H The j-th storage unit can use the encoding methods shown in Table 1 when representing signed numbers:

[0042]

[0043]

[0044] Table 1

[0045] Where GND indicates that the WLj word line is off and encoded as 0, and VDD indicates that the WLj word line is on and encoded as 1. When the WLj word line is on, the encoding is represented as +1, R L In the low resistance state (LRS), R H In the high-impedance state (HRS), the transient voltage of SLi increases; when the encoding is -1, R L In the high-resistivity state, R H In the low-resistance state, the transient voltage of SLi decreases; when the encoding is 0, R L and R H Both are in a high-resistivity state, and the transient voltage of SLi remains unchanged.

[0046] Further integration Figure 2 The figure shown is a simulation diagram provided by an embodiment of the present invention. The vertical axis represents the voltage of SLi (in V), and the horizontal axis represents time (in μs). Figure 2 The simulation data uses a scenario where nine word lines are enabled. Combined with... Figure 2 As shown by the nine curves, if the R lines connected by the nine word lines... L All are in low impedance state, and the R connected to the 9 word lines H Both are in a high-resistance state, at which point R LTOT The value of R is the smallest RTOT The value of is the largest, therefore the transient voltage rise on SLi is the highest (i.e., Figure 2 (Corresponding curve for transient voltage greater than 0.8V). With R... L The number of low and medium resistance states decreases, while R H As the number of low-to-medium impedance states increases, the transient voltage on SLi decreases accordingly; furthermore, the R connected to the 9 word lines... L All are in a high-impedance state, and the R connected to the 9 word lines H When both are in low-resistance state, the transient voltage across SLi drops to its minimum, and the relevant trend is as follows:Figure 2 As indicated by the dashed arrow. Figure 2 As can be seen from the data shown, the in-memory computing circuit provided in this embodiment of the invention functions correctly.

[0047] like Figure 3 The diagram shown is a schematic of another in-memory computing circuit provided in an embodiment of the present invention. The in-memory computing circuit includes: first bit line BL1 to the Mth bit line BLm, first complementary bit line BLB1 to the Mth complementary bit line BLBm, first source line SL1 to the Mth source line SLm, first voltage read circuit 101 to the Mth voltage read circuit 10m, and first word line WL1 to the Nth word line WLn, where M and N are both integers greater than 0.

[0048] A first memory cell to a Nth memory cell are connected between the i-th bit line BLi and the i-th complementary bit line BLBi. The j-th memory cell 20 includes a first resistive inverter 211, a second resistive inverter 221, a first transistor 212, and a second transistor 222. The first terminal of the first resistive inverter 211 is connected to the i-th bit line BLi, the second terminal of the first resistive inverter 211 is connected to the first terminal of the first transistor 212, the second terminal of the first transistor 212 is connected to the i-th source line SLi, and the gate of the first transistor 212 is connected to the j-th word line WLj. The first terminal of the second resistive inverter 221 is connected to the i-th complementary bit line BLBi, the second terminal of the second resistive inverter 221 is connected to the first terminal of the second transistor 222, the second terminal of the second transistor 222 is connected to the i-th source line SLi, and the gate of the second transistor 222 is connected to the j-th word line WLj. i is a positive integer less than or equal to M, and j is a positive integer less than or equal to N.

[0049] Furthermore, the i-th source line SLi is connected to the i-th voltage reading circuit 10i; wherein, during the pre-charging phase, the i-th bit line BLi is connected to the first voltage signal, the i-th complementary bit line BLBi is connected to the second voltage signal, and the i-th source line SLi is connected to the third voltage signal.

[0050] like Figure 3 As shown, the first transistor 212 and the second transistor 222 provided by the present invention are both N-type transistors.

[0051] and such Figure 3 As shown, the i-th voltage reading circuit 10i provided in this embodiment of the invention can be an i-th analog-to-digital converter, and the invention does not impose specific limitations on it.

[0052] Example 2

[0053] Accordingly, embodiments of the present invention also provide an in-memory computing method, employing the in-memory computing circuit provided in any of the above embodiments. For example... Figure 4The diagram shows a flowchart of an in-memory computing method provided by an embodiment of the present invention, wherein the method includes:

[0054] S1. Precharge the i-th bit line, the i-th complementary bit line and the i-th source line, wherein the i-th bit line is connected to a first voltage signal, the i-th complementary bit line is connected to a second voltage signal and the i-th source line is connected to a third voltage signal.

[0055] and such Figure 4 As shown, after the pre-charging in step S1, the following steps are included:

[0056] S2. Select and enable multiple preset word lines from the first word line to the Nth word line according to the input data, and the i-th voltage reading circuit reads the transient voltage change of the i-th source line.

[0057] It is understood that in the technical solution provided by the embodiments of the present invention, the first transistor and the second transistor in the j-th memory cell adopt a common gate and common source connection, so that the i-th bit line, the i-th complementary bit line and the i-th source line share charge. Compared with the existing calculation method based on current convergence, the embodiments of the present invention provide that there is no DC current during the calculation process, which solves the problem of excessive current convergence in the prior art and reduces the power consumption of the in-memory calculation circuit.

[0058] Furthermore, in the technical solution provided by the embodiments of the present invention, the voltage on the i-th source line connected to the i-th voltage reading circuit is the result of subtracting the positive and negative products of the word line input value and the stored value of the storage unit. There is no need to set up more reading structures, which saves the area occupied by the in-memory calculation circuit and the delay overhead.

[0059] Furthermore, the technical solution provided by the embodiments of the present invention, due to the connection method between the storage unit and the bit line, source line and complementary bit line, makes the in-memory calculation process essentially equivalent to the calculation of differential signals, thereby suppressing the impact of non-ideal factors such as process fluctuations on the calculation accuracy.

[0060] Example 3

[0061] Accordingly, embodiments of the present invention also provide a resistive variable memory, wherein the resistive variable memory includes the in-memory computing circuit provided in any of the above embodiments.

[0062] This invention provides an in-memory computing circuit and method, and a resistive inverter memory, comprising: a first bit line to the Mth bit line, a first complementary bit line to the Mth complementary bit line, a first source line to the Mth source line, a first voltage readout circuit to the Mth voltage readout circuit, and a first word line to the Nth word line, where M and N are both integers greater than 0; a first memory cell to the Nth memory cell are connected between the i-th bit line and the i-th complementary bit line, the j-th memory cell including a first resistive inverter, a second resistive inverter, a first transistor, and a second transistor, the first terminal of the first resistive inverter being connected to the i-th bit line, and the second terminal of the first resistive inverter being connected to the first terminal of the first transistor, wherein the j-th memory cell includes a first resistive inverter, a second resistive inverter, a first transistor, and a second transistor. The second terminal of a transistor is connected to the i-th source line, and the gate of the first transistor is connected to the j-th word line; the first terminal of the second resistive inverter is connected to the i-th complementary bit line, the second terminal of the second resistive inverter is connected to the first terminal of the second transistor, the second terminal of the second transistor is connected to the i-th source line, and the gate of the second transistor is connected to the j-th word line, where i is a positive integer less than or equal to M, and j is a positive integer less than or equal to N; and the i-th source line is connected to the i-th voltage readout circuit; wherein the i-th bit line is connected to a first voltage signal, the i-th complementary bit line is connected to a second voltage signal, and the i-th source line is connected to a third voltage signal.

[0063] As can be seen from the above, in the technical solution provided by the embodiments of the present invention, the first transistor and the second transistor in the j-th memory cell adopt a common gate and common source connection, so that the i-th bit line, the i-th complementary bit line and the i-th source line share charge. Compared with the existing calculation method based on current convergence, the embodiments of the present invention provide that there is no DC current during the calculation process, which solves the problem of excessive current convergence in the prior art and reduces the power consumption of the in-memory calculation circuit.

[0064] Furthermore, in the technical solution provided by the embodiments of the present invention, the voltage on the i-th source line connected to the i-th voltage reading circuit is the result of subtracting the positive and negative products of the word line input value and the stored value of the storage unit. There is no need to set up more reading structures, which saves the area occupied by the in-memory calculation circuit and the delay overhead.

[0065] Furthermore, the technical solution provided by the embodiments of the present invention, due to the connection method between the storage unit and the bit line, source line and complementary bit line, makes the in-memory calculation process essentially equivalent to the calculation of differential signals, thereby suppressing the impact of non-ideal factors such as process fluctuations on the calculation accuracy.

[0066] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An in-memory computing circuit, characterized in that, include: The first bit line to the Mth bit line, the first complementary bit line to the Mth complementary bit line, the first source line to the Mth source line, the first voltage readout circuit to the Mth voltage readout circuit, and the first word line to the Nth word line, where M and N are both integers greater than 0; A first memory cell to a Nth memory cell are connected between the i-th bit line and the i-th complementary bit line. The j-th memory cell includes a first resistive inverter, a second resistive inverter, a first transistor, and a second transistor. The first terminal of the first resistive inverter is connected to the i-th bit line, the second terminal of the first resistive inverter is connected to the first terminal of the first transistor, the second terminal of the first transistor is connected to the i-th source line, and the gate of the first transistor is connected to the j-th word line. The first terminal of the second resistive inverter is connected to the i-th complementary bit line, the second terminal of the second resistive inverter is connected to the first terminal of the second transistor, the second terminal of the second transistor is connected to the i-th source line, and the gate of the second transistor is connected to the j-th word line. i is a positive integer less than or equal to M, and j is a positive integer less than or equal to N. Furthermore, the i-th source line is connected to the i-th voltage reading circuit; wherein, during the pre-charging phase, the i-th bit line is connected to a first voltage signal, the i-th complementary bit line is connected to a second voltage signal, and the i-th source line is connected to a third voltage signal; During the evaluation phase, multiple preset word lines are activated according to the selection of the first word line to the Nth word line, and the i-th voltage reading circuit reads the transient voltage change of the i-th source line.

2. The in-memory computing circuit according to claim 1, characterized in that, The first voltage signal is a high-level signal, and the voltage value is Vh.

3. The in-memory computing circuit according to claim 2, characterized in that, The second voltage signal is a low-level signal, and the voltage value is Vl.

4. The in-memory computing circuit according to claim 3, characterized in that, The voltage value of the third voltage signal is V MID = (Vh + Vl) / 2.

5. The in-memory computing circuit according to claim 1, characterized in that, The first transistor and the second transistor are N-type transistors.

6. The in-memory computing circuit according to claim 1, characterized in that, The i-th voltage reading circuit is the i-th analog-to-digital converter.

7. An in-memory computation method, characterized in that, The method using the in-memory computing circuit according to any one of claims 1-6 includes: The i-th bit line, the i-th complementary bit line, and the i-th source line are pre-charged, wherein the i-th bit line is connected to a first voltage signal, the i-th complementary bit line is connected to a second voltage signal, and the i-th source line is connected to a third voltage signal. After the pre-charge, the following is included: Based on the input data, multiple preset word lines from the first word line to the Nth word line are selected to be turned on, and the i-th voltage reading circuit reads the transient voltage change of the i-th source line.

8. A resistive random access memory, characterized in that, The resistive variable memory includes the in-memory computing circuit according to any one of claims 1-6.

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