Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device

Abstract

The present application aims at suppressing the occurrence of insulation breakdown when a high dV / dt is applied, even if a process defect occurs, in a silicon carbide semiconductor device. A MOSFET (101) has a gate electrode (33) and an etching stopper layer (51) formed over a field insulation film (32) of a gate pad region (13), and an interlayer insulation film (34) formed over the gate electrode (33) and over the etching stopper layer (51). The etching stopper layer (51) is composed of a material having a selectivity of greater than or equal to 5.0 with respect to etching of the interlayer insulation film (34) and the field insulation film (32), and is provided at least at the gate pad region (13) at a position farthest from a well contact hole (HW1) of a gate lower well contact region (12).

Description

Technical Field

[0001] This invention relates to silicon carbide semiconductor devices. Background Technology

[0002] In vertically oriented semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) with gate structures, a relatively wide area is ensured because terminals are connected to the gate pad region via wire bonding or the like. During reverse bias, the displacement current below the gate pad region is depleted by flowing to the gate lower well contact located outside the gate pad region, and the withstand voltage is maintained by the PN junction within the silicon carbide semiconductor. However, during the high-speed operation (applying high dV / dt) required by silicon carbide semiconductor devices, a high electric field is applied to the insulating film because the voltage is applied before depletion is complete.

[0003] Patent Document 1 discloses a structure in which a capacitor consisting of a thin oxide film and a conductor is disposed on the semiconductor surface below the gate pad region. This reduces the electric field applied to the insulating film when a high dV / dt is applied.

[0004] Patent Document 1: International Publication No. 2018-038133

[0005] In the case of existing semiconductor devices including the structure disclosed in Patent Document 1, if formed without defects, a film thickness is formed that will not cause insulation failure when high dV / dt is applied. However, if defects in the insulating film, such as the incorporation of foreign matter, cause thinning of the insulating film, there is a risk of insulation failure when high dV / dt is applied. Furthermore, in order to eliminate semiconductor devices with thinned insulating films through electrical testing in subsequent processes, a high dV / dt test is required, thus posing a risk of insulation failure. Summary of the Invention

[0006] The present invention was proposed to solve the above-mentioned problems, and its purpose is to suppress the occurrence of insulation breakdown when high dV / dt is applied in silicon carbide semiconductor devices, even if process defects occur.

[0007] The silicon carbide semiconductor device of the present invention is divided into multiple regions when viewed from above. These multiple regions include a device region forming a switching element, a gate pad region forming a gate pad, and a gate-below-well contact region between the device region and the gate pad region. The silicon carbide semiconductor device has a semiconductor layer made of silicon carbide, the semiconductor layer having: a drift layer of a first conductivity type; and a well region formed on the surface of the drift layer across the gate pad region and the gate-below-well contact region. The semiconductor layer also has: a field insulating film formed on the upper surface of the semiconductor layer at the gate pad region; a gate electrode; and an etch barrier layer formed at the field insulating film of the gate pad region. The field insulating film is formed on the gate electrode and the etch barrier layer. A surface electrode is formed on the interlayer insulating film at the gate lower well contact region and contacts the well region via a well contact hole through which the field insulating film and the interlayer insulating film pass. A gate pad is formed on the interlayer insulating film at the gate pad region and contacts the gate electrode via a gate contact hole through which the interlayer insulating film passes. The etch barrier layer is composed of a material with a selectivity greater than or equal to 5.0 relative to the etching of the interlayer insulating film and the field insulating film. The etch barrier layer is disposed at least at the gate pad region at the position furthest from the well contact hole of the gate lower well contact region.

[0008] The effects of the invention

[0009] According to the silicon carbide semiconductor device of the present invention, even if process defects occur, the occurrence of insulation breakdown under high dV / dt conditions is suppressed. Attached Figure Description

[0010] Figure 1 This is a top view of the first configuration of the MOSFET in Embodiment 1.

[0011] Figure 2 This is a top view of the second configuration of the MOSFET in Embodiment 1.

[0012] Figure 3 This is a cross-sectional view of the MOSFET in Embodiment 1.

[0013] Figure 4 This is a graph showing the simulation results of the potential distribution generated when a high dV / dt is applied at the gate pad region of the MOSFET of the first type.

[0014] Figure 5 This is a graph showing the simulation results of the potential distribution generated when a high dV / dt is applied at the gate pad region of the MOSFET in pattern 2.

[0015] Figure 6 This is a cross-sectional view of a MOSFET in proportion.

[0016] Figure 7 This is a cross-sectional view showing the manufacturing process of the MOSFET in Embodiment 1.

[0017] Figure 8 This is a cross-sectional view showing the manufacturing process of the MOSFET in Embodiment 1.

[0018] Figure 9 This is a cross-sectional view showing the manufacturing process of the MOSFET in Embodiment 1.

[0019] Figure 10 This is a cross-sectional view showing the manufacturing process of the MOSFET in Embodiment 1.

[0020] Figure 11 This is a cross-sectional view showing the manufacturing process of the MOSFET in Embodiment 1.

[0021] Figure 12 This is a cross-sectional view showing the manufacturing process of the MOSFET in Embodiment 1.

[0022] Figure 13 This is a cross-sectional view of a MOSFET in a modified embodiment of implementation 1.

[0023] Figure 14 This is a top view of the first configuration of the MOSFET in Embodiment 2.

[0024] Figure 15 This is a top view of the second style of the MOSFET in Embodiment 2.

[0025] Figure 16 This is a cross-sectional view of the MOSFET in Embodiment 2.

[0026] Figure 17 This is a cross-sectional view of the MOSFET in a modified embodiment 2.

[0027] Figure 18 This is a cross-sectional view of a MOSFET with defects in both the interlayer insulating film and the field insulating film, as shown in a modified example of Embodiment 2.

[0028] Figure 19 It means and Figure 18 Top view of the corresponding etch barrier layer and interlayer insulating film.

[0029] Figure 20 This is a cross-sectional view showing the state in which defects have been generated in the interlayer insulating film and the field insulating film, respectively, for the MOSFET of Embodiment 2.

[0030] Figure 21 It means and Figure 20 Top view of the corresponding etch barrier layer and interlayer insulating film.

[0031] Figure 22 This is a cross-sectional view showing the device region, gate underwell contact region, and gate pad region of the MOSFET in Embodiment 3.

[0032] Figure 23 This is a cross-sectional view showing the device region of the MOSFET, the temperature sensing pad well contact region, the temperature sensing pad region, and the temperature sensing diode region of Embodiment 3.

[0033] Figure 24 This is a cross-sectional view showing the manufacturing process of the MOSFET device region, gate underwell contact region, gate pad region, and temperature sensing diode region in Embodiment 3.

[0034] Figure 25 This is a cross-sectional view showing the manufacturing process of the MOSFET device region, gate underwell contact region, gate pad region, and temperature sensing diode region in Embodiment 3.

[0035] Figure 26 This is a cross-sectional view showing the manufacturing process of the MOSFET device region, gate underwell contact region, gate pad region, and temperature sensing diode region in Embodiment 3.

[0036] Figure 27 This is a cross-sectional view of the MOSFET in a modified embodiment 3.

[0037] Figure 28 This is a top view of the etch barrier layer of the MOSFET in a modified example of Embodiment 3.

[0038] Figure 29 This is a top view of the etch barrier layer of the MOSFET in a modified example of Embodiment 3.

[0039] Figure 30 This is a top view of the MOSFET in embodiment 4.

[0040] Figure 31 This is a cross-sectional view showing the device region, gate underwell contact region, and gate pad region of the MOSFET in Embodiment 4.

[0041] Figure 32 This is a cross-sectional view showing the device region, end well contact region, gate wiring region, and end region of the MOSFET in Embodiment 4.

[0042] Figure 33 This is a cross-sectional view showing the formation of cracks in the etch barrier layer that forms on the step.

[0043] Figure 34 This is a top view of the MOSFET in embodiment 5. Detailed implementation mode

[0044] In the following description, as the conductivity type of the semiconductor, the n-type is set as the first conductivity type and the p-type is set as the second conductivity type, but these conductivity types can also be reversed. In addition, n-type means that the n-type impurity concentration is lower than that of n-type, and N + type means that the n-type impurity concentration is higher than that of n-type. Similarly, p-type means that the p-type impurity concentration is lower than that of p-type, and P + type means that the p-type impurity concentration is higher than that of p-type.

[0045] <A. Embodiment 1>

[0046] <A-1. Structure>

[0047] Figure 1 is a top view of the first style of the silicon carbide semiconductor device, i.e., MOSFET 101, in Embodiment 1. Figure 2 is a top view of the second style of MOSFET 101. Figure 3 is along Figure 1 the A-A line of Figure 2 or a cross-sectional view of MOSFET 101 along the B-B line of Figure 1 and Figure 2 In, the dashed line 3 indicates the position of the well contact hole HW1, and the dashed line 4 indicates the position of the gate contact hole HG. In addition, the point P represents the point in the gate pad region 13 that is the farthest from the gate under well contact region 12, that is, the well contact hole HW1.

[0048] MOSFET 101 has a source electrode 1 and a gate pad 2. The gate pad 2 can be arranged at the center of one side of the chip as shown in Figure 1 or at the corner of the chip as shown in Figure 2 . The materials of the source electrode 1 and the gate pad 2 are, for example, Al. A protective film for the semiconductor device, such as polyimide, is formed between the end portions of the chip and the electrodes.

[0049] As shown in [[ID=4)] Figure 3 , MOSFET 101 has an n-type drift layer 22. The drift layer 22 is formed by epitaxial growth on an n-type SiC substrate, but the illustration of the SiC substrate is omitted in Figure 3 . The impurity concentration of the drift layer 22 is lower than that of the SiC substrate, for example, greater than or equal to 1×10 13 cm -3 ]'and less than or equal to 1×10<( 18 cm -3 . The thickness of the drift layer 22 is, for example, greater than or equal to 4 μm and less than or equal to 200 μm. A drain electrode is provided on the lower surface of the SiC substrate by sputtering or plating (in Figure 3(Not shown in the figure) is used as the back electrode. During the formation of the back electrode, the SiC substrate is, for example, polished to achieve a desired film thickness of 100 μm or greater and 300 μm or less. Then, after depositing Ni or Ti on the lower surface of the SiC substrate, the deposited Ni or Ti is silicided by annealing at a temperature of 800°C or greater and 1000°C. This results in a low-resistance contact. Finally, the material required for substrate bonding (e.g., Ni, Au, etc. if solder bonding) is deposited on the Ni or Ti.

[0050] Figure 3 The cross-sectional structure of the MOSFET 101 shown is divided into a device region 11, a gate lower well contact region 12, and a gate pad region 13 when viewed from above. The region forming the gate pad 2 is designated as the gate pad region 13. The region adjacent to the gate pad region 13 in the region forming the source electrode 1 is designated as the gate lower well contact region 12, and the other regions are designated as the device region 11.

[0051] On the surface of drift layer 22, a p-type first well region 23 is formed in device region 11, and a second well region 26 is formed in gate lower well contact region 12 and gate pad region 13. The second well region 26 has: a p-type well body region 26L, which is formed in gate lower well contact region 12 and gate pad region 13 on the surface of drift layer 22; and a p-type well body region 26L. + A type of well contact region 26H is formed on the surface of the well body region 26L, which is located below the gate well contact region 12 and the gate pad region 13. The well contact region 26H is also referred to as the well low resistance layer.

[0052] An n-type source region 24 is provided on the surface of the first well region 23. Furthermore, an n-type source region 24 is provided that extends from the surface of the source region 24 through the source region 24 to the first well region 23. + Type of trap contact area 25.

[0053] A gate insulating film 31 is disposed on the first well region 23 and its periphery, and on the end of the second well region 26 near the device region 11. For example... Figure 3 As shown, the gate insulating film 31 can also be disposed on the drift layer 22 between the first well region 23 and the second well region 26. Alternatively, the gate insulating film 31 can also be disposed on the source region 24. The gate insulating film 31 is formed, for example, by thermal oxidation or deposition. Thermal oxidation is carried out in an oxidizing gas environment such as a humid environment, an oxygen (O2) environment, or a nitrogen oxide (NO or N2O) environment. Deposition can also be performed using a high dielectric constant material, the so-called "high-k material".

[0054] A field insulating film 32 is disposed in the area on the upper surface of the second well region 26 where the gate insulating film 31 is not disposed. The field insulating film 32 is disposed in the gate pad region 13 and the gate lower well contact region 12. The field insulating film 32 is thicker than the gate insulating film 31. The field insulating film 32 is formed in the same manner as the gate insulating film 31, for example, by thermal oxidation or deposition. The field insulating film 32 is, for example, made of TEOS (Tetraethyl orthosilicate).

[0055] A gate electrode 33 is disposed on the gate insulating film 31 and the field insulating film 32. The surface layer of the first well region 23, sandwiched between the source region 24 and the drift layer 22, is a channel region. The gate electrode 33 has a portion disposed on the channel region with the gate insulating film 31 in between. The gate electrode 33 is formed, for example, by film deposition obtained by CVD and patterning using photolithography. The film deposition uses, for example, polysilicon material. Preferably, the polysilicon used has low resistance by containing P atoms or B atoms. Impurities such as P or B can be introduced during the polysilicon film deposition or after film deposition by ion implantation or the like. The gate electrode 33 can also be a multi-region film composed of polysilicon and metal, a multi-region film composed of polysilicon and metal silicide, or a metal film. Preferably, the outermost peripheral end face of the gate electrode 33 is disposed on the field insulating film 32 rather than on the gate insulating film 31. Therefore, it is possible to prevent the quality deterioration caused by excessive etching in the dry etching process used for patterning the gate electrode 33, which would result in etching of the gate insulating film 31 near the outermost peripheral end face of the gate electrode 33.

[0056] An etch stop layer 51 is disposed on the field insulating film 32 in addition to the gate electrode 33. An interlayer insulating film 34 is disposed on the gate electrode 33 and the etch stop layer 51 in a manner that covers them. At device region 11, a source contact hole HS is formed on the interlayer insulating film 34. The source contact hole HS overlaps with the opening of the gate insulating film 31 and is located on the source region 24 and the well contact region 25. Therefore, the source electrode 1 contacts the source region 24 and the well contact region 25 through the source contact hole HS. At the gate lower well contact region 12, a well contact hole HW1 (first well contact hole) is formed on the interlayer insulating film 34. The well contact hole HW1 penetrates the field insulating film 32 to reach the well contact region 26H. Therefore, the source electrode 1 contacts the well contact region 26H through the well contact hole HW1. At the gate pad region 13, a gate contact hole HG is formed on the interlayer insulating film 34. The gate pad 2 contacts the gate electrode 33 through the gate contact hole HG. The interlayer insulating film 34 is composed of, for example, an oxide or silicon dioxide film. The interlayer insulating film 34 is formed by deposition methods such as CVD. The contact holes are formed using photolithography and dry etching techniques.

[0057] The field insulating film 32 and the interlayer insulating film 34 are sufficiently thick compared to the gate insulating film 31. Even as individual film units, they have sufficient thickness in the region below the gate pads to withstand the electric field applied during reverse bias under DC operation and high dV / dt (AC) operation. Preferably, the field insulating film 32 and the interlayer insulating film 34 have high insulating properties, such as TEOS oxide films, with a thickness of ≥8MV / cm and ≤10MV / cm, and can be deposited by CVD to a thickness of ≥0.8μm.

[0058] The gate pad 2 is connected to the gate electrode 33 through the gate contact hole HG of the interlayer insulating film 34. The interface between the gate electrode 33 and the gate pad 2 at the gate contact hole HG of the interlayer insulating film 34 can be silicided. In addition to the gate pad 2, a gate wiring portion 11w extending from the gate pad 2 may also be provided. The gate wiring portion 11w is connected to the gate electrode 33 through the gate contact hole HG of the interlayer insulating film 34. The gate wiring portion 11w may also surround the source electrode 1 in a planar layout. The gate pad 2 and the gate wiring portion 11w are electrically connected to the gate electrode 33 of the unit cell, thereby applying a gate voltage supplied from an external control circuit to the gate electrode 33. The gate wiring portion 11w is formed of doped polycrystalline Si or the like.

[0059] Source electrode 1 is connected to source region 24 and well contact region 25 via source contact hole HS. Additionally, source electrode 1 is connected to second well region 26 via well contact hole HW1. Typically, source electrode 1 is positioned in the center of a planar layout. Source electrode 1 includes an ohmic electrode. The ohmic electrode contacts source region 24 and well contact region 25 at source contact hole HS, and contacts second well region 26 at well contact hole HW1.

[0060] In the gate pad region 13, an etch stop layer 51 is provided in at least a portion of the area between the interlayer insulating film 34 and the field insulating film 32. The etch stop layer 51 is made of a material such as polysilicon or silicon nitride (SiN) with a high selectivity (hereinafter referred to as "etch selectivity") relative to the etching of the interlayer insulating film 34 and the field insulating film 32. When the interlayer insulating film 34 or the field insulating film 32 is used as the film to be etched and the etch stop layer 51 is used as the mask, the etch selectivity is obtained by dividing the etching rate of the interlayer insulating film 34 or the field insulating film 32 by the etching rate of the etch stop layer 51. Preferably, the etch selectivity is at least greater than or equal to 5.0. In the etching process of the interlayer insulating film 34 or the field insulating film 32, the thickness of the etch stop layer 51 is preferably greater than or equal to {(thickness of the interlayer insulating film 34 or the field insulating film 32) / etch selectivity}. If the etch selectivity is small, the thickness of the etch stop layer 51 needs to be large. As a result, the step between the upper surface of the gate electrode 33 exposed in the gate contact hole HG and the upper surface of the interlayer insulating film 34 becomes larger, making it difficult to embed the gate pad 2 into the gate contact hole HG.

[0061] An etch barrier layer 51 is disposed in the gate pad region 13 at the point P furthest from the gate lower well contact region 12, i.e., the well contact hole HW1. By providing the etch barrier layer 51, even if defects such as foreign matter are generated during the manufacturing process of the MOSFET 101, or if at least any one of the interlayer insulating film 34 and field insulating film 32 is damaged, an insulating film with a thickness that can withstand high dV / dt can be retained, and the occurrence of insulation breakdown under high dV / dt can be suppressed. The reasons for this are explained below.

[0062] <a 2.蚀刻阻挡层>

[0063] Figure 4 This is a simulation result showing the potential distribution generated at the gate pad region 13 of the MOSFET 101 of the first type when a high dV / dt is applied. Additionally, Figure 5 The simulation results show the potential distribution generated at the gate pad region 13 of the MOSFET 101 of the second type when a high dV / dt is applied. If the dV / dt application condition is set to 10kV / μs and the size of the gate pad region 13 is set to 1000μm square, the maximum potential generated in the gate pad region 13 is greater than or equal to 200V and less than or equal to 300V, which is greater than the typical gate operating voltage of about 15V. Moreover, the highest potential is at point P in the gate pad region 13, which is farthest from the gate lower well contact region 12. Therefore, it is effective to place the etch barrier layer 51 at the high potential location including point P.

[0064] If the etch stop layer 51 is a non-conductive layer such as silicon nitride (SiN), at the field insulating film 32 and the interlayer insulating film 34 formed by different processes respectively, as long as there is no defect at the overlapping part when viewed from above, the insulation breakdown when applying a high dV / dt can be suppressed.

[0065] Even the etch stop layer 51 alone can have a sufficient film thickness with insulation tolerance for the electric field applied during reverse bias in the operation at high dV / dt (AC).

[0066] In addition, the etch stop layer 51 can also have conductivity, but in the gate pad region 13, it is preferable that the film thickness of one of the interlayer insulating film 34 or the field insulating film 32 is sufficiently larger than that of the other and the gate insulating film.

[0067] Figure 6 The cross-sectional structure of the MOSFET 100 without an etch stop layer is shown as a comparative example. Except for not having the etch stop layer 51, the MOSFET 100 has the same structure as the MOSFET 101. During reverse bias, under the gate pad region 13, holes 28 move from the p-type well body region 26L to the P + type well contact region 26H, and electrons 29 move downward from the interface of the n-type drift layer 22 with the well body region 26L. Moreover, at the well contact region 26H, the displacement current Id flows from the gate pad region 13 toward the gate under well contact region 12, whereby the pn junction formed by the second well region 26 and the drift layer 22 is depleted and the breakdown voltage is maintained. However, during the high-speed operation (applying a high dV / dt) required for the silicon carbide semiconductor device, since a voltage is applied before the pn junction is completely depleted, a high electric field is applied to the field insulating film 32 and the interlayer insulating film 34. In Figure 6 it shows a state where the field insulating film 32 and the interlayer insulating film 34 are defective and the insulating film becomes thinner at the region 64. If such a high electric field is applied to such a part, insulation breakdown will occur.

[0068] <A-3. Manufacturing process>[[ID=​​​​​​Then, a p-type first well region 23 is formed on the surface of the drift layer 22 at device region 11, and a p-type well body region 26L is formed on the surface of the drift layer 22 at gate lower well contact region 12 and gate pad region 13. Additionally, an n-type source region 24 and an N-type source region 25 are formed on the surface of the first well region 23. + The trap contact region 25 of the type forms a P on the surface of the trap body region 26L. + Type of trap contact area 26H.

[0071] The first well region 23, source region 24, well contact region 25, well body region 26L, and well contact region 26H are formed by selective ion implantation using an implantation mask (not shown) for the required number of times. For example, a resist mask or an oxide mask can be used as the implantation mask. During ion implantation, the semiconductor substrate can be inactively heated, or it can be heated to approximately 200°C or higher and less than or equal to 800°C. For ion implantation, Al (aluminum) or B (boron) is preferred for p-type implantation, and N (nitrogen) or P (phosphorus) is preferred for n-type implantation. Thus, a... Figure 7 The cross-sectional structure shown.

[0072] Next, a field insulating film 32 is formed in the gate lower well contact region 12 and the gate pad region 13. The field insulating film 32 is patterned, for example, after being formed over the entire surface of the semiconductor layer, so that it remains only in the desired area. Then, a gate insulating film 31 is formed on the upper surface of the semiconductor layer where the field insulating film 32 is not formed. Thus, a... Figure 8 The cross-sectional structure shown.

[0073] Next, a gate electrode 33 is formed and patterned in device region 11, gate lower well contact region 12, and gate pad region 13. This yields... Figure 9 The cross-sectional structure shown.

[0074] Next, an etch stop layer 51 is formed and patterned in the gate pad region 13. The etch stop layer 51 is formed in such a way that it contacts the end of the gate electrode 33 formed in the gate pad region 13 on the opposite side of the gate lower well contact region 12. Furthermore, an interlayer insulating film 34 is formed and patterned in the device region 11, the gate lower well contact region 12, and the gate pad region 13. Thus, the etch stop layer 51 is sandwiched between the field insulating film 32 and the interlayer insulating film 34 in the gate pad region 13. In this way, a... Figure 10 The cross-sectional structure shown.

[0075] Thereafter, a source contact hole HS that penetrates the interlayer insulating film 34 and the gate insulating film 31 and reaches the source region 24 and the well contact region 25 is formed in the device region 11. In addition, a well contact hole HW1 that penetrates the interlayer insulating film 34 and the field insulating film 32 and reaches the well contact region 26H is formed in the under-gate well contact region 12. In addition, a gate contact hole HG that penetrates the interlayer insulating film 34 and reaches the gate electrode 33 is formed in the gate pad region 13. Thereafter, a source electrode 1 is formed as a surface electrode in the device region 11 and the under-gate well contact region 12, and a gate pad 2 is formed in the gate pad region 13. The source electrode 1 contacts the source region 24 and the well contact region 25 through the source contact hole HS, and contacts the well contact region 26H through the well contact hole HW1. The gate pad 2 contacts the gate electrode 33 through the gate contact hole HG. Thus, Figure 11 the cross-sectional structure shown is obtained.

[0076] Next, a protective film 41 such as polyimide is formed on the surface electrode. In addition, a drain electrode 7 is formed as a back electrode on the back side of the SiC substrate 21. Thus, Figure 12 the MOSFET 101 with the cross-sectional structure shown is completed.

[0077] <A-4. Modified Example> <00002​​​​​​​​​​​​​​​​​​​​​In embodiment 1, the MOSFET 101, when viewed from above, is divided into multiple regions, including a device region 11 forming a switching element, a gate pad region 13 forming a gate pad 2, and a gate lower well contact region 12 between the device region 11 and the gate pad region 13. The MOSFET 101 has a semiconductor layer made of silicon carbide. This semiconductor layer has an n-type drift layer 22 and a second well region 26 formed on the surface of the drift layer 22 across the gate pad region 13 and the gate lower well contact region 12. MOSFET 101 includes: a field insulating film 32 formed on the upper surface of a semiconductor layer in a gate pad region 13; a gate electrode 33 and an etch barrier layer 51 formed on the field insulating film 32 in the gate pad region 13; an interlayer insulating film 34 formed on the gate electrode 33 and the etch barrier layer 51; a surface electrode, i.e., a source electrode 1, formed on the interlayer insulating film 34 in a gate lower well contact region 12 and contacting a second well region 26 via a well contact hole HW1 through which the field insulating film 32 and the interlayer insulating film 34 pass; and a gate pad 2 formed on the interlayer insulating film 34 in the gate pad region 13 and contacting the gate electrode 33 via a gate contact hole HG through which the interlayer insulating film 34 passes. The etch barrier layer 51 is made of a material with a selectivity greater than or equal to 5.0 relative to the etching of the interlayer insulating film 34 and the field insulating film 32. This etch barrier layer 51 is disposed at least in the gate pad region 13 at the position furthest from the well contact hole HW1 of the gate lower well contact region 12. According to this structure, even if at least either the field insulating film 32 or the interlayer insulating film 34 is damaged in the region where the highest electric field is applied, the insulation performance can be maintained by the etch barrier layer 51. As a result, insulation breakdown under high dV / dt conditions can be suppressed.

[0082] Furthermore, in the case of the MOSFET 101A in Embodiment 1, the etch barrier layer 51A is made of the same material as the gate electrode 33. Therefore, the etch barrier layer 51A can be formed simultaneously with the gate electrode 33.

[0083] The manufacturing method of the silicon carbide semiconductor device of Embodiment 1 is as follows: a drift layer 22 made of n-type silicon carbide is formed, and a second well region 26 is formed on the surface layer of the drift layer 22 so as to straddle the gate pad region 13 and the under-gate well contact region 12. At the gate pad region 13, a field insulating film 32 is formed on the drift layer 22 and the second well region 26. On the field insulating film 32 in the gate pad region 13, a gate electrode 33 and an etch stop layer 51 are formed. On the gate electrode 33 and the etch stop layer 51, an interlayer insulating film 34 is formed. At the under-gate well contact region 12, a source electrode 1, which is a surface electrode that contacts the second well region 26 through a well contact hole HW1 penetrating the field insulating film 32 and the interlayer insulating film 34, is formed on the interlayer insulating film 34. At the gate pad region 13, a gate pad 2 that contacts the gate electrode 33 through a gate contact hole HG penetrating the interlayer insulating film 34 is formed on the interlayer insulating film 34. The etch stop layer 51 is made of a material with a selectivity ratio of 5.0 or greater with respect to the etching of the interlayer insulating film 34 and the field insulating film 32, and the etch stop layer 51 is formed at least at the gate pad region 13 at the position farthest from the well contact hole HW1 of the under-gate well contact region 12. Therefore, according to the manufacturing method of the silicon carbide semiconductor device of Embodiment 1, in the region of the silicon carbide semiconductor device where the highest electric field is applied, even if at least any one of the field insulating film 32 and the interlayer insulating film 34 is damaged, the insulating performance can be maintained by the etch stop layer 51. As a result, the insulation breakdown when a high dV / dt is applied can be suppressed.

[0084] <B. Embodiment 2>

[0085] <B-1. Structure>

[0086] Figure 14 It is a top view of the first pattern of the MOSFET 102, which is the silicon carbide semiconductor device of Embodiment 2. Figure 15 It is a top view of the second pattern of the MOSFET 102. Figure 16 It is along Figure 14 the C-C line of Figure 15 or Figure 14 and Figure 15 the D-D line of the cross-sectional view of the MOSFET 102. In

[0087] As Figure 16As shown, the difference between MOSFET 102 and MOSFET 101 is that etch stop layer 52 is provided instead of etch stop layer 51. Etch stop layer 52 is made of low-resistance polysilicon, similar to etch stop layer 51A in the first variation of Embodiment 1. However, etch stop layer 52 is separated from gate electrode 33 by interlayer insulating film 34. The interlayer insulating film 34 existing between etch stop layer 52 and gate electrode 33 is also referred to as separation region 60.

[0088] A gate contact hole HG is provided at least a portion of the outer periphery of the gate pad 2 in the gate pad region 13. A gate lower well contact hole HW1 is provided along the outer periphery of the gate pad 2 in the gate lower well contact region 12. The gate lower well contact region 12 is provided at least in the region of the gate lower well contact region 12 opposite to the gate contact hole HG. A separation region 60 between the etch stop layer 52 and the gate electrode 33 is disposed near the gate contact hole HG. Figure 14 and Figure 15 In the diagram, solid line D3 indicates the location of separation region 60. By providing separation region 60 between etch barrier layer 52 and gate electrode 33, insulation breakdown can be suppressed even if the interlayer insulating film 34 is defective.

[0089] The etch barrier layer 52 is preferably non-conductive. However, the etch barrier layer 52 can also be conductive, and insulation breakdown can be suppressed by setting the thickness of one of the interlayer insulating film 34 or the field insulating film 32 to be sufficiently larger than the thickness of the other or the gate insulating film below the gate pad region 13.

[0090] exist Figure 14 In the example, the gate contact hole HG is provided along three of the four sides of the rectangular gate pad region 13. Additionally, in Figure 15 In the example, the gate contact hole HG is provided along two of the four sides of the rectangular gate pad region 13. For example... Figure 4 and Figure 5As shown, the potential generated in the gate pad region 13 when a high dV / dt is applied becomes smaller as it gets closer to the under-gate well contact region 12. Therefore, the gate contact hole HG is disposed near the outer periphery of the gate pad 2, the well contact hole HW1 is disposed near the gate contact hole HG, and the etch stop layer 52 and the separation region 60 of the gate electrode 33 are disposed near the gate contact hole HG. Thus, even if at least any one of the field insulating film 32 or the interlayer insulating film 34 has a defect in the separation region 60, since the potential generated in the separation region 60 when a high dV / dt is applied becomes smaller, it is possible to suppress dielectric breakdown when a high dV / dt is applied. In order to prevent dielectric breakdown in the separation region 60 even if at least any one of the field insulating film 32 or the interlayer insulating film 34 has a defect, it is preferable that the width of the separation region 60 is greater than or equal to the thickness of the interlayer insulating film 34.

[0091] At the edge of the end of the gate pad region 13 where the gate contact hole HG is not disposed, the separation region 60 does not need to be disposed within the gate pad region 13. For example, it is preferably disposed to overlap the boundary between the gate pad region 13 and the under-gate well contact region 12. Thus, even if at least any one of the field insulating film 32 or the interlayer insulating film 34 has a defect, it is possible to suppress dielectric breakdown between the surface electrodes, that is, between the source electrode 1 and the gate pad 2.

[0092] <B-2. Modified Example>

[0093] Figure 17 It is a cross-sectional view of the MOSFET 102A which is a modified example of Embodiment 2. The top view of the MOSFET 102A is as Figure 14 or Figure 15 shown. Figure 17 It shows a cross-sectional structure along Figure 14 the C-C line of Figure 15 or the D-D line of

[0094] The difference between the MOSFET 102A and the MOSFET 102 is that it has an etch stop layer 52A instead of the etch stop layer 52. The difference between the etch stop layer 52A and the etch stop layer 52 is that it is divided into a plurality of regions 52A1, 52A2, 52A3, 52A4 by the interlayer insulating film 34. In other words, the etch stop layer 52A is divided into a plurality of regions 52A1, 52A2, 52A3, 52A by the division region 65 formed by the interlayer insulating film 34.

[0095] The advantages of dividing the etch stop layer 52A into a plurality of regions 52A1, 52A2, 52A3, 52A4 will be described below.

[0096] Figure 18It is a cross-sectional view of the MOSFET 102A showing a state where defects 61 and 62 have occurred in the interlayer insulating film 34 and the field insulating film 32, respectively. Figure 19 It shows Figure 18 A top view of the etch stop layer 52A and the interlayer insulating film 34 of the MOSFET 102A shown. Figure 20 It is a cross-sectional view of the MOSFET 102 showing a state where defects 61 and 62 have occurred in the interlayer insulating film 34 and the field insulating film 32, respectively. Figure 21 It shows Figure 20 A top view of the etch stop layer 52 and the interlayer insulating film 34 of the MOSFET 102 shown. As Figure 20 and Figure 21 shown, if defects 61 and 62 occur simultaneously in the interlayer insulating film 34 and the field insulating film 32, there is a risk of dielectric breakdown when a high dV / dt is applied at the defects 61 and 62 in the MOSFET 102.

[0097] On the other hand, for the MOSFET 102A, as Figure 18 and Figure 19 shown, the region 52A2 of the etch stop layer 52A directly below the defect 61 and the region 52A1 of the etch stop layer 52A directly above the defect 62 are separated by the interlayer insulating film 34. Therefore, suppression of dielectric breakdown when a high dV / dt is applied due to the defects 61 and 62 is achieved. Thus, for the MOSFET 102A, as long as defects do not occur simultaneously in the regions of the field insulating film 32 and the interlayer insulating film 34 corresponding to the same region of the etch stop layer 52A, suppression of dielectric breakdown when a high dV / dt is applied is achieved.

[0098] <B-3. Effect>

[0099] For the MOSFET 102 of Embodiment 2, the etch stop layer 52 is separated from the gate electrode 33 by the interlayer insulating film 34. Therefore, even if the interlayer insulating film 34 is defective, suppression of dielectric breakdown can be achieved.

[0100] For the MOSFET 1 *0*2A of Embodiment 2, the etch stop layer 52A is divided into multiple regions 52A1, 52A2, *52A3*, 52A4 by the insulating film. Therefore, for the MOSFET 102A, as long as defects do not occur simultaneously in the regions of the field insulating film 32 and the interlayer insulating film 34 corresponding to the same region of the etch stop layer 52A, suppression of dielectric breakdown when a high dV / dt is applied is achieved.

[0101] <C. Embodiment 3>

[0102] <C-1. Structure>

[0103] In addition to the device region 11, the gate lower well contact region 12, and the gate pad region 13, the silicon carbide semiconductor device MOSFET 103 of Embodiment 3 also has a temperature sensing diode region 14, a temperature sensing pad well contact region 15, and a temperature sensing pad region 16. Figure 22 This is a cross-sectional view showing the device region 11, the gate lower well contact region 12, and the gate pad region 13 of the MOSFET 103. Figure 23 (a) is a cross-sectional view showing the device region 11, the temperature sensing pad well contact region 15, and the temperature sensing pad region 16 of the MOSFET 103. Figure 23 (b) is a cross-sectional view showing the temperature sensing diode region 14 of MOSFET 103.

[0104] like Figure 22 As shown, in the gate pad region 13 of MOSFET 103, at a location including the point P furthest from the well contact hole HW1, an etch barrier layer 53 is provided between the field insulating film 32 and the interlayer insulating film 34. The etch barrier layer 53 is, for example, p-type polysilicon. In addition, a separation insulating film 35 is provided above the field insulating film 32 and above the gate electrode 33. The other structures in the device region 11, the gate lower well contact region 12, and the gate pad region 13 of MOSFET 103 are the same as those in MOSFETs 101 and 102 of Embodiment 1 or Embodiment 2.

[0105] like Figure 23 As shown in (a), the temperature sensing pad well contact region 15 has the same structure as the gate lower well contact region 12 of the MOSFET 103. Furthermore, except that the temperature sensing pad 8 is provided instead of the gate pad 2, and there is no gate contact hole HG or gate electrode 33, the temperature sensing pad region 16 has the same structure as the gate pad region 13 of the MOSFET 103. That is, in the temperature sensing pad region 16, an etch barrier layer 53 is similarly provided between the field insulating film 32 and the interlayer insulating film 34. The temperature sensing pad 8 is electrically connected to the temperature sensing diode in the temperature sensing diode region 14.

[0106] like Figure 23As shown in (b), the temperature sensing diode region 14 has a drift layer 22, a field insulating film 32, a separation insulating film 35, an n-type region 36, a p-type region 37, an interlayer insulating film 34, an anode electrode 5, and a cathode electrode 6. The field insulating film 32 is provided on the drift layer 22. The separation insulating film 35 is provided on the field insulating film 32. The n-type region 36 and the p-type region 37 are provided adjacent to each other on the separation insulating film 35. The n-type region 36 and the p-type region 37 are made of polysilicon. The interlayer insulating film 34 is provided on the separation insulating film 35, the n-type region 36, and the p-type region 37. The anode electrode 5 and the cathode electrode 6 are provided in the interlayer insulating film 34. The anode electrode 5 and the cathode electrode 6 are in contact with the n-type region 36 and the p-type region 37 respectively through contact holes in the interlayer insulating film 34. In the temperature sensing diode region 14, a lateral pn diode is formed by the n-type region 36 and the p-type region 37 as the temperature sensing diode.

[0107] In the above, the etching stopper layer 53 is made of n-type polysilicon, but it may also be p-type polysilicon.

[0108] <C-2. Manufacturing process>

[0109] Figures 24 to 26 It is a cross-sectional view showing the manufacturing process of the device region 11, the under-gate well contact region 12, the gate pad region 13, and the temperature sensing diode region 14 of the MOSFET 103 of Embodiment 3. Figure 24 (a), Figure 25 (a), Figure 26 (a) shows the manufacturing process of the device region 11, the under-gate well contact region 12, and the gate pad region 13, Figure 24 (b), Figure 25 (b), Figure 26 (b) shows the manufacturing process of the temperature sensing diode region 14. Hereinafter, the manufacturing processes of the device region 11, the under-gate well contact region 12, the gate pad region 13, and the temperature sensing diode region 14 of the MOSFET 103 will be described.

[0110] First, a drift layer 22 is formed by epitaxial growth on the SiC substrate 21. Next, a first well region 23, a source region 24, and a well contact region 25 are formed in the device region 11, and a second well region 26 is formed in the under-gate well contact region 12 and the gate pad region 13. After that, a field insulating film 32 is formed in the gate pad region 13, a part of the under-gate well contact region 12, and the temperature sensing diode region 14. In addition, a gate insulating film 31 is formed in the region of the under-gate well contact region 12 where the field insulating film 32 is not formed and in the device region 11. After that, gate electrodes are formed in the device region 11, the under-gate well contact region 12, and the gate pad region 13.

[0111] Next, a separation insulating film 35 for insulating the gate electrode and the temperature sensing diode is formed in the device region 11, the under-gate well contact region 12, the gate pad region 13, and the temperature sensing diode region 14. The separation insulating film 35 is, for example, TEOS.

[0112] After that, an n-type region 36 and a p-type region 37 are formed on the separation insulating film 35 in the temperature sensing diode region 14, and an etch stop layer 53 is formed in the gate pad region 13. Specifically, n-type polysilicon is formed over the entire surface of the gate pad region 13 and the temperature sensing diode region 14. Thus, the n-type polysilicon deposited in the gate pad region 13 becomes the etch stop layer 53. Next, a p-type impurity is selectively implanted into the n-type polysilicon deposited in the temperature sensing diode region 14 using a mask or the like, and the implanted region is inverted to p-type. The polysilicon inverted to p-type becomes the p-type region 37, and the region where the p-type impurity is not implanted becomes the n-type region 36. In this way, the Figure 24 cross-sectional structure shown is obtained.

[0113] Next, an interlayer insulating film 34 is formed in the device region 11, the under-gate well contact region 12, the gate pad region 13, and the temperature sensing diode region 14 and patterned. In addition, a source contact hole HS, a well contact hole HW1, and a gate contact hole HG are formed. Then, as surface electrodes, a source electrode 1 is formed in the device region 11 and the under-gate well contact region 12, a gate pad 2 is formed in the gate pad region 13, and an anode electrode 5 and a cathode electrode 6 are formed in the temperature sensing diode region 14. In this way, the Figure 25 cross-sectional structure shown is obtained.

[0114] Next, a protective film 41 such as polyimide is formed over the surface electrodes. In addition, a drain electrode 7 is formed on the back side of the SiC substrate 21 as a back electrode. In this way, Figure 26 the MOSFET 103 with the cross-sectional structure shown is completed.

[0115] <C-3. Variation>

[0116] Figure 27 is a cross-sectional view of the device region 11, the under-gate well contact region 12, and the gate pad region 13 of the MOSFET 103A which is a variation of Embodiment 3. The temperature sensing diode region 14, the temperature sensing pad well contact region 15, and the temperature sensing pad region 16 of the MOSFET 103A are the same as those of the MOSFET 103. Alternatively, an etch stop layer 53A described later may be provided in the temperature sensing pad region 16 of the MOSFET 103A instead of the etch stop layer 53.

[0117] Compared to MOSFET 103, MOSFET 103A has an etch barrier layer 53A instead of etch barrier layer 53 at the gate pad region 13. The etch barrier layer 53A is composed of multiple p-type regions 53A1 and multiple n-type regions 53A2, and is disposed at the gate pad region 13 between the field insulating film 32 and the interlayer insulating film 34, similar to the etch barrier layer 53. The multiple p-type regions 53A1 and multiple n-type regions 53A2 are arranged alternately in an adjacent manner. The p-type regions 53A1 are composed of p-type doped polysilicon, and the n-type regions 53A2 are composed of n-type doped polysilicon.

[0118] Figure 28 and Figure 29 This is a top view showing the configuration of the p-type region 53A1 and the n-type region 53A2 of the etch barrier layer 53A of the MOSFET 103A. Figure 28 This illustrates an example of arranging the roughly rectangular p-type region 53A1 and n-type region 53A2 into a checkered pattern. Figure 29 An example is shown where the approximately triangular p-type regions 53A1 and n-type regions 53A2 are arranged in a scale-like pattern. In this way, when multiple p-type regions 53A1 and multiple n-type regions 53A2 are arranged alternately without gaps, each p-type region 53A1 or each n-type region 53A2 contacts other p-type regions 53A1 and other n-type regions 53A2 at their corners. Here, to prevent p-type regions 53A1 from contacting each other or n-type regions 53A2 from contacting each other, a dividing region 66 formed by an interlayer insulating film 34 is provided at the corner of each p-type region 53A1 or each n-type region 53A2. Thus, the p-type regions 53A1 and n-type regions 53A2 can be arranged without gaps, and conduction of regions with the same conductivity type is avoided. Therefore, the p-type regions 53A1 and n-type regions 53A2 are not strictly rectangular or triangular, but rather approximately rectangular or approximately triangular with the corners of rectangles or triangles reduced by an amount equivalent to the dividing region 66.

[0119] Multiple pn diodes are formed by the aforementioned etch barrier layer 53A. Furthermore, in the area of ​​the gate pad region 13 where the etch barrier layer 53A is located, the number of pn diode connections increases as the distance between any two points when viewed from above increases. Therefore, even if defects occur in both the field insulating film 32 and the interlayer insulating film 34, as long as the locations of these two defects are a certain distance apart, voltage division can be achieved through the pn diodes, thus suppressing insulation breakdown when high dV / dt is applied.

[0120] In addition, such as Figure 28 and Figure 29As shown, since the division region 66 is provided only at the corners of each p-type region 53A1 or each n-type region 53A2, the area can be made smaller compared to the division region 65 of the MOSFET 102A of the modified example of Embodiment 2. Thus, the occurrence of dielectric breakdown when a high dV / dt is applied can be suppressed.

[0121] <C - 4. Effect>

[0122] In the MOSFET 103 of Embodiment 3, the multiple regions divided when viewed from above include a temperature-sensing diode region 14 having a temperature-sensing diode made of polysilicon and a temperature-sensing pad region 16 having a temperature-sensing pad 8 electrically connected to the temperature-sensing diode. The field insulating film 32 is formed on the upper surface of the semiconductor layer at the gate pad region 13 and the temperature-sensing pad region 16. The etch stop layer 53 is made of polysilicon and is formed on the field insulating film 32 at the gate pad region 13 and the temperature-sensing pad region 16. With the above structure, in the MOSFET 103 having a temperature-sensing diode, as in Embodiment 1, the occurrence of dielectric breakdown when a high dV / dt is applied can be suppressed.

[0123] Regarding the MOSFET 103A of the modified example of Embodiment 3, the etch stop layer 53A includes a plurality of p-type regions 53A1 and a plurality of n-type regions 53A2 alternately and repeatedly arranged. Moreover, a division region 66 made of an insulating film is provided between adjacent p-type regions 53A1 and between adjacent n-type regions 53A2. With the above structure, as Figure 28 and Figure 29 shown, since the division region 66 is provided only at the corners of each p-type region 53A1 or each n-type region 53A2, its area can be made smaller. Thus, the occurrence of dielectric breakdown when a high dV / dt is applied can be suppressed.

[0124] <D. Embodiment 4>

[0125] <D - 1. Structure>

[0126] Figure 30 is a plan view of the silicon carbide semiconductor device, i.e., the MOSFET 104, of Embodiment 4. The MOSFET 104 has a device region 11 where a source electrode 1 is formed and a gate-under-trap contact region 12, a gate pad region 13 where a gate pad 2 is formed, and an end region 19 on the outer periphery of the chip. Between the end region 19 and the device region 11, there are an end-trap contact region 17 and a gate wiring region 18.

[0127] Figure 31 is along Figure 30Cross-sectional views of the device region 11, the under-gate well contact region 12, and the gate pad region 13 of the MOSFET 104 along the E-E line. Figure 32 is along Figure 30 Cross-sectional views of the device region 11, the end well contact region 17, the gate wiring region 18, and the end region 19 of the MOSFET 104 along the F-F line. In the end region 19, a p-type electric field relaxation layer 26A is provided on the surface layer of the drift layer 22.

[0128] Compared with the MOSFET 101 of Embodiment 1, the MOSFET 104 is different in that an etching stopper layer 54 made of silicon nitride (SiN) is provided instead of the etching stopper layer 51, and the etching stopper layer 54 is provided not only in the gate pad region 13 but also in the end region 19. The etching stopper layer 54 has different materials and physical properties from those of the field insulating film 32 and the interlayer insulating film 34. The field insulating film 32 and the interlayer insulating film 34 are formed of a CVD film such as SiO2 or TEOS.

[0129] In the case of the silicon carbide semiconductor layer, even if a high electric field is applied inside, dielectric breakdown does not occur. However, if the electric field on the surface of the silicon carbide semiconductor layer becomes high, hydrolysis is induced in the presence of moisture in the vicinity, an oxide film is formed on the surface and bulges, and sometimes the film above the silicon carbide semiconductor layer is damaged. In this regard, the etching stopper layer 54 made of silicon nitride has high moisture resistance and can suppress the intrusion of moisture from the outside of the MOSFET 104. Therefore, as Figure 32 shown, it is preferable that the etching stopper layer 54 is provided in the end region 19 of the chip where the electric field becomes high.

[0130] Since the etching stopper layer 54 is made of silicon nitride, it has a high selectivity ratio with respect to the etching of the interlayer insulating film 34 and the field insulating film 32. Therefore, the etching stopper layer 54 is formed on the stacked film such as the field insulating film 32 or the gate electrode 33 formed before the etching stopper layer 54 in a manner having an acute-angle step portion. Here, the acute-angle step portion includes, for example, a conical or inverted conical step portion having a cone angle of 8° or more and less than 90°. Figure 33 Shows a state where the etching stopper layer 54 is formed on the step between the gate electrode 33 and the field insulating film 32. Since the silicon nitride film is likely to generate cracks, if the etching stopper layer 54 is formed on the step, stress is applied in the region G and cracks 63 are likely to occur.And if the crack 63 develops to the high electric field region, moisture intrudes into the high electric field region, resulting in the damage of the deposited film as described above. Therefore, it is preferable that the etching stopper layer 54 is not formed on the step generated by the stacked film such as the field insulating film 32 or the gate electrode 33 formed before the etching stopper layer 54.

[0131] <D-2. Effect>

[0132] In the MOSFET 104 of Embodiment 4, a plurality of regions divided when viewed from above include an end region 19 surrounding the device region 11. The field insulating film 32 is formed on the upper surface of the semiconductor layer at the gate pad region 13 and the end region 19. The etching stopper layer 54 is made of silicon nitride and is formed on the field insulating film 32 in the gate pad region 13 and the end region 19. With the above structure, in the MOSFET 104, moisture intrusion from the outside of the MOSFET 104 can be suppressed by the etching stopper layer 54 provided in the end region 19.

[0133] In addition, in the MOSFET 104, the etching stopper layer 54 is not formed on the step between the field insulating film 32 and the gate electrode 33. Therefore, cracks in the etching stopper layer 54 can be suppressed.

[0134] <E. Embodiment 5>

[0135] <E-1. Structure>

[0136] Figure 34 It is a cross-sectional view of a silicon carbide semiconductor device, i.e., the MOSFET 105, of Embodiment 5. The top view of the MOSFET 105 is as Figure 1 or Figure 2 shown. Figure 34 Shows the cross-sectional structure along the Figure 1 A-A line of, or Figure 2 the B-B line of.

[0137] In the MOSFET 10, at the gate pad region 13 and the gate under-trap contact region 12, instead of the P + -type trap contact region 26H, it has an N + -type trap contact region 26H1. In addition, in the MOSFET 105, at the gate pad region 13 and the gate under-trap contact region 12, a conductive film 38 is provided on the surface of the semiconductor layer. In addition, in the MOSFET 105, below the trap contact hole HW1 in the gate under-trap contact region 12, a p-type trap contact region 25 that penetrates the trap contact region 26H1 and reaches the trap main region 26L is provided. In the above aspects, the MOSFET 105 is different from the MOSFET 101 of Embodiment 1.

[0138] The conductive film 38 is a metal film or the like having a resistivity lower than that of the semiconductor layer.

[0139] According to the above structure, in the gate pad region 13 and the gate-under well contact region 12, the resistance of the conductive film 38 is small, so the displacement current can easily flow, and the electric field applied to the insulating film itself decreases when a high dV / dt is applied. Therefore, even if a defect occurs in the field insulating film 32 or the interlayer insulating film 34, it is possible to suppress the occurrence of dielectric breakdown when a high dV / dt is applied according to the remaining film thickness.

[0140] When the well contact region 26H1 is p-type, according to the usage conditions, bipolar operation occurs in the gate-under well contact region 12. Therefore, when there is a stacking fault in the silicon carbide semiconductor layer, the stacking fault grows, resulting in an increase in on-resistance or an increase in leakage current. In order to suppress such defects, the well contact region 26H1 is made n-type.

[0141] <E-2. Effects>

[0142] Regarding the MOSFET 105 of Embodiment 5, the second well region 26 has a p-type well body region 26L formed on the surface layer of the drift layer 22 and an n-type well contact region 26H1 formed on the surface layer of the well body region 26L. In addition, the MOSFET 105 has a conductive film 38 on the upper surface of the well contact region 26H1, and the conductive film 38 has a lower resistivity than the drift layer 22. Therefore, in the gate pad region 13 and the gate-under well contact region 12, the resistance of the conductive film 38 is small, so the displacement current can easily flow, and the electric field applied to the insulating film itself decreases when a high dV / dt is applied. Therefore, even if a defect occurs in the field insulating film 32 or the interlayer insulating film 34, it is possible to suppress the occurrence of dielectric breakdown when a high dV / dt is applied according to the remaining film thickness.

[0143] In addition, the various embodiments can be freely combined, and the various embodiments can be appropriately modified or omitted.

[0144] Description of reference numerals

[0145] 1 Source electrode, 2 Gate pad, 5 Anode electrode, 6 Cathode electrode, 7 Drain electrode, 8 Temperature sensing pad, 11 Device region, 11w Gate wiring section, 12 Gate lower well contact region, 13 Gate pad region, 14 Temperature sensing diode region, 15 Temperature sensing pad well contact region, 16 Temperature sensing pad region, 17 Terminal well contact region, 18 Gate wiring region, 19 Terminal region, 21 SiC substrate, 22 Drift layer, 23 First well region, 2 4. Source region, 25. Well contact region, 26. Second well region, 26A. Electric field mitigation layer, 26H, 26H1. Well contact regions, 26L. Well body region, 28. Hole, 29. Electron, 31. Gate insulating film, 32. Field insulating film, 33. Gate electrode, 34. Interlayer insulating film, 35. Separation insulating film, 36. n-type region, 37. p-type region, 38. Conductive film, 41. Protective film, 51, 51A, 52, 52A, 53, 53A, 54. Etch barrier layer, 53A1. p-type region, 53A2. n-type region, 60. Separation region, 61, 62. Defect, 63. Crack, 65, 66. Segmentation region.

Claims

1. A silicon carbide semiconductor device, which, when viewed from above, is divided into multiple regions, the multiple regions including a device region forming a switching element, a gate pad region forming a gate pad, and a gate lower well contact region between the device region and the gate pad region. The silicon carbide semiconductor device has a semiconductor layer made of silicon carbide. The semiconductor layer has: Drift layer of the first conductivity type; as well as A well region, which spans the gate pad region and the gate lower well contact region, is formed on the surface of the drift layer. The semiconductor layer also has: A field insulating film with a thickness greater than or equal to 0.8 μm is formed on the upper surface of the semiconductor layer at the gate pad region; Gate electrode and etch barrier layer, which are formed on the field insulating film in the gate pad region; An interlayer insulating film is formed on the gate electrode and the etch barrier layer; A surface electrode is formed on the interlayer insulating film at the gate lower well contact region and contacts the well region via a well contact hole that penetrates the field insulating film and the interlayer insulating film; as well as A gate pad, formed on the interlayer insulating film at the gate pad region, contacts the gate electrode via a gate contact hole that penetrates the interlayer insulating film. The etch barrier layer is composed of a material with a selectivity greater than or equal to 5.0 relative to the etching of the interlayer insulating film and the field insulating film, and the etch barrier layer and the field insulating film are disposed at least in the gate pad region at the position furthest from the well contact hole of the gate lower well contact region.

2. The silicon carbide semiconductor device according to claim 1, wherein, The etch barrier layer is made of the same material as the gate electrode.

3. The silicon carbide semiconductor device according to claim 2, wherein, The etch barrier layer is separated from the gate electrode by an insulating film.

4. The silicon carbide semiconductor device according to claim 3, wherein, The etching barrier layer is divided into multiple regions by an insulating film.

5. The silicon carbide semiconductor device according to any one of claims 1 to 4, wherein, The silicon carbide semiconductor device is divided into multiple regions, including a temperature sensing diode region having a temperature sensing diode made of polysilicon and a temperature sensing pad region having temperature sensing pads electrically connected to the temperature sensing diode. The field insulating film is formed on the upper surface of the semiconductor layer in the gate pad region and the temperature sensing pad region. The etch barrier layer is made of polysilicon and is formed on the field insulating film in the gate pad region and the temperature sensing pad region.

6. The silicon carbide semiconductor device according to claim 5, wherein, The etch barrier layer comprises a plurality of p-type regions and a plurality of n-type regions that are alternately and repeatedly configured. Dividing regions consisting of insulating films are provided between adjacent p-type regions and between adjacent n-type regions.

7. The silicon carbide semiconductor device according to any one of claims 1 to 4, wherein, The silicon carbide semiconductor device is divided into multiple regions, including an end region that surrounds the device region. The field insulating film is formed on the upper surface of the semiconductor layer at the gate pad region and the end region. The etch barrier layer is made of silicon nitride and is formed on the field insulating film in the gate pad region and the end region.

8. The silicon carbide semiconductor device according to claim 7, wherein, The etch barrier layer is not formed on the step between the field insulating film and the gate electrode.

9. The silicon carbide semiconductor device according to any one of claims 1 to 4, wherein, The well region has: A p-type trap body region, formed on the surface of the drift layer; and The n-type trap contact region is formed on the surface of the trap body region. The well region also has a conductive film on the upper surface of the well contact region, which has a lower resistivity than the drift layer.

10. A method for manufacturing a silicon carbide semiconductor device, the silicon carbide semiconductor device being divided into multiple regions when viewed from above, the multiple regions including a device region forming a switching element, a gate pad region forming a gate pad, and a gate underwell contact region between the device region and the gate pad region. In the manufacturing method of this silicon carbide semiconductor device, A drift layer composed of n-type silicon carbide is formed. A well region is formed on the surface of the drift layer in a manner that spans the gate pad region and the gate lower well contact region. At the gate pad region, a field insulating film with a thickness greater than or equal to 0.8 μm is formed over the drift layer and the well region. A gate electrode and an etch barrier layer are formed on the field insulating film in the gate pad region. An interlayer insulating film is formed on the gate electrode and on the etch barrier layer. At the gate lower well contact region, a surface electrode is formed on the interlayer insulating film, contacting the well region via a well contact hole that penetrates the field insulating film and the interlayer insulating film. In the gate pad region, a gate pad is formed on the interlayer insulating film, which contacts the gate electrode via a gate contact hole that penetrates the interlayer insulating film. The etch barrier layer is composed of a material with a selectivity greater than or equal to 5.0 relative to the etching of the interlayer insulating film and the field insulating film, and the etch barrier layer and the field insulating film are formed at least in the gate pad region at the position furthest from the well contact hole of the gate lower well contact region.

Images