Array substrate manufacturing method and display panel manufacturing method
By employing a two-stage etching process to form vias during the fabrication of the array substrate, the problems of deep via etching depth and long etching time are solved, thereby improving product yield, reducing costs, and simplifying the manufacturing process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- FUZHOU BOE OPTOELECTRONICS TECH CO LTD
- Filing Date
- 2021-07-19
- Publication Date
- 2026-07-03
AI Technical Summary
In the prior art, the etching depth of the vias in the array substrate is deep and the etching time is long, which leads to an increase in polymer inside the vias, affecting the product yield and quality of the display device, while also increasing the complexity and cost of manufacturing.
Vias are formed by two etching processes. Sub-vias are formed in the third, second and first insulating layers through a patterning process. Then, the fourth insulating layer and part of the insulating layer are removed by etching, which reduces the depth and time of a single etching and prevents the accumulation of polymer.
It improves the product yield and quality of display devices, reduces preparation steps and costs, and simplifies the manufacturing process.
Smart Images
Figure CN115701882B_ABST
Abstract
Description
Technical Field
[0001] This disclosure belongs to the field of display technology, specifically relating to a method for preparing an array substrate and a method for preparing a display panel. Background Technology
[0002] In recent years, with the increasingly widespread application of liquid crystal display products, liquid crystal display technology has become increasingly mature. TFT-LCD (Thin Film Transistor-Liquid Crystal Display) occupies a very important position in the display field due to its advantages such as high-quality image display, low power consumption, and environmental friendliness.
[0003] For liquid crystal displays, the quality of the array substrate is very important. In the process of manufacturing the array substrate, an insulating layer needs to be deposited on the array substrate, and an etching process is used to etch the insulating layer to form vias, thereby realizing the electrical connection between the metal layers in different layers. Summary of the Invention
[0004] This disclosure aims to at least solve one of the technical problems existing in the prior art, and to provide a method for fabricating an array substrate and a method for fabricating a display panel.
[0005] In a first aspect, embodiments of this disclosure provide a method for fabricating an array substrate, comprising:
[0006] A first conductive portion is formed on the substrate;
[0007] A first insulating layer is formed on the side of the first conductive portion away from the substrate, a second insulating layer is formed on the side of the first insulating layer away from the substrate, and a third insulating layer is formed on the side of the second insulating layer away from the substrate.
[0008] A first sub-via is formed through a single patterning process, penetrating a first portion of the third insulating layer, the second insulating layer, and the first insulating layer. The first portion of the first insulating layer has a first thickness. The orthographic projection of the first sub-via on the substrate at least partially overlaps with the orthographic projection of the first conductive portion on the substrate. The remaining thickness of the first insulating layer at the location of the first sub-via is a second thickness.
[0009] A fourth insulating layer is formed on the side of the third insulating layer that is opposite to the substrate;
[0010] The fourth insulating layer and the second thickness of the first insulating layer at the first sub-via are etched away to form the first via, and the first via exposes the first conductive part.
[0011] A first connection electrode is formed on the side of the fourth insulating layer opposite to the substrate, and the first connection electrode is electrically connected to the first conductive part through the first via.
[0012] Optionally, the step of forming the first sub-via through a first portion of the third insulating layer, the second insulating layer, and the first insulating layer in a single patterning process specifically includes:
[0013] A groove penetrating the third insulating layer is formed through a single patterning process, and the orthographic projection of the groove on the substrate at least partially overlaps with the orthographic projection of the first conductive part on the substrate.
[0014] The second insulating layer and the first insulating layer of a first thickness at the location of the groove are etched away to obtain the first sub-via. The orthographic projection of the groove on the substrate covers the orthographic projection of the first sub-via on the substrate. The thickness of the remaining first insulating layer at the location of the first sub-via is the second thickness.
[0015] Optionally, the step of forming a first insulating layer on the side of the first conductive portion away from the substrate specifically includes:
[0016] A second sub-insulating layer with a second thickness is formed on the side of the first conductive portion away from the substrate;
[0017] A first sub-insulating layer with a first thickness is formed on the side of the first sub-insulating layer opposite to the substrate;
[0018] The specific steps of etching away the second insulating layer and the first insulating layer of the first thickness at the groove location to obtain the first sub-via include:
[0019] The second insulating layer and the first sub-insulating layer at the groove location are removed by etching to obtain the first sub-via.
[0020] The step of etching away the fourth insulating layer and the second-thickness first insulating layer at the first sub-via to form the first via includes:
[0021] The fourth and second insulating layers at the first sub-via are etched away to form the first via.
[0022] Optionally, the material of the first sub-insulating layer includes silicon oxide, and the materials of the second sub-insulating layer and the fourth insulating layer include silicon nitride.
[0023] Optionally, between the step of forming the first insulating layer and the step of forming the second insulating layer, a second conductive portion is further formed on the side of the first sub-insulating layer opposite to the substrate;
[0024] The groove is formed in the third insulating layer by a single patterning process, wherein the orthographic projection of the groove on the substrate also at least partially overlaps with the orthographic projection of the second conductive portion on the substrate;
[0025] The second insulating layer and the first sub-insulating layer at the groove location are removed by etching, and a second sub-via is obtained;
[0026] The step of forming a fourth insulating layer on the side of the third insulating layer opposite to the substrate further includes:
[0027] The fourth insulating layer and the second insulating layer at the second sub-via are etched away to form the second via, and the second via exposes the second conductive part.
[0028] A first connection electrode is formed on the side of the fourth insulating layer opposite to the substrate, and the first connection electrode is also electrically connected to the second conductive part through the second via.
[0029] Optionally, the array substrate includes a display area and a peripheral area surrounding the display area. A gate driving circuit is disposed in the peripheral area. The gate driving circuit includes a shift register. Each shift register includes a plurality of thin-film transistors. The plurality of thin-film transistors include at least a pull-down control transistor. The gate of the pull-down control transistor is electrically connected to its source.
[0030] Wherein, the first conductive part is the gate of the pull-down control transistor, and the second conductive part is the source of the pull-down control transistor.
[0031] Optionally, the array substrate includes a display area and a peripheral area surrounding the display area. The array substrate also includes a gate line extending from the display area to the peripheral area. A gate driving circuit is disposed in the peripheral area. The gate driving circuit includes a plurality of shift registers. Each shift register includes a plurality of thin-film transistors. The plurality of thin-film transistors include at least an output transistor. The drain of the output transistor is connected to a signal output terminal, and the signal output terminal is connected to the gate line.
[0032] Wherein, the first conductive part is the gate line, and the second conductive part is the signal output terminal.
[0033] Optionally, the array substrate includes multiple gate lines and multiple data lines arranged in a cross pattern, as well as multiple sub-pixels, each sub-pixel including a thin-film transistor, a pixel electrode, and a common electrode;
[0034] The gate line and the gate of the thin-film transistor are also formed at the same time as the first conductive portion is formed;
[0035] The common electrode is formed at the same time as the first connecting electrode.
[0036] Optionally, the array substrate further includes a common electrode line, with the first conductive portion serving as the common electrode line.
[0037] Optionally, the method for fabricating the array substrate further includes:
[0038] A third conductive portion is also formed on the side of the first sub-insulating layer opposite to the substrate;
[0039] A third sub-via is also formed in the third insulating layer through a single patterning process, wherein the orthographic projection of the third sub-via on the substrate at least partially overlaps with the orthographic projection of the third conductive part on the substrate;
[0040] The second insulating layer inside the third sub-via is etched away to form the third via.
[0041] A second connection electrode layer is formed on the side of the fourth insulating layer opposite to the substrate. The second connection electrode is formed by a patterning process. The second connection electrode is electrically connected to the third conductive part through the third via.
[0042] Optionally, the step of etching away the second insulating layer and the first insulating layer at the location of the first sub-via to obtain the second sub-via specifically includes:
[0043] The second sub-via is obtained by dry etching to remove the second insulating layer and the first sub-insulating layer at the location of the first sub-via.
[0044] Optionally, the gases used in the dry etching process include NF3 and O2.
[0045] Optionally, the step of etching away the fourth insulating layer and the second insulating layer at the second sub-via to form the first via specifically includes:
[0046] The first via is formed by removing the fourth insulating layer and the second insulating layer at the second sub-via using dry etching, wherein the etching gas includes SF6 and O2.
[0047] Secondly, embodiments of this disclosure provide a method for manufacturing a display panel, including the method for manufacturing the array substrate described above. Attached Figure Description
[0048] Figure 1 This is a schematic diagram of an exemplary array substrate;
[0049] Figure 2 This is a schematic diagram of another exemplary array substrate structure;
[0050] Figure 3 A process flow diagram of a method for fabricating an array substrate provided in this disclosure embodiment;
[0051] Figures 4a-4f for Figure 3 The diagram shows the structural schematics of the array substrate in each step of the process flow chart shown.
[0052] Figure 5 for Figure 3 A flowchart detailing the specific steps of step S103;
[0053] Figure 6 is Figure 5 The flowchart is a schematic diagram of the structure of the array substrate.
[0054] Figure 7 A process flow diagram of another method for fabricating an array substrate provided in this disclosure embodiment;
[0055] Figures 8a-8g for Figure 7 The diagram shows the structural schematics of the array substrate in each step of the process flow chart shown.
[0056] Figure 9 A process flow diagram of another method for fabricating an array substrate provided in this disclosure embodiment;
[0057] Figures 10a-10g for Figure 9 The diagram shows the structural schematics of the array substrate in each step of the process flow chart.
[0058] Figure 11 This is a schematic diagram of the structure of an array substrate;
[0059] Figure 12 This is a circuit diagram of a shift register. Detailed Implementation
[0060] To enable those skilled in the art to better understand the technical solutions of this disclosure, the disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0061] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.
[0062] Figure 1 This is a schematic diagram of an exemplary array substrate, such as... Figure 1 As shown, the array substrate includes a common electrode line 12, a first insulating layer 13, a second insulating layer 14, a third insulating layer 15, a fourth insulating layer 16, and a connecting electrode 17 stacked on a substrate 11. The common electrode line 12 is disposed on the substrate 11. The first insulating layer 13 is disposed on the side of the common electrode line 12 facing away from the substrate 11. The second insulating layer 14 is disposed on the side of the first insulating layer 13 facing away from the substrate 11. The third insulating layer 15 is disposed on the side of the second insulating layer 14 facing away from the substrate 11. The fourth insulating layer 16 is disposed on the side of the third insulating layer 15 facing away from the substrate 11. The connecting electrode 17 is disposed on the side of the fourth insulating layer 16 facing away from the substrate 11. The connecting electrode 17 is connected to the common electrode line 11 through a via C penetrating the first insulating layer 13, the second insulating layer 14, the third insulating layer 15, and the fourth insulating layer 16.
[0063] Figure 1 The method for forming the via C in the array substrate generally includes: forming a common electrode line 12 on the substrate 11 using a patterning process; sequentially forming a first insulating layer 13, a second insulating layer 14, a third insulating layer 15, and a fourth insulating layer 16 on the common electrode line 12; and removing the fourth insulating layer 16, the third insulating layer 15, the second insulating layer 14, and the first insulating layer 13 in one etching process to obtain the via C.
[0064] The above-mentioned via C formation method has the problem of deep etching depth and long etching time because it uses one-step etching to remove four insulating layers. The long etching time will increase the amount of polymer in the via, affecting the subsequent metal bonding in the via, and thus affecting the product yield and quality of the display device.
[0065] Figure 2 This is a schematic diagram of another exemplary array substrate structure, such as... Figure 2 As shown, the array substrate includes a common electrode line 22, a first insulating layer 23, a second insulating layer 25, a third insulating layer 26, a fourth insulating layer 27, a first via D, a second via E, a connecting electrode 28, and a transition electrode 24, all stacked on a substrate 21. The first via D penetrates the first insulating layer 23 and the second insulating layer 25, and the second via E penetrates the third insulating layer 26 and the fourth insulating layer 27. The common electrode line 22 is electrically connected to the transition electrode 24 through the first via D, and the transition electrode 24 is electrically connected to the connecting electrode 28 through the second via E, thereby achieving the electrical connection between the common electrode line 22 and the connecting electrode 28.
[0066] In this example, the common electrode line 22 is electrically connected to the adapter electrode 24 through the first via D, and the adapter electrode 24 is electrically connected to the connecting electrode 28 through the second via E. This achieves the electrical connection between the common electrode line 22 and the connecting electrode 28, which can improve the problem of deep via etching depth and long etching time. However, the array substrate in this example needs to be fabricated with two vias, which adds a patterning process (i.e., a mask), thereby increasing the manufacturing complexity of the array substrate and increasing the manufacturing cost.
[0067] To address at least one of the aforementioned technical problems, this disclosure provides a method for fabricating an array substrate and an array substrate. The method for fabricating an array substrate and an array substrate provided in this disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0068] It should be noted that, in this embodiment, the patterning process may include only photolithography, or may include both photolithography and etching steps, and may also include other processes such as printing and inkjet printing to form a predetermined pattern; photolithography refers to the process of forming a pattern using photoresist, photomask, exposure machine, etc., including film formation, exposure, and development. The appropriate patterning process can be selected based on the structure formed in this embodiment.
[0069] In a first aspect, embodiments of this disclosure provide a method for fabricating an array substrate. Figure 3 This is a process flow diagram of a method for fabricating an array substrate according to an embodiment of the present disclosure. Figures 4a-4f for Figure 3 The diagram shows the structural schematics of the array substrate in each step. Figures 3-4f As shown, the method for fabricating the array substrate includes:
[0070] S101. A first conductive portion 120 is formed on the substrate 110.
[0071] Specifically, such as Figure 4aAs shown, in this step, the substrate 110 is made of transparent materials such as glass, resin, sapphire, and quartz, and has been pre-cleaned. In this step, a first conductive film is formed using sputtering, thermal evaporation, plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), or electron cyclotron resonance chemical vapor deposition (ECR-CVD). The first conductive film is then subjected to photoresist coating, exposure, development, etching, and photoresist stripping to form the first conductive portion 120, as shown. Figure 4a As shown.
[0072] The material of the first conductive part 120 is not specifically limited. For example, the material of the first conductive part 120 is a single layer or a multilayer composite layer formed by one or more of the following materials: molybdenum (Mo), molybdenum-niobium alloy (MoNb), aluminum (Al), aluminum-neodymium alloy (AlNd), titanium (Ti) and copper (Cu). Preferably, it is a single layer or a multilayer composite film composed of Mo, Al or an alloy containing Mo and Al.
[0073] S102, a first insulating layer 130 is formed on the side of the first conductive portion 120 away from the substrate 110, a second insulating layer 140 is formed on the side of the first insulating layer 130 away from the substrate 110, and a third insulating layer 150 is formed on the side of the second insulating layer 140 away from the substrate 110.
[0074] Specifically, such as Figure 4b As shown, in this step, a first insulating layer 130, a second insulating layer 140, and a third insulating layer 150 are sequentially formed on the side of the first conductive part away from the substrate using methods such as thermal growth, atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, plasma-assisted chemical vapor deposition, and sputtering.
[0075] The materials of the first insulating layer 130, the second insulating layer 140, and the third insulating layer 150 can be selected as needed and are not specifically limited here. For example, they can be silicon oxide (SiOx), silicon nitride (SiNx), hafnium oxide (HfOx), silicon oxynitride (SiON), aluminum oxide (AlOx), etc.
[0076] S103. A sub-via F1 is formed through a single patterning process, penetrating a first portion of the third insulating layer 150, the second insulating layer 140, and the first insulating layer 130. The first portion of the first insulating layer 130 has a first thickness. The orthographic projection of the sub-via F1 onto the substrate 110 at least partially overlaps with the orthographic projection of the first conductive portion 120 onto the substrate 110. The remaining thickness of the first insulating layer 130 at the location of the sub-via F1 is a second thickness.
[0077] Specifically, such as Figure 4c As shown, a layer of photoresist is coated on the third insulating layer 150. The photoresist can be coated by spin coating, blade coating, or roll coating. The photoresist coated on the third insulating layer 150 is exposed and developed to form a photoresist pattern. Using the photoresist pattern as an etching mask, a first sub-via F1 is formed through a first etching process, penetrating a first portion of the third insulating layer 150, the second insulating layer 140, and the first insulating layer 130. Then, the photoresist is removed.
[0078] For example, the first etching process can employ dry etching. Dry etching can utilize methods such as reactive ion etching (RIE), ion beam etching (IBE), and inductively coupled plasma (ICP) etching. For instance, the first etching process can employ ICP etching technology. ICP etching features low DC bias damage, high etching rate, and controllable ion density and energy, thereby shortening etching time and allowing for precise control of the etching morphology.
[0079] For example, the first etching process can employ ICP etching technology, using a mixture of NF3 and O2 as the etching gas. For instance, etching parameters can be adjusted to make the sidewalls of the vias smooth and the slope gentle. These parameters could include, for example, the operating pressure, power, etching gas flow rate, and composition ratio of the ICP etching equipment.
[0080] S104. A fourth insulating layer 160 is formed on the side of the third insulating layer 150 opposite to the substrate 110.
[0081] Specifically, such as Figure 4d As shown, in this step, a fourth insulating layer 160 is sequentially formed on the side of the third insulating layer 150 away from the substrate 110 using methods such as thermal growth, atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, plasma-assisted chemical vapor deposition, and sputtering.
[0082] The material of the fourth insulating layer 160 can be selected as needed and is not specifically limited here. For example, it can be silicon oxide (SiOx), silicon nitride (SiNx), hafnium oxide (HfOx), silicon oxynitride (SiON), aluminum oxide (AlOx), etc.
[0083] S105, etch away the fourth insulating layer and the first insulating layer 130 of the second thickness at the first sub-via F1 to form the first via G, and expose the first conductive part 120 at the first via G.
[0084] Specifically, such as Figure 4e As shown, the fourth insulating layer 160 and the first insulating layer 130 of the second thickness at the first sub-via F1 are etched away using the second etching process to form the first via G, which exposes the first conductive part 120.
[0085] For example, the second etching process can employ dry etching. Dry etching can utilize methods such as reactive ion etching (RIE), ion beam etching (IBE), and inductively coupled plasma (ICP) etching.
[0086] For example, the second etching process can employ ICP etching technology using a mixture of SF6 and O2 as the etching gas. SF6 and O2 offer a faster etching rate, reducing production time. Furthermore, SF6 and O2 react with the insulating layer to generate volatile gases that are promptly removed by the vacuum system, effectively eliminating residual foreign matter generated during etching and preventing it from affecting subsequent etching processes. This also ensures the insulating layer remains uncontaminated by residual foreign matter. For instance, etching parameters can be adjusted to ensure smooth sidewalls and gentle slopes in the first via. These parameters could include the operating pressure, power, etching gas flow rate, and composition ratio of the ICP etching equipment.
[0087] S106. A first connecting electrode 170 is formed on the side of the fourth insulating layer 160 away from the substrate 110. The first connecting electrode 170 is electrically connected to the first conductive part 120 through the first via G.
[0088] Specifically, such as Figure 4fAs shown, a first connecting electrode 170 is formed on the side of the fourth insulating layer 160 facing away from the substrate 110. The first connecting electrode 170 is electrically connected to the first conductive part 120 through a first via G. For example, a metal thin film of the connecting electrode is formed by sputtering, thermal evaporation, plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition. Then, the first connecting electrode 170 is formed by a first patterning process (film formation, exposure, development, wet etching, or dry etching) using a half-tone mask (HTM) or a gray-tone mask (GTM). The material of the first connecting electrode 170 is a single layer or multilayer composite layer formed by one or more of molybdenum (Mo), molybdenum-niobium alloy (MoNb), aluminum (Al), aluminum-neodymium alloy (AlNd), titanium (Ti), and copper (Cu), preferably a single layer or multilayer composite film composed of Mo, Al, or an alloy containing Mo or Al.
[0089] In this embodiment, the via is fabricated through two etching processes, compared to fabricating the via through a single etching process. Figure 1 The fabrication method of the array substrate shown reduces the etching depth, i.e., the etching time, thereby preventing the accumulation of polymer within the vias and affecting the subsequent metal bonding within the vias, thus improving the product yield and quality of the display device. Meanwhile, compared to... Figure 2 The fabrication method of the array substrate shown reduces one via, that is, reduces one mask, thereby reducing the fabrication steps and saving costs.
[0090] In some embodiments, such as Figure 5 As shown, step S103, forming the first sub-via penetrating the third insulating layer, the second insulating layer, and the first insulating layer through a single patterning process, specifically includes:
[0091] S1031. A groove H is formed through the third insulating layer 150 by a single patterning process. The orthographic projection of the groove H on the substrate 110 at least partially overlaps with the orthographic projection of the first conductive part 120 on the substrate 110.
[0092] Specifically, such as Figure 6a As shown, a first etching process is used to form a groove H that penetrates the third insulating layer 150. For example, the first etching process can be performed using dry etching technology with a mixture of NF3 and O2 as the etching gas.
[0093] S1032, Etch away the second insulating layer 140 and the first insulating layer 130 of the first thickness at the location of the groove H to obtain the first sub-via F1. The orthographic projection of the groove H on the substrate 110 covers the orthographic projection of the first sub-via F1 on the substrate 100. The thickness of the remaining first insulating layer 130 at the location of the first sub-via F1 is the second thickness.
[0094] Specifically, such as Figure 6b As shown, a second etching process is used to etch and remove the second insulating layer 140 and the first insulating layer 130 of the first thickness at the location H of the groove, resulting in the first sub-via F1. For example, the first etching process can employ dry etching technology with a mixture of NF3 and O2 as the etching gas. By adjusting the etching parameters, the sidewalls of the first sub-via can be made smooth and the slope gentle.
[0095] In this embodiment, the first sub-via is formed by two etching processes, which reduces the etching time of the first sub-via and prevents the increase of polymer in the first sub-via from affecting the bonding of metal in subsequent vias, thereby improving the product yield and quality of the display device.
[0096] Figure 7 This is a process flow diagram of another method for fabricating an array substrate according to an embodiment of this disclosure. Figures 8a-8g for Figure 7 Schematic diagrams of the array substrate structure in each step. (See attached diagram.) Figures 7-8g As shown, this disclosure provides another method for fabricating an array substrate, the method comprising:
[0097] S201, such as Figure 8a As shown, a first conductive portion 120 is formed on the substrate 110. Step S201 is the same as step S101 in the above embodiment, and will not be described again here.
[0098] S202, such as Figure 8b As shown, a second sub-insulating layer 131 with a second thickness is formed on the side of the first conductive portion 120 away from the substrate 110; a first sub-insulating layer 132 with a first thickness is formed on the side of the second sub-insulating layer 131 away from the substrate 110; a second insulating layer 140 is formed on the side of the first sub-insulating layer 132 away from the substrate 110; and a third insulating layer 150 is formed on the side of the second insulating layer 140 away from the substrate 110.
[0099] Specifically, in this step, a second sub-insulating layer 131, a first sub-insulating layer 132, a second insulating layer 140 and a third insulating layer 150 are sequentially formed on the side of the first conductive part 120 away from the substrate using methods such as thermal growth, atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, plasma-assisted chemical vapor deposition, and sputtering.
[0100] The materials of the first sub-insulating layer 132, the second sub-insulating layer 131, the second insulating layer 140, and the third insulating layer 150 can be selected according to the circumstances, and will not be elaborated here. Optionally, the first sub-insulating layer 132 and the second insulating layer 131 are both made of silicon oxide, the second sub-insulating layer 132 is made of silicon nitride, and the third insulating layer 150 is made of an organic material.
[0101] S203, such as Figure 8c As shown, a groove H is formed through the third insulating layer 150 by a single patterning process. The orthographic projection of the groove H on the substrate 110 at least partially overlaps with the orthographic projection of the first conductive part 120 on the substrate 110.
[0102] Specifically, a first etching process is used to form a groove H that penetrates the third insulating layer 150. For example, the first etching process can be performed using dry etching technology with a mixture of NF3 and O2 as the etching gas.
[0103] S204, such as Figure 8d As shown, the second insulating layer and the first sub-insulating layer 132 at the location of the groove H are etched away to obtain the first sub-via F1. The orthographic projection of the groove H on the substrate 110 covers the orthographic projection of the first sub-via F1 on the substrate 110, wherein the second sub-insulating layer 131 is exposed at the location of the first sub-via F1.
[0104] S205, such as Figure 8e As shown, a fourth insulating layer 160 is formed on the side of the third insulating layer 150 facing away from the substrate 110. Step S205 is the same as step S104 in the above embodiment, and will not be described again here. The materials of the third insulating layer 150 and the fourth insulating layer 160 can be selected as needed. Preferably, the material of the fourth insulating layer 160 is the same as the material of the second sub-insulating layer 131, both of which are silicon nitride.
[0105] S206, such as Figure 8f As shown, the fourth insulating layer 160 and the second insulating layer 131 at the first sub-via F1 are etched away to form the first via G, which exposes the first conductive portion 120. Step 206 is the same as step S105 in the above embodiment, and will not be described again here.
[0106] S207, such as Figure 8g As shown, a first connecting electrode 170 is formed on the side of the fourth insulating layer 160 away from the substrate 110, and the first connecting electrode 170 is electrically connected to the first conductive part 120 through the first via G.
[0107] In this embodiment, the first via G is fabricated through multiple etching processes, compared to fabricating the via through a single etching process. Figure 1The array substrate fabrication method shown reduces the depth and time of a single etching operation, thereby preventing the accumulation of polymer within the first via G and its impact on the subsequent metal bonding within the first via G, thus improving the product yield and quality of the display device. Simultaneously, compared to... Figure 2 The fabrication method of the array substrate shown reduces one via, that is, reduces one mask, thereby reducing the fabrication steps and saving costs.
[0108] Meanwhile, since the second insulating layer 140 is made of the same material as the first sub-insulating layer 132, the first sub-insulating layer 132 can be etched simultaneously when the second insulating layer 140 is etched. Also, since the fourth insulating layer 160 is made of the same material as the second sub-insulating layer 131, the second sub-insulating layer 131 can be etched simultaneously when the fourth insulating layer 160 is etched, thereby reducing the etching time.
[0109] Figure 9 This is a process flow diagram of another method for fabricating an array substrate provided in this disclosure. Figures 10a-10g for Figure 9 The diagram shows the structural schematics of the array substrate in each step. Figures 9-10g As shown, this disclosure provides another method for fabricating an array substrate, the method comprising:
[0110] S301, such as Figure 10a As shown, a first conductive portion 120 is formed on the substrate 110.
[0111] S302, such as Figure 10b As shown, a second sub-insulating layer 131 with a second thickness is formed on the side of the first conductive portion 120 away from the substrate 110; a first sub-insulating layer 132 with a first thickness is formed on the side of the second sub-insulating layer 131 away from the substrate 110; a second conductive portion 121 is formed on the side of the first sub-insulating layer 132 away from the substrate 110; a second insulating layer 140 is formed on the side of the second conductive portion 121 away from the substrate 110; and a third insulating layer 150 is formed on the side of the second insulating layer 140 away from the substrate 110.
[0112] S303, such as Figure 10c As shown, a groove H1 is formed through the third insulating layer 150 by a single patterning process. The orthographic projection of the groove H1 on the substrate 110 at least partially overlaps with the orthographic projection of the first conductive part 120 on the substrate 110. The orthographic projection of the groove H1 on the substrate 110 also at least partially overlaps with the orthographic projection of the second conductive part 121 on the substrate 110.
[0113] S304, such as Figure 10dAs shown, the second insulating layer 140 and the first sub-insulating layer 132 at the location of the groove H1 are etched away to obtain the first sub-via K1 and the second sub-via K2. The second sub-insulating layer 131 is exposed at the location of the first sub-via K1, and the second conductive part 120 is exposed at the location of the second sub-via K2.
[0114] S305, such as Figure 10e As shown, a fourth insulating layer 160 is formed on the side of the third insulating layer 150 that is opposite to the substrate 110.
[0115] S306, such as Figure 10f As shown, the fourth insulating layer 160 and the second insulating layer 131 at the first sub-via K1 are etched away to form the first via G1 and the second via G2. The first via G1 exposes the first conductive part 120, and the second via G2 exposes the second conductive part 121.
[0116] S307, such as Figure 10g As shown, a first connecting electrode 170 is formed on the side of the fourth insulating layer 160 away from the substrate 110. The first connecting electrode 170 is electrically connected to the first conductive part 120 through the first via G1, and the first connecting electrode 170 is electrically connected to the second conductive part 121 through the second via G2.
[0117] It should be noted that the process and materials used in this embodiment are the same as those in the above embodiments, and will not be repeated here.
[0118] In this embodiment, the via is fabricated through multiple etching processes, compared to fabricating the via through a single etching process. Figure 1 The array substrate fabrication method shown reduces the etching depth and etching time of a single etching process, thereby preventing the increase of polymer in the first via G1 and the second via G2, which would affect the subsequent metal bonding in the first via G1 and the second via G2, and thus improve the product yield and quality of the display device.
[0119] In some embodiments, Figure 11 This is a schematic diagram of the structure of an array substrate, such as... Figure 11 As shown, the array substrate includes a display area AA and a peripheral area BB surrounding the display area. A gate driving circuit 1101 is disposed in the peripheral area BB, and the gate driving circuit 1101 includes a plurality of shift registers 1105.
[0120] Figure 12 This is a circuit diagram of a shift register 1105, as shown below. Figure 12As shown, the shift register 1105 includes: an input circuit 1, an output circuit 2, a frame reset circuit 3, a pull-down control circuit 4, a pull-down circuit 5, and a first noise reduction circuit 6. The connection node between the input circuit 1, the output circuit 2, and the pull-down circuit 5 is the pull-up node PU; the node between the pull-down control circuit 4 and the pull-down circuit 5 is the pull-down node PD. Input circuit 1 is configured to charge and reset pull-up node PU; output circuit 2 is configured to respond to the potential of pull-up node PU and output a clock signal through signal output terminal Output; frame reset circuit 3 is configured to reset the output of pull-up node PU and signal output terminal Output through a low-level signal in response to a reset signal during the blanking phase; pull-down control circuit 4 is configured to respond to a first power supply voltage and control the potential of pull-down node PD through the first power supply voltage; pull-down circuit 5 is configured to respond to pull-up node PU and pull down the potential of pull-down node PD through a low-level signal; first noise reduction channel is configured to perform noise reduction on the output of pull-up node PU and signal output terminal Output in response to the potential of pull-down node PD.
[0121] Continue to refer to Figure 12 The input circuit 1 may include an input sub-circuit 11 and a reset sub-circuit 12; wherein, the input sub-circuit 11 is configured to pre-charge the pull-up node PU in response to an input signal; the reset sub-circuit 12 is configured to reset the pull-up node PU in response to a reset signal via a low-level signal. Figure 1 As shown, the input sub-circuit may include a first transistor M1, whose source and gate are both connected to the input signal terminal Input, and whose drain is connected to the pull-up node PU. In this case, when a high-level signal is written to the input signal terminal Input, the first transistor M1 turns on, pre-charging the pull-up node PU through the high-level signal written to the input terminal. The reset sub-circuit may include a second transistor M2, whose source is connected to the pull-up node PU, whose drain is connected to the low-level signal terminal VGL, and whose gate is connected to the reset signal terminal Reset. In this case, when a high-level signal is written to the reset signal terminal Reset, the second transistor M2 turns on, pulling the pull-up node PU low for reset through the low-level signal of the low-level signal terminal VGL.
[0122] Reference Figure 12The output circuit 2 in the shift register may include a third transistor M3 and a storage capacitor C1. The source of the third transistor M3 is connected to the clock signal terminal CLK, the drain of the third transistor M3 is connected to the signal output terminal Output, and the gate of the third transistor M3 is connected to the pull-up node PU. The first plate of the storage capacitor C1 is connected to the pull-up node PU, and the second plate of the storage capacitor C1 is connected to the signal output terminal Output. In this case, when the pull-up node PU is charged to a high-level signal, the storage capacitor C1 stores the high-level signal, and simultaneously the third transistor M3 is turned on, allowing the clock signal input to the clock signal terminal CLK to be output through the signal output.
[0123] Reference Figure 12 The frame reset circuit 3 in the shift register may include a fourth transistor M4 and a seventh transistor M7. The source of the fourth transistor M4 is connected to the signal output terminal Output, the drain of the fourth transistor M4 is connected to the low-level signal terminal VGL, and the gate of the fourth transistor M4 is connected to the reset signal terminal Trst. The source of the seventh transistor M7 is connected to the pull-up node PU, the drain of the seventh transistor M7 is connected to the low-level signal terminal VGL, and the gate of the seventh transistor M7 is connected to the reset signal terminal Trst. In this case, when the display phase of one or more frames ends and the blanking phase begins, a high-level signal is written to the reset signal terminal Trst. At this time, the fourth transistor M4 and the seventh transistor M7 are turned on. The low-level signal of the low-level signal terminal VGL resets the signal output terminal Output through the fourth transistor M4 and resets the pull-up node PU through the seventh transistor M7. By setting the frame reset circuit 3 in the shift register, noise from the pull-up node PU and the signal output terminal Output in one frame of display can be effectively prevented from being transmitted to the next frame of display.
[0124] Reference Figure 12 The pull-down control circuit 4 in the shift register may include a fifth transistor M5 and a ninth transistor M9. The source of the fifth transistor M5 is connected to the first power supply voltage terminal VDD, the drain of the fifth transistor M5 is connected to the pull-down node PD, and the gate of the fifth transistor M5 is connected to the drain of the ninth transistor M9. The source and gate of the ninth transistor M9 are connected to the first power supply voltage terminal VDD. In this case, the first power supply voltage at the first power supply voltage terminal VDD controls the fifth transistor M5 and the ninth transistor M9 to turn on, pulling up the potential of the pull-down node PD.
[0125] Reference Figure 12The pull-down circuit 5 in the shift register may include a sixth transistor M6 and an eighth transistor M8. The source of the sixth transistor M6 is connected to the pull-down node PD, its drain is connected to the low-level signal terminal VGL, and its gate is connected to the pull-up node PU. The source of the eighth transistor M8 is connected to the pull-down control circuit 4, its drain is connected to the low-level signal terminal VGL, and its gate is connected to the pull-up node PU. In this case, when the potential of the pull-up node PU is a high-level signal, both the sixth transistor M6 and the eighth transistor M8 are turned on. The low-level signal at the low-level signal terminal VGL pulls down the potential of the pull-down node PD through the sixth transistor M6 and pulls down the potential of the pull-down control circuit 4 through the eighth transistor M8.
[0126] Reference Figure 12 The first noise reduction circuit 6 in the shift register may include a tenth transistor M10 and an eleventh transistor M11. The source of the tenth transistor M10 is connected to the pull-up node PU, the drain of the tenth transistor M10 is connected to the low-level signal terminal VGL, and the gate of the tenth transistor M10 is connected to the pull-down node PD. The source of the eleventh transistor M11 is connected to the signal output terminal Output, the drain of the eleventh transistor M11 is connected to the low-level signal terminal VGL, and the gate of the eleventh transistor M11 is connected to the pull-down node PD. In this case, when the pull-down node PD is high, the tenth transistor M10 and the eleventh transistor M11 are turned on. The low-level signal of the low-level signal terminal VGL is used to reduce the noise of the output of the pull-up node PU through the tenth transistor M10, and also to reduce the noise of the output of the signal output terminal Output through the tenth transistor M10.
[0127] like Figure 12 As shown, the gate and source of the pull-down control transistor M9 are electrically connected. Figure 10g In the illustrated embodiment, the first conductive portion 120 may be the gate of the pull-down control transistor M9, the second conductive portion 121 may be the source of the pull-down control transistor M9, and the gate of the pull-down control transistor M9 and the source of the pull-down control transistor M9 are electrically connected through the first connecting electrode 170.
[0128] It should be noted that this embodiment uses the 16T1C shift register circuit as an example for illustration. Of course, the shift register circuit can also be of other types, and no specific limitation is made here.
[0129] In this embodiment, the via is fabricated through multiple etching processes, compared to fabricating the via through a single etching process. Figure 1The array substrate fabrication method shown reduces the etching depth and etching time of a single etching process, thereby preventing the increase of polymer in the first via G1 and the second via G2, which would affect the subsequent metal bonding in the first via G1 and the second via G2, and thus improve the product yield and quality of the display device.
[0130] In some embodiments, such as Figure 11 As shown, the array substrate includes a display area AA and a peripheral area BB surrounding the display area. The array substrate also includes a gate line 1103 extending from the display area AA to the peripheral area BB. A gate driving circuit 1101 is disposed within the peripheral area BB. The gate driving circuit 1101 includes multiple shift registers 1105, wherein the signal output terminal output of each shift register 1105 is electrically connected to the gate line 1103. This embodiment is based on... Figure 12 The following explanation uses shift register 1105 as an example. Figure 12 As shown, the drain of the output transistor M3 in the shift register is connected to the signal output terminal, and the signal output terminal is connected to the gate line 1103.
[0131] like Figure 10g In the embodiment shown, the first conductive part 120 may be the gate line 1103, and the second conductive part 121 may be the signal output terminal output of the gate driving circuit 1101. The signal output terminal output of the gate driving circuit 1101 is electrically connected to the gate line 1103 through the first connecting electrode 170.
[0132] In this embodiment, the first via is fabricated through multiple etching processes, compared to fabricating the via through a single etching process. Figure 1 The array substrate fabrication method shown reduces the etching depth and etching time of a single etching process, thereby preventing the increase of polymer in the first via G1 and the second via G2, which would affect the subsequent metal bonding in the first via G1 and the second via G2, and thus improve the product yield and quality of the display device.
[0133] In some embodiments, such as Figure 11 As shown, the array substrate includes multiple gate lines 1103 and multiple data lines 1102 arranged in a cross configuration, as well as multiple sub-pixels. Each sub-pixel includes a thin-film transistor, a pixel electrode, and a common electrode 1104. The gate lines 1103 and the gate of the thin-film transistor are formed concurrently with the formation of the first conductive portion; the common electrode 1104 is formed concurrently with the formation of the first connection electrode 170.
[0134] In some embodiments, the array substrate further includes a common electrode line, and the first conductive portion can also be used as the common electrode line.
[0135] In some embodiments, such as Figures 10a-10g As shown, it should be noted that Figures 10a-10g The array substrate shown is divided into a first part and a second part, wherein the first part and the second part are located on different cross-sections of the array substrate. In the second part, as shown... Figures 10a-10g The method for fabricating the array substrate further includes: forming a third conductive portion 123 on the side of the first sub-insulating layer 132 facing away from the substrate 100; forming a third sub-via in the third insulating layer 150 through a single patterning process, wherein the orthographic projection of the third sub-via on the substrate 100 at least partially overlaps with the orthographic projection of the third conductive portion 123 on the substrate 100; etching away the second insulating layer 140 within the third sub-via to form the third via; forming a second connection electrode layer on the side of the fourth insulating layer 140 facing away from the substrate 100; forming a second connection electrode 180 through a patterning process; and electrically connecting the second connection electrode 180 to the third conductive portion 120 through the third via. In this embodiment, the third via in region B can be fabricated simultaneously during the fabrication of the first via in region A, reducing fabrication steps and saving fabrication costs.
[0136] Secondly, embodiments of this disclosure provide a method for manufacturing a display panel, including the method for manufacturing the array substrate described above.
[0137] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.
Claims
1. A method for fabricating an array substrate, characterized in that, include: A first conductive portion is formed on the substrate; A first insulating layer is formed on the side of the first conductive portion away from the substrate, a second insulating layer is formed on the side of the first insulating layer away from the substrate, and a third insulating layer is formed on the side of the second insulating layer away from the substrate. A first sub-via is formed through a single patterning process, penetrating a first portion of the third insulating layer, the second insulating layer, and the first insulating layer. The first portion of the first insulating layer has a first thickness. The orthographic projection of the first sub-via on the substrate at least partially overlaps with the orthographic projection of the first conductive portion on the substrate. The remaining thickness of the first insulating layer at the location of the first sub-via is a second thickness. A fourth insulating layer is formed on the side of the third insulating layer that is opposite to the substrate; The fourth insulating layer and the second thickness of the first insulating layer at the first sub-via are etched away to form the first via, and the first via exposes the first conductive part. A first connection electrode is formed on the side of the fourth insulating layer opposite to the substrate, and the first connection electrode is electrically connected to the first conductive part through the first via. The step of forming the first sub-via through a first portion of the third insulating layer, the second insulating layer, and the first insulating layer using a single patterning process specifically includes: A groove penetrating the third insulating layer is formed through a single patterning process, and the orthographic projection of the groove on the substrate at least partially overlaps with the orthographic projection of the first conductive part on the substrate. The second insulating layer and the first insulating layer of the first thickness at the location of the groove are etched away to obtain the first sub-via. The orthographic projection of the groove on the substrate covers the orthographic projection of the first sub-via on the substrate. The thickness of the remaining first insulating layer at the location of the first sub-via is the second thickness. The step of forming a first insulating layer on the side of the first conductive portion away from the substrate specifically includes: A second sub-insulating layer with a second thickness is formed on the side of the first conductive portion away from the substrate; A first sub-insulating layer with a first thickness is formed on the side of the second sub-insulating layer opposite to the substrate; The specific steps of etching away the second insulating layer and the first insulating layer of the first thickness at the groove location to obtain the first sub-via include: The second insulating layer and the first sub-insulating layer at the groove location are removed by etching to obtain the first sub-via. The step of etching away the fourth insulating layer and the second-thickness first insulating layer at the first sub-via to form the first via includes: The fourth and second insulating layers at the first sub-via are etched away to form the first via.
2. The method for fabricating an array substrate according to claim 1, characterized in that, The first sub-insulating layer is made of silicon oxide, and the second and fourth sub-insulating layers are made of silicon nitride.
3. The method for fabricating an array substrate according to claim 1, characterized in that, Between the step of forming the first insulating layer and the step of forming the second insulating layer, a second conductive portion is further formed on the side of the first sub-insulating layer opposite to the substrate; The groove is formed in the third insulating layer by a single patterning process, wherein the orthographic projection of the groove on the substrate also at least partially overlaps with the orthographic projection of the second conductive portion on the substrate; The second insulating layer and the first sub-insulating layer at the groove location are removed by etching, and a second sub-via is obtained; The step of forming a fourth insulating layer on the side of the third insulating layer opposite to the substrate further includes: The fourth insulating layer and the second insulating layer at the second sub-via are etched away to form the second via, and the second via exposes the second conductive part. A first connection electrode is formed on the side of the fourth insulating layer opposite to the substrate, and the first connection electrode is also electrically connected to the second conductive part through the second via.
4. The method for fabricating an array substrate according to claim 3, characterized in that, The array substrate includes a display area and a peripheral area surrounding the display area. A gate driving circuit is disposed in the peripheral area. The gate driving circuit includes a shift register. Each shift register includes multiple thin-film transistors. The multiple thin-film transistors include at least a pull-down control transistor. The gate of the pull-down control transistor is electrically connected to its source. Wherein, the first conductive part is the gate of the pull-down control transistor, and the second conductive part is the source of the pull-down control transistor.
5. The method for fabricating an array substrate according to claim 3, characterized in that, The array substrate includes a display area and a peripheral area surrounding the display area. The array substrate also includes a gate line extending from the display area to the peripheral area. A gate driving circuit is disposed in the peripheral area. The gate driving circuit includes a plurality of shift registers. Each shift register includes a plurality of thin-film transistors. The plurality of thin-film transistors include at least an output transistor. The drain of the output transistor is connected to a signal output terminal, and the signal output terminal is connected to the gate line. Wherein, the first conductive part is the gate line, and the second conductive part is the signal output terminal.
6. The method for fabricating an array substrate according to claim 1, characterized in that, The array substrate includes multiple gate lines and multiple data lines arranged in a cross pattern, as well as multiple sub-pixels. Each sub-pixel includes a thin-film transistor, a pixel electrode, and a common electrode. The gate line and the gate of the thin-film transistor are also formed at the same time as the first conductive portion is formed; The common electrode is formed at the same time as the first connecting electrode.
7. The method for fabricating an array substrate according to claim 6, characterized in that, The array substrate also includes a common electrode line, and the first conductive portion serves as the common electrode line.
8. The method for fabricating an array substrate according to claim 3, characterized in that, Also includes: A third conductive portion is also formed on the side of the first sub-insulating layer opposite to the substrate; A third sub-via is also formed in the third insulating layer through a single patterning process, wherein the orthographic projection of the third sub-via on the substrate at least partially overlaps with the orthographic projection of the third conductive part on the substrate; The second insulating layer inside the third sub-via is etched away to form the third via. A second connection electrode layer is formed on the side of the fourth insulating layer opposite to the substrate. The second connection electrode is formed by a patterning process. The second connection electrode is electrically connected to the third conductive part through the third via.
9. The method for fabricating an array substrate according to claim 2, characterized in that, The step of etching away the second insulating layer and the first sub-insulating layer at the location of the first sub-via to obtain the second sub-via specifically includes: The second sub-via is obtained by dry etching to remove the second insulating layer and the first sub-insulating layer at the location of the first sub-via.
10. The method for fabricating an array substrate according to claim 9, characterized in that, The gases used in the dry etching process include NF3 and O2.
11. The method for fabricating an array substrate according to claim 2, characterized in that, The step of etching away the fourth insulating layer and the second insulating layer at the second sub-via to form the first via specifically includes: The first via is formed by removing the fourth insulating layer and the second insulating layer at the second sub-via using dry etching, wherein the etching gas includes SF6 and O2.
12. A method for manufacturing a display panel, characterized in that, The method for preparing the array substrate according to any one of claims 1-11.