Dynamic status register array

Abstract

This application relates to dynamic status register arrays. An apparatus can include one or more memory dies coupled with a data bus. The apparatus can further include a controller coupled with each of the plurality of memory dies via the data bus, the controller configured to transmit a first command associated with a first operation to a first memory die. The first command can be an operation (e.g., the first operation) associated with an allocation of a queue slot of a status store associated with at least the first memory die. The controller can further transmit a second command to the first memory die to request a status of the first operation. The controller can receive the status of the first operation via a channel (e.g., a first channel) of the data bus based on the allocated queue slot of the status store.

Description

[0001] CROSS-REFERENCE

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 399,889, titled “DYNAMIC STATUS REGISTERS ARRAY” and filed on August 11, 2021, for Cariello et al., assigned to the present assignee and expressly incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The technical field relates to dynamic status registers array. BACKGROUND

[0004] Memory devices are widely used in various electronic devices such as computers, user devices, wireless communication devices, cameras, digital displays, and the like to store information. Information is stored by programming memory cells within the memory device into different states. For example, binary memory cells can be programmed into one of two supported states that generally correspond to a logical 1 or a logical 0. In some examples, an individual memory cell can support more than two possible states, and the memory cell can store any one of the two possible states. To access information stored by a memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device to a corresponding state.

[0005] There are a variety of types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), 3-dimensional cross point memory (3D cross point), or NOR and NAND memory devices, among others. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) can lose their programmed state over time unless periodically refreshed by an external power source. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long period of time even in the absence of an external power source. SUMMARY

[0006] An apparatus is described. The apparatus can include a plurality of memory dies, a data bus coupled with each of the plurality of memory dies, and a controller coupled with each of the plurality of memory dies via the data bus, the controller configured to: transmit, to a first memory die of the plurality of memory dies, a first command associated with a first operation, wherein the first command includes an assignment of the first operation for a queue slot of a state storage bank; transmit, to the first memory die, a second command based at least in part on transmitting the first command, wherein the second command requests a state associated with the state storage bank; and receive, via a first lane of the data bus determined based at least in part on the assigned queue slot of the state storage bank, the state of the first operation based at least in part on transmitting the second command to the first memory die.

[0007] An apparatus is described. The apparatus can include a memory array comprising a plurality of memory cells configured to store data, a controller coupled with the memory array and configured to: receive a first command associated with a first operation on the data, wherein the first command includes an assignment of the first operation for a queue slot of a state storage bank; receive, based at least in part on receiving the first command, a second command requesting a state of the first operation, wherein the second command is associated with an output of the state of the state storage bank on a data bus coupled with a plurality of devices, a device of the plurality of devices including the memory array and the controller; generate, based at least in part on receiving the second command, a bit indicating the state of the first operation performed on the memory array; and output, based at least in part on generating the bit and an association between the assigned queue slot of the state storage bank and the first lane, the bit on a first lane of the data bus.

[0008] A non-transitory computer-readable medium storing code is described. The non-transitory computer-readable medium stores code that can include instructions that, when executed by a processor of a memory device, cause the memory device to: transmit, to a first memory die of a plurality of memory dies, a first command associated with a first operation, wherein the first command includes an assignment of the first operation for a queue slot of a state storage bank; transmit, to the first memory die, a second command based at least in part on transmitting the first command, wherein the second command requests a state associated with the state storage bank; and receive, via a first lane of a data bus determined based at least in part on the assigned queue slot of the state storage bank, the state of the first operation based at least in part on transmitting the second command to the first memory die.

[0009] A non-transitory computer-readable medium storing code is described. The non-transitory computer-readable medium stores code that can include instructions that, when executed by a processor of a memory device, cause the memory device to receive a first command associated with a first operation on data, wherein the first command comprises an assignment of the first operation for a queue slot of a state storage bank; receive, based at least in part on receiving the first command, a second command requesting a status of the first operation, wherein the second command is associated with an output of a status of the state storage bank on a data bus coupled with a plurality of devices, a device of the plurality of devices comprising a memory array; generate, based at least in part on receiving the second command, a bit indicating the status of the first operation performed on the memory array; and output, based at least in part on generating the bit and an association between the assigned queue slot of the state storage bank and the first channel, the bit on a first channel of the data bus. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 An example of a system supporting a dynamic status register array is shown in accordance with examples as disclosed herein.

[0011] Figure 2 An example of a system supporting a dynamic status register array is shown in accordance with examples as disclosed herein.

[0012] Figure 3 An example of a block diagram of a system supporting a dynamic status register array is shown in accordance with examples as disclosed herein.

[0013] Figure 4A and 4B An example of a timing diagram of a system supporting a dynamic status register array is shown in accordance with examples as disclosed herein.

[0014] Figure 5 A block diagram of a memory system controller supporting a dynamic status register array is shown in accordance with examples as disclosed herein.

[0015] Figure 6 A block diagram of a memory device supporting a dynamic status register array is shown in accordance with examples as disclosed herein.

[0016] Figure 7 and 8 A flow diagram showing one or more methods of supporting a dynamic status register array is shown in accordance with examples as disclosed herein. DETAILED DESCRIPTION

[0017] A system can include a host system and a memory system storing data for the host system. In some examples, the memory system can include multiple memory devices attached to an interface. For example, the memory system can include multiple NAND devices attached to the same interface (e.g., an open NAND flash interface (ONFI) channel). The host system can transmit access commands (e.g., read commands, program commands, erase commands) to the memory system. In such examples, the memory system can perform operations in response to the commands received from the host system. In examples where the memory system includes multiple memory devices, the memory devices can perform concurrent operations - e.g., operations that can not be initiated simultaneously but are performed in parallel. That is, the memory system can initiate a first operation at a first memory device, then initiate a second operation at a second memory device, then initiate a third operation at a third memory device, and the first operation, the second operation, and the third operation can be performed at least partially in parallel. In some examples, a host system controller or a memory system controller can perform a round-robin polling of a status register of each active memory device to determine whether a given memory device is ready to accept service - e.g., the controller can poll the first memory device, then the second memory device, then the third memory device to determine whether the first memory device, the second memory device, or the third memory device is ready to accept service. In some examples, performing round-robin polling can increase latency and power consumption in the system. For example, the second memory device can be ready to accept service before the first memory device, but can have to idle until the system completes polling of the status register of the first memory device. And, switching from one memory device to another memory device to poll the memory device in a round-robin polling can utilize additional power for bus transitions. And finally, the memory devices waiting for subsequent commands can also increase power consumption.

[0018] Systems, techniques, and devices to perform concurrent or parallel status polling via dedicated commands in a memory system having multiple memory devices are described herein. For example, a controller in a memory system can transmit a command to a plurality of memory devices to allocate each operation to a queue slot of a status bank. Accordingly, the controller can subsequently poll the status bank using a command (e.g., a bank selection poll command), and a device having an operation allocated to a queue slot of the status bank can output a status on a channel of a data bus associated with the queue slot of the status bank. For example, for an eight (8) bit data bus coupled with a memory device having eight (8) banks, polling status of 256 concurrent operations can be supported. By performing concurrent parallel status polling with a status bank, a memory system can reduce power consumption and latency. That is, polling based on a status bank can assist in identifying which memory device is ready to be serviced first, enabling commands to be serviced for a given memory device more quickly. This can reduce the amount of time each memory device idles waiting for service or a subsequent command, reducing power consumption and latency of the system.

[0019] Features of the disclosure are first described in the context of systems and devices of Figure 1 and 2 Features of the disclosure are described in the context of block diagrams and timing diagrams of Figure 3 and 4. Features of the disclosure are further shown and described in the context of device diagrams and flowcharts related to dynamic status register arrays of Figures 5-8 These and other features of the disclosure are described in the context of device diagrams and flowcharts related to dynamic status register arrays of

[0020] Figure 1 An example of a system 100 that supports a dynamic status register array according to examples as disclosed herein is shown. The system 100 includes a host system 105 coupled with a memory system 110.

[0021] The memory system 110 can be or include any device or collection of devices that includes at least one memory array. For example, the memory system 110 can be or include a Universal Flash Storage (UFS) device, an Embedded Multimedia Controller (eMMC) device, a flash device, a Universal Serial Bus (USB) flash device, a Secure Digital (SD) card, a Solid State Drive (SSD), a Hard Disk Drive (HDD), a Dual In-Line Memory Module (DIMM), a Small Outline DIMM (SO-DIMM), or a Non-Volatile DIMM (NVDIMM), among other possibilities.

[0022] The system 100 can be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, an automobile, or other conveyance), an Internet of Things (IoT) enabled device, an embedded computer (e.g., included in a vehicle, industrial equipment, or a networked commercial device), or any other computing device that includes a memory and a processing device.

[0023] The system 100 can include a host system 105 that can be coupled with the memory system 110. In some examples, this coupling can include an engagement with a host system controller 106, which can be an example of a control component configured to cause the host system 105 to perform various operations according to examples as described herein. The host system 105 can include one or more devices, and in some cases, a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 can include an application configured for communication with the memory system 110 or a device therein. The processor chipset can include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect Express (PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 can use the memory system 110, for example, to write data to and read data from the memory system 110. Although one memory system 110 is shown in Figure 1 The host system 105 can be coupled with any number of memory systems 110.

[0024] The host system 105 can be coupled with the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 can be configured to communicate via the physical host interface using an associated protocol (e.g., to exchange or otherwise convey control, address, data, and other signals between the memory system 110 and the host system 105). Examples of physical host interfaces can include, without limitation, a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fibre Channel interface, a small computer system interface (SCSI), a serial attached SCSI (SAS), a double data rate (DDR) interface, a DIMM interface (e.g., a DDR-enabled DIMM socket interface), an open NAND flash interface (ONFI), and a low power double data rate (LPDDR) interface. In some examples, one or more such interfaces can be included in, or otherwise supported between, a host system controller 106 of the host system 105 and a memory system controller 115 of the memory system 110. In some examples, the host system 105 can be coupled with the memory system 110 via a respective physical host interface for each memory device 130 included in the memory system 110, or via a respective physical host interface for each type of memory device 130 included in the memory system 110 (e.g., the host system controller 106 can be coupled with the memory system controller 115).

[0025] The memory system 110 can include a memory system controller 115 and one or more memory devices 130. The memory devices 130 can include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although two memory devices 130-a and 130-b are shown in the example of FIG. 1, the memory system 110 can include any number of memory devices 130. Additionally, if the memory system 110 includes more than one memory device 130, different memory devices 130 within the memory system 110 can include the same or different types of memory cells. Figure 1 The memory system 110 can include a memory system controller 115 and one or more memory devices 130. The memory devices 130 can include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although two memory devices 130-a and 130-b are shown in the example of FIG. 1, the memory system 110 can include any number of memory devices 130. Additionally, if the memory system 110 includes more than one memory device 130, different memory devices 130 within the memory system 110 can include the same or different types of memory cells.

[0026] The memory system controller 115 can be coupled with and communicate with the host system 105 (e.g., via a physical host interface) and can be an example of a control component configured to cause the memory system 110 to perform various operations in accordance with examples as described herein. The memory system controller 115 can also be coupled with and communicate with the memory devices 130 to perform operations at the memory devices 130 that can generally be referred to as access operations, such as reading data, writing data, erasing data, or refreshing data, among other such operations. In some cases, the memory system controller 115 can receive commands from the host system 105 and communicate with the one or more memory devices 130 to perform such commands (e.g., at memory arrays within the one or more memory devices 130). For example, the memory system controller 115 can receive commands or operations from the host system 105 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access of the memory devices 130. In some cases, the memory system controller 115 can exchange data with the host system 105 and the one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 can convert responses (e.g., data packets or other signals) associated with the memory devices 130 into corresponding signals for the host system 105.

[0027] The memory system controller 115 can be configured for other operations associated with the memory devices 130. For example, the memory system controller 115 can perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection operations or error correction operations, encryption operations, caching operations, media management operations, background refresh, health monitoring, and address translations between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory devices 130.

[0028] The memory system controller 115 can include hardware such as one or more integrated circuits or discrete components, a buffer memory, or a combination thereof. The hardware can include circuitry with special-purpose (e.g., hard-coded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 can be or include a microcontroller, special-purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0029] The memory system controller 115 can also include a local memory 120. In some cases, the local memory 120 can include read-only memory (ROM) or other memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions ascribed herein to the memory system controller 115. In some cases, the local memory 120 can additionally or alternatively include static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for internal storage or computation, for example, in connection with the functions ascribed herein to the memory system controller 115.

[0030] The memory devices 130 can include one or more arrays of non-volatile memory cells. For example, the memory devices 130 can include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), resistive memory, other chalcogenide-based memory, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally or alternatively, the memory devices 130 can include one or more arrays of volatile memory cells. For example, the memory devices 130 can include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0031] In some examples, the memory devices 130 can include (e.g., on the same die or within the same package) a local controller 135 that can perform operations on one or more memory cells of the respective memory device 130. The local controller 135 can operate in conjunction with the memory system controller 115, or can perform one or more functions ascribed herein to the memory system controller 115. For example, as shown, the memory device 130-a can include a local controller 135-a, and the memory device 130-b can include a local controller 135-b. Figure 1

[0032] ​In some cases, the memory device 130 can be or include a NAND device (e.g., a NAND flash device). The memory device 130 can be or include a memory die 160. For example, in some cases, the memory device 130 can be a package that includes one or more dies 160. In some examples, a die 160 can be a piece of electronic-grade semiconductor (e.g., a silicon die cut from a silicon wafer) cut from a wafer. Each die 160 can include one or more planes 165, and each plane 165 can include a respective set of blocks 170, where each block 170 can include a respective set of pages 175, and each page 175 can include a set of memory cells.

[0033] In some cases, the NAND memory device 130 can include memory cells configured to each store one bit of information, which can be referred to as single-level cells (SLCs). Additionally or alternatively, the NAND memory device 130 can include memory cells configured to each store multiple bits of information, which can be referred to as multi-level cells (MLCs) if configured to each store two bits of information, triple-level cells (TLCs) if configured to each store three bits of information, quad-level cells (QLCs) if configured to each store four bits of information, or more generally as multi-level memory cells. Multi-level memory cells can provide greater storage density relative to SLC memory cells, but can involve narrower read or write margins or greater complexity for supporting circuitry in some cases.

[0034] In some cases, a plane 165 can refer to a group of blocks 170, and in some cases, concurrent operations can occur within different planes 165. For example, concurrent operations can be performed on memory cells within different blocks 170, so long as the different blocks 170 are in different planes 165. In some cases, performing concurrent operations in different planes 165 can be subject to one or more restrictions, such as performing the same operation on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., with respect to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0035] In some cases, a block 170 can include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 can share a common word line (e.g., coupled with) and memory cells in the same string can share a common digit line (which can alternatively be referred to as a bit line) (e.g., coupled with).

[0036] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first level of granularity (e.g., at a page level of granularity), but can be erased at a second level of granularity (e.g., at a block level of granularity). That is, a page 175 can be a smallest unit of memory (e.g., a set of memory cells) that can be independently programmed or read (e.g., programmed or read concurrently as part of a single programming or reading operation), and a block 170 can be a smallest unit of memory (e.g., a set of memory cells) that can be independently erased (e.g., erased concurrently as part of a single erase operation). Additionally, in some cases, a NAND memory cell can be erased before it can be rewritten with new data. Thus, for example, in some cases, a used page 175 can not be updated until the entire block 170 containing the page 175 has been erased.

[0037] The system 100 can include any number of non-transitory computer- readable media that support a reduced pin state register. For example, the host system 105, the memory system controller 115, or the memory device 130 can include or otherwise have access to one or more non-transitory computer- readable media that store instructions (e.g., firmware) to perform the functions attributed herein to the host system 105, the memory system controller 115, or the memory device 130. Such instructions can cause the host system 105, the memory system controller 115, or the memory device 130 to perform one or more associated functions as described herein, for example, if executed by the host system 105 (e.g., by the host system controller 106), by the memory system controller 115, or by the memory device 130 (e.g., by the local controller 135).

[0038] In some cases, the memory system 110 can utilize the memory system controller 115 to provide a managed memory system, which can include, for example, one or more memory arrays and associated circuitry in combination with a local (e.g., on-die or in-package) controller (e.g., the local controller 135). An example of a managed memory system is a managed NAND (MNAND) system.

[0039] In some examples, the memory system controller 115 can perform polling operations on the memory devices 130 to determine the status of operations performed by each memory device 130. In some cases, the memory system controller 115 can perform polling operations in a round-robin system. For example, the memory system controller 115 can first request the status of a first operation performed at the memory device 130-a, and then request the status of a second operation performed at the memory device 130-b. In some cases, the second operation can be performed prior to the first operation. In such examples, the memory device 130-b can idly wait for the memory system controller 115 to request the status of the second operation. The idle waiting period can increase the power consumption and latency of the system.

[0040] As described herein, the memory system controller 115 can perform concurrent polling operations on the memory devices 130 by utilizing one or more state storage banks. For example, the memory system controller 115 can transmit a command (e.g., a first command) to the memory device 130-a. The command can allocate an operation (e.g., a first operation) to a queue slot of a state storage bank associated with the memory device 130-a. In some cases, the memory system controller 115 can transmit multiple commands to one or more memory devices 130 to allocate operations to queue slots of respective state storage banks. Subsequently, the memory system controller 115 can transmit a command (e.g., a second command, a polling command) to the multiple memory devices 130 requesting the status associated with the state storage banks. The memory device 130-a can output the status of the operation such that, in the event the memory device 130-a is ready to accept service, the memory system controller 115 can proceed to provide service to the memory device 130-a. Thus, the association between the operation, the queue slot of the state storage bank, and the channel of the bus can allow the memory system controller 115 to provide service to a first memory device 130 having a state storage bank ready for use, thereby reducing idle time and reducing the latency and power consumption of the system.

[0041] Figure 2 An example of a system 200 that supports a dynamic status register array in accordance with examples as disclosed herein is shown. The system 200 can be an example of the memory system 110 as described with reference to Figure 1 The system 200 can include a memory system controller 215 and memory devices 230, which can be examples of the memory system controller 115 and memory devices 130, respectively, as described with reference to Figure 1Examples of memory system controller 115 and memory devices 130 are described. Memory system controller 215 can be coupled with memory devices 230 via data bus 205. Memory system controller 215 can also be coupled with each memory device 230 via chip enable line 210 - e.g., memory device 230-a can be coupled with memory system controller 215 via chip enable line 210-a. In some examples, there can be eight (8) memory devices 230 coupled with memory system controller 215. In other examples, there can be more or less than eight (8) memory devices 230 coupled with memory system controller 215. It is noted that the number of memory devices 230 in system 200 is not limited to the claims.

[0042] As described with reference to Figure 1 Memory system controller 215 can be configured to transmit commands from a host system (e.g., host system 105) to memory devices 230, as described. In some examples, memory system controller 215 can be configured to transmit commands 235 to memory devices 230 via data bus 205. In such examples, memory system controller 215 can be configured to activate memory device 230-a via chip enable line 210 to transmit commands 235 from memory system controller 215 to a given memory device 230. For example, memory system controller 215 can activate memory device 230-a via chip enable line 210-a, then transmit a command 235 to memory device 230-a to initiate an operation. In some examples, memory system controller 215 can be configured to transmit commands 235 to initiate concurrent operations - e.g., operations that can not be initiated simultaneously but are performed in parallel. For example, memory system controller 215 can be configured to activate memory device 230-a by transmitting a chip enable signal via chip enable line 210-a. Memory system controller 215 can then transmit a command 235 to memory device 230-a to initiate a first operation. Memory system controller 215 can then activate memory device 230-b via chip enable line 210-b, and transmit a second command 235 to memory device 230-b to initiate a second operation. In such examples, the first and second operations can be performed concurrently (e.g., in parallel) by memory device 230-a and memory device 230-b.

[0043] In some examples, the memory system controller 215 can be configured to transfer data 240 to and from the memory devices 230. For example, the memory system controller 215 can transmit data 240 to the memory devices 230 during a program command and receive data 240 from the memory devices 230 during a read command. The memory system controller 215 can also be configured to receive status 245 from each memory device 230 - for example, the status 245 can indicate a status of a given operation performed at a given memory device 230 and whether the given memory device 230 is ready to accept service. As described with reference to Figure 1 The memory devices 230 can associate a command with one or more status storage banks having one or more queue slots, as described with reference to FIG. 1. The memory system controller 215 can transmit a command to a memory device 230 that has an operation (e.g., a first operation) allocated to a queue slot, and the queue slot can be associated with an address channel or a data channel of the data bus 205 for the status storage bank. Thus, during a poll operation, the memory system controller 215 can determine a status of a memory device 230 (or a portion of a memory device 230, such as a plane) based on the allocated queue slot and the associated channel of the data bus 205.

[0044] The data bus 205 can be configured to transfer signals, commands 235, data 240, and status 245 between the memory system controller 215 and the memory devices 230 - for example, the data bus 205 can be a multiplexed (e.g., tri-stated, bidirectional) bus configured to transfer both addresses and data 240. In some examples, the data bus 205 can be configured to have a number of bits equal to a number of data input / output (DQ) pins of the memory system controller 215. For example, when the memory system controller 215 has eight (8) DQ pins, the data bus 205 can be an eight (8) bit data bus 205. In some examples, the data bus 205 can also include a number of lines (e.g., channels) equal to the number of bits - for example, each channel of the data bus 205 can be configured to transfer a bit of information. In some examples, the data bus 205 can also transfer a status 245 of each memory device 230 performing an operation concurrently. That is, the data bus 205 can be configured to multiplex the status 245 from the memory devices 230 to the memory system controller 215 - for example, a first status 245 from the memory device 230-a can be transferred to the memory system controller 215 on a first line of the data bus 205 and a second status 245 from the memory device 230-h can be transferred to the memory system controller 215 on a second line of the data bus 205 concurrently. As described herein, which channel of the data bus 205 a status is transferred on can be based on an operation allocated to an associated queue slot of the status storage bank.

[0045] Memory devices 230 can be configured to store data. In some examples, memory devices 230 can be configured to receive commands 235 from memory system controller 215. Memory devices 230 can be configured to perform operations concurrently in response to commands received from memory system controller 215. Each memory device 230 can be configured to transfer data 240 to and from memory system controller 215. In some examples, memory devices 230 can also be configured to transfer status 245 of operations to memory system controller 215. Status 245 can be a single bit indicating whether a memory device 230 is ready to accept service - e.g., status 245 of a given operation performed at a memory device 230. Memory devices 230 can be configured to access data bus 205 based on a chip enable signal received from memory system controller 215. For example, when the chip enable signal is in a deactivated (e.g., high) state, memory devices 230 can refrain from driving status 245 or from receiving commands 235 from data bus 205. Alternatively, when the chip enable signal is in an activated (e.g., low) state, memory devices 230 can drive status 245 or receive commands 235 from the data bus - e.g., memory system controller 215 can decouple memory devices 230 from data bus 205 by driving the chip enable signal high. In some examples, each memory device 230 can include multiple independent sections (e.g., banks, partitions, planes). In some examples, a queue slot of a status bank can be configured to store status associated with a particular bank, partition, plane, etc. of memory device 230.

[0046] In some examples, the memory system controller 215 can receive commands from the host system. The memory system controller 215 can then activate the memory devices 230 based on the commands received from the host system - for example, the memory system controller 215 can activate the memory device 230-a, the memory device 230-b, or the memory device 230-h based on the received commands (e.g., via the chip enable lines 210-a, 210-b, and 210-c, respectively). After activating the memory devices 230, the memory system controller 215 can transmit commands 235 to initiate operations (e.g., read, program, or erase operations) at the memory devices 230. For example, the memory system controller can transmit a first command 235 to initiate an erase operation at the memory device 230-a, a second command 235 to initiate a program operation at the memory device 230-b, and a third command 235 to initiate a read operation at the memory device 230-h. The memory system controller 215 can sequentially transmit the commands 235 (e.g., transmit a first command to the memory device 230-a and a last command to the memory device 230-h), while the operations can be at least partially concurrently performed. After initiating each operation, the memory system controller 215 can perform a poll to determine the status of each operation and determine whether the memory devices 230 are ready to accept service.

[0047] In some examples, the memory system controller 215 can perform a round-robin polling of the status registers of each active memory device 230, e.g., each memory device 230 performing an operation. For example, the memory system controller 215 can deactivate chip enable lines 210-b and 210-c to disconnect the data bus 205 from the memory device 230-b and the memory device 230-c, while maintaining chip enable line 210-a in an active state. The memory system controller 215 can then transmit a command 235 to the memory device 230-a requesting the status 245 of the operation performed at the memory device 230-a. The memory device 230-a can then transmit the status 245 to the memory system controller 215 with the eight-bit data bus 205. The memory system controller 215 can then repeat the process to determine the status of the operations at memory devices 230-b and 230-h. In some examples, the memory device 230-h can complete its respective operation first. For example, the memory device 230-h can complete a read operation before the memory device 230-a completes an erase operation. That is, some operations can take longer to perform than others - e.g., a read operation can be performed in a first duration, a program operation can be performed in a second duration, and an erase operation can be performed in a third duration, where the first duration is less than the second and third durations, and the second duration is less than the third duration. In such examples, the memory device 230-h can idly wait for the memory system controller 215 to request the status 245 of the operation. This can increase the latency and power consumption of the system.

[0048] As described herein, the memory system controller 215 can perform a concurrent poll of the status registers of each active memory device 230. For example, after allocating operations for respective queue slots of one or more status banks, the memory system controller 215 can transmit a command 235 to each of the memory devices 230-a, 230-b, and 230-h (e.g., by activating each of the chip enable lines 210-a, 210-b, and 210-h while transmitting the command), which requests the status of the operations associated with a given status bank. The memory devices 230 having operations associated with a queue slot of the given status bank can then drive a status 245 on a respective channel of the data bus 205. For example, the memory devices 230 can concurrently drive the status 245 on a respective channel (e.g., an address channel or a data channel) based on the allocated queue slot of the associated operation. In such an example, the memory devices 230 can drive a first value to indicate that the memory device 230 is busy and a second value to indicate that the memory device 230 is ready to accept service. Accordingly, the memory system controller 215 can determine which memory device 230 is ready to accept service first and transmit a subsequent command 235 based on the determination. For example, the memory device 230-h can drive the second value on a first channel of the data bus 205 associated with a second queue slot of the status bank, which can indicate that the memory device 230-h is ready for use. The memory system controller 215 can then request the data 240 indicated by the read command from the memory device 230-h, while the memory device 230-a and the memory device 230-b can continue to perform their respective operations. By performing the concurrent poll by way of allocating operations for queue slots of the status bank, the memory system controller 215 can reduce latency and reduce additional power consumption.

[0049] Figure 3 An example of a block diagram 300 supporting dynamic status register arrays is shown in accordance with examples as disclosed herein. The block diagram 300 can illustrate a memory system controller 305 coupled with a memory device 310 via a plurality of channels 315 of a data bus. The memory system controller 305, the memory device 310, and the data bus can be as described with reference to the memory system 100, the memory system controller 215, the memory device 230, and the data bus 205, respectively. Figure 2Examples of the memory system controller 215, memory device 230, and data bus 205 described herein. In some instances, the memory system controller 305 may store a mapping 320 (e.g., a table containing the mapping) between queue slots of the state memory of memory device 310 and the plane of memory device 310, which allows the memory system controller 305 to associate received state with a specific memory device and plane. By performing the polling operation as described herein, the memory system controller 305 can service a first memory device 310 that is ready for use, thereby reducing idle time and reducing system latency and power consumption.

[0050] like Figure 3 As shown, the memory device 310 may include four (4) memory dies 325. For example, the memory device 310 may include a first memory die 325-a, a second memory die 325-b, a third memory die 325-c, and a fourth memory die 325-d. Each memory die 325 may include any number of planes, wherein each plane may be configured to perform access operations independently of the other planes of the memory die 325. Furthermore, although in Figure 3 The diagram depicts a queue slot 345 for each state memory cell 325, but each memory die 325 may contain multiple state memory cells 340, and each state memory cell 340 may contain multiple queue slots 345. For example, the number of queue slots 345 in each memory die 325 may be the same as the number of channels 315 in the data bus, and it may have multiple state memory cells, each with the stated number of queue slots 345. Figure 3 As shown, the first channel 315-a can be associated with the first queue slot, the second channel 315-b can be associated with the second queue slot, and the Nth channel 315-n can be associated with the Nth queue slot of the state memory shown. Therefore, a system employing multiple memory dies 325 with eight (8) state memories, each state memory 340 having eight (8) queue slots 345 (e.g., corresponding to eight (8) channels 315 of the data bus), can support concurrent polling (through the state memory) of 256 operations.

[0051] The memory system controller 305 can be configured to transmit commands (e.g., a first command) to the first memory die 325-a. The command can be associated with an operation (e.g., a read operation, a write operation, an erase operation) on a plane of the first memory die 325-a. For example, the first operation can be performed on plane 2 of the first memory die 325-a. The command can also include allocating the first operation to a queue slot associated with the first memory die 325-a in the state memory. Figure 3As shown, a first operation can be assigned to a queue slot of a first state storage bank of the memory device 310. The queue slot can be associated with a first channel 315-a (e.g., channel “0”) of a data bus for the first state storage bank. In some cases, the assignment can be stored to a portion of the first memory die 325-a.

[0052] In some instances, additional operations can be performed on various planes of the memory dies 325. For example, an operation can be performed on plane 1 of the first memory die 325-a, and an operation can be assigned to a fourth queue slot of a first state storage bank of the memory dies 325. Additionally or alternatively, operations can be performed on plane 3 and plane 0 of the second memory die 325-b, plane 2 of the third memory die 325-c, and plane 1 of the fourth memory die 325-d. Operations can be assigned to queue slots of a first state storage bank of the memory dies 325 as shown. Figure 3 As shown, a first operation can be assigned to a queue slot of a first state storage bank of the memory device 310. The queue slot can be associated with a first channel 315-a (e.g., channel “0”) of a data bus for the first state storage bank. In some cases, the assignment can be stored to a portion of the first memory die 325-a.

[0053] The memory system controller 305 can store a mapping 320 between the memory dies 325, planes (e.g., operations performed on the planes), and channels 315 of a data bus. For example, the mapping 320 can indicate that an operation was performed on plane 2 of memory die 0 (e.g., memory die 325-a) associated with a first queue slot of a first state storage bank. Additionally or alternatively, the mapping 320 can not contain any entries for a queue slot of a state storage bank if no command has been transmitted and assigned to the given queue slot. For example, no command can have been transmitted to a memory die 325 associated with a sixth or seventh queue slot (e.g., which are associated with channels 315-f and 315-g, respectively) of a state storage bank as shown, which is represented by the mapping 320 indicating “X” for the die and “X” for the respective queue slot. However, the mapping 320 can be updated accordingly if a command and state associated with the sixth or seventh queue slot of the state storage bank are transmitted. Additionally, although the mapping for the memory system controller 305 is shown for one state storage bank, the mapping can contain a number of state storage banks, each with a number of queue slots (e.g., the number corresponding to the number of channels 315).

[0054] In some cases, the memory system controller 305 can transmit a command (e.g., a second command) requesting a status of one or more operations. For example, the second command can be transmitted to the first memory die 325-a, and the memory controller associated with the first memory die 325-a can generate and output a status bit on the first channel 315-a and the fourth channel 315-d of the data bus. As described herein, the status bit can indicate whether the associated plane of the memory die 325-a is ready to accept service. In other examples, the second command can be transmitted to multiple memory dies 325 concurrently, and each memory die 325 can output zero, one, or more than one status bit. For example, if the second command is transmitted to the memory dies 325-a, 325-b, 325-c, and 325-d and indicates to output a status associated with the illustrated status bank, the memory die 325-a can output a status of plane 2 on channel 315-a and a status of plane 1 on channel 315-d, the memory die 325-b can output a status of plane 3 on channel 315-b and a status of plane 0 on channel 315-n, the memory die 325-c can output a status of plane 2 on channel 315-c, and the memory die 325-d can output a status of plane 1 on channel 315-e. The memory system controller 305 can thus perform a concurrent polling of multiple operations across multiple memory dies 325 and can service the first memory die 325 with a status assigned to a selected status bank to indicate a readiness for use. Additionally, the memory system controller 305 can maintain multiple status banks, where each status bank is capable of supporting a concurrent polling of one or more memory dies 325. Once a memory die 325 accepts service, the associated portion of the mapping 320 stored to the memory system controller 305 and the associated mapping stored to the memory die 325 can be removed or replaced. For example, when plane 2 of the first memory die 325-a accepts service, the assignment of the plane to the queue slot of the status bank can be removed (e.g., changed to have a value of “X”). Thus, a subsequent operation can be assigned to the first queue slot of the first status bank for the memory die 325-a, or an operation can be assigned for a different memory die 325.

[0055] By performing a concurrent polling by way of assigning operations to queue slots for status banks, the memory system controller 305 can reduce latency and reduce additional power consumption. Moreover, the memory system controller 305 can be configured to manage polling operations for a relatively large number of operations in parallel.

[0056] Figure 4AAn example of a timing diagram 400-a that supports dynamic status register array in accordance with examples as disclosed herein is shown. The timing diagram 400-a can be performed by processing logic that can include hardware (e.g., processing system, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some examples, the timing diagram 400-a can be performed by a system as described with reference to Figure 2 For example, the timing diagram 400-a can be performed by a memory system controller (e.g., memory system controller 215 as described with reference to Figure 2 For example, the timing diagram 400-a can be performed by a memory system controller (e.g., memory system controller 215 as described with reference to Figure 2 For example, the timing diagram 400-a can be performed by a memory system controller (e.g., memory system controller 215 as described with reference to Figure 4A The system 100 can be shown to perform a concurrent polling operation while signals and commands are communicated between the memory system controller and the memory device (e.g., commands 235, data 240, and status 245 as described with reference to Figure 2

[0057] Figure 4A A snapshot read command can be shown to be transmitted from the memory system controller to the memory device (e.g., memory die of the memory device). The snapshot read command can be associated with an operation (e.g., a read operation) and can also allocate a first operation for a queue slot of a status bank, as described with reference to Figure 3 In some cases, the snapshot read command can be transmitted to the memory device prior to the status operation being performed, as described below with reference to Figure 4B

[0058] The snapshot read command can include a first field 403 (e.g., 00h) that can indicate a type of command (e.g., a memory command indicated by “00h”). In some cases, the first field 403 can be or can include an opcode for a read command. A second field 407 (e.g., ADD) can include a column and row address, and a third field 409 (e.g., random read (RR)) can indicate a command for a snapshot read (e.g., a random read). Additionally or alternatively, the snapshot read command can include a fourth field 411 (e.g., SR#) that can indicate a queue slot of a status bank (e.g., status register) of the memory device for which an associated operation is to be allocated. For example, as described with reference to Figure 3 ​​As described, the SR# can allocate operations associated with a plane associated with a command for a particular queue slot and state bank of a memory device. Thus, when a state operation is performed, a state bit can be output, and the memory system controller can determine a plane and die associated with the state bit based on a mapping (e.g., as referenced Figure 3 As described, the mapping 320) and further perform a read operation based on the determined plane and die. In some cases, the snapshot read command can include a fifth field 413 (e.g., 21h) that can indicate that the polling of the command is to be via a state bank. In some cases, the fifth field 413 can specify a particular type of read to be performed. For example, the fifth field 413 can specify a 4kB iWL read to be performed.

[0059] Figure 4B An example of a timing diagram 400-b that supports dynamic state register arrays is shown in accordance with examples as disclosed herein. The timing diagram 400-b can be performed by processing logic that can include hardware (e.g., processing system, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some examples, the timing diagram 400-b can be performed by a system (e.g., system 200) as described herein. For example, the timing diagram can be performed by a memory system controller (e.g., memory system controller 215) and a memory device (e.g., memory device 230) as described herein. Figure 2 For example, the timing diagram can be performed by a memory system controller (e.g., memory system controller 215) and a memory device (e.g., memory device 230) as described herein. In some examples, the memory system controller can execute a set of codes to control the functional elements of the memory system to perform the functions described below. Figure 2 For example, the timing diagram can be performed by a memory system controller (e.g., memory system controller 215) and a memory device (e.g., memory device 230) as described herein. In some examples, the memory system controller can execute a set of codes to control the functional elements of the memory system to perform the functions described below. Figure 2 For example, the timing diagram can be performed by a memory system controller (e.g., memory system controller 215) and a memory device (e.g., memory device 230) as described herein. In some examples, the memory system controller can execute a set of codes to control the functional elements of the memory system to perform the functions described below. Figure 4A For example, the timing diagram can be performed by a memory system controller (e.g., memory system controller 215) and a memory device (e.g., memory device 230) as described herein. In some examples, the memory system controller can execute a set of codes to control the functional elements of the memory system to perform the functions described below. Figure 2 For example, the timing diagram can be performed by a memory system controller (e.g., memory system controller 215) and a memory device (e.g., memory device 230) as described herein. In some examples, the memory system controller can execute a set of codes to control the functional elements of the memory system to perform the functions described below.

[0060] In some cases, the timing diagram 400-b can illustrate a polling operation performed after one or more commands (e.g., including a snapshot read command) have been issued. For example, a plurality of snapshot read commands can have been previously issued, resulting in an operation allocation as illustrated in Figure 4A For example, the timing diagram can be performed by a memory system controller (e.g., memory system controller 215) and a memory device (e.g., memory device 230) as described herein. In some examples, the memory system controller can execute a set of codes to control the functional elements of the memory system to perform the functions described below. Figure 3 For example, the timing diagram can be performed by a memory system controller (e.g., memory system controller 215) and a memory device (e.g., memory device 230) as described herein. In some examples, the memory system controller can execute a set of codes to control the functional elements of the memory system to perform the functions described below.

[0061] In some examples, the cycle type 405 can indicate a current cycle of the memory system controller or memory device— for example, via a data bus (e.g., as referenced Figure 2The described data bus 205) conveys types of signals between a memory system controller and one or more memory devices. A DQ pin can be an instance of a data line 410 (e.g., a channel 410) on a data bus and a number of DQ pins on a memory system controller. In instances where the data bus is an eight (8) bit data bus, the data bus can include eight (8) data lines - e.g., data lines 0-7. In some instances, a memory device can be configured to output a state associated with a first queue slot of a selected state storage bank on a first channel of the data bus (e.g., DQ0) and a second state associated with a second queue slot on a second channel (e.g., DQ1) of the data bus. Figure 4A The described SR#) of a snapshot read command outputs a state on a given data bus. In instances where a memory device has multiple state storage banks, each queue slot can be associated with a dedicated channel of a data bus - e.g., memory device 230-a can be configured to output a first state associated with a first queue slot of a selected state storage bank on channel 0 (e.g., DQ0) and a second state associated with a second queue slot on channel 1 (e.g., DQ1).

[0062] In some cases, a CE 415 can indicate a chip enable signal transmitted by a memory system controller to a given memory device via a chip enable line (e.g., as described with reference to Figure 2 The described chip enable line 210) can transmit a chip enable signal to a given memory device. For example, CE 0 can indicate a chip enable signal driven to a first memory device. As described with reference to Figure 2 The described CE signal can be active low polarity. That is, a chip enable signal on a chip enable line 210 driven low can enable a memory device (e.g., to couple a data bus for commands, data input or output, or state output), and a chip enable signal driven high can disable a memory device (e.g., the memory device can decouple inputs and drivers from a data bus). Alternatively, the CE signal can operate in a similar manner using active high polarity.

[0063] At 420, a command can be transmitted. For example, a memory system controller can transmit a command (e.g., a second command) to a memory device via a data bus having fields “7Bh” and “SB#”. The memory system controller can transmit the command to request a state output from a particular state storage bank. For example, the SB# field can indicate a state storage bank selected to output state information therefrom. As described herein, the memory system controller can have initiated an operation at the memory device based on issuing a snapshot read command as described above with reference to Figure 4A The described snapshot read command can have initiated an operation at the memory device based on issuing a snapshot read command as described above with reference to Figure 3 The selected state storage bank can be configured as shown.

[0064] At 425, the status of the devices under test (Duts) can be received. For example, the memory system controller can receive the status from the status storage bank indicated by the command 420. The status of the devices can be received concurrently on channels 0 through 7 according to the operations assigned for the queue slots of the selected status storage bank. For example, as described with reference to Figure 3 The memory system controller can be configured to determine the memory die and plane associated with the status based on the mapping 320. In some examples, the memory devices can transmit “0b,” which can indicate that one or more planes associated with the status storage bank are busy. For example, each channel 410 can be driven by “0b” until the planes associated with the status storage bank have completed operations and are ready to accept service. For example, the first channel 410 (e.g., DQ0) can be driven by “0b” until plane 2 of the first memory die 325-a has completed operations and is ready for use as described with reference to Figure 3

[0065] Additionally, as described with reference to Figure 3 The status can be received from additional memory dies having planes associated with the queue slots of the selected status storage bank according to the command 420. For example, at 425, channel DQ[l] can be driven according to the status of D1P3 (e.g., plane 3 of memory die 325-b), channel DQ[2] can be driven according to the status of D2P2 (e.g., plane 2 of memory die 325-c), channel DQ[3] can be driven according to the status of D0P1 (e.g., plane 1 of memory die 325-a), channel DQ[4] can be driven according to the status of D3P1 (e.g., plane 1 of memory die 325-d), and channel DQ[7] can be driven according to the status of D1P0 (e.g., plane 0 of memory die 325-b), while channels DQ[5] and DQ[6] can not be associated with operations for any of the memory dies 325 for the selected status storage bank and thus can remain floating while each memory die 325 sets the driver to “Xb” (e.g., high impedance). Thus, at 425, any queue slots that have operations allocated within the status storage bank selected by the command at 420 (e.g., by a snapshot read command) can output the status of the respective operations. As shown Figure 4B

[0066] ​​At 430, another command can be transmitted. For example, the memory system controller can transmit a command to plane 2 of the first memory die 325-a based on the preparation of plane 2 to accept service as described with reference to Figure 3 The plane 2 of the first memory die 325-a described transmits the command. In some examples, the memory system can transmit a command to request data from the plane 2 of the first memory die 325-a associated with the completed operation. The transmitted command can indicate the type of command (e.g., a read command indicated by “06h”), column and row addresses (e.g., C&R Add), and additional information related to the second command (e.g., “E0h”). For example, the memory system controller can indicate that the read command is a single-plane read, a multi-plane read, a single-page read, a multi-page read, or a cache read after the transmission of the second command (e.g., by transmitting “E0h”).

[0067] At 435, data can be received. For example, the memory system controller can receive data from the plane 2 of the first memory die 325-a in response to the transmission of the command 430. In examples where the operation performed is a program operation, at step 435, the memory system controller can transmit data to the plane 2 of the first memory die 325-a. In other examples, when the operation is an erase operation, at step 435, the memory die 325-a can transmit a response to the memory system controller indicating that the operation has completed.

[0068] After 435, the memory system controller can transmit additional snapshot read commands or commands (e.g., second commands) to request states output from the same state storage (or a different state storage). For example, after reading data from the plane 2 of the first memory die, the memory system controller can transmit a second command to again request states output from the same state storage as indicated by the command at 420. Thus, the memory system controller can again perform a concurrent poll associated with the state storage to determine whether any additional planes or memory dies are ready for use and perform additional ready-for-use commands. By performing the concurrent poll by means of allocating operations for the queue slots of the state storage, the memory system controller can reduce latency and reduce additional power consumption. Further, the memory system controller can be configured to manage polling operations for a relatively large number of operations in parallel.

[0069] Figure 5 A block diagram 500 of a memory system controller 520 that supports dynamic state register arrays in accordance with examples as disclosed herein is shown. The memory system controller 520 can be as described with reference to Figure 1Examples of aspects of the memory system controller described at 4. The memory system controller 520, or various components thereof, can be examples of means for performing aspects of a dynamic status register array as described herein. For example, the memory system controller 520 can include a transmission component 525, a reception component 530, a determination component 535, or any combination thereof. Each of these components can communicate, directly or indirectly (e.g., via one or more buses), with one another.

[0070] The transmission component 525 can be configured as or otherwise support a means for transmitting, to a first memory die of a plurality of memory dies, a first command associated with a first operation, where the first command includes an assignment of the first operation for a queue slot of a status bank. In some examples, the transmission component 525 can be configured as or otherwise support a means for transmitting, to the first memory die, a second command based at least in part on transmitting the first command, where the second command requests a status associated with the status bank.

[0071] In some examples, the transmission component 525 can be configured as or otherwise support a means for transmitting, to a second memory die of the plurality of memory dies, a third command associated with a second operation after transmitting the first command, where the third command includes an assignment of the second operation for a second queue slot of the status bank. In some examples, the transmission component 525 can be configured as or otherwise support a means for concurrently transmitting, to the first memory die and the second memory die, the second command based at least in part on transmitting the first command and the third command, where the second command is further configured to request the status associated with the status bank from the second memory die.

[0072] In some examples, the transmission component 525 can be configured as or otherwise support a means for transmitting, to a first memory die of a plurality of memory dies, a fourth command associated with a third operation based at least in part on receiving an indication of completion of the first operation, where the fourth command includes an assignment of the third operation for the queue slot of the status bank. In some examples, the transmission component 525 can be configured as or otherwise support a means for transmitting the first command via an address channel or a data channel coupled with the first memory die, where the first command includes an association between the queue slot of the status bank and a first channel of the data bus.

[0073] The receiving component 530 can be configured as or otherwise support a means for receiving, via a first channel of the data bus determined based at least in part on an assigned queue slot of the state storage, a status based at least in part on a first operation to transmit a second command to the first memory die. In some examples, the receiving component 530 can be configured as or otherwise support a means for receiving, via a second channel of the data bus determined based at least in part on an assigned second queue slot of the state storage, a status based at least in part on a second operation to concurrently transmit the second command to the first memory die and the second memory die.

[0074] In some examples, the first command is configured to initiate the first operation on at least one plane of the first memory die, and the determining component 535 can be configured as or otherwise support a means for determining that the received status of the first operation is associated with the at least one plane of the first memory die based at least in part on the assigned queue slot of the state storage. In some examples, the determining component 535 can be configured as or otherwise support a means for determining that the received status of the first operation is associated with the at least one plane of the first memory die by identifying a mapping between the assigned queue slot of the state storage and the first memory die.

[0075] In some examples, the first memory die includes a plurality of queue slots for each of a plurality of state storages. In some examples, each queue slot of the plurality of queue slots for each of the plurality of state storages is associated with a respective channel of the data bus.

[0076] Figure 6 A block diagram 600 of a memory device 620 that supports dynamic state register arrays in accordance with examples as disclosed herein is shown. The memory device 620 can be an example of aspects of the memory devices as described with reference to Figures 1 to 4B The memory device 620, or various components thereof, can be an example of means for performing various aspects of dynamic state register arrays as described herein. For example, the memory device 620 can include a receiving component 625, a bit generation component 630, an output component 635, a queue assignment component 640, a mapping component 645, or any combination thereof. Each of these components can communicate, directly or indirectly, with one another (e.g., via one or more buses).

[0077] Receive component 625 can be configured as or otherwise support a means for receiving a first command associated with a first operation on data, where the first command includes an assignment of the first operation for a queue slot of a state storage. In some examples, receive component 625 can be configured as or otherwise support a means for receiving a second command requesting a state of the first operation based at least in part on receiving the first command, where the second command is associated with an output of the state of the state storage on a data bus coupled with a plurality of devices, a device of the plurality of devices including a memory array and a controller.

[0078] In some examples, receive component 625 can be configured as or otherwise support a means for receiving a third command associated with a second operation on data, where the third command is associated with a third plane of the memory array, and where the first command includes an assignment of the second operation for a second queue slot of the state storage different from the queue slot.

[0079] Bit generation component 630 can be configured as or otherwise support a means for generating a bit indicating a state of the first operation performed on the memory array based at least in part on receiving the second command.

[0080] Output component 635 can be configured as or otherwise support a means for outputting the bit onto a first channel of the data bus based at least in part on generating the bit and an association between the assigned queue slot of the state storage and the first channel.

[0081] In some examples, queue assignment component 640 can be configured as or otherwise support a means for assigning a queue slot for the first operation based at least in part on receiving the first command, where the first command is associated with a first plane of the memory array, where the generated bit indicates a state of the first operation performed on the first plane of the memory array, and outputting the bit onto the first channel of the data bus based at least in part on assigning the queue slot for the first operation.

[0082] In some examples, mapping component 645 can be configured as or otherwise support a means for storing a mapping between the assigned queue slot of the state storage and a first plane of the memory array associated with the first operation.

[0083] In some examples, a second channel of the data bus is associated with a concurrent output of a state of a second operation on a second plane of the memory array according to assigning a second queue slot of the state storage associated with the second channel for the second operation.

[0084] Figure 7A flow diagram illustrating a method 700 that supports dynamic status register array in accordance with examples as disclosed herein is shown. The operations of method 700 can be implemented by a memory system controller or its components as described herein. For example, the operations of method 700 can be performed by a memory system controller as described with reference to Figures 1 to 5 FIG. 1 through FIG. 7. In some examples, a memory system controller can execute a set of instructions to control the functional elements of a device to perform the described functions. Additionally or alternatively, the memory system controller can perform aspects of the described functions using special-purpose hardware.

[0085] At 705, the method can include transmitting, to a first memory die of a plurality of memory dies, a first command associated with a first operation, where the first command includes an assignment of the first operation for a queue slot of a status bank. Operation 705 can be performed according to examples as disclosed herein. In some examples, aspects of operation 705 can be performed by transmission component 525 as described with reference to Figure 5 FIG. 1 through FIG. 7. In some examples, a memory system controller can execute a set of instructions to control the functional elements of a device to perform the described functions. Additionally or alternatively, the memory system controller can perform aspects of the described functions using special-purpose hardware.

[0086] At 710, the method can include transmitting, to the first memory die based at least in part on transmitting the first command, a second command requesting a status associated with the status bank. Operation 710 can be performed according to examples as disclosed herein. In some examples, aspects of operation 710 can be performed by transmission component 525 as described with reference to Figure 5 FIG. 1 through FIG. 7. In some examples, a memory system controller can execute a set of instructions to control the functional elements of a device to perform the described functions. Additionally or alternatively, the memory system controller can perform aspects of the described functions using special-purpose hardware.

[0087] At 715, the method can include receiving, via a first channel of a data bus determined based at least in part on an assigned queue slot of the status bank, a status of the first operation based at least in part on transmitting the second command to the first memory die. Operation 715 can be performed according to examples as disclosed herein. In some examples, aspects of operation 715 can be performed by reception component 530 as described with reference to Figure 5 FIG. 1 through FIG. 7. In some examples, a memory system controller can execute a set of instructions to control the functional elements of a device to perform the described functions. Additionally or alternatively, the memory system controller can perform aspects of the described functions using special-purpose hardware.

[0088] In some examples, an apparatus as described herein can perform one or more methods, such as method 700. The apparatus can include features, circuitry, logic, means, or instructions (e.g., stored on a non-transitory computer-readable medium and executable by a processor) for transmitting, to a first memory die of a plurality of memory dies, a first command associated with a first operation, where the first command includes an assignment of the first operation for a queue slot of a status bank; transmitting, to the first memory die based at least in part on transmitting the first command, a second command requesting a status associated with the status bank; and receiving, via a first channel of a data bus determined based at least in part on an assigned queue slot of the status bank, a status of the first operation based at least in part on transmitting the second command to the first memory die.

[0089] Some examples of the method 700 and the apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for transmitting, to a second memory die of the plurality of memory dies, a third command associated with a second operation after transmitting the first command, where the third command includes allocating the second operation for a second queue slot of the state storage bank.

[0090] Some examples of the method 700 and the apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for concurrently transmitting, to the first memory die and the second memory die, a second command based at least in part on transmitting the first command and the third command, where the second command can be further configured to request a state associated with the state storage bank from the second memory die; and receiving a status of a second operation based at least in part on concurrently transmitting the second command to the first memory die and the second memory die via a second channel of a data bus determined based at least in part on the allocated second queue slot of the state storage bank.

[0091] In some examples of the method 700 and the apparatus described herein, the method, apparatus, and non-transitory computer-readable medium can include further operations, features, circuitry, logic, means, or instructions for transmitting, to a first memory die of the plurality of memory dies, a fourth command associated with a third operation based at least in part on receiving the indication that the first operation is complete, where the fourth command includes allocating the third operation for a queue slot of the state storage bank.

[0092] In some examples of the method 700 and the apparatus described herein, the first command can be configured to initiate the first operation on at least one plane of the first memory die, and the method, apparatus, and non-transitory computer-readable medium can include further operations, features, circuitry, logic, means, or instructions for determining that the received status of the first operation can be associated with the at least one plane of the first memory die based at least in part on the allocated queue slot of the state storage bank.

[0093] Some examples of the method 700 and the apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for determining that the received status of the first operation can be associated with the at least one plane of the first memory die by identifying a mapping between the allocated queue slot of the state storage bank and the first memory die.

[0094] Some examples of the method 700 and the apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for transmitting, via an address channel or a data channel coupled with the first memory die, a first command, where the first command includes an association between a queue slot of a state bank and a first channel of a data bus.

[0095] In some examples of the method 700 and the apparatus described herein, the first memory die includes a plurality of queue slots for each of a plurality of state banks, where each queue slot of the plurality of queue slots for each of the plurality of state banks can be associated with a respective channel of a data bus.

[0096] Figure 8 A flow chart illustrating a method 800 of supporting a dynamic state register array in accordance with examples as disclosed herein is shown. The operations of method 800 can be implemented by a memory device or its components as described herein. For example, the operations of method 800 can be performed by a memory device as described with reference to Figure 1 FIGS. 1 through 6. In some examples, a memory device can execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory device can perform various ones of the described functions using special-purpose hardware.

[0097] At 805, the method can include receiving a first command associated with a first operation on data, where the first command includes an assignment of the first operation for a queue slot of a state bank. Operation 805 can be performed according to examples as disclosed herein. In some examples, aspects of operation 805 can be performed by a receiving component 625 as described with reference to Figure 6 FIGS. 1 through 6. In some examples, a memory device can execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory device can perform various ones of the described functions using special-purpose hardware.

[0098] At 810, the method can include receiving, based at least in part on receiving the first command, a second command requesting a state of the first operation, where the second command is associated with an output of the state of the state bank on a data bus coupled with a plurality of devices, a device of the plurality of devices including a memory array and a controller. Operation 810 can be performed according to examples as disclosed herein. In some examples, aspects of operation 810 can be performed by a receiving component 625 as described with reference to Figure 6 FIGS. 1 through 6. In some examples, a memory device can execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory device can perform various ones of the described functions using special-purpose hardware.

[0099] At 815, the method can include generating, based at least in part on receiving the second command, a bit indicating a state of the first operation performed on the memory array. Operation 815 can be performed according to examples as disclosed herein. In some examples, aspects of operation 815 can be performed by a bit generating component 630 as described with reference to Figure 6 FIGS. 1 through 6. In some examples, a memory device can execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory device can perform various ones of the described functions using special-purpose hardware.

[0100] At 820, the method can include outputting the bit onto a first channel of the data bus based at least in part on generating the bit and an association between the allocated queue slot of the status storage and the first channel. Operation 820 can be performed according to examples as disclosed herein. In some examples, aspects of operation 820 can be performed by an output component 635 as described with reference to Figure 6

[0101] In some examples, an apparatus as described herein can perform one or more methods, such as method 800. The apparatus can include features, circuitry, logic, means, or instructions (e.g., instructions stored on a non-transitory computer-readable medium that are executable by a processor) for receiving a first command associated with a first operation on data, where the first command includes an allocation of the first operation for a queue slot of a status storage; receiving a second command requesting a status of the first operation based at least in part on receiving the first command, where the second command is associated with an output of the status of the status storage on a data bus coupled with a plurality of devices, a device of the plurality of devices including a memory array and a controller; generating a bit indicating the status of the first operation performed on the memory array based at least in part on receiving the second command; and outputting the bit onto a first channel of the data bus based at least in part on generating the bit and an association between the allocated queue slot of the status storage and the first channel.

[0102] Some examples of the method 800 and apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for allocating the queue slot for the first operation based at least in part on receiving the first command, where the first command can be associated with a first plane of the memory array, where the generated bit indicates the status of the first operation performed on the first plane of the memory array, and the bit can be output onto the first channel of the data bus based at least in part on allocating the queue slot for the first operation.

[0103] In some examples of the method 800 and apparatus described herein, a second channel of the data bus can be associated with a concurrent output of a status associated with a second operation on a second plane of the memory array according to allocating a second queue slot of the status storage associated with the second channel for the second operation.

[0104] Some examples of the method 800 and apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for storing a mapping between the allocated queue slot of the status storage and a first plane of the memory array that can be associated with the first operation.

[0105] ​Some examples of the method 800 and apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for receiving a third command associated with a second operation on data, where the third command can be associated with a third plane of a memory array, and where the first command includes allocating the second operation to a second queue slot of a state storage bank that can be different from the queue slot.

[0106] It should be noted that the methods described above describe possible implementations, and that the operations and the steps can be rearranged or otherwise modified and that other implementations are possible. Furthermore, portions from two or more of the methods can be combined.

[0107] An apparatus is described. The apparatus can include a plurality of memory dies, a data bus coupled with each of the plurality of memory dies, and a controller coupled with each of the plurality of memory dies via the data bus, the controller configured to transmit a first command associated with a first operation to a first memory die of the plurality of memory dies, where the first command includes allocating the first operation to a queue slot of a state storage bank, transmit a second command to the first memory die based at least in part on transmitting the first command, where the second command requests a state associated with the state storage bank, and receive the state of the first operation based at least in part on transmitting the second command to the first memory die via a first lane of the data bus determined based at least in part on the allocated queue slot of the state storage bank.

[0108] An apparatus is described. The apparatus can include a memory array comprising a plurality of memory cells configured to store data, a controller coupled with the memory array and configured to receive a first command associated with a first operation on the data, where the first command includes allocating the first operation to a queue slot of a state storage bank, receive a second command requesting a state of the first operation based at least in part on receiving the first command, where the second command is associated with an output of the state of the state storage bank on a data bus coupled with a plurality of devices, a device of the plurality of devices including the memory array and the controller, generate a bit indicating the state of the first operation performed on the memory array based at least in part on receiving the second command, and output the bit on a first lane of the data bus based at least in part on generating the bit and an association between the allocated queue slot of the state storage bank and the first lane.

[0109] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings can illustrate signals as single signals; however, such signals can represent a bus of signals, where the bus can have a variety of bit widths.

[0110] The terms“electronically communicates,”“electrically contacts,”“connected,” and“coupled” can refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication with each other (or electrically contact each other, or are connected to each other, or are coupled to each other) if there is any conductive path that can support the flow of signals between the components at any time. The conductive path between components that are in electronic communication with each other (or electrically contact each other, or are connected to each other, or are coupled to each other) can be an open circuit or a closed circuit at any given time, based on the operation of the device that includes the connected components. The conductive path between connected components can be a direct conductive path between the components, or the conductive path between connected components can be an indirect conductive path that can include intermediate components such as switches, transistors, or other components. In some examples, the flow of signals between connected components can be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0111] The term“coupled” refers to the condition of components moving from an open circuit relationship between the components, in which signals cannot currently pass between the components through a conductive path, to a closed circuit relationship between the components, in which signals can pass between the components through the conductive path. If a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components through a conductive path in which signals were not previously permitted to flow.

[0112] The term“isolated” refers to a relationship between components in which signals cannot currently flow between the components. Components are isolated from each other if there is an open circuit between the components. For example, components that are separated by a switch positioned between the two components are isolated from each other when the switch is open. If a controller isolates two components, the controller implements a change that prevents signals from flowing between the components using a conductive path in which signals were previously permitted to flow.

[0113] The terms“if,”“when,”“based on,” or“based at least in part on” can be used interchangeably. In some examples, the terms“if,”“when,”“based on,” or“based at least in part on” can be used interchangeably to describe a conditional relationship between two or more processes, actions, or other events.

[0114] The term "in response to" can refer to a condition or action that occurs at least partially, if not entirely, as a result of a prior condition or action. For example, a first condition or action can be performed, and a second condition or action can occur at least partially as a result of the occurrence of the prior condition or action, whether directly after the first condition or action or after one or more other intervening conditions or actions after the first condition or action.

[0115] Additionally, the term "directly in response to" or "directly responsive to" can refer to a condition or action that occurs as a direct result of a prior condition or action. In some examples, a first condition or action can be performed, and a second condition or action can occur directly as a result of the occurrence of the prior condition or action, independent of whether other conditions or actions occur. In some examples, a first condition or action can be performed, and a second condition or action can occur directly as a result of the occurrence of the prior condition or action, such that no other intervening conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intervening steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being performed "based on," "at least in part on," or "in response to" some other step, action, event, or condition can additionally or alternatively (e.g., in alternative examples) be performed "directly in response to" or "directly in response to" such other condition or action.

[0116] Devices discussed herein that include memory arrays can be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In some other examples, the substrate can be a silicon-on-insulator (SOI) substrate such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or sub-regions of the substrate can be controlled by doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0117] The switching components or transistors discussed herein can represent field effect transistors (FETs) and include three-terminal devices that include a source, a drain, and a gate. The terminals can be connected to other electronic elements by conductive materials, such as metals. The source and drain can be conductive and can include heavily doped (e.g., degenerate) semiconductor regions. The source and drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., majority carriers are electrons), the FET can be referred to as an n-type FET. If the channel is p-type (i.e., majority carriers are holes), the FET can be referred to as a p-type FET. The channel can be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type or p-type FET, respectively, can render the channel conductive. A transistor can be "on" or "activated" if a voltage greater than or equal to the threshold voltage of the transistor is applied to the gate of the transistor. A transistor can be "off' or "deactivated" if a voltage less than the threshold voltage of the transistor is applied to the gate of the transistor.

[0118] The description set forth herein, in connection with the appended drawings, describes example configurations and does not represent all the instances that can be implemented or that are within the scope of the claims. The term "exemplary" used herein means "serving as an example, instance, or illustration," and not "preferred" over other instances. The detailed description includes specific details for the purpose of providing an understanding of the described techniques. These techniques, however, can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts described herein.

[0119] In the appended figures, similar components or features can have the same reference label. Further, various components of the same type can be distinguished by following the convention, in which the first digit or digits identify the component, the second digit identifies the number of that component, and the third digit identifies a specific instance of the component. The specific instances of generally similar components of the same type need not be distinguished when there are no instances in which more than one of those generally similar components exist.

[0120] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described above can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions can also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.

[0121] For example, various illustrative blocks and components described in connection with the disclosure herein can be implemented or performed with a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor can be a microprocessor; but in the alternative, the processor can be any processor, controller, microcontroller, or state machine. A processor can be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0122] As used herein, including in the claims,“or” as used in a list of items (for example, a list of items prefaced by a term such as“at least one of’ or“one or more of’) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as

[0123] Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium can be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, ROM, electrically erasable programmable read only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program elements in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray® disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0124] The description herein is presented to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus for storing data, comprising: a plurality of memory dies; a data bus coupled with each of the plurality of memory dies; and a controller coupled with each of the plurality of memory dies via the data bus, the controller configured to: transmit, to a first memory die of the plurality of memory dies, a first command associated with a first operation, wherein the first command comprises an assignment of the first operation for a queue slot of a state storage bank; transmit, to the first memory die based at least in part on transmitting the first command, a second command requesting a state associated with the state storage bank; transmit, to a second memory die of the plurality of memory dies after transmitting the first command, a third command associated with a second operation, wherein the third command comprises a second assignment of the second operation for a second queue slot of the state storage bank; and receive, based at least in part on transmitting the second command to the first memory die, the state of the first operation via a first channel of the data bus determined based at least in part on the assigned queue slot of the state storage bank.

2. The apparatus of claim 1, wherein receiving the state of the first operation comprises receiving an indication of completion of the first operation, wherein the controller is further configured to: transmit, to the first memory die of the plurality of memory dies based at least in part on receiving the indication of completion of the first operation, a fourth command associated with a third operation, wherein the fourth command comprises a third assignment of the third operation for the queue slot of the state storage bank.

3. The apparatus of claim 1, wherein the first command is configured to initiate the first operation on at least one plane of the first memory die, wherein the controller is further configured to: determine that a received state of the first operation is associated with the at least one plane of the first memory die based at least in part on the assigned queue slot of the state storage bank.

4. The apparatus of claim 3, wherein the controller is further configured to: determine that the received state of the first operation is associated with the at least one plane of the first memory die by identifying a mapping between the assigned queue slot of the state storage bank and the first memory die.

5. The apparatus of claim 1, wherein the controller is further configured to: transmit the first command via an address channel or a data channel coupled with the first memory die, wherein the first command comprises an association between the queue slot of the state storage bank and the first channel of the data bus.

6. An apparatus for storing data, comprising: a plurality of memory dies; a data bus coupled with each of the plurality of memory dies; and a controller coupled with each of the plurality of memory dies via the data bus, the controller configured to: transmitting a first command associated with a first operation to a first memory die of the plurality of memory dies, wherein the first command comprises an assignment of the first operation for a queue slot of a state storage bank; transmitting a second command to the first memory die based at least in part on transmitting the first command, wherein the second command requests a state associated with the state storage bank; transmitting a third command associated with a second operation to a second memory die of the plurality of memory dies after transmitting the first command, wherein the third command comprises a second assignment of the second operation for a second queue slot of the state storage bank; concurrently transmitting the second command to the first memory die and the second memory die based at least in part on transmitting the first command and the third command, wherein the second command is further configured to request the state associated with the state storage bank from the second memory die; receiving the state of the first operation based at least in part on transmitting the second command to the first memory die via a first lane of the data bus determined based at least in part on the assigned queue slot of the state storage bank; and receiving the state of the second operation based at least in part on concurrently transmitting the second command to the first memory die and the second memory die via a second lane of the data bus determined based at least in part on the assigned second queue slot of the state storage bank.

7. An apparatus for storing data, comprising: a plurality of memory dies; a data bus coupled with each of the plurality of memory dies; and a controller coupled with each of the plurality of memory dies via the data bus, the controller configured to: transmit a first command associated with a first operation to a first memory die of the plurality of memory dies, wherein the first command comprises an assignment of the first operation for a queue slot of a state storage bank, wherein the first memory die comprises a plurality of queue slots of each of a plurality of state storage banks, wherein each queue slot of the plurality of queue slots of each of the plurality of state storage banks is associated with a respective lane of the data bus; transmit a second command to the first memory die based at least in part on transmitting the first command, wherein the second command requests a state associated with the state storage bank; and receive the state of the first operation based at least in part on transmitting the second command to the first memory die via a first lane of the data bus determined based at least in part on the assigned queue slot of the state storage bank.

8. An apparatus for storing data, comprising: a memory array comprising a plurality of memory cells configured to store data; and a controller coupled with the memory array and configured to: receive a first command associated with a first operation on the data, wherein the first command comprises an assignment of the first operation for a queue slot of a state storage bank; transmit a second command to the first memory die based at least in part on transmitting the first command, wherein the second command requests a state associated with the state storage bank; receive a second command requesting a status of the first operation based at least in part on receiving the first command, wherein the second command is associated with an output of the status of the status storage associated with a data bus coupled to a plurality of devices, a device of the plurality of devices comprising the memory array and the controller; receive a third command associated with a second operation on the data, wherein the third command is associated with a third plane of the memory array, and wherein the third command comprises a second allocation of the second operation allocated to a second queue slot of the status storage different from the queue slot; generate a bit indicating the status of the first operation performed on the memory array based at least in part on receiving the second command; and output the bit onto a first channel of the data bus based at least in part on generating the bit and an association between the allocated queue slot of the status storage and the first channel of the data bus.

9. The apparatus of claim 8, wherein the controller is further configured to: allocate the queue slot for the first operation based at least in part on receiving the first command, wherein the first command is associated with a first plane of the memory array, wherein the generated bit indicates the status of the first operation performed on the first plane of the memory array, and output the bit onto the first channel of the data bus based at least in part on allocating the queue slot for the first operation.

10. The apparatus of claim 9, wherein the second channel of the data bus is associated with a concurrent output of a second status associated with the second operation on a second plane of the memory array in accordance with the second allocation of the second operation allocated to the second queue slot of the status storage associated with the second channel of the data bus.

11. The apparatus of claim 9, wherein the controller is further configured to: store a mapping between the allocated queue slot of the status storage and the first plane of the memory array associated with the first operation.

12. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of a memory device, cause the memory device to: transmit a first command associated with a first operation to a first memory die of a plurality of memory dies, wherein the first command comprises an allocation of the first operation to a queue slot of a status storage; transmit a second command to the first memory die based at least in part on transmitting the first command, wherein the second command requests a status associated with the status storage; transmit a third command associated with a second operation to a second memory die of the plurality of memory dies after transmitting the first command, wherein the third command comprises a second allocation of the second operation to a second queue slot of the status storage; and transmit a bit indicating the status of the first operation performed on the memory array based at least in part on receiving the second command. a first lane of a data bus determined based at least in part on an assigned queue slot of the state storage, receiving a status of the first operation based at least in part on transmitting the second command to the first memory die.

13. The non-transitory computer-readable medium of claim 12, wherein the instructions, which when executed by the processor of the memory device, further cause the memory device to: transmit the second command concurrently to the first memory die and the second memory die based at least in part on transmitting the first command and the third command, wherein the second command is further configured to request the status associated with the state storage from the second memory die; and receive the status of the second operation based at least in part on concurrently transmitting the second command to the first memory die and the second memory die via a second lane of the data bus determined based at least in part on an assigned second queue slot of the state storage.

14. The non-transitory computer-readable medium of claim 12, wherein receiving the status of the first operation comprises receiving an indication of completion of the first operation, wherein the instructions, which when executed by the processor of the memory device, further cause the memory device to: transmit a fourth command associated with a third operation to the first memory die of the plurality of memory dies based at least in part on receiving the indication of completion of the first operation, wherein the fourth command comprises a third assignment of the queue slot of the state storage for the third operation.

15. The non-transitory computer-readable medium of claim 12, wherein the first command is configured to initiate the first operation on at least one plane of the first memory die, wherein the instructions, which when executed by the processor of the memory device, further cause the memory device to: determine that a received status of the first operation is associated with the at least one plane of the first memory die based at least in part on the assigned queue slot of the state storage.

16. The non-transitory computer-readable medium of claim 15, wherein the instructions, which when executed by the processor of the memory device, further cause the memory device to: determine that the received status of the first operation is associated with the at least one plane of the first memory die by identifying a mapping between the assigned queue slot of the state storage and the first memory die.

17. The non-transitory computer-readable medium of claim 12, wherein the instructions, which when executed by the processor of the memory device, further cause the memory device to: transmit the first command via an address lane or a data lane coupled with the first memory die, wherein the first command comprises an association between the queue slot of the state storage and the first lane of the data bus.

18. The non-transitory computer-readable medium of claim 12, wherein the first memory die comprises a plurality of queue slots for each of a plurality of state storage banks, wherein each queue slot of the plurality of queue slots for each of the plurality of state storage banks is associated with a respective lane of the data bus.

19. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of a memory device, cause the memory device to: receive a first command associated with a first operation on data, wherein the first command comprises an assignment of the first operation for a queue slot of a state storage bank; receive, based at least in part on receiving the first command, a second command requesting a status of the first operation, wherein the second command is associated with an output of the status of the state storage bank on a data bus coupled with a plurality of devices, a device of the plurality of devices comprising a memory array; receive a third command associated with a second operation on the data, wherein the third command is associated with a third plane of the memory array, and wherein the third command comprises a second assignment of the second operation for a second queue slot of the state storage bank different from the queue slot; generate, based at least in part on receiving the second command, a bit indicating the status of the first operation performed on the memory array; and output the bit on a first lane of the data bus based at least in part on generating the bit and an association between the assigned queue slot of the state storage bank and the first lane of the data bus.

20. The non-transitory computer-readable medium of claim 19, wherein the instructions, when executed by the processor of the memory device, further cause the memory device to: assign the queue slot for the first operation based at least in part on receiving the first command, wherein the first command is associated with a first plane of the memory array, wherein the generated bit indicates the status of the first operation performed on the first plane of the memory array, and output the bit on the first lane of the data bus based at least in part on assigning the queue slot for the first operation.

21. The non-transitory computer-readable medium of claim 20, wherein the second lane of the data bus is associated with a concurrent output of a second status associated with the second operation on a second plane of the memory array in accordance with the second assignment of the second operation for the second queue slot of the state storage bank associated with the second lane of the data bus.

22. The non-transitory computer-readable medium of claim 20, wherein the instructions, when executed by the processor of the memory device, further cause the memory device to: store a mapping between the assigned queue slot of the state storage bank and the first plane of the memory array associated with the first operation.

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