Array refresh state determination circuit and method, refresh circuit, electronic device

Abstract

The present disclosure relates to an array refresh state determination circuit, an array refresh state determination method, a refresh circuit and an electronic device, and relates to the technical field of integrated circuits. The array refresh state determination circuit comprises: a refresh array determination module, configured to determine the refresh activation state of each array within a single array refresh period; and an array refresh state determination module, configured to determine the refresh state of each array according to the refresh activation state of each array. The present disclosure provides an array refresh state determination circuit suitable for DDR5.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular, to an array refresh state determination circuit, an array refresh state determination method, a refresh circuit and an electronic device. BACKGROUND

[0002] Double Data Rate fifth-generation Synchronous Dynamic Random-Access Memory (DDR5 SDRAM) is a kind of high-bandwidth computer storage module.

[0003] The refresh command of DDR5 contains a single array refresh command. Under the single array refresh command, only one array is refreshed each time. It is usually desired that all arrays can be refreshed within a single array refresh period.

[0004] Therefore, in order to monitor the refresh status of all arrays within a single array refresh period, it becomes an urgent problem to determine an array refresh state determination circuit suitable for DDR5.

[0005] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0006] The purpose of the present disclosure is to provide an array refresh state determination circuit, an array refresh state determination method, a refresh circuit and an electronic device, so as to provide an array refresh state determination circuit suitable for DDR5.

[0007] Other characteristics and advantages of the present disclosure will become apparent from the following detailed description, or will be learned by practice of the present disclosure.

[0008] According to a first aspect of the present disclosure, an array refresh state determination circuit is provided, comprising:

[0009] A refresh array determination module is configured to determine the refresh activation state of each array within a single array refresh period.

[0010] An array refresh state determination module is configured to determine the refresh state of each array according to the refresh activation state of each array.

[0011] According to a second aspect of the present disclosure, an array refresh state determination method is provided, comprising:

[0012] Under the single array refresh period command, the refresh activation state of each array is determined.

[0013] According to the refresh activation state of each array, a refresh state of each array is determined.

[0014] According to a third aspect of the present disclosure, there is provided a refresh circuit comprising the array refresh state determination circuit described above.

[0015] According to a fourth aspect of the present disclosure, there is provided an electronic device comprising:

[0016] a plurality of arrays;

[0017] an array control unit, wherein the array refresh state determination circuit described above is arranged in the array control unit.

[0018] The technical solutions provided by the present disclosure can have the following beneficial effects:

[0019] The array refresh state determination circuit provided by the exemplary embodiments of the present disclosure can preliminarily count the refresh state of each array by determining the refresh activation state of each array in a single array refresh period; then, the refresh state of each array can be determined according to the refresh activation state of each array, so that the refresh state of each array can be counted to determine whether a refresh cycle is completed in a single array refresh period. Similarly, the refresh address count that has been refreshed under a single array refresh command can be implemented.

[0020] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and are not intended to limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0021] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure. It should be apparent to those skilled in the art that the accompanying drawings are only some embodiments of the present disclosure, and other drawings can be obtained from the accompanying drawings without creative labor. In the drawings:

[0022] Figure 1 a block diagram of an array refresh state determination circuit according to an exemplary embodiment of the present disclosure is schematically shown;

[0023] Figure 2 a circuit diagram of a refresh array determination module according to an exemplary embodiment of the present disclosure is schematically shown;

[0024] Figure 3 a circuit diagram of an array refresh state determination module according to an exemplary embodiment of the present disclosure is schematically shown;

[0025] Figure 4 FIG. 6 schematically illustrates a block diagram of another array refresh state determination circuit according to an example embodiment of the present disclosure;

[0026] Figure 5 FIG. 7 schematically illustrates a circuit diagram of a reset signal generation module according to an example embodiment of the present disclosure;

[0027] Figure 6 FIG. 8 schematically illustrates a circuit diagram of a determination refresh period signal according to an example embodiment of the present disclosure;

[0028] Figure 7 FIG. 9 schematically illustrates a flowchart of an array refresh state determination method according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, however, can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the description.

[0030] Moreover, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring aspects of the disclosure.

[0031] The block diagrams in the drawings show only the functionality of the various embodiments and do not imply any particular physical or architectural arrangement of the components. For example, the functions could be provided in software, hardware, or a combination thereof. Connections can be logical or physical, and can be implemented by software programs, electronic circuits, or other means. Any of the depicted connections can also be implemented as a bus. Some of the connections can be implemented directly between components, while others can be implemented through one or more intermediary components.

[0032] DDR4 is the abbreviation of the fourth generation of DDR SDRAM, and DDR5 is the abbreviation of the fifth generation of DDR SDRAM. DDR SDRAM is the abbreviation of Double Data Rate SDRAM in English, which is translated as double data rate SDRAM in Chinese. SDRAM is the abbreviation of Synchronous Dynamic Random Access Memory, which is translated as synchronous dynamic random access memory. Therefore, in combination, DDR4 is the fourth generation of double data rate synchronous dynamic random access memory, and DDR5 is the fifth generation of double data rate synchronous dynamic random access memory. From DDR4 to DDR5, the refresh instruction is changed from a single refresh command to a full array refresh command REFab (Refresh All BANK) and a single array refresh command REFsb (Refresh Same BANK). Among them, a full array refresh command REFab refreshes all arrays (BANK), and a single array refresh command REFsb only refreshes one array.

[0033] For the case of single array refresh, a series of single array refresh commands REFsb are usually issued in a refresh cycle to refresh all arrays. Only when all arrays have been refreshed under the single array refresh command REFsb, it means that the current refresh cycle is complete.

[0034] In order to count the refresh state of all arrays in a refresh cycle under the single array refresh command REFsb, so as to master the refresh state of each array and facilitate to determine whether all arrays are refreshed under a series of single array refresh commands REFsb. The exemplary embodiments of the present disclosure provide an array refresh state determination circuit, which can be used in DDR5 or other memories containing single array refresh command REFsb, and the exemplary embodiments of the present disclosure do not make special limitation.

[0035] Referring to Figure 1 The array refresh state determination circuit 100 can include a refresh array determination module 120 and an array refresh state determination module 140; wherein,

[0036] The refresh array determination module 120 can be used to determine the refresh activation state of each array in a single array refresh period.

[0037] In the exemplary embodiments of the present disclosure, the single array refresh period refers to the above-mentioned single array refresh command REFsb in a refresh cycle. In a single array refresh period, multiple single array refresh commands REFsb are usually issued to ensure that each array can be refreshed.

[0038] In the exemplary embodiment of the present disclosure, in a single-array refresh period, the array that executes the single-array refresh command REFsb is equivalent to the refresh state of the array being activated, and the refresh state of the array can be preliminarily counted through the refresh activation state.

[0039] The array refresh state determination module 140 can be configured to determine the refresh state of each array according to the refresh activation state of each array.

[0040] According to the refresh activation state of each array determined above, the refreshed array and the un-refreshed array can be distinguished, so that the refresh state of the array can be determined according to the refresh activation state. The refresh state of the array can indicate whether the array is refreshed in a single-array refresh period, so that it can be determined whether a refresh cycle is completed. Since a refresh cycle can be completed only when all arrays are refreshed, the refresh state of each array can be determined to determine whether a refresh cycle is completed in a single-array refresh period.

[0041] The array refresh state determination circuit provided by the exemplary embodiment of the present disclosure can preliminarily count the refresh state of each array by determining the refresh activation state of each array in a single-array refresh period, and then determine the refresh state of each array according to the refresh activation state of each array, so that the refresh state of each array can be counted to determine whether a refresh cycle is completed in a single-array refresh period. Similarly, the refresh address count that is refreshed under the single-array refresh command can be implemented.

[0042] In the exemplary embodiment of the present disclosure, the refresh array determination module 120 can be configured to output the refresh activation signal REFsbact corresponding to the array when the array is refreshed at least once in a single-array refresh period. That is, as long as an array is refreshed once in a single-array refresh period, the refresh activation signal REFsbact is output to mark, so that the count of the refreshed array can be implemented.

[0043] Specifically, referring to Figure 2 The exemplary embodiment of the present disclosure provides a circuit diagram of the refresh array determination module. In Figure 2 The refresh array determination module 120 includes a plurality of XOR gates 121 and a plurality of first AND gates 122, wherein the number of XOR gates 121 is the same as the number of arrays, one XOR gate 121 corresponds to one array, and one XOR gate 121 corresponds to only one first AND gate 122.

[0044] In actual application, the number of XOR gates 121 is determined by the number of arrays, and the number of arrays is determined according to actual conditions. For example, in Figure 2In the embodiment, there are four arrays in total, and the preset array addresses of the four arrays can be marked as BA1, BA2, BA3 and BA4.

[0045] In the exemplary embodiment of the present disclosure, the input ends of each of the exclusive OR gates 121 are connected to the preset array addresses BA1, BA2, BA3 or BA4 and the refreshed array address REF_BA, and the output end of each of the exclusive OR gates 121 is connected to one of the input ends of the corresponding first AND gate 122; the other input end of the first AND gate 122 is connected to the single-array refresh command REFsb, and the output end of the first AND gate 122 outputs the refresh activation signal REFsbact1, REFsbact2, REFsbact3 or REFsbact4.

[0046] In actual application, if one array is refreshed, the preset array address of the array input into the exclusive OR gate 121 is the same as the refreshed array address REF_BA. Assuming that the first array is refreshed, the refreshed array address REF_BA becomes BA1, and the two addresses input into the exclusive OR gate 121 corresponding to the first array are equal, at this time, the exclusive OR gate 121 outputs low level 0, and the first AND gate 122 outputs low level 0 as well, and the low level signal output by the first AND gate 122 is the refresh activation signal REFsbact1. After that, even if the first array is refreshed again, the refresh activation signal REFsbact1 will not change.

[0047] In addition, in the case that other arrays are not refreshed, the exclusive OR gates 121 corresponding to the other arrays output high level 1. The high level 1 and the single-array refresh command REFsb pass through the first AND gate 122, so that the first AND gate 122 outputs high level 1. In these other arrays, when one array is refreshed, the first AND gate 122 also outputs low level 0.

[0048] That is, in the refresh array determination module 120 shown in the figure, when the refresh activation signal REFsbact is low level 0, it means that the array has been refreshed at least once; when the refresh activation signal REFsbact is high level 1, it means that the array has not been refreshed. Through the refresh activation signal, the refresh situation of each array can be counted. Figure 2

[0049] ​In addition, the refresh array determination module 120 provided by the example embodiments of the present disclosure can not only output the refresh activation signal REFsbact when one array is refreshed at least once, i.e., generate the refresh activation signal REFsbact when the array is refreshed for the first time, but also maintain the refresh activation signal REFsbact unchanged after the array is refreshed multiple times in the single array refresh period, so as to achieve the purpose of marking the refreshed array.

[0050] In the example embodiments of the present disclosure, the array refresh state determination module 140 can be configured to determine the refresh state signal REFstutus of each array according to the refresh activation signal REFsbact. The refresh state signal REFstutus can mark the final refresh state of the array.

[0051] The circuit structure of the array refresh state determination module 140 will be described below by taking the case of high level effective as an example. In the example embodiments of the present disclosure, the array refresh state determination module 140 can include a plurality of counters 141 and a plurality of inverters 142. The number of the counters 141 is the same as the number of the arrays, one counter 141 corresponds to one array, one counter 141 corresponds to the above-mentioned one first AND gate 122, and one counter 141 also corresponds to one inverter 142.

[0052] With Figure 2 The refresh array determination module 120 is provided in correspondence with the above-mentioned refresh array determination module 120. Figure 3 The example embodiments of the present disclosure provide a circuit diagram of an array refresh state determination module. In the example embodiments of the present disclosure, the array refresh state determination module 140 can include a plurality of counters 141 and a plurality of inverters 142. Figure 3 In the example embodiments of the present disclosure, the counter 141 has four, and the corresponding inverter 142 also has four.

[0053] In the example embodiments of the present disclosure, the set end of the counter 141 can be connected to the refresh activation signal REFsbact1, REFsbact2, REFsbact3 or REFsbact4, and the reset end of the counter 141 can be connected to the reset signal RSTB. The reset signal RSTB is a signal used when the refresh state signal REFstutus is reset. The output end of the counter 141 is connected to the input end of the inverter 142, and the output end of the inverter 142 outputs the refresh state signal REFstutus1, REFstutus2, REFstutus3 or REFstutus4.

[0054] In actual application, when the reset signal RSTB is low 0, the output refresh status signal REFstutus can be reset to 0. When the reset signal RSTB is high 1, if the output of the first AND gate 122 is low 0, the output refresh status signal REFstutus after the counter 141 and the inverter 142 is high 1. If the output of the first AND gate 122 is high 1, the output refresh status signal REFstutus is determined by the value of the last time, and the refresh status signal REFstutus can be changed under the influence of the low 0 output of the corresponding first AND gate 122 or the reset signal RSTB.

[0055] That is, the final output refresh status signal REFstutus can be determined according to the refresh activation signal REFsbact. If an array is refreshed, the corresponding refresh status signal REFstutus is high 1. In order to distinguish from other arrays that are not refreshed, the reset signal RSTB can be used to reset the reset end of the counter 141 at the beginning of the single array refresh period, so that the output refresh status signal REFstutus of all inverters 142 is low 0. Then, the reset signal RSTB is set to high 1. At this time, only when the refresh activation signal REFsbact is low 0, the refresh status signal REFstutus is changed to high 1, that is, the refresh status signal REFstutus of the array to be refreshed is high 1, and the refresh status signal REFstutus of the array not to be refreshed is low 0.

[0056] The above circuit structure corresponds to the high level effective case. In the low level effective case, the array refresh status determination module 140 can only include a plurality of counters 141, and the above plurality of inverters 142 can be removed. The logic principle is the same as above, which will not be described here.

[0057] In the exemplary embodiments of the present disclosure, the counter 141 can be a latch, for example, an SR latch. Under the action of the SR latch, even if the same array is repeatedly refreshed, the counter 141 will not be accumulated, so that the refresh order between arrays does not need to be considered, and the logic structure is simple.

[0058] The array refresh status determination module 140 provided by the exemplary embodiments of the present disclosure can count the refresh activation signal REFsbact according to actual needs through the reset signal RSTB, and obtain the corresponding valid refresh status signal REFstutus when the array is refreshed. In the case of repeated refreshing of the array, the validity of the refresh status signal REFstutus will not be changed, so as to achieve the purpose of counting the refreshed array.

[0059] Referring to Figure 4 The array refresh state determination circuit 100 provided by the example embodiment of the present disclosure can further include a reset signal generation module 160. The reset signal generation module 160 can be configured to generate a reset signal RSTB according to the full array refresh command REFab, the self refresh command SREF, the system reset signal RST, and the refresh cycle signal REF_1CYCLE, and the reset signal RSTB is used to reset the refresh state of each array. Referring to Figure 3 The reset signal RSTB can reset the refresh state signal REFstutus corresponding to each array to low level 0, so as to be used for re-counting or ending the counting under the single array refresh command REFsb.

[0060] Referring to Figure 5 In the example embodiment of the present disclosure, the reset signal generation module 160 can include an NOR gate 161, wherein the input end of the NOR gate 161 is connected to the full array refresh command REFab, the self refresh command SREF, the system reset signal RST, and the refresh cycle signal REF_1CYCLE, and the output end of the NOR gate 161 outputs the reset signal RSTB. That is, when any one of the full array refresh command REFab, the self refresh command SREF, the system reset signal RST, and the refresh cycle signal REF_1CYCLE is enabled, the reset signal RSTB is triggered. The reset signal RSTB triggered will reset the refresh state signal REFstutus, and end the counting of the array when the full array refresh command REFab, the self refresh command SREF, the system reset signal RST, or the refresh cycle signal REF_1CYCLE is enabled.

[0061] In actual application, the full array refresh command REFab, the self refresh command SREF, and the system reset signal RST are all automatically triggered by the system, and only the refresh cycle signal REF_1CYCLE needs to be determined according to the refresh state signal REFstutus corresponding to each array.

[0062] In the example embodiment of the present disclosure, referring to Figure 6 The array refresh state determination circuit 100 described above further needs to include a second AND gate 180 for determining the refresh cycle signal REF_1CYCLE. The input end of the second AND gate 180 is connected to the output end of the plurality of inverters 142, that is, connected to the refresh state signal REFstutus, for example, connected to Figure 3The refresh state signals REFstutus1, REFstutus2, REFstutus3 and REFstutus4 in the refresh state determination circuit are input to the first AND gate 170, and the output end of the first AND gate 170 outputs the refresh cycle signal REF_1CYCLE.

[0063] In summary, the array refresh state determination circuit provided by the example embodiments of the present disclosure can generate refresh activation states of each array through the refresh array determination module, and determine refresh states of each array according to the refresh activation states of each array, so as to realize the marking of the refreshed array. Moreover, through the refresh array determination module and the array refresh state determination module, even if the same array is repeatedly refreshed, the refresh state will not be affected, and the refresh order between arrays does not need to be considered, the logic structure is simple, and the array refresh state determination circuit can be applied to any memory with a single array refresh command REFsb.

[0064] The example embodiments of the present disclosure further provide an array refresh state determination method. Referring to Figure 7 The array refresh state determination method can specifically include the following steps:

[0065] In step S702, refresh activation states of each array are determined under the single array refresh period command.

[0066] In step S704, refresh states of each array are determined according to the refresh activation states of each array.

[0067] In some embodiments of the present disclosure, determining refresh activation states of each array under the single array refresh period command includes: outputting a refresh activation signal corresponding to the array when the array is refreshed at least once under the single array refresh period command.

[0068] In some embodiments of the present disclosure, the method further includes: generating a reset signal according to a full array refresh command, a self-refresh command, a system reset signal and a refresh period signal; and the reset signal is used to reset the refresh states of each array.

[0069] The specific details of each step in the array refresh state determination method have been described in detail in the corresponding array refresh state determination circuit, and thus will not be described here.

[0070] The example embodiments of the present disclosure further provide a refresh circuit, which includes the array refresh state determination circuit described above. The specific structure and working principle of the array refresh state determination circuit have been described in detail in the above embodiments, and thus will not be described here.

[0071] The electronic device can include a plurality of arrays and an array control unit in which the array refresh state determination circuit is disposed. The specific structural details of the array refresh state determination circuit have been described in detail in the above embodiments, and will not be described here again.

[0072] In the above embodiments, the implementation can be achieved by software, hardware, firmware or any combination thereof, entirely or partially. When implemented by software, the implementation can be achieved in the form of a computer program product, entirely or partially. The computer program product includes one or more computer commands. When the computer program commands are loaded and executed on a computer, the processes or functions described in the embodiments of the present disclosure are entirely or partially generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer commands can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. The computer-readable storage medium can be any available medium that can be accessed by a computer or data storage device including one or more service modules, data centers, etc. integrated with the medium. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state disk (SSD)), etc. In the embodiments of the present disclosure, the computer can include the device described above.

[0073] Although the present disclosure is described herein in conjunction with various embodiments, other variations and modifications of the disclosed embodiments can be understood and implemented by those skilled in the art through viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "one" does not exclude a plurality. A single processing module or other unit can implement several functions listed in the claims. Some measures are described in mutually different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0074] Although the present disclosure has been described in connection with certain specific features and embodiments thereof, it is to be understood that it is provided as an exemplification of the principles of the present disclosure and the features set forth herein are intended to be illustrative rather than limiting, and that numerous modifications and variations therein can be expected by those skilled in the art. Accordingly, it should be understood that the description and drawings are illustrative of the present disclosure and are not intended to be limiting. It should be understood that various changes can be made to the implementations described and the embodiments presented herein without departing from the spirit and scope of the present disclosure. It is intended that all such changes be considered as within the scope of the present disclosure.

Claims

1. An array refresh status determination circuit, comprising: The application relates to an array refresh state determination circuit. The array refresh state determination circuit comprises a refresh array determination module, an array refresh state determination module and a reset signal generation module. The refresh array determination module is used for determining refresh activation states of arrays in a single array refresh period, and outputting refresh activation signals corresponding to the arrays when the arrays are refreshed at least once. The refresh array determination module comprises a plurality of XOR gates and a plurality of first AND gates, one of the XOR gates corresponding to one of the first AND gates.

2. The array refresh state determination circuit of claim 1, wherein, The input end of each of the XOR gates is connected to a preset array address and a refreshed array address, the output end of the XOR gate is connected to one of the input ends of the corresponding first AND gate, the other input end of the first AND gate is connected to a single array refresh command, and the output end of the first AND gate outputs the refresh activation signal.

3. The array refresh state determination circuit of claim 2, wherein, The array refresh state determination module is used for determining refresh states of the arrays according to the refresh activation states of the arrays. The array refresh state determination module is used for determining refresh state signals of the arrays according to the refresh activation signals. The array refresh state determination module comprises a plurality of counters and a plurality of inverters.

4. The array refresh state determination circuit of claim 3, wherein, The set end of the counter is connected to the refresh activation signal, and the reset end of the counter is connected to a reset signal.

5. The array refresh state determination circuit of claim 3, wherein, The output end of the counter is connected to the input end of the inverter, and the output end of the inverter outputs the refresh state signal. One of the counters corresponds to one of the inverters.

6. The array refresh state determination circuit of claim 5, wherein, The reset signal generation module is used for generating a reset signal according to a full array refresh command, a self-refresh command, a system reset signal and a refresh period signal. The reset signal is used for resetting the refresh states of the arrays.

7. The array refresh status determination circuit of claim 5 or 6, wherein, The reset signal generation module comprises an NOR gate. The input end of the NOR gate is connected to the full array refresh command, the self-refresh command, the system reset signal and the refresh period signal, and the output end of the NOR gate outputs the reset signal. The second AND gate is used for outputting the refresh period signal.

8. A refresh circuit, comprising: The input end of the second AND gate is connected to the output ends of the plurality of inverters, and the output end of the second AND gate outputs the refresh period signal.

9. An electronic device, comprising: The array refresh state determination circuit comprises the array refresh state determination circuit in any one of claims 1-7. The application relates to an array refresh state determination circuit. The application relates to an array refresh state determination circuit. The application relates to an array refresh state determination circuit. The application relates to an array refresh state determination circuit.

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