Electrostatic discharge protection devices and electrostatic discharge protection circuits

Abstract

This invention provides an electrostatic discharge (ESD) protection device and circuit. The ESD protection device includes: a substrate of a first conductivity type and a deep well region of a second conductivity type located within the substrate of the first conductivity type; a doped region of the first conductivity type and a heavily doped region of the second conductivity type located on the surface of the deep well region of the second conductivity type; the doped region of the first conductivity type includes a heavily doped region of the first conductivity type and at least one of the following: a lightly doped region of the first conductivity type and a well region of the first conductivity type; the heavily doped region of the first conductivity type is located within the lightly doped region of the first conductivity type or on the surface of the well region of the first conductivity type; the heavily doped region of the second conductivity type is spaced apart from the heavily doped region of the first conductivity type. This invention can reduce the capacitance of the ESD protection device, improve the response speed of integrated circuits, and maintain the original ESD protection capability.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more specifically, to an electrostatic discharge (ESD) protection device and an ESD protection circuit. Background Technology

[0002] As semiconductor manufacturing processes become more advanced, semiconductor devices become smaller, junction depths become shallower, and oxide layers become thinner, the reliability challenges faced by semiconductor integrated circuits become greater, especially making electrostatic discharge (ESD) protection increasingly important. Figure 1 The schematic diagram of an existing electrostatic discharge (ESD) protection circuit shown uses two diodes to shunt the current and prevent excessive voltage from being applied to the protected circuit. However, the capacitance of the diodes affects the charging and discharging speed of the ESD protection circuit, and thus its response speed. If the capacitance is large, the response speed is slow, and the ESD protection circuit fails to activate in time, potentially causing the components in the main circuit to be damaged by the large current. Summary of the Invention

[0003] This invention can solve the problem that the large capacitance of diodes in existing electrostatic discharge (ESD) protection circuits affects the response speed of the ESD protection circuit.

[0004] This invention provides an electrostatic discharge (ESD) protection device connected to a power supply terminal, comprising: a substrate of a first conductivity type and a deep well region of a second conductivity type located within the substrate of the first conductivity type; a doped region of the first conductivity type and a heavily doped region of the second conductivity type located on the surface of the deep well region of the second conductivity type; the doped region of the first conductivity type includes a heavily doped region of the first conductivity type and at least one of the following: a lightly doped region of the first conductivity type and a well region of the first conductivity type; the heavily doped region of the first conductivity type is located within the lightly doped region of the first conductivity type or on the surface of the well region of the first conductivity type; the heavily doped region of the second conductivity type is spaced apart from the heavily doped region of the first conductivity type.

[0005] Optionally, the doping concentration of the lightly doped region of the first conductivity type is in the range of 10. 19 -10 20 atom / cm 3 The well region doping concentration of the first conductivity type ranges from 10. 17 -10 18 atom / cm 3 The junction depth of the lightly doped region of the first conductivity type ranges from 10 to 20 nm, and the junction depth of the well region of the first conductivity type ranges from 1.5 to 2 μm.

[0006] Optionally, the doped region of the first conductivity type includes a heavily doped region of the first conductivity type and a lightly doped region of the first conductivity type, wherein the lightly doped region of the first conductivity type surrounds the heavily doped region of the first conductivity type; the device further includes a deep well region of the second conductivity type and a first well region and a second well region of the second conductivity type located on the substrate surface of the first conductivity type; the first well region is adjacent to the lightly doped region of the first conductivity type and located at one end away from the heavily doped region of the second conductivity type, and the second well region is adjacent to the heavily doped region of the second conductivity type and located at one end away from the heavily doped region of the first conductivity type.

[0007] Optionally, the doped region of the first conductivity type includes a heavily doped region of the first conductivity type and a well region of the first conductivity type, wherein the well region of the first conductivity type is located at the bottom of the heavily doped region of the first conductivity type; the device further includes a deep well region of the second conductivity type and a first well region and a second well region of the second conductivity type located on the substrate surface of the first conductivity type; the first well region and the second well region are respectively located on both sides of the well region of the first conductivity type, and the heavily doped region of the second conductivity type is located on the surface of the second well region.

[0008] Optionally, the doped region of the first conductivity type includes a heavily doped region of the first conductivity type, a lightly doped region of the first conductivity type, and a well region of the first conductivity type; the well region of the first conductivity type is located on the surface of the deep well region of the second conductivity type, the lightly doped region of the first conductivity type is located on the surface of the well region of the first conductivity type, and the lightly doped region of the first conductivity type surrounds the heavily doped region of the first conductivity type; the device further includes a first well region and a second well region of the second conductivity type located on the deep well region of the second conductivity type and the substrate surface of the first conductivity type; the first well region and the second well region are respectively located on both sides of the well region of the first conductivity type, and the heavily doped region of the second conductivity type is located on the surface of the second well region.

[0009] Optionally, it also includes a shallow trench isolation structure, wherein the shallow trench isolation structure is located between the heavily doped region of the second conductivity type and the heavily doped region of the first conductivity type, and is also located at one end of the heavily doped region of the first conductivity type away from the heavily doped region of the second conductivity type, and at one end of the heavily doped region of the second conductivity type away from the heavily doped region of the first conductivity type, and the depth of the shallow trench isolation structure is less than 0.3 μm.

[0010] Optionally, the heavily doped region of the first conductivity type is connected to the input / output interface terminal, and the heavily doped region of the second conductivity type is connected to the power supply terminal.

[0011] Optionally, the first conductivity type includes P-type, and the second conductivity type includes N-type.

[0012] This invention provides an electrostatic discharge (ESD) protection device for a grounding terminal, comprising: a substrate of a first conductivity type, and a doped region of a second conductivity type and a heavily doped region of the first conductivity type located within the substrate of the first conductivity type; the doped region of the second conductivity type includes a heavily doped region of the second conductivity type and at least one of the following: a lightly doped region of the second conductivity type and a well region of the second conductivity type; the heavily doped region of the second conductivity type is located within the lightly doped region of the second conductivity type or on the surface of the well region of the second conductivity type; the heavily doped region of the second conductivity type is spaced apart from the heavily doped region of the first conductivity type.

[0013] Optionally, the doping concentration of the lightly doped region of the second conductivity type is in the range of 10. 19 -10 20 atom / cm 3 The well region doping concentration of the second conductivity type ranges from 10. 17 -10 18 atom / cm 3 The junction depth of the lightly doped region of the second conductivity type ranges from 10 to 20 nm, and the junction depth of the well region of the second conductivity type ranges from 1.5 to 2 μm.

[0014] Optionally, the doped region of the second conductivity type includes a heavily doped region of the second conductivity type and a lightly doped region of the second conductivity type;

[0015] The lightly doped region of the second conductivity type is located on the substrate surface of the first conductivity type, and the lightly doped region of the second conductivity type surrounds the heavily doped region of the second conductivity type.

[0016] Optionally, the doped region of the second conductivity type includes a heavily doped region of the second conductivity type and a well region of the second conductivity type;

[0017] The well region of the second conductivity type is located on the substrate surface of the first conductivity type, and the heavily doped region of the second conductivity type is located on the surface of the well region of the second conductivity type.

[0018] Optionally, the doped region of the second conductivity type includes a heavily doped region of the second conductivity type, a lightly doped region of the second conductivity type, and a well region of the second conductivity type;

[0019] The well region of the second conductivity type is located on the substrate surface of the first conductivity type, the lightly doped region of the second conductivity type is located on the surface of the well region of the second conductivity type, and the lightly doped region of the second conductivity type surrounds the heavily doped region of the second conductivity type.

[0020] Optionally, it also includes a shallow trench isolation structure, wherein the shallow trench isolation structure is located between the heavily doped region of the second conductivity type and the heavily doped region of the first conductivity type, and is also located at one end of the heavily doped region of the first conductivity type away from the heavily doped region of the second conductivity type, and at one end of the heavily doped region of the second conductivity type away from the heavily doped region of the first conductivity type, and the depth of the shallow trench isolation structure is less than 0.3 μm.

[0021] Optionally, the heavily doped region of the second conductivity type is connected to the input / output interface terminal, and the heavily doped region of the first conductivity type is connected to the ground terminal.

[0022] Optionally, the first conductivity type includes P-type, and the second conductivity type includes N-type.

[0023] This invention provides an electrostatic discharge (ESD) protection circuit, including a power supply terminal, a ground terminal, an input / output interface terminal located between the power supply terminal and the ground terminal, an ESD protection device connected to the power supply terminal, and an ESD protection device connected to the ground terminal. The power supply terminal is electrically connected to a heavily doped region of a second conductivity type of the ESD protection device connected to the power supply terminal, and the input / output interface terminal is electrically connected to a heavily doped region of a first conductivity type of the ESD protection device connected to the power supply terminal. The ground terminal is electrically connected to a heavily doped region of a first conductivity type of the ESD protection device connected to the ground terminal, and the input / output interface terminal is electrically connected to a heavily doped region of a second conductivity type of the ESD protection device connected to the ground terminal.

[0024] The electrostatic discharge (ESD) protection device and circuit provided in this invention can reduce the capacitance of the ESD protection device, improve the response speed of the integrated circuit, and maintain the original ESD protection capability. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of an existing electrostatic discharge (ESD) protection circuit.

[0026] Figure 2-4 A schematic diagram of the planar structure and corresponding cross-sectional structure of the electrostatic discharge protection device connected to the power supply terminal provided in an embodiment of the present invention;

[0027] Figure 5-7 A schematic diagram of the planar structure and corresponding cross-sectional structure of the electrostatic discharge protection device for the grounding terminal provided in an embodiment of the present invention. Detailed Implementation

[0028] As mentioned in the background section, current DRAM speeds are increasing, requiring I / O interfaces to not only have reliable electrostatic discharge (ESD) protection capabilities but also relatively small capacitance. This invention provides an ESD protection device and circuit with low capacitance, offering a fast-response ESD protection solution.

[0029] Figure 1 The schematic diagram of an existing electrostatic discharge (ESD) protection circuit is shown. The ESD protection circuit includes diodes 101 and 102, which are coupled in series. Diode 101 is connected between the power supply terminal VDD and the input / output (I / O) terminal, with its cathode coupled to VDD and its anode coupled to I / O. Diode 102 is connected between the ground terminal VSS and the I / O terminal, with its cathode coupled to I / O and its anode coupled to VSS. The capacitance of diodes 101 and 102 affects the charging and discharging speed of the ESD protection circuit, and consequently, its response speed. If the capacitance is large, the response speed is slow, and the ESD protection circuit may not activate in time, potentially causing damage to components in the main circuit due to high current.

[0030] This invention provides an electrostatic discharge (ESD) protection device connected to a power supply terminal, comprising: a substrate of a first conductivity type and a deep well region of a second conductivity type located within the substrate of the first conductivity type; and a doped region of the first conductivity type and a heavily doped region of the second conductivity type located on the surface of the deep well region of the second conductivity type.

[0031] The doped region of the first conductivity type includes a heavily doped region of the first conductivity type and at least one of the following: a lightly doped region of the first conductivity type and a well region of the first conductivity type;

[0032] The heavily doped region of the first conductivity type is located within the lightly doped region of the first conductivity type or on the surface of the well region of the first conductivity type; the heavily doped region of the second conductivity type is spaced apart from the heavily doped region of the first conductivity type.

[0033] Specifically, if the doped region of the first conductivity type includes a heavily doped region and a lightly doped region of the first conductivity type, then the lightly doped region of the first conductivity type surrounds the heavily doped region of the first conductivity type; the device also includes a deep well region of the second conductivity type and a first well region and a second well region of the second conductivity type located on a substrate of the first conductivity type. The first well region is adjacent to the lightly doped region of the first conductivity type and located at an end away from the heavily doped region of the second conductivity type, and the second well region is adjacent to the heavily doped region of the second conductivity type and located at an end away from the heavily doped region of the first conductivity type.

[0034] Specifically, if the doped region of the first conductivity type includes a heavily doped region of the first conductivity type and a well region of the first conductivity type, then the device further includes a deep well region of the second conductivity type and a first well region and a second well region of the second conductivity type located on the substrate surface of the first conductivity type. The first well region and the second well region are located on opposite sides of the well region of the first conductivity type, and the heavily doped region of the second conductivity type is located on the surface of the second well region.

[0035] Specifically, if the doped region of the first conductivity type includes a heavily doped region of the first conductivity type, a lightly doped region of the first conductivity type, and a well region of the first conductivity type, then the well region of the first conductivity type is located on the surface of the deep well region of the second conductivity type, the lightly doped region of the first conductivity type is located on the surface of the well region of the first conductivity type, and the lightly doped region of the first conductivity type surrounds the heavily doped region of the first conductivity type. Optionally, the device further includes a first well region and a second well region of the second conductivity type located on the surface of the deep well region of the second conductivity type and the substrate of the first conductivity type; the first well region and the second well region are respectively located on both sides of the well region of the first conductivity type, and the heavily doped region of the second conductivity type is located on the surface of the second well region.

[0036] The heavily doped region of the second conductivity type is spaced apart from the heavily doped region of the first conductivity type. Optionally, the device further includes a shallow trench isolation structure (STI), located between the heavily doped region of the second conductivity type and the heavily doped region of the first conductivity type. This shallow trench isolation structure is located between the heavily doped region of the second conductivity type and the heavily doped region of the first conductivity type, and also at one end of the deep well region of the first conductivity type away from the deep well region of the second conductivity type. Optionally, the depth of the shallow trench isolation structure is less than 0.3 μm.

[0037] Optionally, the heavily doped region of the first conductivity type is connected to the input / output interface terminal, and the heavily doped region of the second conductivity type is connected to the power supply terminal.

[0038] During the fabrication process of the aforementioned device, the doping concentration and distribution of the heavily doped region of the first conductivity type can be altered by increasing the lightly doped region or the well region of the first conductivity type. This increases the depletion region of the PN junction, thereby reducing the capacitance of the electrostatic discharge (ESD) protection device and meeting the low capacitance requirement of the ESD protection device for the I / O circuit's connection to the power supply terminal. Optionally, the doping concentration of the lightly doped region of the first conductivity type is in the range of 10. 19 -10 20 atom / cm 3 The doping concentration of the well region for the first conductivity type ranges from 10. 17 -10 18 atom / cm 3 The junction depth of the lightly doped region of the first conductivity type ranges from 10 to 20 nm, and the junction depth of the well region of the first conductivity type ranges from 1.5 to 2 μm, thereby achieving the purpose of reducing the capacitance of the electrostatic protection device.

[0039] It should be noted that the doping concentration or energy of the heavily doped region implanted in the first conductivity type remains unchanged.

[0040] The electrostatic discharge (ESD) protection device for the power supply terminal provided in this embodiment of the invention changes the doping concentration and distribution of the heavily doped region of the first conductivity type by increasing the lightly doped region or the well region of the first conductivity type, thereby increasing the depletion region of the PN junction, reducing the capacitance of the ESD protection device, improving the speed of the integrated circuit, and maintaining the original ESD protection capability.

[0041] Optionally, the first conductivity type mentioned above includes P-type, and the second conductivity type includes N-type.

[0042] The following section uses a P-type heavily doped region / Nwell electrostatic discharge (ESD) device as an example to describe in detail the specific implementation methods of various ESD devices connected to the power supply terminal provided in the embodiments of the present invention.

[0043] Figure 2 The diagram shows a planar structure and corresponding cross-sectional structure of an electrostatic discharge protection device connected to a power supply terminal according to an embodiment of the present invention. It shows a P-type substrate 201 and an N-type deep well 202 located in the P-type substrate 201. A P-type doped region and an N-type heavily doped region 205 are generated on the surface of the N-type deep well 202.

[0044] The P-type doped region includes a heavily doped P-type region 203 and a lightly doped P-type region 204. The electrostatic protection device also includes a first N-type well region 207 and a second N-type well region 206 spanning the surface of the N-type deep well 202 and the P-type substrate 201.

[0045] The first N-type well region 207 is adjacent to the lightly doped P-type region 204, and the second N-type well region 206 is adjacent to the heavily doped N-type region 205. Figure 2 The diagram also shows that shallow trench isolation structures 208 are provided on both sides of the P-type lightly doped region 204 and the N-type heavily doped region 205.

[0046] The P-type heavily doped region 203 is connected to the input / output interface (I / O), and the N-type heavily doped region 205 is connected to the power supply (VDD).

[0047] Figure 3 The diagram shows a planar structure and a corresponding cross-sectional structure of another electrostatic discharge protection device for power supply terminals provided in an embodiment of the present invention. It shows a P-type substrate 301 and an N-type deep well 302 located in the P-type substrate 301. A P-type doped region and an N-type heavily doped region 307 are formed on the surface of the N-type deep well 302.

[0048] The P-type doped region includes a heavily doped P-type region 303 and a P-type well region 304. The electrostatic protection device also includes a first N-type well region 306 and a second N-type well region 305 spanning the surface of the N-type deep well 302 and the P-type substrate 301.

[0049] The first N-type well region 306 and the second N-type well region 305 are located on both sides of the P-type well region 304, and the heavily doped N-type region 307 is located on the surface of the second N-type well region 305. Figure 3 The image also shows that shallow trench isolation structures 308 are provided on both sides of the P-type heavily doped region 303 and the N-type heavily doped region 307.

[0050] The P-type heavily doped region 303 is connected to the input / output interface (I / O), and the N-type heavily doped region 307 is connected to the power supply (VDD).

[0051] Figure 4 The diagram shows a planar structure and a corresponding cross-sectional structure of another electrostatic discharge protection device for connecting to the power supply terminal provided in an embodiment of the present invention. It shows a P-type substrate 401 and an N-type deep well 402 located in the P-type substrate 401. A P-type doped region and an N-type heavily doped region 403 are formed on the surface of the N-type deep well 402.

[0052] The P-type doped region includes a heavily doped P-type region 405, a lightly doped P-type region 404, and a P-type well region 406. The P-type well region 406 is located on the surface of the N-type deep well 402, the lightly doped P-type region 404 is located on the surface of the P-type well region 406, and the heavily doped P-type region 405 is located within the lightly doped P-type region 404.

[0053] The diode also includes a first N-type well region 408 and a second N-type well region 407 spanning the surface of the N-type deep well 402 and the P-type substrate 401; the first N-type well region 408 and the second N-type well region 407 are located on both sides of the P-type well region 406, and the heavily doped N-type region is located on the surface of the second N-type well region 407.

[0054] The P-type heavily doped region 405 is connected to the input / output interface (I / O), and the N-type heavily doped region 403 is connected to the power supply (VDD).

[0055] The present invention provides an electrostatic discharge protection device for a grounding terminal, comprising a substrate of a first conductivity type and a doped region of a second conductivity type and a heavily doped region of the second conductivity type located within the substrate of the first conductivity type.

[0056] The doped region of the second conductivity type includes a heavily doped region of the second conductivity type and at least one of the following: a lightly doped region of the second conductivity type and a well region of the second conductivity type. The heavily doped region of the second conductivity type is located within the lightly doped region of the second conductivity type or on the surface of the well region of the second conductivity type; the heavily doped region of the second conductivity type is spaced apart from the heavily doped region of the first conductivity type.

[0057] Specifically, if the doped region of the second conductivity type includes a heavily doped region of the second conductivity type and a lightly doped region of the second conductivity type, then the lightly doped region of the second conductivity type is located on the substrate surface of the first conductivity type, and the lightly doped region of the second conductivity type surrounds the heavily doped region of the second conductivity type.

[0058] Specifically, if the doped region of the second conductivity type includes a heavily doped region of the second conductivity type and a well region of the second conductivity type, then the well region of the second conductivity type is located on the substrate surface of the first conductivity type, and the heavily doped region of the second conductivity type is located on the surface of the well region of the second conductivity type.

[0059] Specifically, if the doped region of the second conductivity type includes a heavily doped region of the second conductivity type, a lightly doped region of the second conductivity type, and a well region of the second conductivity type, then the well region of the second conductivity type is located on the substrate surface of the first conductivity type, the lightly doped region of the second conductivity type is located on the surface of the well region of the second conductivity type, and the lightly doped region of the second conductivity type surrounds the heavily doped region of the second conductivity type.

[0060] The heavily doped region of the second conductivity type is spaced apart from the heavily doped region of the first conductivity type. Optionally, the device further includes a shallow trench isolation structure located between the heavily doped region of the second conductivity type and the heavily doped region of the first conductivity type.

[0061] Optionally, the heavily doped region of the second conductivity type is connected to the input / output interface terminal, and the heavily doped region of the first conductivity type is connected to the ground terminal.

[0062] During the fabrication process of the aforementioned device, the doping concentration and distribution of the heavily doped region of the second conductivity type can be altered by adding a lightly doped region or a well region of the second conductivity type. This increases the depletion region of the PN junction, thereby reducing the capacitance of the electrostatic discharge (ESD) protection device and meeting the low capacitance requirement of the I / O circuit for the ESD protection device at the ground terminal. Optionally, the doping concentration of the lightly doped region of the second conductivity type is in the range of 10. 19 -10 20 atom / cm 3 The well region doping concentration of the second conductivity type ranges from 10. 17 -10 18 atom / cm 3The junction depth of the lightly doped region of the second conductivity type is 10-20 nm, and the junction depth of the well region of the second conductivity type is 1.5-2 μm, thereby achieving the purpose of reducing the capacitance of the electrostatic protection device.

[0063] It should be noted that the doping concentration or energy of the heavily doped region implanted in the second conductivity type remains unchanged.

[0064] The electrostatic discharge (ESD) protection device for the ground terminal provided in this embodiment of the invention changes the doping concentration and distribution of the heavily doped region of the second conductivity type of the device by increasing the lightly doped region or the well region of the second conductivity type, thereby increasing the depletion region of the PN junction, thereby reducing the capacitance of the ESD protection device, improving the speed of the integrated circuit, and maintaining the original ESD protection capability.

[0065] Optionally, the first conductivity type mentioned above includes P-type, and the second conductivity type includes N-type. The following describes in detail the specific implementation methods of various grounding terminal electrostatic protection devices provided in the embodiments of the present invention, taking an N-type heavily doped region / Pwell electrostatic protection device as an example.

[0066] Figure 5 The diagram shows a planar structure and a corresponding cross-sectional structure of an electrostatic discharge protection circuit for a grounding terminal provided by an embodiment of the present invention, showing a P-type substrate 501 and an N-type doped region and a P-type heavily doped region 504 located within the P-type substrate 501.

[0067] The N-type doped region includes a heavily doped N-type region 503 and a lightly doped N-type region 502; the lightly doped N-type region 502 is located on the surface of the N-type substrate 501, and the heavily doped N-type region 503 is located within the lightly doped N-type region 502. Figure 5 The diagram also shows that the N-type heavily doped region 503 is connected to the input / output interface (I / O), and the P-type heavily doped region 504 is connected to the ground terminal (VSS).

[0068] exist Figure 5 The diagram also shows that shallow trench isolation structures 505 are provided on both sides of the P-type heavily doped region 504 and the N-type lightly doped region 502.

[0069] Figure 6 The diagram shows a planar structure and a corresponding cross-sectional structure of another grounding terminal electrostatic protection circuit provided in an embodiment of the present invention, showing a P-type substrate 601 and an N-type doped region and a P-type heavily doped region 604 located in the P-type substrate 601.

[0070] The N-type doped region includes a heavily doped N-type region 602 and an N-type well region 603; the N-type well region 603 is located on the surface of the N-type substrate 601, and the heavily doped N-type region 703 is located on the surface of the N-type well region 603. Figure 6The diagram also shows the N-type heavily doped region 602 connected to the input / output interface (I / O), and the P-type heavily doped region 604 connected to the ground terminal (VSS).

[0071] exist Figure 6 The diagram also shows that shallow trench isolation structures 605 are provided on both sides of the P-type heavily doped region 604 and the N-type heavily doped region 602.

[0072] Figure 7 The diagram shows a planar structure and a corresponding cross-sectional structure of another grounding terminal electrostatic protection circuit provided in an embodiment of the present invention, showing a P-type substrate 701 and an N-type doped region and a P-type heavily doped region 705 located in the P-type substrate 701.

[0073] The N-type doped region includes an N-type heavily doped region 702, an N-type lightly doped region 703, and an N-type well region 704. The N-type well region 704 is located on the surface of the N-type substrate 701, the N-type lightly doped region 703 is located on the surface of the N-type well region 704, and the N-type heavily doped region 702 is located within the N-type lightly doped region 703.

[0074] exist Figure 7 The diagram also shows that shallow trench isolation structures 706 are provided on both sides of the P-type heavily doped region 705 and the N-type heavily and lightly doped region 703.

[0075] The embodiments of the present invention introduce NMLDD and PMLDD through double diffusion on the basis of the original electrostatic protection circuit, which changes the doping concentration and distribution of N+ and P+, reduces the capacitance of the electrostatic protection device, and improves the speed of integrated circuit, while maintaining the original electrostatic protection capability.

[0076] This invention also provides an electrostatic discharge (ESD) protection circuit, including a power supply terminal, a ground terminal, and an input / output interface terminal located between the power supply terminal and the ground terminal, as well as an ESD protection device connected to the power supply terminal and an ESD protection device connected to the ground terminal.

[0077] Specifically, the power supply terminal is electrically connected to the heavily doped region of the second conductivity type of the electrostatic protection device connected to the power supply terminal, and the input / output interface terminal is electrically connected to the heavily doped region of the first conductivity type of the electrostatic protection device connected to the power supply terminal; the grounding terminal is electrically connected to the heavily doped region of the first conductivity type of the electrostatic protection device connected to the grounding terminal, and the input / output interface terminal is electrically connected to the heavily doped region of the second conductivity type of the electrostatic protection device connected to the grounding terminal.

[0078] The low-capacitance electrostatic discharge (ESD) protection circuit provided in this embodiment of the invention has a low capacitance of its ESD protection device, which improves the speed of the integrated circuit and maintains the original ESD protection capability.

[0079] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. An electrostatic discharge protection device connected to a power supply terminal, characterized in that, include: A substrate of a first conductivity type and a deep well region of a second conductivity type located within the substrate of the first conductivity type; A doped region of the first conductivity type and a heavily doped region of the second conductivity type are located on the surface of the deep well region of the second conductivity type; in a direction perpendicular to the substrate surface, the orthographic projection of the heavily doped region of the second conductivity type partially coincides with the orthographic projection of the deep well region of the second conductivity type. The doped region of the first conductivity type includes a heavily doped region of the first conductivity type and at least one of the following: a lightly doped region of the first conductivity type and a well region of the first conductivity type; The heavily doped region of the first conductivity type is located within the lightly doped region of the first conductivity type or on the surface of the well region of the first conductivity type. The heavily doped region of the second conductivity type is spaced apart from the heavily doped region of the first conductivity type; The device further includes a deep well region of the second conductivity type and a first well region and a second well region of the second conductivity type located on the surface of the substrate of the first conductivity type; The first well region and the second well region are located on both sides of the well region of the first conductivity type, the heavily doped region of the second conductivity type is located on the surface of the second well region, and the second well region is located below the heavily doped region of the second conductivity type.

2. The device according to claim 1, characterized in that, The doping concentration range of the lightly doped region of the first conductivity type is 10. 19 -10 20 atom / cm 3 The well region doping concentration of the first conductivity type ranges from 10. 17 -10 18 atom / cm 3 The junction depth of the lightly doped region of the first conductivity type ranges from 10 to 20 nm, and the junction depth of the well region of the first conductivity type ranges from 1.5 to 2 μm.

3. The device according to claim 1, characterized in that, The doped region of the first conductivity type includes a heavily doped region of the first conductivity type and a well region of the first conductivity type, with the well region of the first conductivity type located at the bottom of the heavily doped region of the first conductivity type.

4. The device according to claim 1, characterized in that, The doped region of the first conductivity type includes a heavily doped region of the first conductivity type, a lightly doped region of the first conductivity type, and a well region of the first conductivity type. The well region of the first conductivity type is located on the surface of the deep well region of the second conductivity type, the lightly doped region of the first conductivity type is located on the surface of the well region of the first conductivity type, and the lightly doped region of the first conductivity type surrounds the heavily doped region of the first conductivity type.

5. The device according to any one of claims 1-4, characterized in that, It also includes a shallow trench isolation structure, which is located between the heavily doped region of the second conductivity type and the heavily doped region of the first conductivity type, and is also located at one end of the heavily doped region of the first conductivity type away from the heavily doped region of the second conductivity type, and at one end of the heavily doped region of the second conductivity type away from the heavily doped region of the first conductivity type, and the depth of the shallow trench isolation structure is less than 0.3 μm.

6. The device according to any one of claims 1-4, characterized in that, The heavily doped region of the first conductivity type is connected to the input / output interface terminal, and the heavily doped region of the second conductivity type is connected to the power supply terminal.

7. The device according to any one of claims 1-4, characterized in that, The first conductivity type includes P-type, and the second conductivity type includes N-type.

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