Field effect transistor and method of manufacturing the same

Abstract

A field effect transistor includes a semiconductor substrate and a plurality of trenches disposed at a top surface of the semiconductor substrate. The trenches extend along a first direction at the top surface of the semiconductor substrate and are disposed spaced apart in a direction perpendicular to the first direction. A connection region is disposed below a body region. In a top view of the semiconductor substrate, the connection region extends in a second direction that intersects the first direction and is spaced apart in a direction perpendicular to the second direction. A field relaxation region is disposed below the connection region and the trenches. In the top view of the semiconductor substrate, the field relaxation region extends in a third direction that intersects the first direction and the second direction and is spaced apart in a direction perpendicular to the third direction.

Description

Technical Field

[0001] This disclosure relates to field-effect transistors, and to methods of manufacturing field-effect transistors. Background Technology

[0002] JP 2019-046908 A discloses a field-effect transistor (FET) including a trench-type gate electrode. The FET disclosed in JP 2019-046908 A includes multiple body regions, multiple connection regions, and multiple field relaxation regions. Each body region is p-type and is disposed in an inter-trench semiconductor region located between trenches. Each body region is in contact with a gate insulating film on a side surface of the trench. An n-type drift region is in contact with the body region at the bottom. When the FET is turned on, a channel is formed in a region adjacent to the gate insulating film of each body region, and the channel connects to the drift region. Each connection region is a p-type region protruding downward from the corresponding body region. Each connection region extends along the trench. Each connection region is disposed at a location separate from each trench. Each field relaxation region is a p-type region disposed below each connection region. Each field relaxation region is disposed below the gate electrode and extends in a direction intersecting the gate electrode. Each field relaxation region is connected to the body region via a connection region. As a result, the potential of each field relaxation region is stabilized.

[0003] When the field-effect transistor is turned off, a depletion layer extends from each field relaxation region to its surroundings. This depletion layer, extending from each field relaxation region, reduces the electric field applied to the gate insulating film near the bottom of each trench. Therefore, this field-effect transistor exhibits a higher breakdown voltage. Summary of the Invention

[0004] To increase channel density, trench gate electrodes are formed at a higher density. In other words, the spacing between trench gate electrodes is narrow. When the spacing between trench gate electrodes becomes too narrow to the limit of machining accuracy, such as... Figure 15 , Figure 16 As shown, each connection region 136 is in contact with the trench, in other words, in contact with the gate insulating film. Figure 15 , Figure 16 Each of these diagrams illustrates the main region 134, the field relaxation region 138, and the drift region 140. In Figure 15 , Figure 16 In the structure shown, within the inter-trench semiconductor region with the connection region, the channel formed in the main region is not connected to the drift region. In other words, current does not flow in the region where the inter-trench semiconductor region is located. Figure 15 , Figure 16 In this design, to ensure the flow of current, the connection region is only located within a portion of the inter-trench semiconductor region. Figure 15 , Figure 16In a field-effect transistor (FET) in the ON state, current does not flow through the entire inter-trench semiconductor region containing the connection region. Therefore, the current is concentrated in the inter-trench semiconductor region adjacent to the one containing the connection region. Figure 15 , Figure 16 In each of the field-effect transistors shown, the allowable current that can be conducted is relatively low. The object of this disclosure is to provide a field-effect transistor having multiple trench gate electrodes arranged at a higher density while reducing current concentration.

[0005] According to a first aspect of this disclosure, a field-effect transistor includes a semiconductor substrate, trenches, a gate insulating film, a gate electrode, and a source electrode. The trenches are disposed on the top surface of the semiconductor substrate. The gate insulating film is disposed in each trench. The gate electrode is disposed in each trench. The source electrode covers the top surface of the semiconductor substrate. The trenches extend along a first direction on the top surface and are spaced apart in a direction perpendicular to the first direction. The semiconductor substrate includes a plurality of inter-trench semiconductor regions, and each inter-trench semiconductor region is disposed between two adjacent trenches. Each inter-trench semiconductor region includes a source region, a contact region, and a body region. Each source region is an n-type region in contact with the source electrode and the gate insulating film. Each contact region is a p-type region in contact with the source electrode. Each body region is a p-type region having a lower p-type impurity concentration than each contact region, and is in contact with the gate insulating film on a side closer to the bottom surface of the semiconductor substrate than the gate insulating film, and is in contact with a corresponding contact region and a corresponding source region on a side closer to the bottom surface of the semiconductor substrate than the contact region and the source region. The semiconductor substrate includes p-type connection regions, p-type field relaxation regions, and n-type drift regions. The connection regions are located on a side of the semiconductor substrate closer to the bottom surface than the body regions. In a top view of the semiconductor substrate, the connection regions extend in a second direction intersecting a first direction and are spaced apart in a direction perpendicular to the second direction. The connection regions connect to the body regions at their intersections with the body regions. The field relaxation regions are located on a side of the semiconductor substrate closer to the bottom surface than the connection regions and trenches. In a top view of the semiconductor substrate, the field relaxation regions extend upward in a third direction intersecting the first and second directions and are spaced apart in a direction perpendicular to the third direction. The field relaxation regions connect to the connection regions at their intersections with the connection regions. The drift regions are located at a first interval between two adjacent connection regions, a second interval between two adjacent field relaxation regions, and on a side closer to the bottom surface of the semiconductor substrate than the field relaxation regions. The drift region contacts the main region on the side closer to the bottom surface of the semiconductor substrate than the main region, and contacts the gate insulating film on the side closer to the bottom surface of the semiconductor substrate than the gate insulating film.

[0006] The field relaxation region may partially overlap with the connecting region and the trench in the depth direction. In other words, at least one field relaxation region is disposed below the connecting region, and at least one field relaxation region is disposed below the trench.

[0007] In this field-effect transistor, each connection region extends in a second direction intersecting the first and third directions. Each trench extends in the first direction. Each field relaxation region extends upward in the third direction. The connection regions are connected to the field relaxation regions at their respective intersections. Furthermore, the connection regions are connected to the body regions at their respective intersections. Therefore, the field relaxation regions are connected to the body regions via the connection regions. As a result, the potential of each field relaxation region is stabilized. When the field-effect transistor is turned on, the channel is not connected to the drift region, and current does not flow at the intersections where the connection regions intersect the trenches. Because the field relaxation regions extend in the direction intersecting the trenches, the intersections where the field relaxation regions intersect the trenches are distributed throughout the trenches. As a result, current concentration flowing through specific trench-interval semiconductor regions can be suppressed. According to the field-effect transistor described above, current concentration can be suppressed.

[0008] According to a second aspect of this disclosure, a method for manufacturing the field-effect transistor described above includes implanting p-type impurities into contact regions and connection regions through a common mask.

[0009] The method described above can be used to efficiently manufacture field-effect transistors. Attached Figure Description

[0010] The above-described objects, features, and advantages of this disclosure will become more apparent from the following detailed description with reference to the accompanying drawings. In the drawings:

[0011] Figure 1 A cross-sectional perspective view of a metal-oxide-semiconductor field-effect transistor (MOSFET) according to an embodiment is shown, and a top surface of a semiconductor substrate, a cross-section of the semiconductor substrate of the MOSFET along the xz plane, and a cross-section of the semiconductor substrate along the yz plane are also shown.

[0012] Figure 2 A plan view of the top surface of the semiconductor substrate of the MOSFET according to an embodiment is shown;

[0013] Figure 3 The following is illustrated according to an embodiment. Figure 2 A cross-sectional view of the MOSFET along the xz plane, taken from line III-III;

[0014] Figure 4 The following is illustrated according to an embodiment. Figure 2 A cross-sectional view of the MOSFET along the xz plane, taken by line IV-IV;

[0015] Figure 5 The following is illustrated according to an embodiment. Figure 2 A cross-sectional view of the MOSFET along the yz plane, taken from line VV;

[0016] Figure 6 The following is illustrated according to an embodiment. Figure 2 A cross-sectional view of the MOSFET along the yz plane, taken from line VI-VI;

[0017] Figure 7 A cross-sectional perspective view of a MOSFET according to an embodiment is shown, and a cross-section of a MOSFET region including a connection region along the xy plane, a MOSFET cross-section along the xz plane, and a MOSFET cross-section along the yz plane are also shown.

[0018] Figure 8 A plan view showing the arrangement of trenches, interconnect regions, and field relaxation regions in a top view of a semiconductor substrate is shown.

[0019] Figure 9 It shows the source Figure 3 The channel and current path;

[0020] Figure 10 It shows the corresponding Figure 2 A comparative example of a MOSFET planar diagram;

[0021] Figure 11 A method for manufacturing a MOSFET according to an embodiment is shown;

[0022] Figure 12 It shows the results from Figure 8 The diagram shows a plan view of the first variant of the MOSFET modified by the diagram.

[0023] Figure 13 It shows the results from Figure 8 The diagram shows a plan view of the second variant of the MOSFET modified by the diagram.

[0024] Figure 14 It shows the results from Figure 3 The diagram shows a plan view of the third variant of the MOSFET modified from the previous one.

[0025] Figure 15 A cross-sectional view of a MOSFET according to a comparative example is shown; and

[0026] Figure 16 A plan view of the MOSFET based on the comparative example is shown. Detailed Implementation

[0027] The following reference Figures 1 to 5 A metal-oxide-semiconductor field-effect transistor (MOSFET) 10 according to an embodiment is described below. The MOSFET 10 may also be simply referred to as a field-effect transistor. Hereinafter, the direction parallel to the top surface 12a of the semiconductor substrate 12 may also be referred to as the x-direction, the thickness direction of the semiconductor substrate 12 may also be referred to as the z-direction, and the direction perpendicular to both the x-direction and the z-direction may also be referred to as the y-direction. The semiconductor substrate 12 is made of silicon carbide (SiC). However, the semiconductor substrate 12 may also be made of other materials such as silicon or gallium nitride. Figure 1 The source electrode 22 arranged on the top surface 12a of the semiconductor substrate 12 is omitted from the illustration.

[0028] like Figure 1 , Figure 2 As shown, a plurality of trenches 14 are disposed on the top surface 12a of the semiconductor substrate 12. The trenches 14 extend along the y-direction on the top surface 12a. The trenches 14 are arranged to be spaced apart in the x-direction.

[0029] like Figures 1 to 5 As shown, the inner surface of each trench 14 is covered by a gate insulating film 16. This inner surface can also be referred to as the bottom and side surfaces of each trench 14. A gate electrode 18 is disposed in each trench 14. The gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. Figures 3 to 5 As shown, the top surface of the gate electrode 18 is covered by an interlayer insulating film 20.

[0030] like Figures 3 to 6 As shown, the source electrode 22 is disposed on the top of the semiconductor substrate 12. The source electrode 22 is covered by an interlayer insulating film 20. The source electrode 22 is insulated from the gate electrode 18 through the interlayer insulating film 20. The source electrode 22 contacts the top surface 12a of the semiconductor substrate 12 in the portion where the interlayer insulating film 20 is not disposed. The drain electrode 24 is disposed on the bottom of the semiconductor substrate 12. The drain electrode 24 contacts the entire area of ​​the bottom surface 12b of the semiconductor substrate 12.

[0031] like Figure 1 , Figure 3 , Figure 4 As shown, the semiconductor substrate 12 includes inter-trench semiconductor regions 26 respectively sandwiched between trenches 14. Each inter-trench semiconductor region 26 extends along the trench 14 in the y-direction. A source region 30, a contact region 32, and a body region 34 are disposed in each inter-trench semiconductor region 26.

[0032] like Figures 1 to 4As shown, multiple source regions 30 and multiple contact regions 32 are disposed in the region including the top surface 12a of the semiconductor substrate 12. Each source region 30 is n-type and has a relatively high n-type impurity concentration. Each contact region 32 is p-type and has a relatively high p-type impurity concentration. Figure 3 , Figure 4 As shown, source region 30 and contact region 32 are in ohmic contact with source electrode 22. Figure 1 , Figure 2 As shown, each source region 30 and each contact region 32 has a rectangular shape in a direction 100 that obliquely intersects the length direction (in other words, the y-direction) of each trench 14. The source regions 30 and contact regions 32 are arranged alternately in a direction perpendicular to direction 100. In other words, as... Figure 2 As shown, contact areas 32 are arranged at intervals in a direction perpendicular to direction 100, and extend in a direction 100 intersecting the y-direction in the top view of the semiconductor substrate 12. Figure 2 As shown, source regions 30 are arranged at intervals in a direction perpendicular to direction 100, and extend in a direction 100 intersecting the y-direction in a top view of the semiconductor substrate 12. Source regions 30 are arranged between contact regions 32, and contact regions 32 are arranged between source regions 30. Figure 1 , Figure 3 As shown, each source region 30 is in contact with the gate insulating film 16 at the uppermost part of the side surface of the trench 14. Each contact region 32 is in contact with the gate insulating film 16 at the uppermost part of the side surface of the trench 14.

[0033] Each main body region 34 is p-type and has a lower p-type impurity concentration than the contact region 32. For example... Figure 1 , Figure 3 , Figure 4 , Figure 6 As shown, the body region 34 is disposed below the source region 30 and the contact region 32. In each inter-trench semiconductor region 26, each body region 34 is distributed along the entire x and y directions. The body region 34 contacts the upper source region 30 and the contact region 32, respectively. Each body region 34 contacts the gate insulating film 16 at the side surface of the trench 14 located below the source region 30 and the contact region 32.

[0034] like Figures 3 to 6 As shown, the semiconductor substrate 12 includes a plurality of connection regions 36, a plurality of field relaxation regions 38, a drift region 40, a buffer zone 42, and a drain region 44.

[0035] Each linker region 36 is p-type and has a higher concentration of p-type impurities than the host region 34. For example... Figure 1 , Figures 3 to 6 As shown, the connecting area 36 is arranged below the main body area 34. Figure 7As shown, in the top view of the semiconductor substrate 12, the connection region 36 extends in a direction 100 that is inclined to intersect the y-direction. In the top view of the semiconductor substrate 12, the connection regions 36 are arranged at intervals in a direction perpendicular to the direction 100. Figure 1 , Figure 3 As shown, each connection region 36 is disposed directly below its corresponding contact region 32. Therefore, in the top view of the semiconductor substrate 12, each contact region 32 extends in direction 100 to overlap with its corresponding connection region 36. Figure 3 , Figure 4 and Figure 6 As shown, the connection region 36 is connected to the body region 34 at intersection portions 35 where it intersects with the body region 34. The connection region 36 extends downward from the bottom surface of each body region 34 to a position below the bottom end of each body region 34. Each connection region 36 contacts the gate insulating film 16 at the side surface of the trench 14 located below the body region 34.

[0036] Each field relaxation region 38 is p-type. Each field relaxation region 38 has a higher p-type impurity concentration than the main region 34 but lower than the connecting region 36. For example... Figure 1 , Figure 3 , Figure 5 , Figure 6 As shown, the field relaxation region 38 is arranged below the connecting region 36. Figure 1 , Figure 8 As shown, each field relaxation region 38 comprises an elongated shape in the x-direction. In other words, in a top view of the semiconductor substrate 12, each field relaxation region 38 extends in the x-direction, intersecting with both the y-direction and direction 100. The y-direction corresponds to the length direction of the trench 14, and direction 100 corresponds to the length direction of the connection region 36. The field relaxation regions 38 are spaced apart in the y-direction perpendicular to the x-direction. Figure 3 , Figure 5 , Figure 6 As shown, the top portion of each field relaxation region 38 is arranged in a depth region overlapping with the bottom portion of the connection region 36. The field relaxation regions 38 are connected to the connection regions 36 at intersection portions 37, which intersect with the connection regions 36 respectively. The field relaxation regions 38 are connected to the source electrode 22 through the connection region 36, the body region 34 and the contact region 32.

[0037] Drift region 40 is n-type. For example... Figure 1 , Figures 3 to 6As shown, drift regions 40 are distributed from a position contacting the bottom surface of each body region 34 to a position below the field relaxation region 38. In other words, drift regions 40 are distributed in the spacer portions 36x between the connection regions 36, the spacer portions 38x between the field relaxation regions 38, and the region below the field relaxation region 38. Drift regions 40 contact the bottom surface of the body region 34 in the spacer portions 36x between the connection regions 36. Drift regions 40 within the spacer portions 36x contact the gate insulating film 16 on the side surface of the trench 14 and on the bottom surface of the trench 14 located below the corresponding body region 34. Drift regions 40 include high-concentration regions 40a and low-concentration regions 40b. The n-type impurity concentration in the high-concentration region 40a is higher than that in the low-concentration region 40b. In other words, high-concentration regions 40a are distributed in the spacer portions 36x between the connection regions 36, the spacer portions 38x between the field relaxation regions 38, and the region below the field relaxation region 38. The low-concentration zone 40b is positioned below the high-concentration zone 40a. The low-concentration zone 40b contacts the high-concentration zone 40a from below.

[0038] Buffer 42 is n-type and has a higher n-type impurity concentration than the low-concentration region 40b of drift region 40. Viewed from below, buffer 42 is in contact with the low-concentration region 40b.

[0039] Drain region 44 is n-type and has a higher n-type impurity concentration than buffer region 42. Viewed from below, drain region 44 is in contact with buffer region 42. Drain region 44 is disposed in the region including bottom surface 12b of semiconductor substrate 12. Drain region 44 is in ohmic contact with drain electrode 24 at bottom surface 12b.

[0040] When using MOSFET 10, a higher potential than that applied to the drain electrode 24 is used compared to the source electrode 22. When a potential above a threshold is applied to the gate electrode 18, as... Figure 9 As shown, a channel 50 is formed in the body region 34 near the gate insulating film 16. The channel 50 connects the source region 30 and the drift region 40. Figure 9 As indicated by the middle arrow 102, electrons flow from the source region 30 to the drift region 40 through the channel 50. Therefore, electrons flow from the source electrode 22 to the drain electrode 24 through the source region 30, the channel 50, the drift region 40, and the buffer zone 42.

[0041] When the potential of each gate electrode 18 decreases from a value equal to or greater than the gate threshold to a value less than the gate threshold, the channel 50 disappears and electron flow stops. In other words, the MOSFET 10 is turned off. When the channel 50 disappears, the potential of the drift region 40 rises. On the other hand, since the body region 34 is connected to the source electrode 22 through the contact region 32, the potential of each body region 34 remains substantially the same as that of the source electrode 22, in other words, a relatively low potential. When the channel 50 disappears, a reverse voltage is applied to the pn junction at the boundary surface between the corresponding body region 34 and the drift region 40. Therefore, the depletion layer extends from the body region 34 into the drift region 40. The field relaxation region 38 is connected to the source electrode 22 through the connection region 36, the body region 34, and the contact region 32. Therefore, the potential of each connection region 36 also remains substantially the same as that of the source electrode 22, in other words, a relatively low potential. When the channel 50 disappears, a reverse voltage is applied to the pn junction at the boundary surface between the corresponding field relaxation region 38 and the drift region 40, and the depletion layer extends from the corresponding field relaxation region 38 into the drift region 40. The depletion layer extending from the corresponding field relaxation region 38 rapidly depletes the drift region 40 around the bottom of the trench 14. As a result, the concentration of the electric field around the bottom of the trench 14 can be suppressed.

[0042] In the MOSFET 10 according to this embodiment, as Figure 8 As shown, since each connection region 36 extends in a direction intersecting with the field relaxation region 38, it is possible to ensure that the field relaxation region 38 is connected to the main body region 34 through the connection region 36. Therefore, the depletion layer can easily extend from the corresponding field relaxation region 38 to the drift region 40 to effectively suppress the concentration of the electric field at the bottom of the corresponding trench 14.

[0043] In the MOSFET 10 according to this embodiment, as Figure 8 As shown, since each connection region 36 extends in a direction intersecting with the trench 14, electric field concentration can be suppressed when the MOSFET 10 is turned on. The suppression of electric field concentration is described below. Figure 9 As shown, in the overlapping portion where the connection region 36 overlaps with the trench 14, since the connection region 36 exists below the main body region 34, the channel 50 formed in the main body region 34 is not connected to the drift region 40. Therefore, no current flows through the channel 50 in the overlapping portion where the connection region 36 overlaps with the trench 14. In this embodiment, as... Figure 8 As shown, since each connection region 36 extends in a direction intersecting with the trench 14, the overlapping portions of the connection regions 36 and the trench 14 are arranged to be dispersed above the trench 14. In other words, in the MOSFET 10 according to this embodiment, there is no such... Figure 15 , Figure 16The case shown illustrates the situation where the entire side surface of a specific trench overlaps with the connecting area 136. For example... Figure 15 , Figure 16 As shown, when the entire side surface of a particular trench overlaps with the connection region 136, current concentrates in the channel adjacent to the overlapping portion. In contrast, in the MOSFET 10 according to this embodiment, as... Figure 8 As shown, since the overlapping portions of the connection regions 36 and the trench 14 are distributed over the trench 14, the areas where current does not flow are dispersed, and current concentration is less likely to occur. The overlapping portions correspond to the intersecting portions. In this embodiment, since each connection region 36 intersects the trench 14 at an angle, the overlapping portions, in other words, the intersecting portions, are distributed along the length direction of the trench 14. The MOSFET 10 according to this embodiment suppresses current concentration. For this reason, the MOSFET according to this embodiment has a higher current tolerance that can be conducted.

[0044] In the MOSFET 10 according to this embodiment, in a top view of the semiconductor substrate 12, each contact region 32 is arranged at a position overlapping with a corresponding connection region 36. As a result, the on-resistance of the MOSFET 10 is reduced. The reduction in on-resistance is described below. Figure 9 As shown, in the overlapping portion where the contact region 32 overlaps with the trench 14, since the contact region 32 exists above the main body region 34, the channel 50 formed in the main body region 34 is not connected to the source region 30. Therefore, no current flows through the channel 50 in the overlapping portion where the contact region 32 overlaps with the trench 14. As shown in the diagram... Figure 10 In the MOSFET of the comparative example shown, when the connection region 36 and the contact region 32 extend in different directions, the overlapping portions of the contact region 32 and the trench 14, and the overlapping portions of the connection region 36 and the trench 14, are formed at different locations. Each overlapping portion described above corresponds to a portion where current does not flow through the channel. For this reason, the area where current can flow is narrow. In contrast, in the MOSFET 10 according to this embodiment, the contact region 32 and the connection region 36 extend in direction 100 in an overlapping state. In the top view of the semiconductor substrate 12, the position of the intersection portion of the contact region 32 and the trench 14 is substantially the same as the position of the intersection portion of the connection region 36 and the trench 14. Therefore, a wider area where current can flow can be ensured. As a result, the MOSFET 10 according to this embodiment has a relatively low on-resistance.

[0045] In the MOSFET 10 according to this embodiment, each connection region 36 intersects the trench 14 at an angle. For example... Figure 8As shown, the spacing W1 between the connection regions 36 is narrower than the spacing W2 between the connection regions 36 along the direction of the trench 14. When a higher voltage is applied to the MOSFET 10 in the off state, the depletion layer extends from the corresponding connection region 36 to the drift region 40 around the connection region 36, and the voltage is maintained by the depletion layer. Since the spacing W1 is narrow, the drift region 40 within the area of ​​the spacing W1 is easily depleted by the depletion layer extending from the corresponding connection region 36. According to the above structure, the breakdown voltage can be improved; in other words, the withstand voltage of the MOSFET 10 can be improved. When the spacing W2 along the direction of the trench 14 is ensured to be wider, a wider area where current can flow through the trench (in other words, the trench 14 in the area that does not overlap with the connection regions 36) can be ensured. As a result, the on-resistance of the MOSFET can be reduced. As described above, according to this structure, a higher breakdown voltage and a lower on-resistance are possible.

[0046] The method for manufacturing the MOSFET 10 according to this embodiment is described below. Since this manufacturing method has features in the formation of the contact region 32 and the connection region 36, the formation of both the contact region 32 and the connection region 36 is described below.

[0047] In the formation of both contact area 32 and connection area 36, ​​such as Figure 11 As shown, a mask 90 is formed on the top surface 12a of the semiconductor substrate 12. The mask 90 is formed to provide an opening 92 at the top of the region corresponding to the contact region 32 and the connection region 36. Then, p-type impurity ions are implanted into the semiconductor substrate 12 through the mask 90. ​​By changing the ion implantation energy, p-type impurities are implanted into the depth regions of the connection region 36 and the contact region 32. Subsequently, the connection region 36 and the contact region 32 are formed by performing impurity activation annealing. In this manufacturing method, the connection region 36 and the contact region 32 can be formed by ion implantation using a common mask 90. ​​As a result, the MOSFET 10 can be manufactured efficiently.

[0048] (First variant)

[0049] In the MOSFET 10 according to the above embodiment, the side surface of each connection region 36 extends in a linear shape in the direction 100. For example, in a first variation of this disclosure, the side surface of each connection region 36 may extend while bending along the direction 100, such as... Figure 12 As shown in the figure. However, in regions closer to the limits of semiconductor process precision, particularly pattern exposure precision, when the connection region 36 is formed with such... Figure 12 When the side surface is curved as shown, the difference in the corresponding shape of the connecting area becomes more pronounced. In contrast, as... Figure 8As shown, the side surface of each connection region 36 extends in a linear shape in direction 100, thereby enabling the formation of each connection region 36 with higher precision and suppressing differences in the characteristics of the MOSFET 10.

[0050] (Second variant)

[0051] In the above embodiments, such as Figure 8 As shown, in a top view of the semiconductor substrate 12, the field relaxation region 38 extends in a direction perpendicular to the trench 14. However, as Figure 13 As shown, in the second variation of this disclosure, the field relaxation region 38 may extend in a direction that intersects the trench 14 at an inclination.

[0052] (Third variant)

[0053] In the above embodiments, such as Figure 3 As shown, a gap is provided between the field relaxation zone 38 and the bottom end of the trench 14. However, in a third variation of this disclosure, as... Figure 14 As shown, the field relaxation zone 38 can contact the bottom end of the trench 14.

[0054] The y-direction described in this embodiment corresponds to the first direction. The direction 100 described in this embodiment corresponds to the second direction. The x-direction described in this embodiment corresponds to the third direction.

[0055] In the field-effect transistor described in this disclosure, each contact region in a top view of the semiconductor substrate may extend in a second direction to overlap with one of the corresponding connection regions.

[0056] When a field-effect transistor (FET) is turned on, the channel is not connected to the source electrode, and current does not flow at the intersection of each contact region and each trench. Since each contact region overlaps with its corresponding connection region, the non-current-flowing portions lie on top of each other. In other words, the intersections of the connection regions and trenches and the corresponding contact regions and trenches overlap. Therefore, the areas where current does not flow are reduced. Consequently, the on-resistance of the FET can be lowered.

[0057] In the field-effect transistor described in this disclosure, the second direction may be tilted relative to the first direction.

[0058] According to the above structure, the intersecting portions of the connection areas with the trenches are distributed along the length of the trenches. The length direction corresponds to the first direction. Therefore, current concentration can be effectively reduced.

[0059] In the field-effect transistors described in this disclosure, each connection region has a side surface of a linear shape that can extend in a second direction.

[0060] As a result, the characteristics of the field-effect transistor can be stabilized.

[0061] Although embodiments have been described in detail above, these are merely examples and do not limit the scope of this disclosure. The techniques described in this disclosure include various variations and modifications to the specific examples described above. The technical elements described in this disclosure or the accompanying drawings demonstrate technical usefulness individually or in various combinations, and are not limited to the combinations described in this disclosure at the time of submission. Furthermore, the techniques shown in this specification or the accompanying drawings simultaneously achieve multiple objectives, and achieving one of these objectives is itself technically practical.

Claims

1. A field-effect transistor, comprising: Semiconductor substrate (12); Multiple trenches (14) are provided on the top surface of the semiconductor substrate; A gate insulating film (16) is disposed in each of the trenches; A gate electrode (18) is disposed in each of the trenches; as well as The source electrode (22) covering the top surface of the semiconductor substrate, The grooves extend along a first direction on the top surface, and are spaced apart in a direction perpendicular to the first direction. The semiconductor substrate includes a plurality of inter-trench semiconductor regions (26), and each inter-trench semiconductor region is disposed between two adjacent trenches. The inter-trench semiconductor region includes multiple source regions (30), multiple contact regions (32), and multiple host regions (34). Each of the source regions is an n-type electrode that is in contact with both the source electrode and the gate insulating film. Each of the contact regions is a p-type contact area that contacts the source electrode. Each of the main body regions is a p-type impurity region with a lower p-type impurity concentration than each of the contact regions. Each of the main regions is in contact with the gate insulating film on a side closer to the bottom surface of the semiconductor substrate than the source region, and is in contact with a corresponding one of the contact regions and a corresponding one of the source regions on a side closer to the bottom surface of the semiconductor substrate than the contact region and the source region. The semiconductor substrate further includes: Multiple connection regions (36), each of the connection regions (36) being p-type; Multiple field relaxation regions (38), each of which is p-type; and n-type drift region (40), The connection region is located on a side of the semiconductor substrate that is closer to the bottom surface than the main body region. The connection regions extend in a second direction intersecting the first direction in the top view of the semiconductor substrate, and are spaced apart in a direction perpendicular to the second direction in the top view of the semiconductor substrate. The connecting area is connected to the main body area at the intersection points where the connecting area intersects with the main body area. The field relaxation region is located on a side of the semiconductor substrate closer to the bottom surface than the connection region and the trench. The field relaxation regions extend upward in the top view of the semiconductor substrate at a third direction intersecting the first and second directions, and are spaced apart in the top view of the semiconductor substrate in a direction perpendicular to the third direction. Wherein, the field relaxation region is connected to the connection region at the intersection of the field relaxation region and the connection region. The drift region is disposed in a first spacing portion (36x) between two adjacent connection regions of the connection region, a second spacing portion (38x) between two adjacent field relaxation regions of the field relaxation region, and at a position closer to the bottom surface of the semiconductor substrate than the field relaxation region. The drift region contacts the body region on a side closer to the bottom surface of the semiconductor substrate than the body region, and contacts the gate insulating film on a side closer to the bottom surface of the semiconductor substrate than the gate insulating film. In the top view of the semiconductor substrate, each of the contact areas extends in the second direction to overlap with a corresponding one of the connection areas.

2. The field-effect transistor according to claim 1, in, The second direction intersects the first direction at an angle.

3. The field-effect transistor according to any one of claims 1 to 2, in, Each of the connection regions has a side surface with a linear shape extending in the second direction.

4. A method for manufacturing a field-effect transistor, the method comprising: p-type impurities are implanted into multiple contact regions and multiple connection regions of the semiconductor substrate through a common mask. The field-effect transistor includes: The semiconductor substrate (12); Multiple trenches (14) are provided on the top surface of the semiconductor substrate; A gate insulating film (16) is disposed in each of the trenches; A gate electrode (18) is disposed in each of the trenches; and The source electrode (22) covering the top surface of the semiconductor substrate, The grooves extend along a first direction on the top surface, and are spaced apart in a direction perpendicular to the first direction. The semiconductor substrate includes a plurality of inter-trench semiconductor regions (26), and each inter-trench semiconductor region is disposed between two adjacent trenches. The inter-trench semiconductor region includes multiple source regions (30), contact regions (32), and multiple body regions (34), wherein each source region is an n-type region in contact with the source electrode and the gate insulating film. Each of the contact regions is a p-type contact area that contacts the source electrode. Each of the main body regions is a p-type impurity region with a lower p-type impurity concentration than each of the contact regions. Each of the main regions is in contact with the gate insulating film on a side closer to the bottom surface of the semiconductor substrate than the source region, and is in contact with a corresponding one of the contact regions and a corresponding one of the source regions on a side closer to the bottom surface of the semiconductor substrate than the contact region and the source region. The semiconductor substrate further includes: Connection regions (36), each of the connection regions (36) is p-shaped; Multiple field relaxation regions (38), each of which is p-type; and n-type drift region (40), The connection region is located on a side of the semiconductor substrate that is closer to the bottom surface than the main body region. The connection regions extend in a second direction intersecting the first direction in the top view of the semiconductor substrate, and are spaced apart in a direction perpendicular to the second direction in the top view of the semiconductor substrate. The connecting area is connected to the main body area at the intersection points where the connecting area intersects with the main body area. The field relaxation region is located on a side of the semiconductor substrate closer to the bottom surface than the connection region and the trench. The field relaxation regions extend upward in the top view of the semiconductor substrate at a third direction intersecting the first and second directions, and are spaced apart in the top view of the semiconductor substrate in a direction perpendicular to the third direction. The field relaxation region is connected to the connection region at the intersection of the field relaxation region and the connection region. The drift region is located at a first interval (36x) between two adjacent connection regions of the connection region, a second interval (38x) between two adjacent field relaxation regions of the field relaxation region, and at a position closer to the bottom surface of the semiconductor substrate than the field relaxation region. The drift region is in contact with the main body region on the side closer to the bottom surface of the semiconductor substrate than the main body region, and in contact with the gate insulating film on the side closer to the bottom surface of the semiconductor substrate than the gate insulating film.

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