Battery protection element and chip thereof

Abstract

The present disclosure provides a battery protection element and a chip thereof. The chip has a buffer circuit and a switch circuit. The buffer circuit is configured to generate a gate control signal according to a first logic control signal, a first voltage, a second voltage and a third voltage. The switch circuit has an inverter circuit and a selection circuit. The inverter circuit is configured to invert a second logic control signal into a third logic control signal. The selection circuit is configured to select the second or third voltage to transmit to the buffer circuit according to the second logic control signal and the third logic control signal. When the battery has an overcharge or an overdischarge, the gate control signal is configured to turn off a power transistor.

Description

[0001] Cross-references

[0002] This application claims priority and benefits to U.S. formal application No. 17 / 400,405, filed on August 12, 2021, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a battery protection element and its chip (wafer). In particular, it relates to a battery protection element and its chip that does not use a diode. Background Technology

[0004] Typically, when a battery is overcharged or over-discharged, multiple transistors and diodes are operated to shut down the battery. However, the critical voltage of these diodes limits the operation of this battery protection. Therefore, avoiding problems caused by the critical voltage of these diodes becomes an important issue in this field.

[0005] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0006] One embodiment of this disclosure provides a chip configured to protect a battery. The chip includes a buffer circuit and a switching circuit. The buffer circuit is configured to generate a gate control signal based on a first logic control signal, a first voltage, a second voltage, and a third voltage. The switching circuit is configured to transmit either the second voltage or the third voltage to the buffer circuit. The switching circuit has an inverting circuit and a selecting circuit. The inverting circuit is configured to invert the second logic control signal to generate a third logic control signal. The selecting circuit is configured to select either the second voltage or the third voltage based on the second logic control signal or the third logic control signal to transmit to the buffer circuit. When the battery experiences an overcharge or an over-discharge, the gate control signal is configured to turn off a power transistor.

[0007] In some embodiments, the first voltage is provided by a cathode of the battery, the second voltage is provided by an anode of the battery, the third voltage is provided by an anode of a charger in a charging mode, and the third voltage is provided by an anode of a load in a discharging mode. The anode of the battery is coupled to a first source / drain of the power transistor.

[0008] In some embodiments, in the charging mode, a cathode of the charger is coupled to the cathode of the battery, and an anode of the charger is coupled to a second source / drain of the power transistor.

[0009] In some embodiments, in the discharge mode, a cathode of the load is coupled to the cathode of the battery, and an anode of the load is coupled to a second source / drain of the power transistor.

[0010] In some embodiments, the chip further includes a logic control circuit, a mode detection circuit, an overcharge detection circuit, and an over-discharge detection circuit. The logic control circuit is configured to generate a first logic control signal and a second logic control signal based on a first detection signal, a second detection signal, and a third detection signal. The mode detection circuit is configured to generate the first detection signal based on a second voltage and a third voltage to indicate whether the circuit is in the charging mode or the discharging mode. The overcharge detection circuit is configured to generate the second detection signal based on the first voltage and the second voltage to indicate whether overcharging has occurred. The over-discharge detection circuit is configured to generate the third detection signal based on the first voltage and the second voltage to indicate whether over-discharge has occurred.

[0011] In some embodiments, the inverting circuit includes a first transistor and a second transistor. The first transistor has a first source, a first drain, and a first gate. The second transistor has a second source, a second drain, and a second gate. The first transistor is a P-type transistor, and the second transistor is an N-type transistor. The first gate and the second gate are configured to receive the second logic control signal, the first source is configured to receive the first voltage, the second source is configured to receive the third voltage, the first drain is coupled to the second drain, and the first drain and the second drain are configured to generate the third logic control signal.

[0012] In some embodiments, the selection circuit includes a third transistor and a fourth transistor. The third transistor has a third source, a third drain, and a third gate. The fourth transistor has a fourth source, a fourth drain, and a fourth gate. The third and fourth transistors are N-type transistors. The third gate is configured to receive the second logic control signal, the fourth gate is configured to receive the third logic control signal, the third source is coupled to the fourth source, the third drain is configured to receive the third voltage, the fourth drain is configured to receive the second voltage, and the third and fourth sources are configured to transmit the second voltage or the third voltage to the buffer circuit.

[0013] In some embodiments, the buffer circuit includes a fifth transistor and a sixth transistor. The fifth transistor has a fifth source, a fifth drain, and a fifth gate. The sixth transistor has a sixth source, a sixth drain, and a sixth gate. The fifth transistor is a P-type transistor, and the sixth transistor is an N-type transistor. The fifth gate and the sixth gate are configured to receive the first logic control signal, the fifth source is configured to receive the first voltage, the sixth source is configured to receive the second voltage or the third voltage, the fifth drain is coupled to the sixth drain, and the fifth drain and the sixth drain are configured to generate the gate control signal.

[0014] In some embodiments, when the overcharge occurs, the switching circuit generates a gate control signal having a voltage equal to the third voltage to turn off the power transistor, wherein the third voltage is lower than the second voltage.

[0015] In some embodiments, when the over-discharge occurs, the switching circuit generates a gate control signal having a voltage equal to the second voltage to turn off the power transistor, wherein the second voltage is lower than the third voltage.

[0016] Another embodiment of this disclosure provides a power protection element including a power transistor and a chip. The power transistor has a control gate, a first source / drain, and a second source / drain. The first source / drain is coupled to an anode of a battery, and the second source / drain is coupled to an anode of a load in a discharge mode. The first source / drain is also coupled to an anode of a charger in a charging mode. The chip includes a buffer circuit and a switching circuit. The buffer circuit is configured to transmit either a first voltage or one of a second voltage and a third voltage as a gate control signal to the control gate according to a first logic control signal. The switching circuit is configured to transmit either the second voltage or the third voltage to the buffer circuit according to a second logic control signal. When the charger is disconnected from the power transistor, the buffer circuit is also configured to continuously transmit the gate signal to the control gate to prevent the power transistor from being turned off.

[0017] In some embodiments, the switching circuit includes an inverter circuit and a selection circuit. The inverter circuit is configured to invert the second logic control signal to generate a third logic control signal. The selection circuit is configured to select either the second voltage or the third voltage to be transmitted to the buffer circuit based on the second logic control signal and the third logic control signal.

[0018] In some embodiments, the inverting circuit includes a first transistor and a second transistor. The first transistor has a first source, a first drain, and a first gate. The second transistor has a second source, a second drain, and a second gate. The first transistor is a P-type transistor, and the second transistor is an N-type transistor. The first gate and the second gate are configured to receive the second logic control signal, the first source is configured to receive the first voltage, the second source is configured to receive the third voltage, the first drain is coupled to the second drain, and the first drain and the second drain are configured to generate the third logic control signal.

[0019] In some embodiments, the selection circuit includes a third transistor and a fourth transistor. The third transistor has a third source, a third drain, and a third gate. The fourth transistor has a fourth source, a fourth drain, and a fourth gate. The third and fourth transistors are N-type transistors. The third gate is configured to receive the second logic control signal, the fourth gate is configured to receive the third logic control signal, the third source is coupled to the fourth source, the third drain is configured to receive the third voltage, the fourth drain is configured to receive the second voltage, and the third and fourth sources are configured to transmit the second voltage or the third voltage to the buffer circuit.

[0020] In some embodiments, the buffer circuit includes a fifth transistor and a sixth transistor. The fifth transistor has a fifth source, a fifth drain, and a fifth gate. The sixth transistor has a sixth source, a sixth drain, and a sixth gate. The fifth transistor is a P-type transistor, and the sixth transistor is an N-type transistor. The fifth gate and the sixth gate are configured to receive the first logic control signal, the fifth source is configured to receive the first voltage, the sixth source is configured to receive the second voltage or the third voltage, and the fifth drain and the sixth drain are coupled to the control gate and configured to transmit the gate control signal.

[0021] In some embodiments, the chip further includes a logic control circuit, a mode detection circuit, an overcharge detection circuit, and an over-discharge detection circuit. The logic control circuit is configured to generate a first logic control signal and a second logic control signal based on a first detection signal, a second detection signal, and a third detection signal. The mode detection circuit is configured to generate the first detection signal based on a second voltage and a third voltage to indicate whether the device is in the charging mode or the discharging mode. The overcharge detection circuit is configured to generate the second detection signal based on the first voltage and the second voltage to indicate whether an overcharge has occurred in the charging mode. The over-discharge detection circuit is configured to generate the third detection signal based on the first voltage and the second voltage to indicate whether an over-discharge has occurred in the discharging mode.

[0022] In some embodiments, the first voltage is provided by a cathode of the battery, the second voltage is provided by the anode of the battery, the third voltage is provided by the anode of the charger in the charging mode, and the third voltage is provided by the anode of the load in the discharging mode.

[0023] In some embodiments, the third voltage in the discharge mode is higher than the third voltage in the charging mode, the third voltage is lower than the second voltage in the charging mode, and the third voltage is higher than the second voltage in the discharge mode.

[0024] In some embodiments, when the overcharge occurs in the charging mode, the switching circuit transmits a gate control signal having a voltage equal to the third voltage to turn off the power transistor.

[0025] In some embodiments, when the over-discharge occurs in the discharge mode, the switching circuit transmits a gate control signal having a voltage equal to the second voltage to turn off the power transistor.

[0026] The technical features and advantages of this disclosure have been broadly summarized above, thus enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the claims. Attached Figure Description

[0027] A more comprehensive understanding of the disclosure of this application can be obtained by referring to the accompanying drawings in conjunction with the embodiments and claims. The same element symbols in the drawings refer to the same elements.

[0028] Figure 1 This is a schematic diagram illustrating battery protection elements according to some embodiments of the present disclosure.

[0029] Figure 2 This is a schematic diagram illustrating some embodiments of the present disclosure of a battery protection element in a charging mode.

[0030] Figure 3 This is a schematic diagram illustrating chips according to some embodiments of this disclosure.

[0031] Figure 4 This is a block diagram illustrating buffer circuits, switching circuits, and power transistors of some embodiments of this disclosure.

[0032] Figure 5 This is an operation diagram illustrating some embodiments of this disclosure in a charging mode.

[0033] Figure 6 The diagram illustrates some embodiments of this disclosure in a discharge mode.

[0034] Explanation of reference numerals in the attached figures:

[0035] 10: Battery protection components

[0036] 100: Chip

[0037] 110: Buffer circuit

[0038] 120: Switching circuit

[0039] 130: Logic control circuit

[0040] 140: Pattern Detection Circuit

[0041] 141: Inverting circuit

[0042] 142: Selection Circuit

[0043] 150: Overcharge detection circuit

[0044] 160: Over-discharge detection circuit

[0045] 200: Power Transistor

[0046] AD1: Anode

[0047] AD2: Anode

[0048] AD3: Anode

[0049] BA: Battery

[0050] CA: Charger

[0051] CD1: Cathode

[0052] CD2: Cathode

[0053] CD3: Cathode

[0054] CDO: Gate control signal

[0055] CG: Control Gate

[0056] D1: Drain

[0057] D2: Drain electrode

[0058] D3: Drain

[0059] D4: Drain

[0060] D5: Drain electrode

[0061] D6: Drain electrode

[0062] DS1: Detection signal

[0063] DS2: Detection signal

[0064] DS3: Detection signal

[0065] G1: Gate

[0066] G2: Gate

[0067] G3: Gate

[0068] G4: Gate

[0069] G5: Gate

[0070] G6: Gate

[0071] I1: Current

[0072] I2: Current

[0073] LA: Load

[0074] N1: Node

[0075] OC1: Operation Chart

[0076] OC2: Operation Chart

[0077] S1: Source

[0078] S2: Source

[0079] S3: Source

[0080] S4: Source

[0081] S5: Source

[0082] S6: Source

[0083] SC1: Logic control signal

[0084] SC2: Logic control signal

[0085] SC3: Logic control signal

[0086] SD1: Source / Drain

[0087] SD2: Source / Drain

[0088] T1: P-type metal-oxide-semiconductor (PMOS) transistor

[0089] T2: N-type metal-oxide-semiconductor (NMOS) transistor

[0090] T3: P-type metal-oxide-semiconductor (PMOS) transistor

[0091] T4: N-type metal-oxide-semiconductor (NMOS) transistor

[0092] T5: N-type metal-oxide-semiconductor (NMOS) transistor

[0093] T6: N-type metal-oxide-semiconductor (NMOS) transistor

[0094] VDD: Voltage

[0095] Vm: Voltage

[0096] VSS: Voltage Detailed Implementation

[0097] Embodiments or examples of the present disclosure shown in the accompanying drawings will now be described using specific language. It should be understood that the scope of this disclosure is not intended to be limited thereto. Any modifications or improvements to the described embodiments, and any further applications of the principles described herein, will be considered commonplace by those skilled in the art. Component numbers may be repeated throughout the embodiments, but this does not necessarily mean that a feature of one embodiment is applicable to another embodiment, even if they share the same component numbers.

[0098] It should be understood that while the terms “first,” “second,” “third,” etc., may be used in this text to describe different elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish an element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, the terms “first element,” “component,” “region,” “layer,” or “section” discussed below may be referred to as a second device, component, region, layer, or part without departing from the teachings of this text.

[0099] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include multiple forms unless the context clearly indicates otherwise. It will be further understood that when the terms “comprises” and / or “comprising” are used in this specification, these terms specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0100] Figure 1 This is a schematic diagram illustrating a battery protection element 10 according to some embodiments of the present disclosure. The battery protection element 10 is coupled to a battery BA and a load LA. Figure 1 In this configuration, battery BA and battery protection element 10 are in a discharge mode. Battery BA is configured to supply a current I1 from a cathode CD1 of battery BA to a cathode CD2 of load LA, and receive current I1 from an anode AD1 of battery BA.

[0101] Battery protection element 10 is configured to prevent over-discharge from occurring in discharge mode. When over-discharge occurs, battery protection element 10 is configured to interrupt the current I1 supplied to the load LA in order to protect the battery BA and the load LA from overcharging.

[0102] The battery protection element 10 is also configured to prevent overcharging in a charging mode. Please refer to [link / reference]. Figure 2 . Figure 2 This is a schematic diagram illustrating the battery protection element 10 in charging mode according to some embodiments of the present disclosure.

[0103] exist Figure 2In the charging mode, battery BA and battery protection element 10 are in charging mode. A charger CA is configured to supply a current I2 from a cathode CD3 to a cathode CD1 of the charger CA, and the current I2 is received by an anode AD3 of the charger CA.

[0104] When overcharging occurs, the battery protection element 10 is configured to interrupt the current I2 supplied to the battery BA in order to protect the battery BA from overcharging with the load LA.

[0105] Please refer to this together. Figure 1 and Figure 2 The battery protection element 10 includes a chip 100 and a power transistor 200. The chip 100 is configured to generate a gate control signal CDO based on a voltage VDD, a voltage VSS, and a voltage Vm. A control gate CG of the power transistor 200 is configured to receive the gate control signal CDO. A source / drain SD1 of the power transistor 200 is coupled to an anode AD1, and a source / drain SD2 of the power transistor 200 is coupled to a node N1. The power transistor 200 is configured to carry current I1 in discharge mode and current I2 in discharge mode. The power transistor 200 is also configured to be turned off by the gate control signal CDO in the event of over-discharge and / or overcharge.

[0106] Voltage VDD is provided by cathode CD1, and voltage VSS is provided by anode AD1. Voltage VDD is higher than voltage VSS, and the difference between voltage VDD and voltage VSS is related to the electromotive force provided by battery BA.

[0107] Voltage Vm is transmitted via node N1. In discharge mode, anode AD2 is coupled to node N1. In charging mode, anodes AD2 and AD3 are coupled to node N1. In other words, voltage Vm is provided by anode AD2 in discharge mode and by anode AD3 in charging mode. Therefore, voltage Vm in charging mode is different from voltage Vm in discharge mode.

[0108] Please refer to Figure 3 . Figure 3 This is a schematic diagram illustrating a chip 100 according to some embodiments of the present disclosure. The chip 100 includes a buffer circuit 110, a switching circuit 120, a logic control circuit 130, a mode detection circuit 140, an overcharge detection circuit 150, and an over-discharge detection circuit 160.

[0109] The buffer circuit 110 is configured to receive a logic control signal SC1 generated by the logic control circuit 130 and a voltage VDD. The buffer circuit 110 is also configured to receive a voltage VSS or a voltage Vm transmitted from the switching circuit 120. The buffer circuit 110 generates a gate control signal CDO based on the logic control signal CS1, the voltage VDD, the voltage VSS, and the voltage Vm.

[0110] The control circuit 120 is configured to receive voltage VSS, voltage Vm, and a logic control signal SC2 generated by the logic control circuit 130. The switching circuit 120 is also configured to transmit voltage VSS or voltage Vm to the buffer circuit 110 according to the logic control signal SC2.

[0111] The logic control circuit 130 is configured to receive a detection signal DS1 generated by the mode detection circuit 140, a detection signal DS2 generated by the overcharge detection circuit 150, and a detection signal DS3 generated by the over-discharge detection circuit 160. The logic control circuit 130 is also configured to generate logic control signals SC1 and SC2 based on the detection signals DS1, DS2, and DS3.

[0112] The mode detection unit 140 is configured to receive voltage VSS and voltage Vm, and is also configured to generate a detection signal DS1 based on voltage VSS and voltage Vm. In some embodiments, the mode detection circuit 140 is configured to detect whether it is in a charging mode or a discharging mode by comparing voltage VSS and voltage Vm. When voltage VSS is higher than voltage Vm, the battery BA and battery protection element 100 are in a charging mode. When voltage VSS is lower than voltage Vm, the battery BA and battery protection element 100 are in a discharging mode. The mode detection circuit 140 generates a detection signal DS1 to indicate whether it is in a charging mode or a discharging mode.

[0113] The overcharge detection circuit 150 is configured to receive voltage VDD and voltage Vm, and is also configured to generate a detection signal DS2 based on voltage VDD and voltage VSS. In some embodiments, in a charging mode, the overcharge detection circuit 150 is configured to detect whether overcharging has occurred by comparing voltage VDD and voltage VSS. When the difference between voltage VDD and voltage VSS is higher than a first predetermined threshold, overcharging occurs, and the overcharge detection circuit 150 generates a detection signal DS2 to indicate that overcharging has occurred.

[0114] The over-discharge detection circuit 160 is configured to receive voltage VDD and voltage VSS, and is also configured to generate a detection signal DS3 based on voltage VDD and voltage VSS. In some embodiments, in discharge mode, the over-discharge detection circuit 160 is configured to detect whether over-discharge has occurred by comparing voltage VDD and voltage VSS. When the difference between voltage VDD and voltage VSS is lower than a second predetermined threshold, over-discharge occurs, and the over-discharge detection circuit 160 generates a detection signal DS3 to indicate that over-discharge has occurred.

[0115] Please refer to Figure 4 . Figure 4 This is a block diagram illustrating a buffer circuit 110, a switching circuit 120, and a power transistor 200 in some embodiments of this disclosure.

[0116] In some embodiments, buffer circuit 110 is an inverter. Buffer circuit 110 inverts logic control signal SC1 to generate gate control signal CDO. When logic control signal SC1 has a digital high level, gate control signal CDO is generated to have a digital low level. Depending on the operation of switching circuit 140, the digital low level is voltage VSS or voltage Vm. In some embodiments, digital high level is equal to voltage VDD. In some embodiments, digital low level is equal to voltage VSS.

[0117] The buffer circuit 110 has a P-type metal-oxide-semiconductor (PMOS) transistor T1 and an N-type metal-oxide-semiconductor (NMOS) transistor T2. The PMOS transistor T1 has a gate G1, a source S1, and a drain D1. The NMOS transistor T2 has a gate G2, a source S2, and a drain D2. Gates G1 and G2 are configured to receive a logic control signal SC1. Source S1 is configured to receive a voltage VDD. Source S2 is coupled to a switching circuit 140. Drain D1 is coupled to drain D2, and drains D1 and D2 are configured to generate a gate control signal CDO.

[0118] When the logic control signal SC1 is at a digital high level to turn on NMOS transistor T2 and turn off PMOS transistor T1, the gate control signal CDO is pulled down to voltage VSS or voltage Vm. When the logic control signal SC1 is at a digital low level to turn off NMOS transistor T2 and turn on PMOS transistor T1, the gate control signal CDO is pulled up to voltage VDD.

[0119] In some embodiments, the switching circuit 120 includes an inverting circuit 141 and a selection circuit 142. The inverting circuit 141 includes a PMOS transistor T3 and an NMOS transistor T4, and the selection circuit 142 includes a NMOS transistor T5 and an NMOS transistor T6.

[0120] PMOS transistor T3 has a gate G3, a source S3, and a drain D3. NMOS transistor T4 has a gate G4, a source S4, and a drain D4. Gates G3 and G4 are configured to receive a logic control signal SC2. Source S3 is configured to receive a voltage VDD. Source S4 is configured to receive a voltage Vm. Drain D3 is coupled to drain D4, and drains D3 and D4 are configured to generate a logic control signal SC3.

[0121] When logic control signal SC2 is at a high level to turn on NMOS transistor T4 and turn off PMOS transistor T3, logic control signal SC3 is pulled down to voltage Vm. When logic control signal SC2 is at a low level to turn off NMOS transistor T4 and turn on PMOS transistor T3, logic control signal SC3 is pulled up to voltage VDD.

[0122] NMOS transistor T5 has a gate G5, a source S5, and a drain D5. NMOS transistor T6 has a gate G6, a source S6, and a drain D6. Gate G5 is configured to receive logic control signal SC3, and gate G6 is configured to receive logic control signal SC2. Drain D5 is configured to receive voltage VSS. Drain D6 is configured to receive voltage Vm. Source S5 is coupled to source S6, and sources S5 and S6 are configured to transfer voltage VSS or voltage Vm to source S2 of NMOS transistor T2 in buffer circuit 110.

[0123] When logic control signal SC2 is at a digital high level and logic control signal SC3 has a voltage Vm, NMOS transistor T5 is turned off and NMOS transistor T6 is turned on. Therefore, voltage Vm is transmitted to the source T2 of NMOS transistor T2 in buffer circuit 110. When logic control signal SC2 is at a digital low level and logic control signal SC3 has a voltage VDD, NMOS transistor T5 is turned on and NMOS transistor T6 is turned off. Therefore, voltage VSS is transmitted to the source S2 of NMOS transistor T2 in buffer circuit 110.

[0124] According to Figures 1 to 4 The battery protection element 10 shown, along with the operation of each charging and discharging mode, is summarized and displayed. Figure 5 and Figure 6 middle.

[0125] exist Figure 5 In this document, an operation diagram OC1 in a charging mode is provided according to some embodiments of the present disclosure. Figure 6 In this disclosure, an operation chart OC2 in the discharge mode is provided according to some embodiments.

[0126] Please refer to Figure 5 In charging mode, voltage VDD is higher than voltage Vm. Charger CA is connected to the battery, load LA, and battery protection element 10. When no overcharging occurs, current I2 flows from source / drain SD1 to source / drain SD2 via power transistor 200. In this case, logic control signal SC1 is digitally low, and gate control signal CDO is voltage VDD. Source / drain SD1 and source / drain SD2 are voltages VSS and Vm, respectively. Gate control signal CDO keeps power transistor 200 on to maintain current I2 flow. In some embodiments, logic control signals SC2 and SC3 are digitally high and voltage Vm, respectively.

[0127] When overcharging occurs, logic control signals SC2 and SC3 are respectively at a digital high level and have a voltage Vm, so that the voltage Vm is transmitted to the source S2 of NMOS transistor T2. Logic control signal SC1 is at a digital high level, and gate control signal CDO has a voltage Vm. Power transistor 200 is turned off by gate control signal CDO.

[0128] When the charger CA disconnects from the battery BA in charging mode, the battery protection element 10 is also configured to prevent the load LA from losing power. In other words, when the charger CA is removed from the load LA and the battery BA, the battery protection element 10 is also configured to maintain the current supplied to the load LA. In this case, due to the disconnection from the charger CA, the voltage Vm rises above the voltage VSS. The mode detection circuit 140 detects the rise in voltage Vm and instructs the logic control circuit 130 to generate logic control signals SC1 and SC2 with a digital high level. At the same time, a gate control signal CDO is generated with voltage Vm. Therefore, the source / drain SD2 of the power transistor 200 also has voltage Vm (which is now above voltage VSS), and current I1 is transferred from the source / drain SD2 to the source / drain SD1 via the power transistor 200. During the disconnection from the charger CA, the load LA remains powered on.

[0129] Please refer to Figure 6In discharge mode, voltage VSS is lower than voltage Vm. Charger CA is disconnected from the battery, load LA, and battery protection element 10. When no over-discharge occurs, current I1 flows from source / drain SD2 to source / drain SD1 via power transistor 200. In this case, logic control signal SC1 is digitally low, and gate control signal CDO is voltage VDD. Source / drain SD1 and source / drain SD2 are voltages VSS and Vm, respectively. Gate control signal CDO keeps power transistor 200 on to maintain current I1 flow. In some embodiments, logic control signal SC2 and logic control signal SC3 are digitally low and voltage VDD, respectively.

[0130] When over-discharge occurs, logic control signals SC2 and SC3 are digitally high and voltage VDD, respectively, to transmit voltage VSS to the source S2 of NMOS transistor T2. Logic control signal SC1 is digitally low, and gate control signal CDO is voltage VSS. Power transistor 200 is turned off by gate control signal CDO.

[0131] When the charger CA is reconnected to the battery BA in discharge mode, the battery protection element 10 is also configured to prevent the load LA from losing power. In other words, when the charger CA is reconnected to both the load LA and the battery BA, the battery protection element 10 is also configured to maintain the current supplied to the load LA. In this case, due to the reconnection to the charger CA, the voltage Vm drops below the voltage VSS. The mode detection circuit 140 detects the drop in voltage Vm and instructs the logic control circuit 130 to generate logic control signals SC1 and SC2, which have digital high and logic low levels, respectively. Simultaneously, a gate control signal CDO is generated with voltage VSS. Therefore, the source / drain SD2 of the power transistor 200 has voltage Vm (which is now below voltage VSS), and current I2 is transferred from the source / drain SD1 to the source / drain SD2 via the power transistor 200. During the reconnection to the charger CA, the load LA remains energized.

[0132] In some traditional methods, battery protection chips use diodes to connect to the system low level, which has different voltage levels. Due to the characteristics of diodes, when the voltage difference between opposite sides of a diode does not exceed its critical value, the diode acts as an open circuit. Therefore, in some cases, the system low level cannot switch correctly or cannot be transmitted via the diode.

[0133] Furthermore, in other traditional methods, when the charger is removed from the load, the load loses power and immediately shuts down. This hardware shutdown can potentially damage components such as mobile phones.

[0134] Compared to the conventional methods described above, the battery protection element 10 provided by this disclosure uses a power transistor 200 without the need for any diodes to control the currents I1 / I2 supplied to the load LA. Because the power transistor 200 can be turned on and off immediately according to the gate control signal CDO without a threshold value, the battery protection element 10 avoids the aforementioned problems in the conventional methods.

[0135] One embodiment of this disclosure provides a chip configured to protect a battery. The chip includes a buffer circuit and a switching circuit. The buffer circuit is configured to generate a gate control signal based on a first logic control signal, a first voltage, a second voltage, and a third voltage. The switching circuit is configured to transmit the second voltage or the third voltage to the buffer circuit. The switching circuit has an inverting circuit and a selecting circuit. The inverting circuit is configured to invert the second logic control signal to generate a third logic control signal. The selecting circuit is configured to select the second voltage or the third voltage based on the second logic control signal or the third logic control signal to transmit to the buffer circuit. When an overcharge or over-discharge occurs, the gate control signal is configured to turn off a power transistor.

[0136] Another embodiment of this disclosure provides a power protection element including a power transistor and a chip. The power transistor has a control gate, a first source / drain, and a second source / drain. The first source / drain is coupled to an anode of a battery, and the second source / drain is coupled to an anode of a load in a discharge mode. The first source / drain is also coupled to an anode of a charger in a charging mode. The chip includes a buffer circuit and a switching circuit. The buffer circuit is configured to transmit either a first voltage or one of a second voltage and a third voltage as a gate control signal to the control gate according to a first logic control signal. The switching circuit is configured to transmit either the second voltage or the third voltage to the buffer circuit according to a second logic control signal. When the charger is disconnected from the power transistor, the buffer circuit is also configured to continuously transmit the gate signal to the control gate to prevent the power transistor from being turned off.

[0137] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be used to replace many of the processes described above.

[0138] Furthermore, the scope of this disclosure is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this disclosure that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A chip configured to electrically connect a battery and a load, wherein a cathode of the battery is connected to a cathode of the load, comprising: A buffer circuit configured to generate a gate control signal based on a first logic control signal, a first voltage, a second voltage, and a third voltage; A switching circuit configured to transmit the second voltage or the third voltage to the buffer circuit, wherein the switching circuit includes: An inverter circuit configured to invert a second logic control signal to generate a third logic control signal; and A selection circuit is configured to select the second voltage or the third voltage to be transmitted to the buffer circuit based on the second logic control signal or the third logic control signal. A logic control circuit is configured to generate the first logic control signal and the second logic control signal based on a first detection signal, a second detection signal and a third detection signal; A mode detection circuit is configured to compare the second voltage with the third voltage and generate a first detection signal to indicate whether it is in a charging mode or a discharging mode, wherein when the second voltage is greater than the third voltage, it is in the charging mode, and when the second voltage is less than the third voltage, it is in the discharging mode. An overcharge detection circuit is configured to detect whether a difference between a first voltage and a second voltage is greater than a first predetermined threshold. When the difference is greater than the first predetermined threshold, the overcharge detection circuit is further configured to generate the second detection signal to indicate that an overcharge has occurred. An over-discharge detection circuit is configured to detect whether the difference is less than a second predetermined value. When the difference is less than the second predetermined value, the over-discharge detection circuit is further configured to generate the third detection signal to indicate that an over-discharge has occurred. When the battery experiences overcharging or over-discharging, the gate control signal is configured to turn off a power transistor, wherein a first source / drain of the power transistor is coupled to an anode of the battery, and a second source / drain of the power transistor is coupled to an anode of the load. When in this charging mode, the cathode and anode of the load are respectively connected to the cathode and anode of a charger, so that the charger charges the battery. When in this discharge mode, the load is disconnected from the charger. When the charger is disconnected from the load, the gate control signal is configured to keep the power transistor on, ensuring that the load continues to receive current from the battery and preventing the load from losing power. When the charger is disconnected and then connected to the load, the gate control signal is configured to keep the power transistor on, so that the load continues to receive a current from the charger and avoids the load losing power.

2. The chip of claim 1, wherein the first voltage is provided by the cathode of the battery, the second voltage is provided by the anode of the battery, the third voltage is provided by the anode of a charger in the charging mode, and the third voltage is provided by the anode of the load in the discharging mode.

3. The chip of claim 2, wherein in the charging mode, the cathode of the charger is coupled to the cathode of the battery, and the anode of the charger is coupled to the second source / drain of the power transistor.

4. The chip of claim 2, wherein in the discharge mode, the cathode of the load is coupled to the cathode of the battery, and the anode of the load is coupled to the second source / drain of the power transistor.

5. The chip of claim 1, wherein the inverting circuit comprises: A first transistor has a first source, a first drain, and a first gate; as well as A second transistor having a second source, a second drain, and a second gate; The first transistor is a P-type transistor, and the second crystal is an N-type transistor; as well as The first gate and the second gate are configured to receive the second logic control signal, the first source is configured to receive the first voltage, the second source is configured to receive the third voltage, the first drain is coupled to the second drain, and the first drain and the second drain are configured to generate the third logic control signal.

6. The chip of claim 1, wherein the selection circuit comprises: A third transistor having a third source, a third drain, and a third gate; as well as A fourth transistor having a fourth source, a fourth drain, and a fourth gate; The third transistor and the fourth transistor are N-type transistors; as well as The third gate is configured to receive the second logic control signal, the fourth gate is configured to receive the third logic control signal, the third source is coupled to the fourth source, the third drain is configured to receive the third voltage, the fourth drain is configured to receive the second voltage, and the third source and the fourth source are configured to transmit the second voltage or the third voltage to the buffer circuit.

7. The chip of claim 1, wherein the buffer circuit comprises: A fifth transistor having a fifth source, a fifth drain, and a fifth gate; as well as A sixth transistor having a sixth source, a sixth drain, and a sixth gate; The fifth transistor is a P-type transistor, and the sixth transistor is an N-type transistor; as well as The fifth gate and the sixth gate are configured to receive the first logic control signal, the fifth source is configured to receive the first voltage, the sixth source is configured to receive the second voltage or the third voltage, the fifth drain is coupled to the sixth drain, and the fifth drain and the sixth drain are configured to generate the gate control signal.

8. The chip of claim 1, wherein when the overcharge occurs, the switching circuit generates the gate control signal having a voltage equal to the third voltage to turn off the power transistor, wherein the third voltage is lower than the second voltage.

9. The chip of claim 1, wherein when the over-discharge occurs, the switching circuit generates the gate control signal having a voltage equal to the second voltage to turn off the power transistor, wherein the second voltage is lower than the third voltage.

10. A battery protection element configured to electrically connect a battery and a load, wherein a cathode of the battery is connected to a cathode of the load, comprising: A power transistor has a control gate, a first source / drain and a second source / drain, the first source / drain being coupled to an anode of the battery, the second source / drain being coupled to an anode of the load in a discharge mode, and the first source / drain being coupled to an anode of a charger in a charging mode. as well as A chip, comprising: A buffer circuit is configured to transmit a first voltage or one of a second voltage and a third voltage as a gate control signal to the control gate according to a first logic control signal. A switching circuit is configured to transmit the second voltage or the third voltage to the buffer circuit according to a second logic control signal; A logic control circuit is configured to generate the first logic control signal and the second logic control signal based on a first detection signal, a second detection signal and a third detection signal; A mode detection circuit is configured to compare the second voltage with the third voltage and generate a first detection signal to indicate whether the circuit is in the charging mode or the discharging mode, wherein the circuit is in the charging mode when the second voltage is greater than the third voltage and in the discharging mode when the second voltage is less than the third voltage. An overcharge detection circuit is configured to detect whether a difference between a first voltage and a second voltage is greater than a first predetermined threshold. When the difference is greater than the first predetermined threshold, the overcharge detection circuit is further configured to generate the second detection signal to indicate that an overcharge has occurred. as well as An over-discharge detection circuit is configured to detect whether the difference is less than a second predetermined value. When the difference is less than the second predetermined value, the over-discharge detection circuit is further configured to generate a third detection signal to indicate that an over-discharge has occurred. When in this charging mode, the cathode and anode of the load are respectively connected to the cathode and anode of the charger, so that the charger charges the battery. When in this discharge mode, the load is disconnected from the charger. When the charger switches from being disconnected to being connected to the load, the gate control signal is configured to keep the power transistor on, ensuring that the load continues to receive current from the charger and preventing the load from losing power. When the charger disconnects from the power transistor, the buffer circuit is also configured to continuously transmit the gate signal to the control gate to prevent the power transistor from being turned off.

11. The battery protection element of claim 10, wherein the switching circuit comprises: An inverter circuit is configured to invert the second logic control signal to generate a third logic control signal; as well as A selection circuit is configured to select either the second voltage or the third voltage to be transmitted to the buffer circuit based on the second logic control signal and the third logic control signal.

12. The battery protection element of claim 11, wherein the inverting circuit comprises: A first transistor has a first source, a first drain, and a first gate; as well as A second transistor having a second source, a second drain, and a second gate; The first transistor is a P-type transistor, and the second transistor is an N-type transistor; as well as The first gate and the second gate are configured to receive the second logic control signal, the first source is configured to receive the first voltage, the second source is configured to receive the third voltage, the first drain is coupled to the second drain, and the first drain and the second drain are configured to generate the third logic control signal.

13. The battery protection element of claim 11, wherein the selection circuit comprises: A third transistor having a third source, a third drain, and a third gate; as well as A fourth transistor having a fourth source, a fourth drain, and a fourth gate; The third transistor and the fourth transistor are N-type transistors; as well as The third gate is configured to receive the second logic control signal, the fourth gate is configured to receive the third logic control signal, the third source is coupled to the fourth source, the third drain is configured to receive the third voltage, the fourth drain is configured to receive the second voltage, and the third source and the fourth source are configured to transmit the second voltage or the third voltage to the buffer circuit.

14. The battery protection element of claim 10, wherein the buffer circuit comprises: A fifth transistor having a fifth source, a fifth drain, and a fifth gate; as well as A sixth transistor having a sixth source, a sixth drain, and a sixth gate; The fifth transistor is a P-type transistor, and the sixth transistor is an N-type transistor; as well as The fifth gate and the sixth gate are configured to receive the first logic control signal, the fifth source is configured to receive the first voltage, the sixth source is configured to receive the second voltage or the third voltage, and the fifth drain and the sixth drain are coupled to the control gate and configured to transmit the gate control signal.

15. The battery protection element of claim 10, wherein the first voltage is provided by the cathode of the battery, the second voltage is provided by the anode of the battery, the third voltage is provided by the anode of the charger in the charging mode, and the third voltage is provided by the anode of the load in the discharging mode.

16. The battery protection element of claim 15, wherein the third voltage in the discharge mode is higher than the third voltage in the charging mode, the third voltage is lower than the second voltage in the charging mode, and the third voltage is higher than the second voltage in the discharge mode.

17. The battery protection element of claim 15, wherein when the overcharge occurs in the charging mode, the switching circuit transmits the gate control signal having a voltage equal to the third voltage to turn off the power transistor.

18. The battery protection element of claim 15, wherein when the over-discharge occurs in the discharge mode, the switching circuit transmits the gate control signal having a voltage equal to the second voltage to turn off the power transistor.

Images