Integrated circuit, power supply circuit

Abstract

Provided is an integrated circuit capable of further reducing power consumption. The integrated circuit, which drives a transistor of a power supply circuit in order for the power supply circuit to generate an output voltage of a target level, includes: a first terminal connected to a first switch that is turned on or off based on an instruction signal that instructs an operation mode of the integrated circuit; a first determination circuit that determines whether the integrated circuit is operating in a first mode or a second mode that has greater power consumption than the first mode, based on a voltage level of the first terminal; a first power supply voltage generation circuit that stops generation of a first power supply voltage when the integrated circuit is operating in the first mode, and generates the first power supply voltage when the integrated circuit is operating in the second mode; and a drive circuit that is supplied with the first power supply voltage to drive the transistor.

Description

Technical Field

[0001] This invention relates to integrated circuits and power supply circuits. Background Technology

[0002] Integrated circuits for controlling power supply circuits already exist (e.g., see references 1 to 7).

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2012-110173

[0006] Patent Document 2: Japanese Patent Application Publication No. 2013-038857

[0007] Patent Document 3: Japanese Patent Application Publication No. 2014-230377

[0008] Patent Document 4: Japanese Patent Application Publication No. 2016-111758

[0009] Patent Document 5: Japanese Patent Application Publication No. 2017-017767

[0010] Patent Document 6: Japanese Patent Application Publication No. 2017-060329

[0011] Patent Document 7: Japanese Patent Application Publication No. 2017-127109 Summary of the Invention

[0012] The technical problem that the invention aims to solve

[0013] Some integrated circuits can change their operating mode according to the load state of the power supply circuit.

[0014] In such integrated circuits, the load sensing circuit, typically used to detect the load status, is always operational. Therefore, even assuming the load is no-load, the integrated circuit continuously consumes a constant amount of power, making it difficult to further reduce the power consumption of the integrated circuit.

[0015] The present invention was made in view of the above-mentioned prior art problems, and its object is to provide an integrated circuit that can further reduce power consumption.

[0016] Technical means for solving technical problems

[0017] The first aspect of the integrated circuit of the present invention, which is mainly used to solve the above-mentioned problems, is an integrated circuit that drives the transistor of the power supply circuit to generate a target level output voltage. The integrated circuit includes: a first terminal connected to a first switch that is turned on or off based on an indication signal indicating the operating mode of the integrated circuit; a first determination circuit that determines whether the integrated circuit operates in a first mode or in a second mode with higher power consumption than the first mode based on the voltage level of the first terminal; a first power supply voltage generation circuit that stops the generation of a first power supply voltage when the integrated circuit operates in the first mode and generates the first power supply voltage when the integrated circuit operates in the second mode; and a driving circuit that is provided with the first power supply voltage to drive the transistor.

[0018] The power supply circuit of the present invention, mainly used to solve the above-mentioned problems, is a power supply circuit for generating a target level output voltage, comprising: a transistor; an integrated circuit driving the transistor; and a first switch that switches on and off based on an indication signal indicating the operating mode of the integrated circuit, the integrated circuit comprising: a first terminal connected to the first switch; a first determination circuit that determines whether the integrated circuit operates in a first mode or in a second mode with higher power consumption than the first mode based on the voltage level of the first terminal; a first power supply voltage generation circuit that stops generating a first power supply voltage when the integrated circuit operates in the first mode and generates the first power supply voltage when the integrated circuit operates in the second mode; and a driving circuit that is provided with the first power supply voltage to drive the transistor.

[0019] The second aspect of the integrated circuit of the present invention, which is mainly used to solve the above-mentioned problems, is an integrated circuit that drives the power transistor of the power supply circuit to switch in order to generate a target level output voltage of the power supply circuit. The integrated circuit includes: a first terminal connected to an external circuit that sets the operating mode of the integrated circuit; and a mode selection circuit that selects based on the voltage level of the first terminal so that the integrated circuit can operate in any of the following modes: a cut-off mode in which no switching operation is performed, a normal mode in which switching operation is performed continuously, and a low standby power mode in which switching operation is repeated alternately and a stop operation is performed.

[0020] Invention Effects

[0021] According to the present invention, an integrated circuit that can further reduce power consumption can be provided. Attached Figure Description

[0022] Figure 1 This is a diagram showing an example of a power supply device 10.

[0023] Figure 2 This is a diagram showing the outline of AC-DC converter 12.

[0024] Figure 3 This is a diagram illustrating an example of a DC-DC converter 13.

[0025] Figure 4 This is a diagram showing an example of the control IC50.

[0026] Figure 5 This is a diagram showing an example of the setting circuit 76.

[0027] Figure 6 This is a graph showing the relationship between the resistance value of resistor Rstb and the driving mode switching method of control IC50.

[0028] Figure 7 This is a diagram showing an example of the drive signals Vdr1 and Vdr2 in "normal mode".

[0029] Figure 8 This is a diagram showing an example of the drive signals Vdr1 and Vdr2 in "low standby power mode".

[0030] Figure 9 This is a diagram showing an example of an interface (IF) circuit 18a.

[0031] Figure 10 This is a graph showing the relationship between the logic level and voltage Vstb of the signals Wakeup and ExtSTB.

[0032] Figure 11 This is a diagram showing the relationship between the logic levels of the Wakeup and ExtSTB signals and the operating mode of the control IC50.

[0033] Figure 12 This is a diagram illustrating an example of a power factor improvement circuit 22.

[0034] Figure 13 This is a diagram illustrating an example of the power factor improvement IC175.

[0035] Figure 14 This is a diagram illustrating an example of the actions of the control IC50.

[0036] Figure 15 This is a diagram showing an example of the interface (IF) circuit 18b.

[0037] Figure 16 This is a graph showing the relationship between the logic level of the signal Wakeup and the voltage Vstb.

[0038] Figure 17This is a diagram showing the relationship between the logic level of the Wakeup signal and the operating modes of the control IC50 and the power factor improvement IC155.

[0039] Figure 18 This is a diagram illustrating an example of the operation of control IC50 and power factor improvement IC175. Detailed Implementation

[0040] Based on the description in this specification and the accompanying drawings, at least the following matters are clearly defined.

[0041] ======This implementation method======

[0042] <<<Overview of Power Supply Unit 10>>>

[0043] Figure 1 This diagram illustrates an example of a power supply device 10. The power supply device 10 is, for example, a device embedded in a television set, generating an output voltage Vout2 from a commercial AC voltage Vac to power a specified load 14. The power supply device 10 comprises a switch 11, an AC-DC converter 12, a DC-DC converter 13, a microcontroller (MCU) 15a, a capacitor 16, a photodiode 17, and an interface (IF) circuit 18a. The switch 11 is located between nodes N2 and N3 and is turned on or off according to a signal SW_sig from the microcontroller 15a.

[0044] When switch 11 is on, AC-DC converter 12 generates output voltage Vout1 based on the AC voltage Vac applied to nodes N1 and N2. On the other hand, when switch 11 is off, AC-DC converter 12 does not generate output voltage Vout1 because no AC voltage Vac is applied.

[0045] DC-DC converter 13 generates an output voltage Vout2 based on the output voltage Vout1 applied to nodes N4 and N5. Load 14 is connected to nodes N6 and N7, is supplied with the output voltage Vout2, and is powered by a load current Iout. Load 14 is, for example, an electronic device that operates using DC voltage, included in a television set. Here, "connection" refers to an electrical connection unless otherwise specified, including connections via resistors.

[0046] The microcontroller 15a controls the power supply 10 based on instructions from the user. The microcontroller 15a receives voltage Vdd from a power supply circuit (not shown) that operates based on a commercial AC voltage Vac, and a capacitor 16 is disposed between the terminal VDD and ground to stabilize the voltage Vdd.

[0047] In addition, the photodiode 17 is disposed between the terminal RCV and the ground, and receives, for example, an infrared signal from a remote controller (not shown) of the television. Further, the microcontroller 15a controls operations of the power supply device 10 and various devices (not shown) of the television based on the signal received by the photodiode 17.

[0048] Further, when the photodiode 17 receives a signal sent from the remote controller to turn on the load 14, the microcontroller 15a transmits a signal SW_sig for turning on the switch 11 which is a relay. As a result, the switch 11 is turned on, so that the AC voltage Vac is applied to the AC-DC converter 12. Thereafter, the AC-DC converter 12 generates an output voltage Vout1.

[0049] In addition, at this time, the microcontroller 15a outputs a signal Wakeup for activating the DC-DC converter 13 to the interface circuit 18a.

[0050] Thereafter, the DC-DC converter 13 is activated based on the voltage Vstb from the interface circuit 18a, and supplies power to the load 14. Further, the microcontroller 15a also outputs a signal ExtSTB for changing the operation mode of the DC-DC converter 13 under a predetermined condition, and the details will be described later.

[0051] On the other hand, when the photodiode 17 receives a signal sent from the remote controller to turn off the load 14, the microcontroller 15a transmits a signal SW_sig for turning off the switch 11. As a result, the switch 11 is turned off, so that the supply of the AC voltage Vac to the AC-DC converter 12 is stopped.

[0052] In addition, at this time, the microcontroller 15a outputs a signal Wakeup for stopping the DC-DC converter 13 to the interface circuit 18a. Accordingly, the interface circuit 18a generates a voltage Vstb at a level higher than a predetermined level, and the details will be described later. Further, the DC-DC converter 13 receives the voltage Vstb, stops generating the output voltage Vout2, stops supplying power to the load 14, the load current Iout flowing into the load 14 becomes zero, and the load 14 enters a so-called no-load state.

[0053] Further, the interface circuit 18a implements change of the operation of the control IC 50 and a cooperative function between the control IC 50 and the power factor correction IC 175 in accordance with the signal Wakeup and the signal ExtSTB from the microcontroller 15a. In addition, details of the interface circuit 18a will be described later. Furthermore, the interface circuit 18a corresponds to an "external circuit".

[0054] <<<Overview of AC-DC Converter>>>

[0055] Figure 2 is a diagram showing the configuration of the AC-DC converter 12 included in the power supply device 10 of the present invention. The AC-DC converter 12 is a power supply circuit that generates an output voltage Vout1 of a target level from the AC voltage Vac of a commercial power supply.

[0056] The AC-DC converter 12 is configured to include diodes 20 and 21, and a power factor correction circuit 22. The diodes 20 and 21 full-wave rectify the AC voltage Vac from nodes N1 and N3, and apply the resulting voltage as a rectified voltage Vrec1 to the control IC 50 described later.

[0057] The power factor correction circuit 22 generates an output voltage Vout1 of a target level from the AC voltage Vac of the commercial power supply based on the voltage Sig from the interface circuit 18a, and applies it to nodes N4 and N5. Details of the power factor correction circuit 22 will be described later.

[0058] <<<Overview of DC-DC Converter 13>>>

[0059] Figure 3 is a diagram showing the configuration of the DC-DC converter 13 included in the power supply device 10 of the present invention. The DC-DC converter 13 is an LLC current resonant power supply circuit that generates an output voltage Vout2 (e.g., 15V) of a target level for the load 14 from a prescribed input voltage Vout1 (e.g., 400V).

[0060] The DC-DC converter 13 is configured to include capacitors 30, 31, 42, NMOS transistors 32, 33, a transformer 34, a control block 35, diodes 40, 41, a constant voltage circuit 43, and a light emitting diode 44.

[0061] The capacitor 30 stabilizes the voltage between the power supply line to which the input voltage Vout1 is applied and the ground line on the ground side, and removes noise and the like. The input voltage Vout1 is a DC voltage of a prescribed level.

[0062] The NMOS transistor 32 is a high-side power transistor, and the NMOS transistor 33 is a low-side power transistor. In the present embodiment, the NMOS transistors 32 and 33 are used as switching elements, but PMOS transistors or bipolar transistors may be used instead, for example.

[0063] Transformer 34 includes a primary coil L1, secondary coils L2 and L3, and an auxiliary coil L4, all of which are insulated from each other. In transformer 34, the voltage change across the primary coil L1 on the primary side generates a voltage in the secondary coils L2 and L3 on the secondary side, and the voltage change across the secondary coils L2 and L3 on the secondary side generates a voltage in the auxiliary coil L4 on the primary side.

[0064] In addition, in the primary coil L1, one end is connected to the source of NMOS transistor 32 and the drain of NMOS transistor 33, and the other end is connected to the source of NMOS transistor 33 via capacitor 31.

[0065] Therefore, when NMOS transistors 32 and 33 begin switching, the voltage of each coil in the secondary coils L2 and L3 and the auxiliary coil L4 changes. Furthermore, the primary coil L1 and the secondary coils L2 and L3 are electromagnetically coupled with the same polarity, and the secondary coils L2 and L3 and the auxiliary coil L4 are also electromagnetically coupled with the same polarity.

[0066] Control block 35 is a circuit block used to control the switching of NMOS transistors 32 and 33, and details will be described later.

[0067] Diodes 40 and 41 rectify the voltages of the secondary coils L2 and L3, and capacitor 42 filters the rectified voltages. As a result, a smoothed output voltage Vout2 is generated in capacitor 42. Furthermore, the output voltage Vout2 becomes the target DC voltage level.

[0068] The constant voltage circuit 43 is a circuit that generates a constant DC voltage, for example, by using a shunt regulator.

[0069] The light-emitting diode 44 is a device that emits light with an intensity corresponding to the difference between the output voltage Vout2 and the output of the constant voltage circuit 43, and together with the phototransistor 62 described later, constitutes an optocoupler. In this embodiment, when the level of the output voltage Vout2 increases, the intensity of the light from the light-emitting diode 44 increases.

[0070] ===Control Block 35===

[0071] The control block 35 includes a control IC 50, a diode 60, capacitors 61, 63, 64, 67, 68, and 154, a phototransistor 62, and resistors 65 and 66.

[0072] The control IC50 is, for example, an integrated circuit that controls the switching of NMOS transistors 32 and 33 according to the state of terminal STB as described later, and has terminals VCC, GND, STB, REG, FB, IS, CA, HO, LO and VH.

[0073] Terminal VCC is the terminal to which the power supply voltage Vcc is applied to activate control IC 50. The cathode of diode 60 and capacitor 61, with one end grounded, are connected to terminal VCC. Therefore, capacitor 61 is charged by current from the startup circuit 70 of control IC 50 (described later) or from diode 60, and the charging voltage of capacitor 61 becomes the voltage Vcc that activates control IC 50.

[0074] Terminal GND is a terminal to which a ground voltage is applied, such as when it is connected to the housing of a device equipped with power supply unit 10.

[0075] Terminal STB is the terminal that receives the voltage generated by interface circuit 18a or the signal output by control IC 50 to power factor improvement IC 175, which is described later. Further details are provided below.

[0076] Terminal REG is the terminal for the output voltage of the internal power supply (REG1) 92 (described later) built into the output control IC50. Further details are explained later. To stabilize the output voltage of the internal power supply 92, as described below... Figure 7 As shown, a capacitor 154 is placed between terminal REG and ground.

[0077] Terminal FB is the terminal that generates a feedback voltage Vfb_a corresponding to the output voltage Vout2, and is connected to phototransistor 62 and capacitor 63. Phototransistor 62 causes a bias current I1 to flow from terminal FB to ground, the magnitude of which corresponds to the intensity of light from LED 44, and capacitor 63 is configured to remove noise between terminal FB and ground. Therefore, phototransistor 62 operates as a transistor that generates sink current.

[0078] Terminal IS is the terminal to which a voltage corresponding to the resonant current of the DC-DC converter 13 is applied. Here, a voltage corresponding to the resonant current of the primary coil L1 is generated at the node where capacitor 64 and resistor 65 are connected. Resistor 66 and capacitor 67 constitute a low-pass filter. Therefore, the voltage applied to terminal IS is a voltage corresponding to the resonant current of the primary coil L1, with noise components removed.

[0079] Furthermore, the resonant current increases according to the input power of the DC-DC converter 13, and the input power of the DC-DC converter 13 increases according to the power consumed in the load 14. Therefore, the voltage applied to terminal IS represents the voltage corresponding to the power consumption of the load 14.

[0080] Terminal CA applies a voltage to capacitor 68 that varies depending on the voltage applied to terminal IS. Specifically, when the power dissipation of load 14 increases, i.e., when load 14 becomes heavily loaded, the voltage applied to capacitor 68 increases. On the other hand, when the power dissipation of load 14 decreases, i.e., when load 14 becomes lightly loaded, the voltage applied to capacitor 68 decreases.

[0081] Additionally, "the state of load 14 is heavy load" means, for example, that the load current Iout flowing through load 14 is greater than a specified value (e.g., 1A). Furthermore, "the state of load 14 is light load" means, for example, that the load current Iout flowing through load 14 is less than a specified value (e.g., 1A).

[0082] Terminal VH is the terminal to which the rectified voltage Vrec1 is applied. In addition, control IC 50 includes a startup circuit 70 (described below), which charges voltage Vcc and starts control IC 50 when the rectified voltage Vrec1 is applied via terminal VH. After startup, control IC 70 operates based on voltage Vcc.

[0083] Terminal HO is the terminal for outputting the drive signal Vdr1 that drives the NMOS transistor 32, and is connected to the gate of the NMOS transistor 32.

[0084] Terminal LO is the terminal that outputs the drive signal Vdr2 to drive NMOS transistor 33, and is connected to the gate of NMOS transistor 33.

[0085] Additionally, terminal STB is equivalent to "terminal 1", terminal VH is equivalent to "terminal 2", terminal VCC is equivalent to "terminal 3", and terminal REG is equivalent to "terminal 4".

[0086] <<<Detailed information about control IC50>>>

[0087] Figure 4 This diagram illustrates the structure of control IC 50. Control IC 50 is an integrated circuit that controls an LLC current resonant power supply circuit. Control IC 50 is configured to include a startup circuit 70, a current source 71, a Zener diode 72, a decision circuit 73, resistors 74 and 75, a setting circuit 76, a reset circuit 90, a low-voltage protection circuit (UVLO) 91, an internal power supply (REG1) 92, an internal power supply (REG2) 93, a load detection circuit 100, an oscillation circuit 101, and a drive circuit 102. Furthermore, the decision circuit 73 corresponds to the "first decision circuit" or "first mode decision circuit".

[0088] ===Starting Circuit 70===

[0089] When the control IC 50 starts up, the startup circuit 70 generates a power supply voltage Vcc based on the rectified voltage Vrec1 to enable the control IC 50 to operate. Specifically, when the control IC 50 starts up, the startup circuit 70 generates a voltage based on the voltage Vcc at terminal VCC using the rectified voltage Vrec1 applied via terminal VH. Figure 3 The capacitor 61 is charged to generate a voltage Vcc.

[0090] Furthermore, when the control IC50 has finished starting, the voltage Vcc is high enough, and the capacitor 61 is being charged by the current from the auxiliary coil L4, the start-up circuit 70 stops charging the capacitor 61.

[0091] Here, "start" refers to the operation from the output signal rst1 (described later) that causes the digital circuit of the control IC50 to operate after the AC voltage Vac is applied to the power supply device 10 until the output signal rst2 (described later) that starts switching.

[0092] Furthermore, the “startup” of the control IC 50 includes the actions shown in steps (1) and (2). In step (1), after applying an AC voltage Vac to the power supply device 10, a “state setting period” is performed to initially set various circuits of the control IC 50. In step (2), after step (1), the startup circuit 70 charges the capacitor 61, and the voltage Vcc level is set to the level at which the control IC 50 starts switching the NMOS transistors 32 and 33 (for example, the specified level Vccon described later). Furthermore, the details of steps (1) and (2) will be described later. The startup circuit 70 of this embodiment is configured to include a constant voltage source 80, a control circuit 81, and a charging circuit 82.

[0093] <<Constant Pressure Source 80>>

[0094] The constant voltage source 80 generates a constant voltage Vstartup (e.g., 30V) based on the rectified voltage Vrec1. Specifically, the constant voltage source 80 generates the constant voltage Vstartup based on the rectified voltage Vrec1 applied via terminal VH, regardless of the operating mode of the control IC 50.

[0095] Furthermore, during the period when the rectified voltage Vrec1 is applied to terminal VH, the constant voltage source 80 applies a constant voltage Vstartup to the control circuit 81, charging circuit 82, current source 71, and determination circuit 73. Additionally, the constant voltage Vstartup is equivalent to a "prescribed voltage".

[0096] <<Control Circuit 81>>

[0097] The control circuit 81 controls the charging circuit 82 to generate a voltage Vcc. Furthermore, between steps (1) and (2) when the control IC 50 is started, the control circuit 81 controls the charging circuit 82.

[0098] Specifically, the determination circuit 73 outputs an indication. Figure 3 When the NMOS transistors 32 and 33 are initiating a switching signal Sb, the control circuit 81 outputs a signal Pon to control the charging circuit 82 based on the voltage value of Vcc. Furthermore, the signal Sb indicating that the NMOS transistors 32 and 33 should begin switching will be referred to below as the "switching signal Sb".

[0099] On the other hand, when the determination circuit 73 outputs a signal Sb indicating that the NMOS transistors 32 and 33 should stop switching, the control circuit 81 outputs a signal Pon to stop the charging circuit 82 from generating voltage Vcc. Furthermore, the signal Sb indicating that the NMOS transistors 32 and 33 should stop switching is referred to as the "signal Sb that should stop switching". The details of the signal Pon will be explained later.

[0100] Here, during the state setting period, when the voltage Vcc level is lower than the specified level Vston (e.g., 9V), the control circuit 81 outputs a signal Pon that causes the charging circuit 82 to charge the capacitor 61. On the other hand, when the voltage Vcc level reaches the specified level Vstoff (e.g., 10V), the control circuit 81 outputs a signal Pon that causes the charging circuit 82 to stop charging the capacitor 61.

[0101] Furthermore, when the voltage Vcc level decreases from the specified level Vstoff to the specified level Vston, the control circuit 81 again outputs a signal Pon to charge the capacitor 61 via the charging circuit 82. Afterwards, when the state setting period is complete, the control circuit 81 outputs the signal Pon to charge the capacitor 61 via the charging circuit 82 until the voltage Vcc level reaches the specified level Vccon.

[0102] Furthermore, after the control IC50 has started up, when the voltage Vcc is sufficiently high and capacitor 61 is being charged by the current from the auxiliary coil L4, the control circuit 81 outputs a signal Pon that stops the charging circuit 82 from charging capacitor 61. After outputting the signal Pon that stops the charging circuit 82 from charging capacitor 61, the constant voltage source 80 no longer needs to provide a constant voltage Vstartup, and the current generated with the generation of the constant voltage Vstartup is almost zero. Therefore, the power consumption of the constant voltage source 80 is almost negligible. Additionally, capacitor 61 is equivalent to the "first capacitor".

[0103] <<Charging Circuit 82>>

[0104] The charging circuit 82 operates based on the voltage Vstartup, charging the capacitor 61 via the terminal VCC to generate the voltage Vcc. Specifically, when the control circuit 81 outputs a signal Pon indicating that the capacitor 61 should be charged, the charging circuit 82 charges the capacitor 61 via the terminal VCC based on the voltage Vstartup. On the other hand, when the control circuit 81 outputs a signal Pon indicating that charging the capacitor 61 should be stopped, the charging circuit 82 stops charging the capacitor 61.

[0105] === Current Source 71 ===

[0106] Current source 71 is a circuit that generates a voltage on terminal STB corresponding to the state of interface circuit 18a connected to terminal STB. Details will be explained later. Based on the level of voltage Vstb at terminal STB, control IC 50 can operate in an operating mode corresponding to a signal from microcontroller 15a. In this embodiment, current source 71 provides current Ia to terminal STB based on signal Sa (described later) from setting circuit 76 when control IC 50 is in a predetermined state. Specifically, during periods other than the state setting period, current source 71 provides current Ia to terminal STB when signal Sa indicating the provision of current Ia is input.

[0107] Furthermore, the current Ia is discussed later. Figure 9 The current used to charge capacitor 150 within the interface circuit 18a shown. Additionally, when the microcontroller 15a outputs a Wakeup signal to stop the DC-DC converter 13, the voltage Vstb generated across capacitor 150 rises above a specified level Vstop (e.g., 5.0V).

[0108] On the other hand, when the microcontroller 15a outputs the Wakeup signal that causes the DC-DC converter 13 to operate, the capacitor 150 passes through... Figure 9 Resistor 151 (described later) discharges, thus reducing the voltage Vstb level below the specified level Vstop. Therefore, the voltage Vstb at terminal STB changes with the current Ia, allowing control IC 50 to operate in response to instructions from microcontroller 15a. Details of interface circuit 18 will be described later.

[0109] ===Zener Diode 72===

[0110] The Zener diode 72 is positioned between terminal STB and ground and is used to ensure that the voltage Vstb at terminal STB does not exceed a specified level (e.g., 5.9V) (i.e., clamping). Additionally, the Zener diode 72 acts as a "clamping element".

[0111] ===Determination Circuit 73===

[0112] The determination circuit 73 determines whether the voltage Vstb at the STB terminal exceeds the specified level Vstop used to determine the operating mode of the control IC 50. Specifically, if the voltage Vstb is lower than the specified level Vstop, the determination circuit 73 outputs a switching signal Sb. Furthermore, the operating mode of the control IC 50 in this case is called the "power-on mode". In addition, when the control IC 50 operates in the "power-on mode", the control IC 50 switches the NMOS transistors 32 and 33 after step (2) described above.

[0113] On the other hand, if the voltage Vstb is higher than the specified level Vstop, the determination circuit 73 outputs a switch-stop signal Sb. Furthermore, the operating mode of the control IC 50 in this situation is called "off mode". In addition, when the control IC 50 is in "off mode", it does not switch the NMOS transistors 32 and 33. Furthermore, "power-on mode" is equivalent to "mode 1", and "off mode" is equivalent to "mode 2". Furthermore, the specified level Vstop is equivalent to "voltage level 1".

[0114] === Resistors 74, 75 ===

[0115] Resistors 74 and 75 generate a voltage Vh for detecting the effective value of the AC voltage Vac based on the rectified voltage Vrec1. Specifically, resistors 74 and 75 are connected in series between the node where the rectified voltage Vrec1 is applied and ground, generating a voltage Vh at the connection point of resistors 74 and 75.

[0116] ===Setting up circuit 76===

[0117] Figure 5 This diagram illustrates an example of the setting circuit 76. The setting circuit 76 outputs various signals for setting the operation of the control IC 50. Specifically, the setting circuit 76 outputs a signal Sa that supplies or stops supplying current Ia to the current source 71.

[0118] Furthermore, when changing the driving mode in "external mode" (described later), the setting circuit 76 detects changes in the level of voltage Vstb and outputs a signal Sc indicating the driving mode of NMOS transistors 32 and 33 to the oscillation circuit 101 (described later). Additionally, the setting circuit 76 outputs a signal Sd indicating the completion of the state setting period and a signal Se indicating the method of changing the driving mode of NMOS transistors 32 and 33. The setting circuit 76 is configured to include a digital section 110 composed of digital circuits (logic circuits) and an analog section 111 composed of analog circuits.

[0119] =====Digital Section 110=====

[0120] The digital unit 110 is configured to include a control circuit 120 and a determination circuit 121.

[0121] === ...

[0122] Control circuit 120 control Figure 4 The current source 71, control circuit 81, internal power supply 92 and Figure 5 Various circuits within the analog section 111. Furthermore, the control circuit 120 is equivalent to a "control circuit".

[0123] === ...

[0124] The determination circuit 121 determines how to change the driving mode of the NMOS transistors 32 and 33 based on the signal from the control circuit 120 and the conversion result (digital value Dvstb) of the analog-to-digital converter (ADC) 132 (described below).

[0125] Furthermore, when the control circuit 120 outputs a timing signal S3 indicating that the conversion result should be acquired, the determination circuit 121 acquires a digital value Dvstb obtained by converting the voltage value of the voltage Vstb corresponding to the resistance value Rstb of the resistor 151 (described later) into a digital value. Then, the determination circuit 121 outputs a signal Se indicating whether the drive mode is changed in "external mode" or "internal mode" based on the digital value Dvstb.

[0126] Here, "external mode" refers to the mode in which the comparator 134, described later, determines whether the voltage Vstb output by the interface circuit 18a based on the logic level of the signal ExtSTB is higher than the specified level Vthstb, described later, and changes the driving mode accordingly.

[0127] On the other hand, the "internal mode" is a mode that changes the driving form based on the voltage Vca output by the load detection circuit 100, which is the state of the load 14, as described later. In addition, the determination circuit 121 is equivalent to the "second determination circuit".

[0128] =====Simulation Department 111=====

[0129] The analog unit 111 is composed of analog circuitry, including a discharge circuit 130, a current source 131, an analog-to-digital converter (ADC) 132, a clamping circuit 133, a comparator 134, and a communication circuit 135. Furthermore, the discharge circuit 130, current source 131, and ADC 132 of the analog unit 111 operate during state setting, based on the following description... Figure 9The resistance value Rstb of resistor 151 shown determines the change Figure 3 The driving mode of NMOS transistors 32 and 33.

[0130] =======Discharge Circuit 130= ...

[0131] The discharge circuit 130, during the state setting period, is described below. Figure 9 The capacitor 150 (described below) is discharged to accurately determine the voltage corresponding to the resistance value Rstb of the resistor 151. Specifically, when the control circuit 120 outputs a signal S1 to discharge the capacitor 150, the discharge circuit 130 discharges the terminal STB connected to the capacitor 150. On the other hand, when the control circuit 120 outputs a signal S1 to stop the capacitor 150 from discharging, the discharge circuit 130 stops discharging to the terminal STB connected to the capacitor 150.

[0132] ====== Current Source 131=======

[0133] Current source 131 supplies current Ib to terminal STB for measurement, as described later, to set the change in drive mode. Figure 9 The resistance value Rstb of resistor 151 is determined. Specifically, when control circuit 120 outputs signal S2 indicating the supply of current Ib, current source 131 supplies current Ib to resistor 151 via terminal STB. Therefore, control IC 50 can determine the resistance value Rstb of resistor 151.

[0134] Furthermore, details will be elaborated later, for users such as Figure 6 As shown, when the method of changing the drive type is set to "external mode", the resistance value Rstb is set to the resistance value Ra. When the method of changing the drive type is set to "internal mode", the resistance value Rstb is set to the resistance value Rb.

[0135] Furthermore, when the resistance value Rstb is the same as the resistance value Ra, the determination circuit 121 outputs a signal Se indicating a change in the driving mode under "external mode". This signal Se, indicating a change in the driving mode under "external mode", is referred to as the "signal Se indicating 'external mode'".

[0136] Furthermore, when the resistance value Rstb is the same as the resistance value Ra, the determination circuit 121 outputs a signal Se indicating a change in the driving mode under "internal mode". This signal Se, indicating a change in the driving mode under "internal mode", is referred to as the "signal Se indicating 'internal mode'".

[0137] =======Analog-to-Digital Converter (ADC) 132========

[0138] Analog-to-digital converter (ADC) 132 converts the voltage value Vstb into a digital value Dvstb. In this embodiment, control circuit 120 outputs a signal S2 indicating the supply of current Ib and a signal S3 indicating the timing at which the digital value Dvstb should be acquired. Then, determination circuit 121 outputs signal Se based on the digital value Dvstb. At this time, ADC 132 converts the voltage value generated in resistor 151 into the digital value Dvstb and outputs the digital value Dvstb to determination circuit 121.

[0139] =======Clamping Circuit 133========

[0140] Clamping circuit 133 generates a voltage to maintain the voltage Vstb at terminal STB at a specified level Vnorm.

[0141] The clamping circuit 133 is configured to include an operational amplifier 140, a PMOS transistor 141, and a resistor 142. When the voltage Vstb input to the non-inverting input terminal of the operational amplifier 140 is lower than the specified voltage Vnorm input to the inverting input terminal, the operational amplifier 140 drives the PMOS transistor 141 to reduce the on-resistance of the PMOS transistor 141.

[0142] On the other hand, when the voltage Vstb is higher than the specified level Vnorm, the operational amplifier 140 drives the PMOS transistor 141 to increase the on-resistance of the PMOS transistor 141. Then, the resistor 142 limits the current corresponding to the voltage Vreg2 and the on-resistance of the PMOS transistor 141, and generates a voltage that makes the voltage Vstb equal to the specified level Vnorm.

[0143] Additionally, the driving capability of the clamping circuit 133 used to drive the STB terminal is less than that of the discharge circuit 130 and the communication circuit 135 (described later). If these circuits do not operate and no ground voltage is applied to the STB terminal from the outside, the clamping circuit 133 generates a voltage that makes the voltage Vstb level a specified level Vnorm.

[0144] ====== Comparator 134 ======

[0145] Comparator 134 determines whether control IC 50 operates in "normal mode" or "low standby power mode" based on the ExtSTB signal from microcontroller 15a.

[0146] Here, "normal mode" refers to the state of control IC50 when the load condition is not light load. Figure 7 The diagram shows the continuous switching operation mode of NMOS transistors 32 and 33.

[0147] On the other hand, "low standby power mode" refers to the mode where, when the load is light, the control IC50, such as... Figure 8 The switching operation mode shown alternates between the continuous switching operation of NMOS transistors 32 and 33 and the intermittent stopping operation, i.e., the switching operation mode is performed in burst mode.

[0148] In addition, "normal mode" and "low standby power mode" indicate the driving mode of NMOS transistors 32 and 33 when the control IC50 operates in "power-on mode".

[0149] Specifically, when the output signal Se indicates "external mode", the comparator 134 outputs the signal Sc indicating "normal mode" when it detects a voltage Vstb that is higher than the specified level Vthstb, and causes the oscillation circuit 101 described below to output the oscillation signal Vosc that switches the NMOS transistors 32 and 33 in "normal mode".

[0150] On the other hand, when comparator 134 detects a voltage Vstb that is lower than the specified level Vthstb, it outputs a signal Sc indicating "low standby power mode" and causes oscillation circuit 101 to output an oscillation signal Vosc that switches NMOS transistors 32 and 33 in "low standby power mode". Furthermore, comparator 134 is equivalent to either a "first signal output circuit" or a "second mode determination circuit", and signal Sc is equivalent to a "second signal". Additionally, the specified level Vthstb is equivalent to a "second voltage level", and determination circuit 73 and comparator 134 are equivalent to a "mode selection circuit".

[0151] === ...

[0152] To achieve cooperative functionality with the power factor improvement IC175, the communication circuit 135 outputs a pulse signal to terminal STB. Specifically, to transmit the effective value of the AC voltage Vac to the power factor improvement IC175, the communication circuit 135 receives a voltage Vh that determines the effective value of the AC voltage Vac based on the rectified voltage Vrec1 applied to terminal VH, and generates and outputs a pulse signal to terminal STB based on this voltage Vh. Furthermore, the pulse signal has an amplitude level lower than a specified level Vstop and higher than a specified level Vthstb.

[0153] This action receives voltage Vh through communication circuit 135 and generates a pulse signal indicating whether the effective value of AC voltage Vac is high (e.g., 200V) or low (e.g., 100V), which is then output to power factor improvement IC 175 via interface circuit 18a (18b) for execution.

[0154] Furthermore, when the output signal Se represents the "internal mode", the communication circuit 135 outputs a pulse signal with a pulse width corresponding to the state of the load 14. Additionally, the communication circuit 135 is equivalent to a "second signal output circuit" or a "signal output circuit", and the pulse signal is equivalent to a "third signal".

[0155] ===Reset Circuit (RESET) 90===

[0156] Return to Figure 4 The reset circuit (RESET) 90 resets the digital circuitry of the control IC 50 when the voltage Vcc is low, stopping the operation of the digital circuitry of the control IC 50. Specifically, when the voltage Vcc level is lower than the specified level Vccrst, the reset circuit 90 outputs a reset signal rst1 to the digital circuitry of the control IC 50.

[0157] On the other hand, when the voltage Vcc exceeds a predetermined level Vccrst, the reset circuit 90 outputs a signal rst1 that causes the digital circuit of the control IC 50 to start operating. In this embodiment, the above-described state setting is performed when the voltage Vcc rises and the reset circuit 90 releases the reset of the digital section's circuit.

[0158] ===Low Voltage Protection Circuit (UVLO) 91===

[0159] The low-voltage protection circuit (UVLO) 91 resets the load detection circuit 100, oscillation circuit 101, and drive circuit 102 (described below) when the voltage Vcc is low, stopping their operation. Specifically, when the power supply voltage Vcc is lower than the specified level Vccon, the low-voltage protection circuit 91 outputs a reset signal rst2 to reset the load detection circuit 100, oscillation circuit 101, and drive circuit 102.

[0160] On the other hand, when the voltage Vcc exceeds the specified level Vccon, the low-voltage protection circuit 91 outputs a signal rst2 that causes the load detection circuit 100, the oscillation circuit 101, and the drive circuit 102 to start operating. In this embodiment, when the voltage Vcc rises and the low-voltage protection circuit 91 releases the reset of various circuits, the control IC 50 starts to perform switching operations.

[0161] ===Internal Power Supply (REG1) 92===

[0162] When the control IC50 starts, if the voltage Vcc rises, the internal power supply (REG1) 92 generates a voltage Vreg1 for the drive signals Vdr1 and Vdr2 output by the drive circuit 102 (described later). Specifically, when the determination circuit 73 outputs a switching signal Sb and the voltage Vcc rises from the ground level, the internal power supply 92 gradually generates the voltage Vreg1 internally.

[0163] Subsequently, when the setting circuit 76 outputs a signal Sd indicating the completion of the state setting period, the internal power supply 92 outputs voltage Vreg1 to terminal REG. Furthermore, when the control IC 50 operates in "power-on mode," when the low-voltage protection circuit 91 outputs the aforementioned signal rst2, the drive circuit 102 causes the NMOS transistors 32 and 33 to begin switching.

[0164] Furthermore, when the determination circuit 73 outputs a signal Sb indicating that the switching should be stopped, the internal power supply 92 stops generating voltage Vreg1. Thus, when the control IC 50 is in "off mode," the drive circuit 102 stops the switching of NMOS transistors 32 and 33. Additionally, the internal power supply 92 acts as a "first power supply voltage generation circuit," and voltage Vreg1 acts as a "first power supply voltage."

[0165] ===Internal Power Supply (REG2) 93===

[0166] When the control IC 50 is started, if the voltage Vcc rises, the internal power supply (REG2) 93 generates a voltage Vreg2 to power various circuits used for setting the execution state. Specifically, when the determination circuit 73 outputs a switching signal Sb and the voltage Vcc rises from the ground level, the internal power supply 93 generates a voltage Vreg2. Thus, when the control IC 50 operates in "power-on mode," various circuits of the control IC 50 (e.g., control circuit 120, discharge circuit 130, and current source 131) receive the supply of voltage Vreg2 and operate accordingly.

[0167] Furthermore, when the determination circuit 73 outputs a stop switch signal Sb, the internal power supply 93 stops generating voltage Vreg2. Therefore, when the control IC 50 is in "off mode," the various circuits of the control IC 50 do not operate. Additionally, the internal power supply 93 acts as a "second power supply voltage generation circuit," and voltage Vreg2 acts as a "second power supply voltage."

[0168] ===Load Detection Circuit 100===

[0169] The load detection circuit 100 detects whether the load 14 is under light or heavy load based on the voltage applied to terminal IS corresponding to the power consumption of the load 14. The load detection circuit 100 outputs a voltage Vca indicating the state of the load 14 to the oscillation circuit 101 and the communication circuit 135.

[0170] Here, the power consumption of load 14 is greater when load 14 is under heavy load than when it is under light load. Therefore, the voltage Vis applied to terminal IS represents the voltage corresponding to the power consumption of load 14. Thus, when the voltage Vis is lower than a specified value, the load detection circuit 100 outputs a voltage Vca indicating that load 14 is under light load.

[0171] On the other hand, when the voltage Vis is higher than the specified value, the load detection circuit 100 outputs a voltage Vca indicating that the load 14 is under heavy load. Furthermore, the heavier the load when the load 14 is under heavy load, the higher the voltage Vca. Additionally, the voltage Vca is equivalent to the "first signal".

[0172] ===Oscillator Circuit 101===

[0173] The oscillation circuit 101 is a voltage-controlled oscillation circuit, which, based on the input feedback voltage Vfb_a, outputs a voltage control oscillation circuit to make the input feedback voltage Vfb_a. Figure 3 The NMOS transistors 32 and 33 are switched using the oscillation signal Vosc.

[0174] Furthermore, when the voltage Vfb_a decreases, the oscillation circuit 101 outputs a high-frequency oscillation signal Vosc. Here, when the load 14 is in a light load state, the output voltage Vout2 rises and exceeds the target level. Therefore, Figure 3 The internal input of the constant voltage circuit 43, which consists of a shunt regulator, increases. In order to keep the output constant, a large current flows through the transistor inside the shunt regulator (not shown).

[0175] As a result, a large current also flows through the light-emitting diode 44. Then, the phototransistor 62 causes a bias current I1 of a magnitude corresponding to the increase in light from the light-emitting diode 44 to flow from the terminal FB to ground, thereby reducing the feedback voltage Vfb_a.

[0176] Furthermore, when the low voltage protection circuit 91 outputs the signal rst2 that causes the oscillation circuit 101 to start operating, the oscillation circuit 101 outputs an oscillation signal Vosc to the control IC 50 based on the signal Sc or the voltage Vca, which causes the NMOS transistors 32 and 33 to switch in "normal mode" or "low standby power mode".

[0177] In addition, when the output is a signal Se indicating "external mode", the oscillation circuit 101 operates based on the logic level of the signal Sc from the setting circuit 76.

[0178] On the other hand, when the output is a signal Se representing the "internal mode", the oscillation circuit 101 operates based on the voltage level of the voltage Vca from the load detection circuit 100.

[0179] <<Changes in Drive Type under "Internal Mode">>

[0180] Furthermore, when the output signal Se indicates "internal mode", and the load detection circuit 100 outputs a voltage Vca that is higher than the specified level Vcastb, the oscillation circuit 101 switches the NMOS transistors 32 and 33 in "normal mode".

[0181] On the other hand, when the load detection circuit 100 outputs a voltage Vca that is lower than the specified level Vcastb, the oscillation circuit 101 switches the NMOS transistors 32 and 33 in the "low standby power mode".

[0182] In addition, the oscillation circuit 101 is equivalent to "oscillation circuit", "normal mode" is equivalent to "mode 3", "low standby power mode" is equivalent to "mode 4", and the oscillation signal Vosc is equivalent to "drive signal".

[0183] ===Driver Circuit 102===

[0184] The driving circuit 102 is supplied with a voltage Vreg1 to drive the NMOS transistors 32 and 33 to switch at the frequency of the oscillation signal Vosc. Specifically, the driving circuit 102 outputs pulsed driving signals Vdr1 and Vdr2, which have the frequency of the oscillation signal Vosc and a duty cycle that is in principle constant (e.g., 50%), to the following circuits: Figure 7 , 8 The NMOS transistors 32 and 33 are shown. In addition, the drive circuit 102 sets a dead time and makes the drive signals Vdr1 and Vdr2 change in a complementary manner, thereby ensuring that the NMOS transistors 32 and 33 do not turn on at the same time.

[0185] Here, when operating in "normal mode," if the output voltage Vout2 rises above the target level, the feedback voltage Vfb_a decreases, thus increasing the frequency of the oscillation signal Vosc. As a result, the output voltage Vout2 of the LLC current resonant power supply circuit, i.e., the DC-DC converter 13, decreases.

[0186] On the other hand, if the output voltage Vout2 decreases below the target level, the feedback voltage Vfb_a increases, and therefore the frequency of the oscillation signal Vosc decreases. As a result, the output voltage Vout2 of the DC-DC converter 13 increases. Therefore, when operating in "normal mode", the DC-DC converter 13 can generate an output voltage Vout2 at the target level.

[0187] <<<Structure and Operation of Interface Circuit 18a>>>

[0188] Figure 9 This is a diagram illustrating an example of interface circuitry 18a. As described above, interface circuitry 18a is based on data from... Figure 1 The microcontroller 15a uses the Wakeup and ExtSTB signals to control changes in the operation of IC50 and to control the collaboration between IC50 and power factor improvement IC175.

[0189] In addition, the interface circuit 18a is configured to include capacitors 150, 154, 159, and 162, resistors 151, 155, 156, 158, and 161, and NMOS transistors 152, 153, 157, and 160.

[0190] Furthermore, as detailed later, capacitors 150 and 154, resistors 151, 155, and 156, and NMOS transistors 152, 153, and 157 set the voltage level Vstb at terminal STB of control IC50. On the other hand, resistors 158 and 161, capacitors 159 and 162, and NMOS transistor 160 enable cooperation between control IC50 and power factor improvement IC175.

[0191] ===Circuit for setting the voltage level Vstb of terminal STB===

[0192] <Structure of circuits related to the Wakeup signal>

[0193] Capacitor 150 is disposed between signal line L1, which is connected to terminal STB of control IC 50, and ground, and is charged using current Ia from current source 71 of control IC 50. Furthermore, capacitor 150 is equivalent to "second capacitor", and signal line 1 is equivalent to "first signal line".

[0194] Resistor 151 has a resistance value Rstb, one end of which is connected to signal line L1, and the other end is connected to ground via NMOS transistor 152. Furthermore, as mentioned above, the resistance value Rstb is set to determine whether control IC 50 is in "external mode" or "internal mode".

[0195] NMOS transistor 152 is based on the gate from Figure 1 The microcontroller 15a uses the Wakeup signal to turn the switch on or off. Additionally, the NMOS transistor 152 is connected in series with the resistor 151.

[0196] ==Operation when the Wakeup signal is low (hereinafter referred to as "L" level)==

[0197] When NMOS transistor 152 receives an "L" level signal (Wakeup) that stops DC-DC converter 13, it turns off, disconnecting resistor 151 from ground. In this case, since capacitor 150 is not discharged through resistor 151, it is charged with current Ia from current source 71, and the voltage Vstb level is as follows: Figure 10 The value becomes higher than the specified level Vstop. As a result, the determination circuit 73 determines that the control IC 50 should be in "off mode".

[0198] That is, the interface circuit 18a sets the control IC50 to "cut-off mode", such as Figure 11 The part showing the Wakeup signal at the "L" level is illustrated below. Furthermore, when the Wakeup signal is at the "L" level, since the NMOS transistor 153 described later is disconnected from ground, the voltage Vstb level is unaffected by the ExtSTB signal.

[0199] ==Operation when the Wakeup signal is high (hereinafter referred to as "H" level)==

[0200] On the other hand, when NMOS transistor 152 receives the Wakeup signal (i.e., a "H" level signal) that enables DC-DC converter 13 to operate, it turns on, and resistor 151, which is connected in series with NMOS transistor 152, is connected to ground. As a result, capacitor 150 discharges through resistor 151, and the voltage Vstb level is as follows: Figure 10 The signal level Vstop becomes lower than the specified level. As a result, the decision circuit 73 determines that the control IC 50 should be in "power-on mode".

[0201] Therefore, control IC50 will operate in "power-on mode", such as... Figure 11 The "H" level portion of the Wakeup signal is shown. Additionally, resistor 151 corresponds to "resistor," NMOS transistor 152 corresponds to "first switch," and the Wakeup signal corresponds to "indication signal." Furthermore, current source 71 corresponds to "current source."

[0202] Then, if the control IC50 is in the state setting period when it is started, the current source 131, which receives the signal S2 indicating the supply of current Ib, causes the current Ib to flow through the resistor 151, generating a specified voltage as voltage Vstb at the terminal STB. As a result, the analog-to-digital converter 132 converts this specified voltage into a digital value Dvstb.

[0203] Then, the determination circuit 121 outputs a signal Se indicating whether the driving mode should be changed to "external mode" or "internal mode" based on the digital value Dvstb. Specifically, when the resistance value Rstb of resistor 151 is the resistance value Ra, the determination circuit 121... Figure 6 The output signal Se represents "external mode".

[0204] On the other hand, when the resistance value Rstb of resistor 151 is the same as the resistance value Rb, the determination circuit 121... Figure 6 The output signal Se represents the "internal mode".

[0205] <Structure of circuits related to the signal ExtSTB>

[0206] NMOS transistor 153 is a switch that changes the level of voltage Vstb based on the signal ExtSTB, and is positioned between NMOS transistor 157 (described later) and NMOS transistor 152. NMOS transistor 153 receives the signal ExtSTB from microcontroller 15a at its gate.

[0207] Before explaining which voltage level Vstb the interface circuit 18a outputs based on the logic level of the signal EXtSTB, the relationship between the terminal REG and the NMOS transistor 157 described later will be explained.

[0208] <Structure of the circuit related to terminal REG>

[0209] Capacitor 154 is placed between terminal REG and ground to stabilize the output voltage Vreg1 of internal power supply 92.

[0210] Resistors 155 and 156 divide the voltage Vreg1, generating a voltage Vreg1_div at their connection point.

[0211] NMOS transistor 157 receives gate voltage Vreg1_div, is positioned between signal line L1 and NMOS transistor 153, and is connected to ground via NMOS transistors 152 and 153. Furthermore, NMOS transistors 153 and 157 are connected in parallel with resistor 151.

[0212] Then, since the internal power supply 92 stops the output of voltage Vreg1 until the state setting period of control IC 50 is completed, NMOS transistor 157 is turned off. Thus, NMOS transistor 157 eliminates the influence of NMOS transistor 153, which receives the signal ExtSTB, on the level of voltage Vst. Furthermore, NMOS transistor 157 acts as a "second switch," and NMOS transistor 153 acts as a "third switch."

[0213] Specifically, since the internal power supply 92 outputs a voltage Vreg1 as a ground voltage until the state setting period of the control IC 50 is completed, the NMOS transistor 157 is turned off, thereby eliminating the effect caused by the NMOS transistor 153 during the state setting period.

[0214] Subsequently, when the internal power supply 92 completes the state setting period of the control IC 50, it outputs voltage Vreg1, and NMOS transistor 157 is turned on. When NMOS transistor 157 is turned on, the on or off state of NMOS transistor 153, due to the on / off state of NMOS transistor 152, causes the level of voltage Vstb to change, and the control IC 50 changes the operating mode according to the signal ExtSTB.

[0215] Then, output indication Figure 3 When the NMOS transistors 32 and 33 are driven by the signal ExtSTB, the NMOS transistor 153 is turned on or off, such as... Figure 10 As shown, the voltage Vstb is set to be lower or higher than the voltage Vthstb.

[0216] Furthermore, when the Wakeup signal is at a "L" level and the control IC50 is in "off mode," the voltage Vstb is unaffected by the ExtSTB signal because the NMOS transistor 153 is disconnected from ground. Therefore, the following explanation will address the voltage Vstb output by the interface circuit 18a based on the ExtSTB signal when the Wakeup signal is at a high "H" level and the control IC50 is in "power-on mode."

[0217] ==Operation when signal ExtSTB is at "H" level==

[0218] Specifically, when the output signal ExtSTB (i.e., "H" level) causes NMOS transistors 32 and 33 to switch in "low standby power mode," NMOS transistor 153 is turned on. At this time, regardless of... Figure 5 How does the clamping circuit 133 operate? Figure 10 As shown, the voltage level Vstb is lower than the specified level Vthstb.

[0219] At this time, comparator 134 outputs a signal Sc indicating "low standby power mode", which causes oscillation circuit 101 to output an oscillation signal Vosc that switches NMOS transistors 32 and 33 in "low standby power mode".

[0220] The result is, as Figure 11 The portion of the signal ExTSTB that is at the "H" level is shown. Interface circuit 18a causes control IC 50 to intermittently switch NMOS transistors 32 and 33.

[0221] ==Operation when signal ExtSTB is at "L" level==

[0222] On the other hand, when the ExtSTB signal (i.e., "L" level) that causes NMOS transistors 32 and 33 to switch in "normal mode" is output, NMOS transistor 153 is turned off. At this time, as... Figure 10 As shown, the voltage level Vstb is higher than the specified level Vthstb.

[0223] At this time, comparator 134 outputs a signal Sc indicating "normal mode", causing oscillation circuit 101 to output an oscillation signal Vosc that switches NMOS transistors 32 and 33 in "normal mode".

[0224] The result is, as Figure 11 The portion of the ExtSTB signal shown is at the "L" level. Interface circuit 18a causes control IC 50 to continuously switch NMOS transistors 32 and 33. Furthermore, the cooperative function of interface circuit 18a will be explained later.

[0225] ==Power Factor Improvement Circuit on IC175 Side==

[0226] As described above, resistors 158 and 161, capacitors 159 and 162, and NMOS transistor 160 enable the cooperative function between control IC50 and power factor improvement IC175.

[0227] Resistor 158 and capacitor 159 constitute a structure for removing Figure 5 The communication circuit 13 outputs a low-pass filter for noise in the pulse signal. Furthermore, when the effective value of the AC voltage Vac is 100V, the pulse signal is configured to be output twice during period T1; when the effective value of the AC voltage Vac is 200V, it is configured to be output once during period T1.

[0228] The NMOS transistor 160 is turned on or off according to the output of the low-pass filter, and outputs the voltage Sig corresponding to the pulse signal output by the communication circuit 135 to the power factor improvement IC 175.

[0229] Resistor 161 is positioned between terminal RT and ground, and reduces the voltage at terminal RT when NMOS transistor 160 is turned off.

[0230] Capacitor 162 is placed between terminal RT and ground to stabilize the voltage at terminal RT.

[0231] <<<Overview of Power Factor Improvement Circuit 22>>>

[0232] Figure 12 This is a diagram showing the structure of the power factor improvement circuit 22. The power factor improvement circuit 22 is a boost chopper power supply circuit that generates a target level output voltage Vout1 based on the AC voltage Vac of the commercial power supply.

[0233] The power factor improvement circuit 22 is configured to include a full-wave rectifier circuit 170, capacitors 171, 174, 183, and 184, a transformer 172, a diode 173, a power factor improvement IC 75, an NMOS transistor 176, and resistors 180 to 182.

[0234] The full-wave rectifier circuit 170 applies the rectified voltage Vrec2, obtained by full-wave rectification of the applied specified AC voltage Vac, to the capacitor 171 and the main coil L5 of the transformer 172. Here, the AC voltage Vac is, for example, a voltage of 100 to 240V with a frequency of 50 to 60Hz.

[0235] Capacitor 171 is a component used to filter the rectified voltage Vrec2, and transformer 172 has a main coil L5 and an auxiliary coil L6 magnetically coupled to the main coil L5. Here, in this embodiment, the auxiliary coil L6 is wound such that the polarity of the voltage generated in the auxiliary coil L6 is opposite to the polarity of the voltage generated in the main coil L5. Furthermore, the voltage Vzcd generated in the auxiliary coil L6 is applied to terminal ZCD.

[0236] The rectified voltage Vrec2 is applied directly to the main coil L5, but it can also be applied to the main coil L5 through a component such as a resistor (not shown).

[0237] Furthermore, the main coil L5, together with diode 173, capacitor 174, and NMOS transistor 176, constitutes a boost chopper circuit. Therefore, the charging voltage of capacitor 174 becomes the DC output voltage Vout1. Additionally, the output voltage Vout1 is, for example, 400V.

[0238] The power factor improvement IC175 is an integrated circuit that controls the switching of NMOS transistor 176 to improve the power factor of AC-DC converter 12 and make the output voltage Vout1 reach a target level (e.g., 400V). Specifically, the power factor improvement IC175 drives NMOS transistor 176 based on the inductor current IL flowing through the main coil L5 and the output voltage Vout1.

[0239] The following section details the power factor correction IC175, which has terminals VH, VCC, RT, FB, ZCD, COMP, and OUT. In addition to these seven terminals, the IC175 also has other terminals, but these are omitted here for simplicity.

[0240] NMOS transistor 176 is a transistor used to control the power supplied by AC-DC converter 12 to DC-DC converter 13. In this embodiment, NMOS transistor 176 is a MOS (Metal Oxide Semiconductor) transistor, but it is not limited to this. NMOS transistor 176 can be any transistor capable of power control, for example, it could be a bipolar transistor. Furthermore, the gate of NMOS transistor 176 is configured to be driven by a signal from terminal OUT.

[0241] Resistors 180 and 181 form a voltage divider circuit for dividing the output voltage Vout1 and generate a feedback voltage Vfb_b used when switching the NMOS transistor 176. Additionally, the feedback voltage Vfb_b generated at the node where resistors 180 and 181 are connected is applied to terminal FB.

[0242] Resistor 182 and capacitors 183 and 184 are phase compensation components for the power factor improvement IC175 used in feedback control, as detailed later. Resistor 182 and capacitor 183 are connected in series between terminal COMP and ground, and capacitor 184 is connected in parallel with resistor 182 and capacitor 183.

[0243] In addition, a pulse signal from interface circuit 18a is input to terminal RT.

[0244] <<<Details about the power factor improvement IC175>>>

[0245] Figure 13This diagram illustrates an example of the structure of a power factor correction IC175. The power factor correction IC175 is configured to include a drive circuit 190, a signal detection circuit 191, and a resistor 192. Additionally, in... Figure 13 In the text, for convenience, the terminals are depicted on the same side as... Figure 12 In different locations, however, the wiring, components, etc., connected to each terminal are... Figure 12 and Figure 13 The same applies to both.

[0246] ===Driver Circuit 190===

[0247] The drive circuit 190 is a circuit that generates a drive signal Vdr to turn the NMOS transistor 176 on or off based on a feedback voltage Vfb_b corresponding to the output voltage Vout1. The drive circuit 190 is configured to include a zero-current detection circuit 200, a delay circuit 201, a pulse circuit 202, a turn-on timer circuit 203, OR gate circuits 204 and 213, an error amplifier circuit 210, an oscillation circuit 211, a comparator 212, an SR flip-flop 220, and a buffer circuit 221.

[0248] =====Zero Current Detection Circuit 200=====

[0249] The zero-current detection circuit 200 detects whether the current value of the inductor current IL is approximately zero (hereinafter referred to as "approximately zero" or "zero") based on the voltage Vzcd at terminal ZCD. Furthermore, when the zero-current detection circuit 200 of this embodiment detects that the current value of the inductor current IL is "zero," i.e., "current value Ia," it outputs a signal Vz at a level of "H." In addition, the zero-current detection circuit 200 is configured to include a comparator (not shown) that compares a predetermined voltage of the auxiliary coil L6 when the inductor current IL changes to "current value Ia" with the voltage Vzcd.

[0250] ==== Delay Circuit 201 ====

[0251] When the zero current detection circuit 200 outputs a signal Vz at the "H" level, the delay circuit 201 outputs the signal after a specified delay.

[0252] ==== Pulse Circuit 202 ====

[0253] When the delay circuit 201 outputs a signal Vz at the "H" level, the pulse circuit 202 outputs a pulse signal Vp1 at the "H" level.

[0254] ====Conduction Timer Circuit 203====

[0255] When the power factor improvement IC175 is activated, or when the AC voltage Vac is cut off and there is no output pulse signal Vp1, the turn-on timer circuit 203 outputs a pulse signal Vp2 to turn on the NMOS transistor 176. Specifically, when there is no output pulse signal Vp1 for a specified period, a "H" level pulse signal Vp2 is output every specified period.

[0256] ===== OR gate circuit 204 =====

[0257] The OR gate circuit 204 performs a logical OR operation on the pulse signals Vp1 and Vp2. Therefore, in this embodiment, the pulse signal Vp1 or pulse signal Vp2 output from the OR gate circuit 204 is used as signal Vp3.

[0258] =====Error Amplifier Circuit 210=====

[0259] Error amplifier circuit 210 is a circuit that amplifies the error between the feedback voltage Vfb_b applied to terminal FB and a specified reference voltage VREF0 or VREF1. Additionally, the ratio of resistors 180 and 181 is adjusted based on the reference voltage VREF0 to make the output voltage Vout1 the desired voltage.

[0260] Furthermore, the reference voltages VREF0 and VREF1 are selected based on the signal enb from the signal detection circuit 191 described later. Additionally, the reference voltage VREF1 is the reference voltage used to generate an output voltage Vout1 that is lower than the target level when the AC input is high (e.g., 200V).

[0261] Furthermore, the phase compensation resistor 182 and capacitors 183 and 184 are connected between the output of the error amplifier circuit 210 and ground via the terminal COMP. Here, the voltage at the node where the output of the error amplifier circuit 210 is connected to the terminal COMP is set as voltage Ve.

[0262] ====Oscillating Circuit 211====

[0263] Whenever a signal Vp1 of “H” level from SR flip-flop 220 is input, oscillation circuit 211 outputs a ramp wave Vr with gradually increasing amplitude.

[0264] ==== Comparator 212 ====

[0265] Comparator 212 compares the voltage Ve with the magnitude of the ramp wave Vr and outputs signal Vc1 as the comparison result. Here, voltage Ve is applied to the inverting input terminal of comparator 212, and ramp wave Vr is applied to the non-inverting input terminal of comparator 212. Therefore, when the level of ramp wave Vr is lower than the level of voltage Ve, signal Vc1 becomes "L" level, and when the level of ramp wave Vr is higher than the level of voltage Ve, signal Vc1 becomes "H" level.

[0266] ===== OR gate circuit 213 =====

[0267] OR gate 213 performs a logical OR operation on signal Vc1 and signal Vsb from signal detection circuit 191, and outputs the result. Therefore, when signal Vc1 or signal Vsb becomes "H" level, signal Vp4 of "H" level is output from OR gate 213.

[0268] ====SR trigger 220====

[0269] Signal Vp3 is input to the S input terminal of SR flip-flop 220, and signal Vp4 is input to the R input terminal. Therefore, when signal Vp3 becomes "H" level, the Q output of SR flip-flop 220, i.e., the drive signal Vq1, becomes "H" level. On the other hand, when signal Vp4 becomes "H" level, the drive signal Vq1 becomes "L" level. Furthermore, SR flip-flop 220 operates in a reset-priority manner; when signal Vp4 is "H" level, it always outputs the "L" level signal Vq1, regardless of signal Vp3.

[0270] =====Buffer Circuit 221=====

[0271] The buffer circuit 221 drives the NMOS transistor 176 based on the drive signal Vq1. Specifically, the buffer circuit 221 drives the NMOS transistor 176, which has a relatively large gate capacitance, using a signal Vdr with the same logic level as the input signal. Furthermore, the buffer circuit 221 turns on the NMOS transistor 176 based on the "H" level drive signal Vq1 and turns it off based on the "L" level drive signal Vq1.

[0272] ===Signal Detection Circuit 191===

[0273] The signal detection circuit 191 causes the control IC 50 to operate in "internal mode," thus realizing the main function when the control IC 50 controls the power factor improvement IC 175. However, this embodiment describes the case where the control IC 50 operates in "external mode."

[0274] Therefore, in this embodiment, when the determination circuit 121 outputs a signal Se representing "external mode", Figure 5 The communication circuit 135 outputs a pulse signal indicating whether the effective value of the AC voltage Vac is high (e.g., 200V) or low (e.g., 100V) to the power factor improvement IC 175 via the interface circuit 18a.

[0275] Then, the signal detection circuit 191 detects whether the AC input is 100V or 200V based on the pulse signal input via terminal RT, and outputs a signal enb indicating whether the AC input is 100V or 200V. Additionally, a resistor 192 is connected to terminal RT to pull up the power supply voltage Vdd from the internal power supply (not shown). Furthermore, other functions of the signal detection circuit 191 will be described later.

[0276] <<<Controlling the Actions of IC50>>>

[0277] Figure 14 This is a diagram illustrating an example of the operation of the control IC50. Additionally, Figure 14 This is an example of the operation of control IC50 when it changes its drive mode to "external mode" after starting. Furthermore, before time t0, microcontroller 15a outputs a "Wakeup" signal (i.e., "L" level) to stop DC-DC converter 13. At this time, control IC50 is in "cut-off mode". Additionally, the effective value of the AC voltage Vac (i.e., AC input) is 100V.

[0278] At time t0, when Figure 1 When the microcontroller 15a outputs a Wakeup signal (i.e., a "H" level signal) that causes the DC-DC converter 13 to operate, Figure 9 The NMOS transistor 152 is turned on. The capacitor 150 discharges through the resistor 151, and the voltage Vstb at terminal STB begins to decrease.

[0279] At time t1, when the voltage Vstb drops to the specified level Vstop, the determination circuit 73 outputs a switching signal Sb that should be performed. Therefore, the control circuit 81 outputs a signal to the charging circuit 82 that... Figure 3 The capacitor 61 begins charging with the signal Pon. Then, the voltage Vcc begins to rise. At this point, control IC 50 switches to "power-on mode". However, since the initial settings of control IC 50 have not yet been completed, NMOS transistors 32 and 33 do not switch.

[0280] At time t2, when the voltage Vcc reaches the specified level Vccrst, the reset circuit 90 outputs a signal rst1 to control the operation of various circuits in the control IC 50. Then, the state setting period begins. Figure 5The control circuit 120 outputs a signal S1 to discharge the capacitor 150, and the discharge circuit 130 discharges the capacitor 150. As a result, the voltage Vstb becomes the ground voltage.

[0281] At time t3, when the voltage Vcc reaches the specified level Vstoff, the control circuit 81 outputs a signal Pon to the charging circuit 82 to stop charging capacitor 61. Then, before time t6 (described later), the control circuit 81 outputs the following signal Pon: when the voltage Vcc reaches the specified level Vston, the charging circuit 82 starts charging. Figure 3 The charging of capacitor 61 is stopped when the voltage Vcc reaches the specified level Vstoff.

[0282] At time t4, when the control circuit 120 outputs signal S1 to stop capacitor 150 from discharging and signal S2 indicating the supply of current Ib, Figure 5 Current source 131 supplies current Ib to resistor 151 via terminal STB. As a result, voltage Vstb becomes the voltage corresponding to the resistance value Rstb of resistor 151. Furthermore, in this embodiment, the resistance value Rstb of resistor 151 is as follows: Figure 6 The resistance value Ra is shown.

[0283] At time t5, when the control circuit 120 outputs a timing signal S3 indicating that the digital value Dvstb should be acquired, the determination circuit 121 acquires the digital value Dvstb of the voltage Vstb. As a result, the determination circuit 121 determines that it is in "external mode" and outputs a signal Se indicating "external mode".

[0284] Subsequently, control circuit 120 outputs signal S1 to discharge capacitor 150, and discharge circuit 130 discharges capacitor 150. As a result, voltage Vstb becomes ground voltage.

[0285] At time t6, when the state setting period is completed, and the control circuit 120 outputs a signal Sd indicating that the initial setting period for the various circuits of the control IC 50 is complete, the control circuit 81 causes the charging circuit 82 to charge the capacitor 61 until the voltage Vcc reaches the specified level Vccon. Additionally, the internal power supply 92 outputs voltage Vreg1 to terminal REG.

[0286] Then, when the control circuit 120 outputs a signal S1 to stop the discharge of the capacitor 150, the discharge circuit 130 stops the discharge of the capacitor 150. As a result, the clamping circuit 133 begins to maintain the voltage Vstb at the voltage Vnorm.

[0287] At time t7, when the voltage Vcc exceeds the specified level Vccon, the low voltage protection circuit 91 outputs... Figure 4 The load detection circuit 100, oscillation circuit 101, and drive circuit 102 start operating with the signal rst2. Furthermore, as the voltage Vcc reaches the specified level Vccon, the control circuit 81 outputs a signal Pon to the charging circuit 82 to stop the capacitor 61 from charging.

[0288] In addition, when the oscillation circuit 101 receives the signal Sc indicating "normal mode" and the signal Se indicating "external mode", it outputs the oscillation signal Vosc to the drive circuit 102 to continuously switch the NMOS transistors 32 and 33.

[0289] Then, control IC50 begins. Figure 3 The NMOS transistors 32 and 33 are switched, and then capacitor 61 is charged by the current from auxiliary coil L4. Furthermore, since the AC input is 100V, communication circuit 135 outputs a pulse signal indicating a low effective value of AC voltage Vac to power factor improvement IC 175 via terminal STB.

[0290] At time t8, microcontroller 15a outputs a signal ExtSTB (i.e., "H" level) to control IC 50 to switch NMOS transistors 32 and 33 in "low standby power mode". The voltage Vstb is lower than the specified level Vthstb. As a result, comparator 134 outputs a signal Sc indicating "low standby power mode".

[0291] Then, when the oscillation circuit 101 receives the signal Sc indicating "low standby power mode" and the signal Se indicating "external mode", it outputs the oscillation signal Vosc to the drive circuit 102 to cause the NMOS transistors 32 and 33 to switch intermittently.

[0292] At time t9, microcontroller 15a outputs a signal ExtSTB to control IC 50 to switch NMOS transistors 32 and 33 in "normal mode" (i.e., at "L" level), with the voltage Vstb being higher than the specified level Vthstb. As a result, comparator 134 outputs a signal Sc indicating "normal mode".

[0293] Then, when the oscillation circuit 101 receives the signal Sc indicating "normal mode" and the signal Se indicating "external mode", it outputs the oscillation signal Vosc to the drive circuit 102 to continuously switch the NMOS transistors 32 and 33.

[0294] At time t10, the same as at time t7, since the AC input is 100V, the communication circuit 135 outputs a pulse signal indicating that the effective value of the AC voltage Vac is low to the power factor improvement IC 175 via the STB terminal.

[0295] The above describes the implementation method of the control IC 50 changing the drive mode in "external mode". Furthermore, the control IC 50 can change its operating mode between "disconnect mode" and "power-on mode" based on the logic level of the Wakeup signal. In "disconnect mode", the circuits except for the startup circuit 70 are stopped, while in "power-on mode", the circuits including the startup circuit 70 are activated.

[0296] Furthermore, in this embodiment, through the structure of the interface circuit 18a, the control IC 50 can appropriately switch the NMOS transistors 32 and 33 in "normal mode" or "low standby power mode" according to the logic level of the signal ExtSTB after startup.

[0297] Therefore, when the control IC50 is in "off mode," it can reduce its own power consumption. Even when the control IC50 operates in "power-on mode," it can change the drive mode to "normal mode" or "low standby power mode" according to the logic level of the ExtSTB signal, thereby reducing the power consumption of the DC-DC converter 13. Moreover, the power consumption of the control IC50 in "off mode" is less than that in "normal mode" or "low standby power mode."

[0298] <<<Structure and Operation of Interface Circuit 18b>>>

[0299] Figure 15 This is a diagram illustrating an example of interface (IF) circuit 18b. Interface circuit 18b is used in "internal mode" to change the drive configuration, and is derived from... Figure 9 The interface circuit 18a has had NMOS transistors 153 and 157 and resistors 155 and 156 removed from it. Therefore, the structure of interface circuit 18b will not be described in detail.

[0300] <<Operation when the Wakeup signal is at "L" level>>

[0301] In addition, with Figure 9 Similarly, when the microcontroller 15b outputs the Wakeup signal (i.e., "L" level) that stops the DC-DC converter 13, the voltage Vstb at terminal STB is as follows: Figure 16 The signal becomes higher than the specified level Vstop. As a result, interface circuit 18b, as shown... Figure 17 The signal Wakeup is shown as "L", which sets the control IC50 to "cut-off mode".

[0302] <<Operation when the Wakeup signal is at level "H">>

[0303] On the other hand, when the microcontroller 15b outputs the Wakeup signal (i.e., "H" level) to activate the DC-DC converter 13, the voltage Vstb level is as follows: Figure 16 The signal becomes lower than the specified level Vstop. As a result, interface circuit 18b, as shown... Figure 17 The signal Wakeup is indicated by the "H" part, which causes the control IC50 to operate in "power-on mode".

[0304] <Description of the cooperative function between control IC50 and power factor improvement IC175>

[0305] Then, when changing the drive type in "internal mode", Figure 5 Communication circuit 135, such as Figure 17 As shown, in order to achieve the cooperative function between the control IC50 and the power factor improvement IC175, a pulse signal is output to the power factor improvement IC175 according to the AC input and the operating mode of the control IC50.

[0306] Specifically, communication circuit 135, such as Figure 17 As shown, the number of pulses contained in the pulse signal is changed according to the AC input (e.g., referring to pulses (a) and (c)), and the pulse width of the pulse is changed according to the operating mode of the control IC50 (e.g., referring to pulses (a) and (b)).

[0307] Then, when the power factor improvement IC175 receives a pulse signal with a pulse width T1 and a pulse count of 2, it detects that the AC input is 100V and that the operating mode should be changed to continuous switching. When the power factor improvement IC175 receives a pulse signal with a pulse width T2 and a pulse count of 2, it detects that the AC input is 100V and that the operating mode should be changed to intermittent switching.

[0308] Furthermore, when the power factor improvement IC175 receives a pulse signal with pulse width T1 and pulse count of 1 (c), it detects that the AC input is 200V and the operating mode should be changed to continuous switching. Furthermore, when the power factor improvement IC175 receives a pulse signal with pulse width T2 and pulse count of 1 (d), it detects that the AC input is 200V and the operating mode should be changed to intermittent switching.

[0309] Furthermore, when a pulse signal with a pulse width of T3 and being a continuous pulse is received, the power factor improvement IC175 stops switching during the period when the pulse signal is received. Additionally, the power factor improvement IC175 stops when the control IC50 is in "off mode". Moreover, the pulse widths T1 to T3 are in the order T2 > T1 > T3.

[0310] <Details of Signal Detection Circuit 191>

[0311] Figure 13 The signal detection circuit 191 detects the voltage Sig at terminal RT, which is supplied with a pulse signal from control IC 50, and detects relevant indications of AC input and switching based on the number of pulses and the pulse width of the pulse signal. Specifically, as described above, the signal detection circuit 191 detects that the AC input is 100V when the pulse signal contains two pulses.

[0312] Then, the signal detection circuit 191 detects that the AC input is 200V when the pulse signal contains a single pulse. Thus, the power factor correction IC 175 can change its operation based on the type of AC input represented by the pulse signal, without needing to detect the AC input itself.

[0313] Furthermore, when the pulse width of the pulse signal is pulse width T1, the signal detection circuit 191 detects that the control IC 50 instructs the power factor improvement IC 175 to perform "continuous switching". In this case, the signal detection circuit 191 outputs the "L" level signal Vsb to the OR gate circuit 213. Then, the power factor improvement IC 175 sets the signal Vdr to the "L" level based on the signal Vc1 output by the comparator 212.

[0314] Furthermore, when the pulse width of the pulse signal is pulse width T2, the signal detection circuit 191 detects that the control IC50 indicates the power factor improvement IC175 to perform "intermittent switching". In this case, the signal detection circuit 191 outputs a "H" level signal Vsb when the voltage Vfb_b becomes a specified level V1, and outputs a "L" level signal Vsb when the voltage Vfb_b drops to a specified level V2.

[0315] Therefore, when the voltage Vfb_b reaches the specified level V1, the signal detection circuit 191 sets the signal Vdr to the "L" level and causes the power factor improvement IC 175 to turn off the NMOS transistor 176. On the other hand, when the voltage Vfb_b drops to the specified level V2, the signal detection circuit 191 causes the power factor improvement IC 175 to drive the NMOS transistor 176 based on the signal Vc1.

[0316] Furthermore, when the pulse width of the pulse signal is pulse width T3, the signal detection circuit 191 detects that the control IC 50 instructs the switching to be stopped during the period when the pulse signal is output to the power factor improvement IC 175. In this case, during the period of pulse signal input, the signal detection circuit 191 outputs a signal Vsb with an "H" level, sets the signal Vdr to an "L" level, and causes the power factor improvement IC 175 to turn off the NMOS transistor 176.

[0317] <<<Coordinated Operation of Control IC50 and Power Factor Correction IC175>>>

[0318] Figure 18 This diagram illustrates an example of the operation of control IC50 and power factor improvement IC155. Additionally, Figure 18 This is an example of the action of control IC50 when control IC50 changes its drive mode in "internal mode" after it starts up.

[0319] Furthermore, before time t20, the microcontroller 15b outputs a Wakeup signal (i.e., a "L" level signal) to stop the DC-DC converter 13. At this time, the control IC 50 is in "off mode". Additionally, the effective value of the AC voltage Vac (i.e., the AC input) is 100V.

[0320] Furthermore, in interface circuit 18b, since the signal ExtSTB and voltage Vreg1_div are not used as inputs, therefore... Figure 18 Not shown in the image. In addition, besides the following points, Figure 18 The action of control IC50 from time t20 to time t27 corresponds to Figure 14 The action of control IC50 from time t0 to time t7.

[0321] At time t25, the determination circuit 121 determines that it is in "internal mode" and outputs a signal Se indicating "internal mode".

[0322] Furthermore, the power factor improvement IC175 stops switching before the control IC50 is in "off mode" at time t21. Additionally, the power factor improvement IC175 stops switching from the time the control IC50 transitions to "on mode" at time t21 until the state setting period is completed and continuous switching begins at time t27. In summary, the operation of the control IC50 and the power factor improvement IC155 after time t27 will be explained below.

[0323] At time t27, when the voltage Vcc exceeds the specified level Vccon, the low voltage protection circuit 91 outputs... Figure 4 The load detection circuit 100, oscillation circuit 101, and drive circuit 102 start operating with a signal rst2. Furthermore, since the voltage Vcc level changes to the specified level Vccon, the control circuit 81 outputs a signal Pon to the charging circuit 82 to stop charging capacitor 61.

[0324] In addition, the oscillator circuit 101 performs interaction with Figure 14 The same action as at time t7. Then, with Figure 14The situation is the same at time t7, after which capacitor 61 is charged by the current from auxiliary coil L4. Furthermore, communication circuit 135 performs... Figure 14 The same action occurs at time t7.

[0325] In addition, the power factor improvement IC175 starts continuous switching when the voltage Vcc level exceeds the specified level Vccon.

[0326] At time t28, Figure 4 The load detection circuit 100 outputs a representation Figure 1 The load 14 is in a light load state and the voltage Vca is below the specified level Vcastb. As a result, when the oscillation circuit 101 receives the voltage Vca indicating that the load 14 is in a light load state and the signal Se indicating "internal mode", it outputs a signal to the drive circuit 102 to enable... Figure 3 The NMOS transistors 32 and 33 intermittently switch on the oscillation signal Vosc. Then, Figure 5 The communication circuit 135 outputs a pulse with a pulse width of T2, which contains two pulse signals.

[0327] At time t29, the power factor correction IC175 detects a 100V AC input based on a pulse signal and determines that intermittent switching is necessary. Therefore, the power factor correction IC175 begins to switch intermittently.

[0328] At time t30, Figure 4 The load detection circuit 100 outputs a representation Figure 1 The load 14 is in a state of heavy load and has a voltage Vca that is higher than the specified level Vcastb. As a result, when the oscillation circuit 101 receives the voltage Vca indicating that the load 14 is in a state of heavy load and the signal Se indicating "internal mode", it outputs an oscillation signal Vosc to the drive circuit 102 to cause the NMOS transistors 32 and 33 to switch continuously.

[0329] At time t31, Figure 5 The communication circuit 135 outputs a pulse signal containing two pulses with a pulse width of T1.

[0330] At time t32, the power factor correction IC175 detects a 100V AC input based on a pulse signal and determines that continuous switching should occur. Therefore, the power factor correction IC175 initiates continuous switching.

[0331] The above describes the implementation method of the control IC50 changing the drive mode in "internal mode". Furthermore, the control IC50 can change its operating mode between "disconnect mode" and "power-on mode" based on the logic level of the Wakeup signal. In "disconnect mode", the circuits except for the startup circuit 70 are stopped, while in "power-on mode", the circuits including the startup circuit 70 are activated.

[0332] Therefore, in this embodiment, through the structure of the interface circuit 18b, the control IC 50 can appropriately switch the NMOS transistors 32 and 33 according to the state of the load 14, either in "normal mode" or "low standby power mode" after startup.

[0333] Therefore, when the control IC 50 is in "off mode," it can reduce its own power consumption. Furthermore, even when operating in "power-on mode," the control IC 50 can change its drive mode to "normal mode" or "low standby power mode" according to the state of the load 14, thereby reducing the power consumption of the DC-DC converter 13. Moreover, the power consumption of the control IC 50 in "off mode" is less than that in "normal mode" or "low standby power mode." In addition, the control IC 50, in conjunction with the power factor improvement IC 175, can reduce the overall power consumption of the power supply device 10.

[0334] ===Summary===

[0335] The power supply device 10 of this embodiment has been described above. The control IC 50 includes a terminal STB, a determination circuit 73, an internal power supply 92, and a drive circuit 102. Furthermore, the control IC 50 controls the internal power supply 92 based on the voltage level (voltage Vstb) of the terminal STB, and can stop the generation of voltage Vreg1 in the internal power supply 92 when operating in "cut-off mode". Moreover, when the internal power supply 92 stops generating voltage Vreg1, the control IC 50 can stop the operation of the circuit that operates by receiving the supply of voltage Vreg1. Therefore, an integrated circuit that can further reduce power consumption can be provided.

[0336] Furthermore, the control IC 50 includes a terminal VH, a constant voltage source 80, and a current source 71. Thus, while the rectified voltage Vrec1 is applied to the terminal VH, even when the control IC 50 is in "off mode," the control IC 50 can also provide the voltage Vstartup to the current source 71 and the decision circuit 73.

[0337] Furthermore, the control IC50 includes a terminal VCC. Therefore, since the internal power supply 92 operates based on voltage Vcc, when the control IC50 is in "off mode," voltage Vcc decreases, thereby promoting the generation of the internal power supply 92's stop voltage Vreg1.

[0338] Furthermore, the control IC 50 includes a charging circuit 82. As a result, since the charging circuit 82 stops the charging of the capacitor 61, the voltage Vcc decreases when the control IC 50 is in "cut-off mode," thereby promoting the generation of the internal power supply 92's stop voltage Vreg1.

[0339] Furthermore, the control IC 50 includes a load detection circuit 100, an oscillation circuit 101, a decision circuit 121, and a comparator 134. Thus, the control IC 50 can change the driving mode of the NMOS transistors 32 and 33 in either "external mode" or "internal mode".

[0340] Furthermore, the control IC50 includes a communication circuit 135. Thus, the control IC50 can output a pulse signal to the power factor improvement IC175 and cooperate with the power factor improvement IC175 when changing the drive mode in "internal mode".

[0341] Furthermore, the control IC50 includes the REG terminal. Therefore, the control IC50 will not malfunction even if the signal ExtSTB is mistakenly input from the microcontroller 15a during state setting.

[0342] Furthermore, the control IC 50 includes a discharge circuit 130 and a control circuit 120. Thus, the control IC 50 can accurately determine the voltage corresponding to the resistance value Rstb of the resistor 151 during the state setting period.

[0343] Furthermore, the control IC50 includes an internal power supply 93. Thus, the control IC can stop the circuitry that operates under the supplied voltage Vreg2 in "off mode".

[0344] Furthermore, the control IC50 includes a Zener diode 72. Therefore, even when capacitor 150 is charged by current source 71, the voltage Vstb does not exceed a specified level.

[0345] Furthermore, the control IC 50 includes a terminal STB and a mode selection circuit (determination circuit 73 and comparator 134). Moreover, based on the voltage level (voltage Vstb) of the terminal STB, the control IC 50 can operate in any of the following modes: "switching mode," "normal mode," or "low standby power mode." Thus, the control IC 50 can further reduce power consumption.

[0346] Furthermore, the mode selection circuit can change the operating mode of the control IC50 based on the voltage level of the STB terminal. Therefore, the operating mode of the control IC50 can be changed simply by detecting the voltage level of the STB terminal.

[0347] Furthermore, the mode selection circuit includes a determination circuit 73 that operates in the "off mode" and a comparator 134 that does not operate in the "off mode". Thus, the control IC 50 can suppress power consumption in the "off mode" and can operate in either the "normal mode" or the "low standby power mode" in the "power-on mode".

[0348] In addition, the control IC 50 includes a load detection circuit 100, an oscillation circuit 101, and a setting circuit 76. Thus, the control IC 50 can change the driving mode of the NMOS transistors 32 and 33 in either "external mode" or "internal mode".

[0349] Furthermore, the control IC 50 includes a communication circuit 135. The communication circuit 135 outputs a pulse signal that is lower than the specified level Vstop and higher than the specified level Vthstb. Therefore, even if the voltage level of terminal STB changes due to the pulse signal, it does not affect the change in the operating mode of the control IC 50.

[0350] Furthermore, the control IC 50 includes an internal power supply 92 and a drive circuit 102. The control IC 50 controls the internal power supply 92 based on the voltage level (voltage Vstb) of terminal STB, and when operating in "off mode," it can stop the generation of voltage Vreg1 by the internal power supply 92. When the internal power supply 92 stops generating voltage Vreg1, the control IC 50 can stop the operation of circuits that operate by receiving the voltage Vreg1.

[0351] Furthermore, the DC-DC converter 13 includes an interface circuit 18a. The interface circuit 18a includes a resistor 151 and NMOS transistors 152, 153, and 157. Thus, the interface circuit 18a can apply a voltage to the STB terminal to set the operating mode of the control IC 50 by turning the NMOS transistors 152, 153, and 157 on or off.

[0352] Furthermore, by turning the NMOS transistor 152 on or off, the interface circuit 18a enables the control IC 50 to operate in either "off mode" or "on mode".

[0353] Furthermore, by turning NMOS transistors 153 and 157 on or off, interface circuit 18a enables control IC 50 to operate in "normal mode" or "low standby power mode".

[0354] The above embodiments are provided to facilitate understanding of the present invention, and are not intended to limit or restrict the interpretation of the invention. Furthermore, the present invention can be modified or improved without departing from its spirit, and its equivalents are naturally included.

[0355] Label Explanation

[0356] 10 Power Supply Unit

[0357] 11 switches

[0358] 12AC-DC converter

[0359] 13DC-DC converter

[0360] 14 loads

[0361] 15a, 15b microcontrollers

[0362] Capacitors 16, 30, 31, 42, 61, 63, 64, 67, 68, 150, 154, 159, 162, 171, 174, 183, 184

[0363] 17 photodiodes

[0364] 18a, 18b interface circuit

[0365] 20, 21, 40, 41, 60, 173 diodes

[0366] 22 Power Factor Improvement Circuit

[0367] 32, 33, 152, 153, 157, 160, 176 NMOS transistors

[0368] 34, 172 transformers

[0369] 35 control blocks

[0370] 43 Constant Voltage Circuit

[0371] 44 LEDs

[0372] 62 phototransistors

[0373] Resistors with ratings of 65, 66, 74, 75, 142, 151, 155, 156, 158, 161, 180, 181, and 182

[0374] 70 Start-up Circuit

[0375] 71, 131 current source

[0376] 72 Zener diode

[0377] 73 Decision Circuit

[0378] 76 Setting Circuit

[0379] 80 constant pressure source

[0380] 81, 120 control circuit

[0381] 82 charging circuit

[0382] 90 Reset Circuit

[0383] 91 Low Voltage Protection Circuit

[0384] 92, 93 Internal Power Supply

[0385] 100 load detection circuit

[0386] 101, 211 oscillation circuits

[0387] 102, 190 drive circuit

[0388] 110 Digital Department

[0389] 111 Simulation Department

[0390] 121 Decision Circuit

[0391] 130 discharge circuit

[0392] 132 analog-to-digital converter

[0393] 133 clamping circuit

[0394] 134, 212 comparators

[0395] 135 communication circuit

[0396] 140 operational amplifier

[0397] 141 PMOS transistor

[0398] 170 full-wave rectifier circuit

[0399] 191 signal detection circuit

[0400] 200 Zero Current Detection Circuit

[0401] 201 Delay Circuit

[0402] 202 pulse circuit

[0403] 203 On-Timer Circuit

[0404] 204, 213 OR gate circuits

[0405] 210 error amplifier circuit

[0406] 220SR trigger

[0407] 221 buffer circuit.

Claims

1. An integrated circuit that drives the power transistors of a power supply circuit to switch in order to generate a target level output voltage, characterized in that, include: The first terminal is connected to a first switch that is turned on or off based on an indication signal indicating the operating mode of the integrated circuit; The first determination circuit determines, based on the voltage level of the first terminal, whether the integrated circuit operates in a first mode or in a second mode with higher power consumption than the first mode. A first power supply voltage generation circuit, which stops generating the first power supply voltage when the integrated circuit operates in the first mode, and generates the first power supply voltage when the integrated circuit operates in the second mode. A driving circuit, which is supplied with the first power supply voltage, drives the power transistor to switch. The second terminal is to which a voltage corresponding to an AC voltage is applied; A constant voltage source, which generates a predetermined voltage based on the voltage applied to the second terminal, whether in the first mode or the second mode; as well as A current source that supplies current to the first terminal. The current source and the first determination circuit operate when the specified voltage is provided.

2. The integrated circuit as described in claim 1, characterized in that, It also includes a third terminal, which is connected to the first capacitor. The power transistor controls the current flowing through the primary coil of a transformer, which includes a primary coil, a secondary coil, and an auxiliary coil. The first capacitor is charged by current from the auxiliary coil. The first power supply voltage generation circuit operates based on the charging voltage of the first capacitor.

3. The integrated circuit as described in claim 2, characterized in that, It also includes a charging circuit that operates based on the specified voltage when the integrated circuit is started, and charges the first capacitor.

4. The integrated circuit as described in any one of claims 1 to 3, characterized in that, Also includes: A load detection circuit that outputs a first signal corresponding to the load of the power supply circuit; An oscillation circuit that outputs oscillation signals corresponding to a third mode among the multiple modes included in the second mode, and a fourth mode used when the load is lighter than the load state in the third mode; The second determination circuit determines, based on the voltage level of the first terminal, whether it is an internal mode in which the switching between the third mode and the fourth mode is performed inside the integrated circuit, or an external mode in which the switching between the third mode and the fourth mode is performed outside the integrated circuit. as well as A first signal output circuit, in the external mode, outputs a second signal corresponding to either the third or fourth mode based on the voltage level of the first terminal. The first terminal is connected to a resistor that is connected in series with the first switch. The oscillation circuit outputs the oscillation signal based on the first signal in the internal mode, and outputs the oscillation signal based on the second signal in the external mode. The driving circuit drives the power transistor to switch based on the oscillation signal.

5. The integrated circuit as described in claim 4, characterized in that, It also includes a second signal output circuit, which, in the internal mode, outputs a third signal to the first terminal based on the first signal, corresponding to either the third mode or the fourth mode.

6. The integrated circuit as described in claim 4, characterized in that, It also includes a fourth terminal, to which the first power supply voltage is applied. The first terminal is connected to the second and third switches. The second switch is turned on when the first power supply voltage is applied to the fourth terminal. The third switch is connected in series with the second switch and is turned on or off according to the third and fourth modes. The second switch and the third switch are connected in parallel with the resistor.

7. The integrated circuit as described in claim 4, characterized in that, Also includes: A discharge circuit that discharges the second capacitor connected to the first terminal; as well as A control circuit controls the discharge circuit so that when the integrated circuit is activated in the second mode, the second capacitor discharges before the resistor is supplied with current.

8. The integrated circuit as described in claim 7, characterized in that, It also includes a second power supply voltage generation circuit, which stops generating the second power supply voltage when the integrated circuit operates in the first mode, and generates the second power supply voltage when the integrated circuit operates in the second mode. The second power supply voltage is provided to the control circuit.

9. The integrated circuit as described in any one of claims 1 to 3, characterized in that, It also includes a clamping element that clamps the voltage of the first terminal at a specified level.

10. A power supply circuit that generates an output voltage at a target level, characterized in that, include: Power transistors; An integrated circuit that drives the power transistor; as well as The first switch is turned on or off based on an indication signal that indicates the operating mode of the integrated circuit. The integrated circuit includes: The first terminal is connected to the first switch; The first determination circuit determines, based on the voltage level of the first terminal, whether the integrated circuit operates in a first mode or in a second mode with higher power consumption than the first mode. A first power supply voltage generation circuit, which stops generating the first power supply voltage when the integrated circuit operates in the first mode, and generates the first power supply voltage when the integrated circuit operates in the second mode. A driving circuit, which is supplied with the first power supply voltage, drives the power transistor to switch. The second terminal is to which a voltage corresponding to an AC voltage is applied; A constant voltage source, which generates a predetermined voltage based on the voltage applied to the second terminal, whether in the first mode or the second mode; and A current source that supplies current to the first terminal. The current source and the first determination circuit operate when the specified voltage is provided.

11. An integrated circuit that drives the power transistors of a power supply circuit to switch in order to generate a target level output voltage, characterized in that, include: The first terminal is connected to an external circuit that sets the operating mode of the integrated circuit; as well as A mode selection circuit selects based on the voltage level of the first terminal, enabling the integrated circuit to operate in one of the following modes: a cutoff mode with no switching action, a normal mode with continuous switching action, and a low standby power mode that alternates between switching action and stop action. The mode selection circuit causes the integrated circuit to operate in the cut-off mode when the voltage level of the first terminal is higher than the first voltage level; causes the integrated circuit to operate in the normal mode when the voltage level is between the first voltage level and the second voltage level which is lower than the first voltage level; and causes the integrated circuit to operate in the low standby power mode when the voltage level is lower than the second voltage level.

12. The integrated circuit as claimed in claim 11, characterized in that, The mode selection circuit includes: A first mode determination circuit determines, when the voltage level is higher than the first voltage level, that the integrated circuit should operate in the cutoff mode. The second mode determination circuit determines that the integrated circuit should operate in the normal mode when the voltage level is lower than the first voltage level and higher than the second voltage level, and determines that the integrated circuit should operate in the low standby power mode when the voltage level is lower than the second voltage level.

13. The integrated circuit as described in claim 11 or 12, characterized in that, Also includes: An oscillation circuit that outputs an oscillation signal corresponding to the operating mode of the integrated circuit; A load detection circuit is used to detect the load status of the power supply circuit. as well as A setting circuit, which sets the state of the oscillation circuit during a state setting period when the integrated circuit is started, sets the state of the oscillation circuit based on the voltage level, such that the oscillation circuit operates in either an external mode based on the voltage level or an internal mode based on the output of the load detection circuit. When the oscillation circuit operates in the external mode, the oscillation circuit outputs the oscillation signal corresponding to the voltage level. When the oscillation circuit operates in the internal mode, the oscillation circuit outputs the oscillation signal corresponding to the output of the load detection circuit.

14. The integrated circuit as claimed in claim 13, characterized in that, It also includes a signal output circuit that outputs a signal to the first terminal with an amplitude level lower than the first voltage level and higher than the second voltage level.

15. The integrated circuit as described in claim 11 or 12, characterized in that, Also includes: A first power supply voltage generation circuit, which stops generating the first power supply voltage when the integrated circuit operates in the cut-off mode, and generates the first power supply voltage when the integrated circuit operates in the normal mode or the low standby power mode. as well as A driving circuit, which is supplied with the first power supply voltage, drives the power transistor to switch.

16. A power supply circuit that generates an output voltage at a target level, characterized in that, include: Power transistors; The integrated circuit as described in any one of claims 11 to 15; as well as External circuit, The external circuit includes: The first signal line connected to the first terminal; A resistor connected at one end to the first signal line; A first switch is connected between the other end of the resistor and ground; A second switch, one end of which is connected to the first signal line and turned on after the integrated circuit is started; and A third switch is connected between the other end of the second switch and the other end of the resistor.

17. The power supply circuit as described in claim 16, characterized in that, When the first switch is open, the external circuit applies a voltage higher than the first voltage level to the first terminal. When the first switch is turned on, the external circuit applies a voltage to the first terminal that is lower than the first voltage level.

18. The power supply circuit as described in claim 17, characterized in that, The external circuit further applies a voltage between the first voltage level and the second voltage level to the first terminal when the first switch and the second switch are turned on and the third switch is turned off. When the first switch, the second switch, and the third switch are turned on, a voltage with a lower level than the second voltage level is applied to the first terminal.

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