Resonant half-bridge flyback converter with omitted cycle and control method thereof

Abstract

A resonant half-bridge flyback converter with omitted cycles and a method of controlling the same. The resonant half-bridge flyback converter includes first and second transistors to form a half-bridge circuit, a transformer and a resonant capacitor coupled in series to each other and to the half-bridge circuit, and a switching control circuit to generate first and second drive signals to control the first and second transistors, respectively, to switch the transformer to generate an output voltage. The first drive signal is to magnetize the transformer. Between two consecutive pulses of the first drive signal, the second drive signal includes at most one pulse. The switching control circuit is to generate omitted cycles when an output power is below a predetermined threshold. Resonant pulses of the second drive signal are omitted in the omitted cycles, wherein the omitted cycles correspondingly increase as the output power decreases.

Description

Technical Field

[0001] This invention relates to a flyback converter, and more particularly to a resonant half-bridge flyback converter with an omitted period. The invention also relates to a control method for controlling the resonant half-bridge flyback converter. Background Technology

[0002] Please see Figure 1 , Figure 1 This prior art, as illustrated in US Patent 5,959,850, describes an asymmetrical duty cycle flyback converter. This prior art discloses a half-bridge flyback converter with zero-voltage switching (ZVS), thereby achieving high power efficiency. Zero-voltage switching can be defined as switching a transistor to conduct when the transistor's transverse voltage (e.g., drain-source voltage) is zero or close to zero. However, a drawback of this prior art is that the power conversion efficiency of the power converter is relatively low under light load conditions.

[0003] Another drawback of the prior art is that the output voltage of the power converter is not variable. Specifically, if the prior art is to be changed into a zero-voltage switching flyback converter with variable output voltage, the switching of the transformer must be controlled by detecting the demagnetization period of the transformer.

[0004] Another prior art US patent 7,151,681 is a multiple-sampling circuit for measuring reflected voltage and discharge time of a transformer. This prior art discloses a method for detecting the output voltage and demagnetization period of a transformer. However, this prior art cannot achieve zero-voltage switching of the power converter, which is used for discontinuous conduction mode (DCM) operation.

[0005] Figure 2This diagram shows the waveforms of a conventional half-bridge flyback converter operating in discontinuous conduction mode under light load. The drive signal SH drives the upper bridge switch of the half-bridge flyback converter to excite the transformer, and the drive signal SL drives the lower bridge switch. The waveform of the excitation current IM indicates that the transformer is operating in discontinuous conduction mode. When the output power of the half-bridge flyback converter decreases, the pulse width PW of the drive signal SH decreases due to the feedback control of the half-bridge flyback converter, and the pulse width of the drive signal SL also decreases accordingly. Therefore, the switching frequency of the half-bridge flyback converter increases, and the switching loss also increases. When the drive signal SH turns to a low level (off), the first pulse of the drive signal SL is enabled during the demagnetizing period of the transformer. The second pulse of the drive signal SL is enabled to generate a circulating current, thereby achieving zero-voltage switching of the upper bridge switch.

[0006] The disadvantage of the prior art is that when operating in discontinuous conduction mode, the drive signal SL needs to switch on / off twice in one switching cycle, which greatly increases the average switching frequency of the drive signal SL, resulting in a large amount of switching loss and energy consumption of the lower bridge switch.

[0007] Compared to the prior art US 7,151,681, the present invention provides a resonant half-bridge flyback converter with an omitted period to improve power efficiency in medium-load and light-load operating conditions.

[0008] Compared to the prior art US patent 5,959,850, the present invention provides a method for generating a demagnetizing signal and a switching control circuit, wherein the duration of the demagnetizing signal is equal to the demagnetizing period of the transformer. The present invention can be used in zero-voltage switching flyback converters with programmable output voltages, such as USB PD power converters.

[0009] Compared to Figure 2 In contrast to existing technologies, this invention provides a control circuit for an asymmetrical half-bridge (AHB) flyback converter, using three transistors to improve power conversion efficiency under medium and light load operating conditions. Summary of the Invention

[0010] From one perspective, the present invention provides a resonant half-bridge flyback converter, comprising: a first transistor and a second transistor for forming a half-bridge circuit; a transformer and a resonant capacitor, connected in series and coupled to the half-bridge circuit; and a switching control circuit for generating a first drive signal and a second drive signal to control the first transistor and the second transistor respectively, thereby switching the transformer to generate an output voltage; wherein the first drive signal is used to excite the transformer; wherein between two consecutive pulses of the first drive signal, the second drive signal includes at most one pulse, wherein the at most one pulse of the second drive signal includes a resonant pulse or a zero-voltage switch. The switching (ZVS) pulse is used to operate the transformer for a resonant cycle after it is energized. The zero-voltage switching pulse is used to realize the zero-voltage switching of the first transistor. The switching control circuit includes a timer, which generates an omission cycle when the output power is lower than a preset threshold, wherein the output power corresponds to the output voltage. A resonant pulse of the second drive signal is omitted in the omission cycle. The omission cycle increases as the output power decreases.

[0011] In a preferred embodiment, the second drive signal does not include a second pulse between two consecutive pulses of the first drive signal, so that the zero-voltage switching of the first transistor is not achieved by the second pulse.

[0012] In a preferred embodiment, both the first drive signal and the second drive signal include zero pulses during the omitted period.

[0013] In a preferred embodiment, the duration of the resonant pulse of the second drive signal is equal to or longer than a demagnetizing period of the transformer.

[0014] In a preferred embodiment, when the first transistor is turned off during the omitted cycle, a portion of a demagnetizing current of the transformer flows through a body diode of the second transistor.

[0015] In a preferred embodiment, the first drive signal comprises at most one pulse between two consecutive pulses of the second drive signal.

[0016] In a preferred embodiment, a pulse of the first drive signal is generated after each pulse of the second drive signal.

[0017] In a preferred embodiment, after the omitted period, the second transistor is turned on by a zero-voltage switching pulse to achieve zero-voltage switching of the first transistor.

[0018] In a preferred embodiment, when the output power is lower than the preset threshold, the omitting period begins at a non-conducting point when the first drive signal turns off.

[0019] In a preferred embodiment, the omission period begins at a non-conducting point when the first drive signal turns off, and when the omission period ends, the second drive signal generates a zero-voltage switching pulse.

[0020] In a preferred embodiment, the resonant period further includes a sustained zero-voltage switching period for implementing zero-voltage switching of the first transistor.

[0021] From another perspective, the present invention also provides a control method for controlling a resonant half-bridge flyback converter, wherein the resonant half-bridge flyback converter includes a first transistor and a second transistor to form a half-bridge circuit; and a transformer and a resonant capacitor, which are connected in series and coupled to the half-bridge circuit. The control method includes: switching the transformer periodically by switching the half-bridge circuit to generate an output voltage; generating an omitted period when an output power is lower than a preset threshold, wherein the output power corresponds to the output voltage; wherein the conduction of the first transistor is used to excite the transformer; the conduction of the second transistor is used to realize a resonant period or to realize zero voltage switching (ZVS) of the first transistor; wherein a resonant pulse used to control the second transistor to realize the resonant period is omitted in the omitted period; wherein the omitted period increases as the output power decreases.

[0022] The following detailed description through specific embodiments will make it easier to understand the purpose, technical content, features, and effects achieved by the present invention. Attached Figure Description

[0023] Figure 1 This demonstrates the existing technology of asymmetric duty cycle flyback converters.

[0024] Figure 2 The waveform diagram shows a prior art half-bridge flyback converter operating in discontinuous conduction mode under light load conditions.

[0025] Figure 3 This diagram shows an embodiment of the resonant half-bridge flyback converter of the present invention.

[0026] Figure 4 The display corresponds to Figure 3 The operation waveform diagram of the embodiment.

[0027] Figure 5 The waveform diagram shows the operation of reducing the switching frequency of drive signal SH and drive signal SL.

[0028] Figure 6 This diagram shows the operating waveforms of an embodiment of the resonant half-bridge flyback converter with omitted period of the present invention.

[0029] Figure 7 A block diagram showing an embodiment of the primary-side controller in the resonant half-bridge flyback converter of the present invention is shown.

[0030] Figure 8 A block diagram showing an embodiment of the primary-side controller in the resonant half-bridge flyback converter of the present invention is shown.

[0031] Figure 9 This diagram shows the waveform of the demagnetizing simulator of the present invention generating a demagnetizing signal.

[0032] Figure 10 This diagram shows a specific embodiment of the demagnetizing simulator of the present invention generating a demagnetizing signal Sdmg.

[0033] Figure 11 This diagram shows a preferred embodiment of the resonant half-bridge flyback converter of the present invention.

[0034] Figure 12 This diagram shows an operating waveform of a preferred embodiment of the primary-side controller 201 of the present invention operating in a discontinuous conduction mode.

[0035] Figure 13 A block diagram showing a preferred embodiment of the primary-side controller of the present invention is shown.

[0036] Explanation of symbols in the diagram

[0037] 10: Transformer

[0038] 100: Secondary controller

[0039] 20: Resonant capacitor

[0040] 200: Primary Side Controller

[0041] 201: Primary Side Controller

[0042] 205: Clock Generator

[0043] 208: Primary Side Controller

[0044] 22: Timer

[0045] 230: Capacitor

[0046] 231: Switch

[0047] 240: Control element

[0048] 243: Control element

[0049] 248: Control element

[0050] 25: Timer

[0051] 250: Demagnetizer

[0052] 255: Resistor

[0053] 260: Period Counter

[0054] 271, 272: Transistors

[0055] 280: Comparator

[0056] 285: Logic Circuits

[0057] 30: First transistor

[0058] 300: Resonant Half-Bridge Flyback Converter

[0059] 35: Body diode

[0060] 40: Second transistor

[0061] 45: Body diode

[0062] 51, 52, 55, 60: Resistors

[0063] 70: Secondary-side synchronous rectifier

[0064] 75: Body diode

[0065] 90: Optical Coupler

[0066] 900: Resonant Half-Bridge Flyback Converter

[0067] C: Capacitance value

[0068] CPO: Comparator Output

[0069] DCM: Discontinuous conduction mode

[0070] ID: Discharge Current

[0071] IM: Magnetizing current

[0072] IP: Primary side switching current

[0073] IS: Secondary side switching current

[0074] kn: knee point

[0075] Lr: Leakage inductance

[0076] LX: Switch Node

[0077] M1: First transistor

[0078] M2: Second transistor

[0079] M3: Third transistor

[0080] n, m: Turns ratio

[0081] NA: Auxiliary winding

[0082] NC: Positive integer

[0083] NNP: Coupled Node

[0084] NP: Primary winding

[0085] NS: Secondary winding

[0086] PW: Pulse Width

[0087] PZV: Zero Voltage Switching Pulse

[0088] Rs: Resistance value

[0089] Rt: Resistance value

[0090] S1: First drive signal

[0091] S2: Second drive signal

[0092] S3: Third drive signal

[0093] Sdmg: Demagnetizing signal

[0094] SG: Drive signal

[0095] SH: Drive signal

[0096] SL: Drive signal

[0097] SMP: Sampling signal

[0098] t1-t9: Time points

[0099] t3': Time point

[0100] ta-te: time point

[0101] TA: First period

[0102] ta', tc': time points

[0103] TB: Second period

[0104] TC: Third Period

[0105] Tcyc1: Switching cycle

[0106] Tcyc2: Switching cycle

[0107] Td1: First non-conducting period

[0108] Td2: Second non-conducting period

[0109] TDS: Demagnetization period

[0110] TDSX: During conduction

[0111] TDSX': During conduction

[0112] TRH: Time Period

[0113] TRL: Time Period

[0114] TSL: During conduction

[0115] TW: Excitation period

[0116] Tx: Omitted period

[0117] TZ: Third non-conducting period

[0118] VAUX: Auxiliary signal

[0119] VC: Transvoltage

[0120] Vcr: Transpressure

[0121] VCS: Current sensing signal

[0122] VCSp: Voltage Level

[0123] VDP: Voltage Drop

[0124] VFB: Feedback signal

[0125] Vg: Voltage level

[0126] VHB: Switching node voltage

[0127] VIN: Input voltage

[0128] Vinx: Voltage Level

[0129] VNA: Auxiliary winding signal

[0130] VO: Output voltage

[0131] VPK: Voltage Surge

[0132] Vref: Reference voltage

[0133] Vth: Voltage threshold

[0134] VX: Reflected voltage Detailed Implementation

[0135] The accompanying drawings in this invention are all schematic and are mainly intended to show the coupling relationship between various circuits and the relationship between various signal waveforms. The circuits, signal waveforms and frequencies are not drawn to scale.

[0136] Figure 3 This diagram illustrates an embodiment of the resonant half-bridge flyback converter of the present invention. The resonant half-bridge flyback converter 300 includes a first transistor 30 and a second transistor 40, forming a half-bridge circuit. A transformer 10 and a resonant capacitor 20 are connected in series and coupled to the switching node LX of the half-bridge circuit. The transformer 10 includes a primary winding NP, a secondary winding NS, and an auxiliary winding NA, wherein the primary winding NP and the secondary winding NS have a turns ratio n, and the secondary winding NS and the auxiliary winding NA have a turns ratio m. A primary-side controller 200 generates drive signals SH and SL, which switch the transformer 10 via the half-bridge circuit to generate an output voltage VO on the secondary side of the transformer 10. The drive signal SH drives the first transistor 30 to magnetize the transformer 10. The drive signal SL turns on the second transistor 40 during the demagnetizing and resonant periods of the transformer 10. The drive signal SL also turns on the second transistor 40 to generate a circulating current flowing through the transformer 10, thereby achieving zero-voltage switching of the first transistor 30. Resistor 60 generates a current sensing signal VCS by detecting the primary side switching current IP of transformer 10.

[0137] Drive signals SH and SL are generated based on feedback signal VFB, which is generated based on the output power of the resonant half-bridge flyback converter 300. Secondary-side controller 100 is coupled to the output voltage VO to generate feedback signal VFB, which is coupled to primary-side controller 200 via optocoupler 90. Secondary-side controller 100 also generates drive signal SG to drive secondary-side synchronous rectifier 70 during the demagnetization period TDS of transformer 10. Auxiliary winding NA generates auxiliary winding signal VNA during transformer 10 switching. Resistors 51 and 52 attenuate auxiliary winding signal VNA to generate auxiliary signal VAUX, which is coupled to primary-side controller 200. In one embodiment, resistor 55 is coupled to primary-side controller 200, and demagnetization signal Sdmg is generated through resistor 55 with set parameters.

[0138] Figure 4 The display corresponds to Figure 3The diagram illustrates the operating waveforms of an embodiment. When the drive signal SH is on, the transformer 10 is magnetized and generates a magnetizing current IM. When the drive signal SH is off, the transformer 10 is demagnetized. During the demagnetization period TDS, the transformer 10 generates a secondary-side switching current IS. The drive signal SL is related to the demagnetization period TDS of the transformer 10. In one embodiment, the on-time TSL (i.e., pulse width) of the drive signal SL is equal to or longer than the demagnetization period TDS of the transformer 10, thereby preventing the transformer 10 from operating in continuous conduction mode (CCM). During the demagnetization period TDS of the transformer 10, a reflected voltage VX is generated across the resonant capacitor 20, wherein the relationship between the reflected voltage VX and the output voltage VO is: VX = n*VO.

[0139] When the drive signal SH is not conducting, the drive signal SL can be conducting, and when the drive signal SL is not conducting, the drive signal SH can be conducting. The time interval between the drive signals SH and SL (i.e., when neither the drive signals SH nor SL is conducting) may include a time delay (e.g., time interval TRH, time interval TRL).

[0140] Figure 4 For operational details at different times, please refer to the following instructions.

[0141] The period from time t1 to time t2 is the excitation transformer cycle. During this period, the first transistor 30 is turned on and the second transistor 40 is turned off. The primary side switching current IP flowing through the transformer 10 increases and the voltage of the resonant capacitor 20 also increases. At this time, the transformer 10 is energized and the resonant capacitor 20 is charged. The secondary side synchronous rectifier 70 is turned off and its body diode 75 has a reverse bias voltage. Therefore, no energy is converted to the secondary side at this time.

[0142] The period from time t2 to time t3 is the first circulating current cycle. During this period, both the first transistor 30 and the second transistor 40 are turned off. The circulating current of the transformer 10 forces the switching node voltage VHB of the half-bridge circuit to drop until the body diode 45 of the second transistor 40 turns on. The period from time t2 to time t3 is related to the quasi-resonant period to achieve zero-voltage switching of the second transistor 40. At this time, the primary voltage of the transformer 10 is the same as the voltage of the resonant capacitor 20 at time t3.

[0143] The period from time point t3 to time point t4 is the resonant period (positive current). During this period, in the zero-voltage switching state, the first transistor 30 is turned off and the second transistor 40 is turned on. At this time, the output voltage VO is equal to the voltage across the resonant capacitor 20 Vcr divided by the turns ratio n. Current begins to flow through the secondary-side synchronous rectifier 70, and the energy stored in the transformer 10 is converted to the output terminal to generate the output voltage VO. Since the leakage inductance Lr of the transformer 10 and the resonant capacitor 20 (Cr) form an inductor-capacitor tank (LC tank), the secondary-side current is sinusoidal in form during the period determined by the resonant frequencies Lr and Cr. The primary-side current of the transformer 10 is the sum of the magnetizing current IM and the secondary-side switching current IS. The current flowing through the resonant tank (Lr, Cr) is still a positive current, which is mainly driven by the magnetizing inductance of the transformer 10 and flows through the resonant capacitor 20.

[0144] The period from time t4 to time t5 is the resonant period (negative current). During this period, the first transistor 30 continues to be turned off and the second transistor 40 continues to be turned on, and energy continues to be converted to the secondary side. However, the resonant tank current is reverse-driven by the voltage of the resonant capacitor 20. The energy of the resonant capacitor 20 is not only converted to the secondary side, but also used to pull the excitation current level of the transformer 10 to a negative value when the second transistor 40 continues to be turned on (e.g., from time t4 to time t5).

[0145] The period from time t5 to time t6 is the reverse excitation transformer cycle (negative current). During this period, from the end of the demagnetization period TDS of transformer 10 to the turn-off of the second transistor 40, the resonant capacitor 20 reverse excites transformer 10 and generates a negative current.

[0146] The period from time t6 to time t7 is the second cycle of current circulation. During this period, both the first transistor 30 and the second transistor 40 are turned off. The negative current of the transformer 10 is generated from time t5 to time t6, which forces the switching node voltage VHB on the switching node LX in the half-bridge circuit to increase until it turns on the body diode 35 of the first transistor 30.

[0147] After time t7, another cycle similar to the period from time t1 to time t2 begins. The first transistor 30 is turned on in the zero-voltage switching state and the second transistor 40 is turned off. If the circulating current in the transformer resonant slot is still negative, the excess energy in the resonant slot will be sent back to the input terminal (the node supplying the input voltage VIN).

[0148] Under light load conditions, when the output power decreases, the pulse widths of drive signals SH and SL will decrease accordingly. Therefore, the switching frequency of drive signals SH and SL increases under light load conditions. Due to the increase in power losses such as core loss and switching loss, the power conversion efficiency of the power converter deteriorates.

[0149] Figure 5 The diagram shows the operating waveforms for reducing the switching frequency of drive signals SH and SL. One way to improve power efficiency is to reduce the switching frequency by extending the time between the turn-off of drive signal SL (e.g., time t3) and the turn-on of drive signal SH (e.g., time t5). However, the turn-off of drive signal SL will generate circulating current, which will lead to a voltage surge VPK at the switching node voltage VHB and a voltage drop VDP in the auxiliary signal VAUX. The voltage surge VPK and voltage drop VDP will cause power loss and noise.

[0150] It should be noted that the on or off of the aforementioned drive signal SH and drive signal SL each correspond to the on or off of the first transistor 30 and the second transistor 40, respectively.

[0151] Figure 6 This diagram shows the operating waveforms of an embodiment of the resonant half-bridge flyback converter with omitted period of the present invention.

[0152] Please see Figure 6 In one embodiment, the drive signal SH is turned on during the excitation cycle of the excitation transformer 10 (e.g., from time t1 to time t2) to excite the transformer 10. After the drive signal SH is turned off, the drive signal SL is turned on during the resonant cycle (e.g., from time t2 to time t3) and has a resonant pulse (e.g., from time t2 to time t3). One excitation cycle and one resonant cycle form a switching cycle (e.g., from time t1 to time t3).

[0153] like Figure 6 As shown, in one embodiment, the omitting period Tx begins at the point when the drive signal SH turns off (e.g., time point t4), and when the omitting period Tx ends (e.g., time point t6), the drive signal SL turns on. In one embodiment, when the output power decreases due to power saving, the omitting period Tx will increase accordingly (i.e., the switching frequency decreases).

[0154] Please continue reading. Figure 6Compared to time periods without an omitted period, such as time points t1 to t3, the driving signal SL does not conduct and has no resonant pulse during the omitted period (e.g., Tx). For example, in the prior art, the driving signal SL has a pulse between time points t4 and t5, i.e., the resonant pulse of the driving signal SL. In this embodiment, this has been omitted. Figure 6 As shown, therefore, no negative circulating current is generated during the omitted period (time point t4 to time point t6). In the prior art, the voltage surge VPK generated by switching node voltage VHB and the voltage drop VDP generated by auxiliary signal VAUX have also been avoided in this embodiment. In one embodiment, as... Figure 6 As shown, the drive signal SH is also in a non-conducting state during the omitted period (e.g., Tx).

[0155] In one embodiment, when the drive signal SH is turned off, a portion of the demagnetizing current of the transformer 10 flows through the body diode 45 of the second transistor 40 during a portion of the omitted period (e.g., a portion of the time between time t4 and time t5). In other words, in one embodiment, there are no double pulses in the drive signal SL. In another embodiment, there are also no double pulses in the drive signal SH. From one perspective, a single pulse of the drive signal SL is generated after a single pulse of the drive signal SH, and a single pulse of the drive signal SH is generated after a single pulse of the drive signal SL, even if the resonant half-bridge flyback converter operates in a state with an omitted period. From another perspective, the drive signal SL includes at most one pulse between two consecutive pulses of the drive signal SH, and the drive signal SH includes at most one pulse between two consecutive pulses of the drive signal SL.

[0156] In one embodiment, an omitting period Tx is generated when the output power is lower than a preset threshold. In another embodiment, the omitting period Tx increases accordingly as the output power decreases. In yet another embodiment, even if the drive signal SL cannot achieve zero-voltage switching of the first transistor 30, the second drive signal does not include a second pulse between two consecutive pulses of the first drive signal, and therefore the zero-voltage switching of the first transistor 30 is not achieved with a second pulse.

[0157] Please continue reading. Figure 6 In one embodiment, the zero-voltage switching pulse (e.g., PZV) of the drive signal SL turns on the second transistor 40 after the omitted period has elapsed, so as to realize the zero-voltage switching period (e.g., from time t6 to time t7).

[0158] like Figure 6 As shown, in one embodiment, at least one switching cycle (e.g., from time t7 to time t9) is then generated after the zero-voltage switching pulse PZV with the cycle omitted.

[0159] Please continue reading. Figure 6 In one embodiment, the resonant period may include a period of sustained zero-voltage switching (e.g., from time t3' to time t3), during which the zero-voltage switching of the first transistor 30 is achieved. In other words, in this embodiment, the first part of the resonant pulse (e.g., from time t2 to time t3') is used to achieve resonance between the transformer 10 and the resonant capacitor 20, while the second part of the resonant pulse (e.g., from time t3' to time t3) is used to generate a circulating current to achieve zero-voltage switching of the first transistor 30.

[0160] Figure 7 This diagram shows a block diagram of an embodiment of the primary-side controller in the resonant half-bridge flyback converter of the present invention. In one embodiment, the primary-side controller 200 includes a timer 25 and a control element 240. In one embodiment, the control element 240 is used to generate drive signals SH and SL based on the input voltage VIN (via the auxiliary signal VAUX) and the feedback signal VFB, and the timer 25 is used to generate the aforementioned omitted period Tx.

[0161] like Figure 7 As shown, in one embodiment, the timer 25 determines whether the output power is lower than a preset threshold based on information related to the output power. When the output power is determined to be lower than the preset threshold, the timer 25 starts to calculate the omission period Tx and controls the control element 240 to omit the pulses of the drive signal SH and the drive signal SL in the omission period Tx.

[0162] Please refer to it again. Figure 4 When the resonant half-bridge flyback converter is under medium or light load, the resonant period from time t4 to time t5 is short and cannot generate enough negative current (energy) to achieve zero voltage switching. Therefore, the main part of the negative current comes from the current generated from time t5 to time t6.

[0163] However, higher negative current will lead to higher power loss. In order to control the negative current that achieves zero voltage switching at an appropriate level, the control of the demagnetization period must be accurate. Therefore, a demagnetization signal Sdmg corresponding to the demagnetization period TDS of transformer 10 needs to be generated.

[0164] Figure 8This diagram shows a block diagram of an embodiment of the primary-side controller in the resonant half-bridge flyback converter of the present invention. In one embodiment, the primary-side controller 208 includes a demagnetizing simulator 250 and a control element 248. In one embodiment, the control element 248 is configured to generate drive signals SH and SL based on the input voltage VIN (via auxiliary signal VAUX) and the feedback signal VFB, and the demagnetizing simulator 250 is configured to generate a demagnetizing signal Sdmg based on a demagnetizing-related signal to simulate the demagnetizing period TDS, wherein the demagnetizing-related signal is, for example, the reflected voltage of transformer 10 (via auxiliary signal VAUX).

[0165] Please also refer to Figure 9 , Figure 9 This diagram shows the waveform of the demagnetizing simulator of the present invention generating a demagnetizing signal.

[0166] During the switching cycle, the resonant half-bridge flyback converter periodically operates in a discontinuous conduction mode (e.g., from time ta to time tc'). The drive signal SH first turns on the first transistor 30 to excite the transformer 10 and generate a primary-side switching current IP (e.g., from time ta' to time tb). After the first transistor 30 turns off, the drive signal SL is used to turn on the second transistor 40 during the resonant cycle (from time tb to time tc) (e.g., from time tb to time tc') and generate a circulating current (e.g., from time tc to time tc') to achieve zero-voltage switching of the first transistor 30. During the switching cycle of the discontinuous conduction mode, the conduction period TSL of the drive signal SL (e.g., from time tb to time tc') is determined by the pulse width (e.g., TDSX') of the demagnetizing signal Sdmg, which is generated by the demagnetizing simulator 250 according to corrections in the previously forcibly inserted discontinuous conduction mode. In one embodiment, the conduction period TDSX' of the demagnetizing signal Sdmg is corrected during the previously actively forced discontinuous conduction mode and used to enable the control element 248 to control the minimum conduction time of the second transistor 40, thereby demagnetizing the transformer 10 during the discontinuous conduction mode after the first transistor 30 is turned off. In one embodiment, as Figure 9 As shown, the conduction period TSL of the drive signal SL (e.g., from time tb to time tc') can be extended by adding a delay time (e.g., from time tc to time tc') to the conduction period TDSX' of the demagnetizing signal Sdmg, so as to establish a negative circulating current on the primary side switching current IP after the demagnetizing period, thereby realizing the zero-voltage switching of the first transistor 30.

[0167] It should be noted that non-discontinuous conduction mode refers to an operating mode that is not a discontinuous conduction mode, such as continuous conduction mode (CCM) or quasi-resonant mode (QRM). Quasi-resonant mode is also known as boundary conduction mode (BCM).

[0168] In one embodiment, when the primary-side switching current IP has already operated in a non-discontinuous conduction mode (e.g., quasi-resonant mode) for a preset number (e.g., a positive integer NC) of switching cycles (e.g., time point ta to time point t1), at least one switching cycle is actively forced to operate in a discontinuous conduction mode (e.g., time point t1 to time point t3). Therefore, the demagnetizing simulator 250 is used to correct the conduction period TDSX of the demagnetizing signal Sdmg according to the demagnetizing period TDS of the transformer 10 in the forced insertion of the discontinuous conduction mode.

[0169] like Figure 9 As shown, in the forced-insertion discontinuous conduction mode, the demagnetization period TDS of transformer 10 begins at the rising edge of the auxiliary signal VAUX and ends at the falling edge (knee point kn) of the auxiliary signal VAUX (e.g., from time point t2 to time point t3). Specifically, in this embodiment, the reflected voltage can be detected by sensing the auxiliary signal VAUX, which originates from the auxiliary winding NA of transformer 10 during the turn-off period of the first transistor 30. The duration of the reflected voltage, i.e., the pulse width of the auxiliary signal VAUX from the rising edge to the knee point kn, is related to the demagnetization period TDS of transformer 10.

[0170] In one embodiment, the primary-side controller 208 further includes a cycle counter 260, which calculates the number of switching cycles operating in discontinuous conduction mode based on the primary-side switching current IP. When the primary-side switching current IP is determined to have already operated in discontinuous conduction mode for a preset number of switching cycles, the cycle counter 260 controls the control element 248 to actively force operation in discontinuous conduction mode. In one embodiment, the cycle counter 260 can sense the primary-side switching current IP via a current sensing signal VCS, thereby determining whether operation is in discontinuous conduction mode.

[0171] In one embodiment, such as Figure 9As shown, during the forced discontinuous conduction mode switching cycle, the drive signal SL continuously controls the second transistor 40 to be non-conducting, so that the half-bridge circuit operates not only in the discontinuous conduction mode but also in the asynchronous switching mode. During the forced discontinuous conduction mode switching cycle, a portion of the demagnetizing current of the transformer 10 (e.g., IP from time t2 to time t2') flows through the body diode 45 of the second transistor 40.

[0172] Please continue reading. Figure 9 After the discontinuous conduction mode (DCM) (e.g., from time t4 to time t5), the first pulse of the drive signal SL turns on the second transistor 40 to excite the transformer 10 through the self-resonant capacitor 20, thereby generating a negative circulating current (IP from time t4 to time t5) to achieve zero-voltage switching of the first transistor 30.

[0173] Figure 10 This diagram illustrates a specific embodiment of the demagnetizing simulator 250 that generates the demagnetizing signal Sdmg according to the present invention. In one embodiment, the demagnetizing simulator 250 includes a timing generator 205, a comparator 280, and logic circuitry 285.

[0174] In one embodiment, the timing generator 205 includes an integrator consisting of a switch 231 and a capacitor 230. The switch 231 is controlled by a sampling signal SMP, which is correlated with a drive signal SH to sample the current sensing signal VCS. A discharge current ID, correlated with n*VO, is used to discharge the voltage VC across the capacitor 230. The voltage VC is compared with a reference voltage Vref by a comparator 280. Logic circuit 285 generates a demagnetizing signal Sdmg based on the comparator output CPO and the sampling signal SMP correlated with the drive signal SH. In one embodiment, the reference voltage Vref is 0 volts, and the current sensing voltage VCS is 0 when the primary-side switching current IP is 0.

[0175] In one embodiment, the duration of the demagnetizing signal Sdmg is related to the voltage level (Vinx) of the input voltage of transformer 10, i.e., as... Figure 3 As shown, the voltage at the coupling node NNP of the primary winding NP and the resonant capacitor 20, and the duration of the demagnetizing signal Sdmg, are also related to the voltage level of the output voltage of the transformer 10 (e.g., n*VO) and the excitation period (TW) of the transformer 10 when the first transistor 30 is turned on. It should be noted that the voltage level Vinx of the input voltage of the transformer 10 is equal to the input voltage VIN minus the trans-voltage Vcr of the resonant capacitor 20.

[0176] Since the magnetic flux demagnetized by transformer 10 is equal to the magnetic flux energized by transformer 10, the following equation 1 can be derived:

[0177] Vinx*TW=n*VO*TDS (Equation 1)

[0178] Where TW is the occurrence time of the input voltage level Vinx of transformer 10 during the excitation period of transformer 10; n*VO is the voltage of transformer 10 during the demagnetization period TDS of transformer 10. n is the turns ratio of the primary winding NP and the secondary winding NS, and VO is the voltage of the secondary winding NS (i.e., the output voltage).

[0179] After transformer 10 is energized, the level VCSp of the current sensing signal VCS is related to the peak value of the primary side switching current IP at the end of the energizing process, and at... Figure 3 The resistor 60 shown is generated, and it can be represented by the following equation 2:

[0180] VCSp=(Vinx / L)*TW*Rs (Equation 2)

[0181] Where L is the inductance of the primary winding NP of transformer 10, Rs is the resistance value of resistor 60, and VCSp is the voltage level of transformer 10 at the end of the excitation process.

[0182] Let ID = n*VO / Rt, where Rt is the resistance value of resistor 55.

[0183] The pulse width TDSX of the demagnetizing signal Sdmg can be expressed as:

[0184] TDSX=(C*VCSp) / ID, where C is the capacitance value of capacitor 230.

[0185] TDSX=(Rt*C*VCSp) / (n*VO)

[0186] TDSX=(Rt*C / (n*VO))*(Rs / L)*Vinx*TW

[0187] Let Rt = L / (Rs*C) (Equation 3)

[0188] TDSX=(Vinx*TW) / (n*VO) (Equation 4)

[0189] When the condition of Equation 3 is met, the conduction period TDSX of the demagnetizing signal Sdmg shown in Equation 4 is equal to the demagnetizing period TDS of transformer 10.

[0190] Please continue reading. Figure 10Switch 231 is turned on to sample the current sensing signal VCS onto capacitor 230. When switch 231 is turned off (i.e., when magnetization ends), the level VCSp of the current sensing signal VCS is held at capacitor 230. Switch 231 is controlled by the sampling signal SMP. When switch 231 is turned off, the demagnetizing signal Sdmg is enabled (e.g., through logic circuit 285). In other words, when the demagnetizing signal Sdmg is enabled, the voltage across capacitor 230 VC is the peak value of the current sensing signal VCS. After switch 231 is turned off, the discharge current ID begins to discharge capacitor 230. When capacitor 230 is fully discharged via the discharge current ID (ID = n*VO / Rt) (VC = 0V), the demagnetizing signal Sdmg is disabled. Figure 10 and Figure 3 The resistor 55 shown is used to set the preset pulse width of the demagnetizing signal Sdmg.

[0191] In one embodiment, during a forced discontinuous conduction mode switching cycle, the pulse width TDSX of the demagnetizing signal Sdmg can be compared by the demagnetizing simulator 250 with the demagnetizing period TDS indicated by the pulse width of the auxiliary signal VAUX. Therefore, the pulse width TDSX of the demagnetizing signal Sdmg can be corrected for use in subsequent discontinuous conduction mode switching cycles. In one embodiment, the demagnetizing simulator 250 is further configured to adjust the resistance value of resistor 255 according to the demagnetizing period TDS detected in the discontinuous conduction mode to correct the pulse period TDSX of the demagnetizing signal Sdmg.

[0192] In other embodiments, besides adjusting the resistance value of resistor 255, the demagnetizing simulator 250 can also correct the pulse period TDSX of the demagnetizing signal Sdmg by adjusting the voltage threshold Vth to determine the end of the demagnetizing signal Sdmg, or adjusting the capacitance value of capacitor 230, or adjusting, for example... Figure 10 The ratio of the current mirror formed by transistors 271 and 272.

[0193] Figure 11 This diagram shows a preferred embodiment of the resonant half-bridge flyback converter of the present invention. The resonant half-bridge flyback converter 900 is similar to... Figure 3 The resonant half-bridge flyback converter 900 includes a first transistor M1, a second transistor M2, and a third transistor M3, which together form a half-bridge circuit. From one perspective, the first transistor M1 and the third transistor M3 are configured as the lower-bridge transistors of the resonant half-bridge flyback converter 900, and the second transistor M2 is configured as the upper-bridge transistor of the resonant half-bridge flyback converter 900.

[0194] Based on the feedback signal VFB and the input voltage VIN, the primary-side controller 201 generates a first drive signal S1, a second drive signal S2, and a third drive signal S3. These three signals are coupled to switch the transformer 10 via a half-bridge circuit, thereby generating an output voltage VO on the secondary side of the transformer 10. The second drive signal S2 drives the second transistor M2 to excite the transformer 10. The third drive signal S3 turns on the third transistor M3 during the demagnetization and resonant periods of the transformer 10. The third drive signal S3 also turns on the third transistor M3 to generate a circulating current flowing through the transformer 10 and achieves zero-voltage switching of the second transistor M2 under heavy load conditions. In other words, the second transistor M2 is the primary-side upper bridge switch of the resonant half-bridge flyback converter 900 and can correspond to... Figure 3 The first transistor 30 and the third transistor M3 are the primary side lower bridge switches of the resonant half-bridge flyback converter 900 and can correspond to Figure 3 The second transistor 40. In one viewpoint, the first transistor M1 is used to connect in parallel with the third transistor M3 and as an auxiliary primary side lower bridge switch, having an independent control signal S1.

[0195] In one embodiment, under light load conditions and operating in discontinuous conduction mode, after the transformer 10 is magnetized by turning on the second transistor M2, the third transistor M3 is controlled to be turned on during the demagnetization and resonance period of the transformer 10. After demagnetization, when the third transistor M3 remains off, the first drive signal S1 is used to turn on the first transistor M1 to generate a circulating current flowing through the transformer 10, thereby achieving zero-voltage switching of the second transistor M2. Therefore, the third transistor M3 can avoid switching twice in one switching cycle of the discontinuous conduction mode.

[0196] Since the first transistor M1 is only used to generate circulating current to achieve zero-voltage switching, in one embodiment, the actual size (e.g., aspect ratio) of the first transistor M1 can be configured to be much smaller than the actual size of the third transistor M3. Therefore, the driving capability and parasitic capacitance (e.g., gate capacitance) of the first transistor M1 are lower than those of the third transistor M3, and the switching loss of the first transistor M1 is also lower than that of the third transistor M3.

[0197] For example, the gate switching loss Pg of a transistor can be expressed as:

[0198] Pg = 0.5 * Ciss * Vg * Vg * Freq

[0199] Where Ciss is the input capacitance of the transistor, Vg is the voltage level of the gate drive signal, and Freq is the switching frequency of the gate drive signal.

[0200] As shown in the switching power loss equation above, the smaller-sized first transistor M1 is used exclusively for zero-voltage switching of the second transistor M2 in discontinuous conduction mode. Therefore, the gate switching loss of the first transistor M1 is lower than that of the larger-sized third transistor M3.

[0201] Furthermore, in one embodiment, the amplitude of the voltage level (i.e., Vg) of the first drive signal S1 is lower than the amplitude of the voltage level of the third drive signal S3, thus reducing the switching loss of the first transistor M1. In another embodiment, the maximum gate rating (e.g., gate-source voltage) of the first transistor M1 is also lower than the maximum gate rating of the third transistor M3.

[0202] Resistor 60 generates a current sensing signal VCS by detecting the primary-side switching current IP of transformer 10. Primary-side controller 201 generates a first drive signal S1 based on the input voltage VIN, and a third drive signal S3 based on the input voltage VIN and / or the output voltage VO. Primary-side controller 201 also generates a second drive signal S2 based on the feedback signal VFB.

[0203] Figure 12This diagram shows an operating waveform of a preferred embodiment of the primary-side controller 201 of the present invention operating in discontinuous conduction mode. In discontinuous conduction mode operation, the primary-side controller 201 operates during a first switching cycle Tcyc1 and controls a first drive signal S1 to turn on the first transistor M1 during a first time period TA, thereby generating a circulating current to achieve zero-voltage switching when the second transistor M2 is turned on. After the first time period TA, the first drive signal S1, the second drive signal S2, and the third drive signal S3 are used to turn off the first transistor M1, the second transistor M2, and the third transistor M3 during a first non-conducting time period Td1 (i.e., a hysteresis period). In one embodiment, the first non-conducting time period Td1 is related to a quasi-resonant time period used to achieve zero-voltage switching of the second transistor M2. After the first non-conducting time period Td1, the second drive signal S2 turns on the second transistor M2 during a second time period TB, and the conduction of the second transistor M2 is achieved through the magnetizing transformer 10. After the second time period TB, the first drive signal S1, the second drive signal S2, and the third drive signal S3 are used to turn off the first transistor M1, the second transistor M2, and the third transistor M3 during the idling period (i.e., the idle period). In one embodiment, the second non-conducting period Td2 is related to another quasi-resonant period used to achieve zero-voltage switching of the third transistor M3. After the second non-conducting period Td2, the third drive signal S3 turns on the third transistor M3 during the third time period TC, and the third transistor M3 is turned on during the demagnetizing period of the transformer 10. After the third time period TC, the first drive signal S1, the second drive signal S2, and the third drive signal S3 are used to turn off the first transistor M1, the second transistor M2, and the third transistor M3 during the third non-conducting period TZ, wherein the excitation current IM remains zero during the third non-conducting period TZ (i.e., discontinuous conduction mode). After the third non-conducting period TZ, another switching cycle Tcyc2 begins.

[0204] Figure 13 This diagram shows a preferred embodiment of the primary-side controller of the present invention. In one embodiment, the primary-side controller 213 includes a timer 22 and a control element 243. The control element 243 is used to generate a first drive signal S1, a second drive signal S2, and a third drive signal S3 based on the input voltage VIN (via VAUX) and the feedback signal VFB.

[0205] Timer 22 is used to generate a third non-conducting period TZ, which begins at the end of the third drive signal S3 pulse (e.g., at the falling edge). In one embodiment, the third non-conducting period TZ increases as the output power of the resonant half-bridge flyback converter decreases. Therefore, the switching frequency of the resonant half-bridge flyback converter also decreases as the output power of the resonant half-bridge flyback converter decreases, thereby improving performance in light-load operation.

[0206] The present invention has been described above with reference to preferred embodiments. However, the above description is only intended to facilitate understanding of the invention by those skilled in the art and is not intended to limit the scope of the invention. The described embodiments are not limited to individual application and can also be used in combination. For example, two or more embodiments can be used in combination, and some components of one embodiment can be used to replace corresponding components in another embodiment. Furthermore, within the same spirit of the invention, those skilled in the art can conceive of various equivalent changes and combinations. For example, the phrase "processing or calculating based on a signal or generating an output result" in the present invention is not limited to the signal itself, but also includes, when necessary, performing voltage-to-current conversion, current-to-voltage conversion, and / or proportional conversion on the signal, and then processing or calculating based on the converted signal to generate an output result. Therefore, within the same spirit of the invention, those skilled in the art can conceive of various equivalent changes and combinations, and there are many ways to combine them, which will not be listed here. Therefore, the scope of the present invention should cover the above and all other equivalent changes.

Claims

1. A resonant half-bridge flyback converter, comprising: a first transistor and a second transistor to form a half-bridge circuit; and a transformer and a resonance capacitor, which are connected in series with each other and coupled to the half-bridge circuit; a switching control circuit to generate a first drive signal and a second drive signal to control the first transistor and the second transistor, respectively, to switch the transformer to generate an output voltage; wherein the first drive signal is to magnetize the transformer; wherein between two consecutive pulses of the first drive signal, the second drive signal includes at most one pulse, wherein the at most one pulse of the second drive signal includes a resonant pulse to operate a resonant period after the transformer is magnetized or a zero voltage switching pulse to achieve zero voltage switching of the first transistor; wherein the switching control circuit includes a timer to generate an omitted period when an output power is below a preset threshold, wherein the output power corresponds to the output voltage; wherein a resonant pulse of the second drive signal is omitted in the omitted period; wherein the omitted period increases as the output power decreases. The second drive signal does not include a second pulse between two consecutive pulses of the first drive signal, and thus does not achieve zero voltage switching of the first transistor with the second pulse.

2. The resonant half bridge flyback converter of claim 1, wherein, In the omitted period, both the first drive signal and the second drive signal include zero pulse.

3. The resonant half bridge flyback converter of claim 1, wherein, A duration of the resonant pulse of the second drive signal is equal to or longer than a demagnetization period of the transformer.

4. The resonant half bridge flyback converter of claim 1, wherein, When the first transistor is turned off in the omitted period, a portion of a demagnetization current of the transformer flows through a body diode of the second transistor.

5. The resonant half bridge flyback converter of claim 1, wherein, The first drive signal includes at most one pulse between two consecutive pulses of the second drive signal.

6. The resonant half bridge flyback converter of claim 1, wherein, A pulse of the first drive signal is generated after each pulse of the second drive signal.

7. The resonant half bridge flyback converter of claim 1, wherein, After the omitted period, the second transistor is turned on by a zero voltage switching pulse to achieve zero voltage switching of the first transistor.

8. The resonant half bridge flyback converter of claim 1 wherein, The omitted period starts at an off point when the first drive signal is turned off when the output power is below the preset threshold.

9. The resonant half bridge flyback converter of claim 1 wherein, The omitted period starts at an off point when the first drive signal is turned off, and when the omitted period ends, the second drive signal generates a zero voltage switching pulse.

10. The resonant half bridge flyback converter of claim 1 wherein, The resonant period further includes an extended zero voltage switching period to achieve zero voltage switching of the first transistor.

11. The resonant half bridge flyback converter of claim 1 wherein, 12. A control method to control a resonant half-bridge flyback converter, wherein the resonant half-bridge flyback converter includes a first transistor and a second transistor to form a half-bridge circuit; and a transformer and a resonant capacitor coupled in series to the half-bridge circuit, the control method comprising: switching the transformer to generate an output voltage in a periodic switching manner by switching the half-bridge circuit; generating an omitted period when an output power is below a preset threshold, wherein the output power corresponds to the output voltage; ​ wherein conduction of the first transistor is used to excite the transformer; and wherein conduction of the second transistor is used to achieve a resonant period or to achieve zero voltage switching of the first transistor; wherein a resonant pulse used to control the second transistor to achieve the resonant period is omitted during the omitted period; and wherein the omitted period increases as the output power decreases.

13. The control method of claim 12, wherein, The duration of the resonant pulse of the second transistor is equal to or longer than a demagnetization period of the transformer.

14. The control method of claim 12, wherein, After the first transistor is turned off during the omitted period, a portion of a demagnetization current of the transformer flows through a body diode of the second transistor.

15. The control method of claim 12, wherein, After the second transistor is turned off, the first transistor is turned on.

16. The control method of claim 12, wherein, After the omitted period, the second transistor is turned on according to a zero voltage switching pulse to achieve zero voltage switching of the first transistor.

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