Image sensor, readout method, and electronic device

Abstract

The application discloses an image sensor, an image reading method and an electronic device, wherein the image sensor comprises a pixel array and a plurality of reading conversion circuits, the reading conversion circuit comprises a comparison circuit connected with an output end of a corresponding column pixel, and is used for comparing an output signal of the column pixel with a ramp signal to output a pulse signal, so as to obtain a first output signal and a second output signal; a selection module is used for selecting the first output signal of the comparison circuit at a first sampling count, and selecting the second output signal of the comparison circuit at a second sampling count; and a counter is used for counting according to the first output signal and the second output signal of the comparison circuit, obtaining a total amount of quantization values of the first sampling count and the second sampling count, and obtaining an actual signal quantization result based on the total amount of quantization values. The application can improve the image reading speed of the image sensor, and has low cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of image technology, and in particular, to an image sensor, an image readout method and an electronic device. BACKGROUND

[0002] An image sensor is an important component of a digital camera, which is a device for converting an optical image into an electrical signal, and is widely used in electronic devices such as digital cameras, mobile terminals, portable electronic devices, etc. The image sensor includes two types of CCD (Charge Coupled Device) image sensors and CMOS (Complementary Metal Oxide Semiconductor) image sensors, and the CMOS image sensor has the advantages of high integration, low power consumption, high speed, low cost, etc., and has been widely used in many products. These products include mobile phones, tablet computers, automobiles, and security monitoring systems, etc.

[0003] At present, the pixel array readout mode of the CMOS image sensor cannot effectively realize correlated double sampling. Generally, the pixel array readout mode of the CMOS image sensor adopts a digital correlated double sampling mode, the first sampling is a quantization of a reset signal by counting down, and the counting result is kept as a starting value for the second sampling, the second sampling is a quantization of a signal by counting up, and through the two opposite direction countings, the digital domain correlated double sampling is realized.

[0004] The above sampling method needs to switch between the down counting and the up counting, so that the image readout of the pixel array is time-consuming and slow, and in addition, an extra holding circuit and a switching circuit need to be added, which is high in cost.

[0005] The foregoing narrative is to provide general background information and does not necessarily constitute the prior art. SUMMARY

[0006] The purpose of the present application is to provide an image sensor, an image readout method and an electronic device, which can improve the image readout speed of the image sensor and is low in cost.

[0007] To achieve the above purpose, the technical solution of the present application is as follows:

[0008] In a first aspect, an embodiment of the present application provides an image sensor, comprising:

[0009] a pixel array comprising a plurality of pixels arranged in rows and columns; and

[0010] a plurality of readout conversion circuits, each of the readout conversion circuits corresponding to at least one column of pixels in the pixel array;

[0011] The readout conversion circuit comprises:

[0012] A comparison circuit is connected to the output end of the corresponding column of pixels, and is configured to compare the output signal of the column of pixels with a ramp signal to output a pulse signal, so as to obtain a first output signal and a second output signal.

[0013] A selection module is connected to the comparison circuit, and is configured to select the first output signal of the comparison circuit at a first sampling count, and select the second output signal of the comparison circuit at a second sampling count.

[0014] A counter is connected to the output end of the selection module, and is configured to count according to the first output signal and the second output signal of the comparison circuit, so as to obtain a total quantization value of the first sampling count and the second sampling count, and obtain an actual signal quantization result based on the total quantization value.

[0015] Optionally, the counter counts in a downward counting manner twice or in an upward counting manner twice according to the first output signal and the second output signal of the comparison circuit, so as to obtain the total quantization value.

[0016] Optionally, the comparison circuit comprises a comparator, a first capacitor and a second capacitor, a first input end of the comparator is connected to the output end of the pixel through the first capacitor, and a second input end of the comparator receives the ramp signal through the second capacitor; and / or, the comparison circuit has a first output end and a second output end, the first output end is configured to output the first output signal, the second output end is configured to output the second output signal, and a first output end and a second output end of the comparator are connected to the input end of the selection module.

[0017] Optionally, the selection module comprises a first control element and a second control element, and the first control element and the second control element control by outputting a selection control signal, wherein when the output selection control signal is at a first level, the first control element is configured to select the first output signal of the comparison circuit; and when the output selection control signal is at a second level, the second control element is configured to select the second output signal of the comparison circuit.

[0018] Optionally, the delay of the path selected based on the first control element is the same as the delay of the path selected based on the second control element.

[0019] Optionally, the selection module is further controlled based on a count enable control signal, and a high level time period of the count enable control signal corresponds to at least a time period in which the first output signal and the second output signal are output respectively.

[0020] Optionally, the selection module comprises a selector and an AND gate circuit connected in sequence, the selector receives the first output signal and the second output signal and forms a first selection module output signal; the AND gate circuit receives the first selection module output signal and the count enable control signal to obtain a second selection module output signal, which is the output signal of the selection module.

[0021] Optionally, one input terminal of the counter is connected to an output terminal of the selection module, and the other input terminal receives a clock signal; the counter comprises an N-bit counter.

[0022] Optionally, the image sensor further comprises a storage circuit, and the signal output by the counter is input to the storage circuit for storage.

[0023] Optionally, the first sampling count corresponds to a reset signal quantization result, the second sampling count corresponds to an image signal quantization result, and the actual signal quantization result is composed of a difference between the image signal quantization result and the reset signal quantization result.

[0024] Optionally, the first sampling count is performed in a first time period, the second sampling count is performed in a second time period, and a preset quantization result in a preset time period is defined, wherein the actual reset signal quantization result is equal to the preset quantization result minus the first time period quantization result, and the actual signal quantization result is obtained based on the preset quantization result and the total quantization value.

[0025] Optionally, when the selection module output is at a first level during the first sampling count, the counter starts to count down or up, and the count value is codex; when the selection module output is at the first level during the second sampling count, the counter continues to count down or up based on the first count, and the count value is code_total=codex+codey; wherein the preset time period is TA, the preset quantization result is code_TA, the reset signal quantization result is code_rst=code_TA-codex, and the actual signal quantization result is code_sig=code_total-code_TA.

[0026] In a second aspect, an embodiment of the present application provides an electronic device comprising the image sensor according to any one of the above-mentioned solutions.

[0027] Thirdly, embodiments of this application provide an image readout method for an image sensor, wherein the readout method can be implemented based on any of the image sensors described in the above-mentioned schemes, and of course, other sensors can also be used. The readout method includes:

[0028] The output row is selected based on the row selection line, and the output signal of the column pixel is output to the comparator circuit based on the column selection line;

[0029] The comparator circuit compares the output signal of the column pixel with the ramp signal and outputs a pulse signal to obtain the first output signal and the second output signal;

[0030] During the first sampling count, the selection module selects the first output signal of the comparator circuit, and during the second sampling count, it selects the second output signal of the comparator circuit.

[0031] The counter counts based on the first and second output signals of the comparison circuit to obtain the total quantized value of the first sampling count and the second sampling count, and then obtains the actual signal quantization result based on the total quantized value.

[0032] The beneficial effects of the technical solutions provided in this application are:

[0033] The image sensor, image readout method, and electronic device provided in this application embodiment compare column pixel data with a ramp signal using a comparison circuit to output a pulse signal. During the first sampling count, a selection module selects the first output signal of the comparison circuit, and during the second sampling count, it selects the second output signal of the comparison circuit. A counter counts based on the first and second output signals of the comparison circuit to obtain the total quantized value of the first and second sampling counts. The actual signal quantization result is obtained based on the total quantized value. Thus, only two unidirectional samples are needed to obtain the quantized value of the actual image signal, and no additional holding and switching circuits are required. This improves the image readout speed of the image sensor and is cost-effective. Attached Figure Description

[0034] Figure 1 This is a structural block diagram of an image sensor provided in an embodiment of this application;

[0035] Figure 2 for Figure 1 Block diagram of the readout conversion circuit;

[0036] Figure 3 This is a timing diagram for image sensor control when using downward counting;

[0037] Figure 4 The diagram shows a counter structure.

[0038] Figure 5 This is a schematic flowchart of an image readout method for an image sensor provided in an embodiment of this application. Detailed Implementation

[0039] The technical solution of this application will be further described in detail below with reference to the accompanying drawings and specific embodiments. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this application's specification is for the purpose of describing particular embodiments only and is not intended to limit this application.

[0040] Figure 1 This is a structural block diagram of an image sensor provided in an embodiment of this application. Figure 2 for Figure 1 Block diagram of the readout conversion circuit. Figure 3 This is a timing diagram for image sensor control when using down-counting. Figure 4 The diagram shown is a schematic of a counter structure. Please refer to it. Figures 1 to 4 The image sensor in this embodiment includes a pixel array 110. The pixel array 110 includes a plurality of pixels arranged in rows and columns. Each column of pixels in the pixel array 110 is connected by a column select line, and each row of pixels is connected by a row select line. Each pixel has a row address and a column address. The row address of a pixel corresponds to a row select line driven by a row decoding and driving circuit 120, and the column address of a pixel corresponds to a column select line driven by a column decoding and driving circuit 130. A control circuit 140 controls the row decoding and driving circuit 120 and the column decoding and driving circuit 130 to selectively read out the output signals of pixels corresponding to appropriate rows and columns in the pixel array.

[0041] The pixel's output signals include a pixel reset signal and a pixel image signal. The pixel reset signal represents the signal obtained by the floating diffusion region of the photosensitive device (such as a photodiode) during reset. The pixel image signal represents the signal obtained after the charge representing the image acquired by the photosensitive device is transferred to the floating diffusion region. Both the pixel reset signal and the pixel image signal are read and processed by multiple readout conversion circuits 150 to output a digitized image signal to obtain the required actual signal.

[0042] like Figure 2 The diagram shows a block diagram of a readout conversion circuit, where each readout conversion circuit corresponds to at least one column of pixels in the pixel array. The readout conversion circuit includes: a comparison circuit 202, a selection module 203, and a counter 204. Figure 2The example only shows the column output line of a pixel array. In one example, the outputs of all pixels in that column of the pixel array are connected to column output line 210. Of course, the pixels in that column may also include clamping pixels that are not connected to the column output line.

[0043] Comparator circuit 202, selection module 203, and counter 204 jointly complete the conversion from analog to digital signal. Comparator circuit 202, connected to the output terminal of the corresponding column pixel, compares the column pixel's output signal with a ramp signal to output a pulse signal; the width of the pulse signal represents the signal strength. The comparison circuit can obtain at least two output signals: a first output signal and a second output signal. Optionally, the first output signal and the second output signal are output by the comparison circuit having a first output terminal cmp_out_b and a second output terminal cmp_out, respectively.

[0044] Specifically, in one example, the comparison circuit 202 includes a comparator, a first capacitor C1, and a second capacitor C2. The first input terminal of the comparator is connected to the output terminal of the pixel through the first capacitor C1, and the second input terminal of the comparator is connected to the ramp generator 206 through the second capacitor C2 to receive a ramp signal. The first output terminal cmp_out_b and the second output terminal cmp_out of the comparator are connected to the input terminal of the selection module 203. It should also be noted that the comparison circuit can be implemented using any comparator in the prior art that can achieve the above functions.

[0045] In one embodiment, the image sensor may further include a ramp generator 120, which is connected to the input of a comparator circuit and outputs a ramp signal to the comparator circuit to reset the comparator. The ramp generator may be an existing ramp generator used in pixel readout of an image sensor to generate pulse waves corresponding to the reset signal and the image signal, thereby obtaining the image signal actually required for correlated double sampling.

[0046] In one embodiment, the output terminal cmp_out_o of the selection module 203 is connected to one input terminal of the counter 204. The counter 204 can be an N-bit counter, and its other input terminal receives the clock signal count_clk_o. The counter 204 is used to perform counting operations on the signal output by the selection module 203 to obtain the actual image signal. In one example, the structure of the counter can be found in [reference needed]. Figure 4 As shown.

[0047] In one embodiment, the selection module 203 is connected to the comparator circuit and is used to select the first output signal of the comparator circuit during the first sampling count, such as the signal output from the first output terminal of the comparator circuit; during the second sampling count, the selection module selects the second output signal of the comparator circuit, such as the signal output from the second output terminal of the comparator circuit; the counter is connected to the output terminal of the selection module and is used to count based on the signals output from the first and second output terminals of the comparator circuit to obtain the total quantized value of the first sampling count and the second sampling count, so as to obtain the actual signal quantization result based on the total quantized value. It should be noted that the selection module can be implemented using any circuit in the prior art that can achieve the above functions.

[0048] In one embodiment, the counter counts the signals output from the first and second output terminals of the comparator circuit using either a two-down or two-up counting method to obtain the total quantized value. That is, during the first sampling count, the counter counts downwards, for example, starting at the rising edge of the clock. Then, during the second sampling count, the counter continues counting downwards based on the first count. Similarly, it can also count upwards twice.

[0049] In one embodiment, the selection module 203 includes a first control element (not shown in the figure) and a second control element (not shown in the figure), both of which output a selection control signal count_out_sel (e.g., ...). Figure 2 As shown in the diagram, in an optional example, the first control element and the second control element can be two switches. Specifically, when the output selection control signal is at a first level (e.g., low level), the signal output from the first output terminal cmp_out_b of the comparator circuit (i.e., the first output signal) is selected based on the first control element; when the output selection control signal is at a second level (e.g., high level), the signal output from the second output terminal cmp_out of the comparator circuit (i.e., the second output signal) is selected based on the second control element.

[0050] In one example, the delay of the path selected based on the first control element is the same as the delay of the path selected based on the second control element.

[0051] As an example, the selection module 203 is also controlled based on the count enable control signal count_en_o, and the high-level time period controlled by the count enable control signal corresponds to at least the time periods of the output of the first output signal and the second output signal, respectively.

[0052] In one example, such asFigure 2 As shown, the selection module includes a selector MUX and an AND gate circuit connected to each other. The selector receives the first output signal and the second output signal and forms a first selection module output signal. The AND gate circuit receives the first selection module output signal and the count enable control signal count_en_o to obtain a second selection module output signal. The second selection module output signal serves as the output signal of the selection module.

[0053] In one embodiment, the image sensor may further include a storage circuit 205, which may be a static random access memory (SRAM). A counter 204 is connected to the storage circuit 205, and the signal output by the counter 204 is input to the storage circuit for storage.

[0054] To reduce differences between pixels, a dual correlation sampling technique is used for the readout signal. In a single imaging operation, the pixel's reset signal and the pixel's image signal are sampled twice. An N-bit counter utilizes bidirectional sampling for dual correlation sampling. Digital correlation dual sampling involves quantizing the reset signal and the actual signal separately and then subtracting them in the digital domain. This maximizes the cancellation of noise and mismatch in the pixel array and readout circuit, effectively eliminating system noise.

[0055] In one embodiment, the first sampling count corresponds to the reset signal quantization result, the second sampling count corresponds to the image signal quantization result, and the actual signal quantization result obtained based on the total quantization value is composed of the difference between the image signal quantization result and the reset signal quantization result.

[0056] In one embodiment, the first sampling count is performed in a first time period, and the second sampling count is performed in a second time period. A preset quantization result is defined within a preset time period, wherein the preset time period is equal to the sum of the reset signal counting time period and the first time period. That is, the quantization result of the actual reset signal is equal to the preset quantization result minus the quantization result of the first time period, so as to obtain the actual signal quantization result based on the preset quantization result and the total number of quantized values. It should be noted that in this invention, the actual reset signal is not directly quantized, but is calculated based on the quantization result of the first time period to obtain the actual signal quantization result.

[0057] In a further example, the selection module is also controlled based on the count enable control signal count_en_o. The working period of the counter controlled by the count enable control signal covers the preset time period; that is, the high-level time period controlled by the count enable control signal covers the preset time period. During the control process of the count enable control signal count_en_o, its timing may include multiple high-level time periods.

[0058] In one embodiment, the selection module is used to select the path between the first output terminal of the comparator and the output terminal of the selection module during the first sampling count. When the output of the selection module is at a first level (e.g., high level), the counter starts counting downwards or upwards, with a count value of codex, which corresponds to a first time period. During the second sampling count, the selection module is used to select the path between the second output terminal of the comparator and the output terminal of the selection module. When the output of the selection module is at a first level (e.g., high level), the counter continues counting downwards or upwards based on the first count, with a count value of code_total = codex + codey, which corresponds to a second time period. The preset time period is TA, corresponding to the preset quantization result code_TA. The quantization result of the reset signal is obtained as code_rst = code_TA - codex, and the quantization result of the actual signal is code_sig = codey - code_rst = codey - (code_TA - codex) = codey + codex - code_TA = code_total - code_TA.

[0059] Specifically, the first sampling count yields the quantized result of the reset signal. During the first sampling count, selection module 203 activates the path between the first output terminal cmp_out_b of the comparator and the output terminal cmp_out_o of selection module 203. When the first output terminal cmp_out_b of the comparator outputs a first level (e.g., a high level) (at which point the selection module output is also at a first level), the counter can count downwards or upwards, for example, starting from 0 (i.e., the counter count gradually decreases or gradually increases), with a count value of codex. Furthermore, for the reference quantity TA, the corresponding total value is code_TA (i.e., code_TA is the corresponding preset quantization result), where TA is a preset time period. Therefore, the quantized result of the reset signal is code_rst = code_TA - codex.

[0060] The second sampling count yields the quantization result of the image signal. During the second sampling count, selection module 203 activates the path between the second output terminal cmp_out of the comparator and the output terminal cmp_out_o of selection module 203. When the second output terminal cmp_out of the comparator is at a first level (e.g., high level) (at which point the selection module output is also at a first level), the counter continues counting downwards or upwards based on the first count, with a count value of code_total. In reality, since the counting is based on the previous count, code_total is actually equal to codex + codey, where codey is the actual count value of the second sampling count. The quantization result of the actual output image signal is code_sig = codey - code_rst = codey - (code_TA - codex) = codey + codex - code_TA = code_total - code_TA. In other words, the quantization result of the actual output image signal is code_sig = code_total - code_TA (i.e., the difference between the count value of the second sampling count and the total value of the first sampling count). In this way, both counts are performed using a down or up counting method, eliminating the need for additional holding and switching circuits, thus improving image readout speed and reducing costs.

[0061] Figure 3 It is an image sensor control timing diagram using downward counting, such as Figure 3 As shown, it is suitable for application to Figure 2 In the readout conversion circuit, bitline represents the pixel output signal, vramp represents the ramp generator output signal, cmp_out_o_ represents the selection module output signal, count_clk_o represents the clock signal, count_en_o represents the count enable control signal, and comp_out_sel represents the output selection control signal.

[0062] In one example, the starting point of the codex stage is the intersection of the ramp generator's output signal (vramp) and the pixel's output signal (bitline), corresponding to the time period when the ramp signal is less than the pixel's output signal. In another example, the selected first time period has a certain time extension at the end compared to the aforementioned time period, such as... Figure 3 As shown. Additionally, the second time period corresponding to the second sampling count corresponds to the time period during which the ramp signal is greater than the pixel output when the image signal is output. In one example, the selected second time period has a certain time extension T before the sampling begins, as shown below. Figure 3As shown. Furthermore, the preset time period TA can be the time period during which the ramp signal is greater than the pixel output when the reset signal is output, and further extended to include the first time period. In one example, the selected preset time period has a certain time extension T before the sampling begins relative to the aforementioned time period, such as... Figure 3 As shown.

[0063] This application uses a readout conversion circuit to process the image signal effectively, thereby obtaining the quantized value of the actual output image signal. Specifically, the comparator compares the output signal of the pixels in the pixel array with the ramp signal of the ramp signal generator, and outputs a pulse signal. The width of the pulse signal represents the signal strength. The pulse signal is sampled and counted twice, either downwards or upwards, by a counter. The quantized result of the actual output image signal is the difference between the quantized image signal result and the quantized result of the reset signal.

[0064] Based on the same concept as the foregoing embodiments, this application provides an electronic device that includes the image sensor described in the above embodiments. The electronic device can be, for example, a camera, a mobile phone, a personal digital assistant, a computer, a monitoring device, a machine vision device, etc.

[0065] In summary, the image sensor and electronic device provided in this application compare column pixel data with a ramp signal using a comparison circuit to output a pulse signal. During the first sampling count, a selection module selects the signal output from the first output terminal of the comparison circuit, and during the second sampling count, it selects the signal output from the second output terminal of the comparison circuit. A counter counts based on the signals output from the first and second output terminals of the comparison circuit to obtain the total quantized value of the first and second sampling counts. Based on this total quantized value, the actual signal quantization result is obtained. Thus, only two samplings are needed to obtain the quantized value of the actual image signal, and no additional holding or switching circuits are required. This improves the image readout speed of the image sensor and is cost-effective.

[0066] The following are method embodiments of this application. For details not described in detail in the method embodiments, please refer to the corresponding device embodiments described above.

[0067] Figure 5 This is a schematic flowchart illustrating an image readout method for an image sensor provided in an embodiment of this application. The image readout method is implemented based on the image sensor provided by this invention. That is, before executing the first step of the method, it further includes providing an image sensor as described in any of the above solutions; then, each step in the method is executed based on the structure of the image sensor response. Of course, the readout method provided by this invention can also be implemented using other sensors. Please refer to... Figure 5The image readout method for this image sensor is applied to image sensors and electronic devices. In this embodiment, the image readout method for the image sensor includes the following steps:

[0068] Step S401: Select the output row based on the row selection line, and output the output signal of the column pixel to the comparator circuit based on the column selection line.

[0069] In step S403, the comparison circuit compares the output signal of the column pixel with the ramp signal and outputs a pulse signal to obtain the first output signal and the second output signal.

[0070] In step S405, during the first sampling count, the selection module selects the first output signal of the comparator circuit, and during the second sampling count, it selects the second output signal of the comparator circuit.

[0071] Step S407: The counter counts according to the first output signal and the second output signal of the comparison circuit to obtain the total quantized value of the first sampling count and the second sampling count, so as to obtain the actual signal quantization result based on the total quantized value.

[0072] Specifically, in step S407, the counter counts based on the signal output from the first output terminal and the signal output from the second output terminal of the comparison circuit to obtain the total quantized value of the first sampling count and the second sampling count. This can be further refined into the following steps: the counter counts based on the signal output from the first output terminal and the signal output from the second output terminal of the comparison circuit using a counting method of two downwards or two upwards to obtain the total quantized value.

[0073] Specifically, step S407 can be further refined into the following steps:

[0074] The counter counts the signals output from the first and second output terminals of the comparator circuit using a double-down or double-up counting method to obtain the total quantized value; or

[0075] The first sampling count is performed in a first time period, and the second sampling count is performed in a second time period. A preset quantization result is defined within a preset time period, wherein the preset time period is equal to the sum of the reset signal counting time period and the first time period. The actual signal quantization result is obtained based on the preset quantization result and the total number of quantization values; or

[0076] During the first sampling count, the selection module selects the path between the first output of the comparator and the output of the selection module. When the output of the selection module is at the first level, the counter starts counting downwards or upwards, with a count value of codex. During the second sampling count, when the output of the selection module is at the first level, the counter continues to count downwards or upwards based on the first count, with a count value of code_total = codex + codey. The preset time period is TA, corresponding to the preset quantization result code_TA. The quantization result of the reset signal is code_rst = code_TA - codex, and the quantization result of the actual signal is code_sig = code_total - code_TA.

[0077] In summary, the image readout method for an image sensor provided in this application compares column pixel data with a ramp signal using a comparison circuit to output a pulse signal. During the first sampling count, a selection module selects the signal output from the first output terminal of the comparison circuit, and during the second sampling count, it selects the signal output from the second output terminal of the comparison circuit. A counter counts based on the signals output from the first and second output terminals of the comparison circuit to obtain the total quantized value of the first and second sampling counts. The actual signal quantization result is then obtained based on the total quantized value. Thus, only two samplings are required to obtain the quantized value of the actual image signal, and no additional holding or switching circuits are needed. This improves the image readout speed of the image sensor and is cost-effective.

[0078] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0079] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0080] It should be understood that although the terms first, second, third, etc., may be used herein to describe various information, such information should not be limited to these terms. These terms are used only to distinguish information of the same type from one another. For example, without departing from the scope of this document, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if," as used herein, can be interpreted as "when," "when," or "in response to determination." Furthermore, as used herein, the singular forms "a," "an," and "the" are intended to also include the plural forms unless the context indicates otherwise. It should be further understood that the terms "comprising," "including," indicate the presence of the stated feature, step, operation, element, component, item, kind, and / or group, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" as used herein are to be interpreted as inclusive, or mean any one or any combination thereof. Therefore, "A, B, or C" or "A, B, and / or C" means "any one of the following: A; B; C; A and B; A and C; B and C; A, B, and C". Exceptions to this definition will only occur if the combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.

[0081] It should be understood that although the steps in the flowcharts of this application's embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the figures may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be performed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps.

[0082] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An image sensor, characterized in that, include: A pixel array, comprising multiple pixels arranged in rows and columns; And multiple readout conversion circuits, each of the readout conversion circuits corresponding to at least one column of pixels in the pixel array; The readout conversion circuit includes: A comparison circuit, connected to the output terminal of the corresponding column pixel, is used to compare the output signal of the column pixel with the ramp signal to output a pulse signal, so as to obtain a first output signal and a second output signal. The comparison circuit has a first output terminal and a second output terminal. The first output terminal is used to output the first output signal, and the second output terminal is used to output the second output signal. The selection module is connected to the input terminal of the comparison circuit, and the first and second output terminals of the comparison circuit are connected to the input terminal of the selection module. It is used to select the first output signal of the comparison circuit during the first sampling count and to select the second output signal of the comparison circuit during the second sampling count. A counter, connected to the output of the selection module, is used to count based on the first and second output signals of the comparison circuit. The counter counts using a double-down or double-up counting method based on the first and second output signals of the comparison circuit to obtain the total quantization value, and then obtains the actual signal quantization result based on the total quantization value.

2. The image sensor as described in claim 1, characterized in that, The comparison circuit includes a comparator, a first capacitor, and a second capacitor. The first input terminal of the comparator is connected to the output terminal of the pixel through the first capacitor, and the second input terminal of the comparator receives the ramp signal through the second capacitor.

3. The image sensor as described in claim 1, characterized in that, The selection module includes a first control element and a second control element, which are controlled by an output selection control signal. When the output selection control signal is at a first level, the first output signal of the comparator circuit is selected based on the first control element; when the output selection control signal is at a second level, the second output signal of the comparator circuit is selected based on the second control element.

4. The image sensor as described in claim 3, characterized in that, The delay of the path selected based on the first control element is the same as the delay of the path selected based on the second control element.

5. The image sensor as described in claim 1, characterized in that, The selection module is also based on a counting enable control signal, and the high-level time period controlled by the counting enable control signal at least corresponds to the time periods of the output of the first output signal and the second output signal, respectively.

6. The image sensor as described in claim 5, characterized in that, The selection module includes a selector and an AND gate circuit connected together. The selector receives the first output signal and the second output signal and forms a first selection module output signal. The AND gate circuit receives the first selection module output signal and the counting enable control signal to obtain a second selection module output signal, which serves as the output signal of the selection module.

7. The image sensor as claimed in claim 1, characterized in that, One input terminal of the counter is connected to the output terminal of the selection module, and the other input terminal receives a clock signal; the counter includes an N-bit counter.

8. The image sensor as claimed in claim 1, characterized in that, The image sensor also includes a storage circuit, and the signal output by the counter is input to the storage circuit for storage.

9. The image sensor according to any one of claims 1-8, characterized in that, The first sampling count corresponds to the reset signal quantization result, the second sampling count corresponds to the image signal quantization result, and the actual signal quantization result is composed of the difference between the image signal quantization result and the reset signal quantization result.

10. The image sensor as claimed in claim 9, characterized in that, The first sampling count is performed in the first time period, and the second sampling count is performed in the second time period. A preset quantization result is defined within a preset time period. The quantization result of the actual reset signal is equal to the preset quantization result minus the quantization result of the first time period. The actual signal quantization result is obtained based on the preset quantization result and the total number of quantization values.

11. The image sensor as claimed in claim 10, characterized in that, During the first sampling count, when the selection module output is at the first level, the counter starts counting downwards or upwards, and the count value is codex. During the second sampling count, when the selection module output is at the first level, the counter continues to count downwards or upwards based on the first count, and the actual count value of the second sampling count is codey, and the count value is code_total = codex + codey. The preset time period is TA, corresponding to the preset quantization result code_TA, resulting in the reset signal quantization result code_rst = code_TA - codex, and the actual signal quantization result code_sig = code_total - code_TA.

12. An electronic device, characterized in that, Including the image sensor as described in any one of claims 1-11.

13. An image readout method for an image sensor, characterized in that, include: The output row is selected based on the row selection line, and the output signal of the column pixel is output to the comparator circuit based on the column selection line; The comparator circuit compares the output signal of the column pixel with the ramp signal and outputs a pulse signal to obtain a first output signal and a second output signal. The comparator circuit has a first output terminal and a second output terminal. The first output terminal outputs the first output signal and the second output terminal outputs the second output signal. During the first sampling count, the input terminal of the selection module is connected to the first and second output terminals of the comparison circuit, and the selection module selects the first output signal of the comparison circuit. During the second sampling count, the second output signal of the comparison circuit is selected. The counter counts according to the first and second output signals of the comparison circuit using a counting method of two down or two up, to obtain the total quantized value of the first sampling count and the second sampling count, and then obtains the actual signal quantization result based on the total quantized value.

14. The image readout method of the image sensor as described in claim 13, characterized in that, The image readout method is implemented based on the image sensor described in any one of claims 1-11.

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