Memory structure

Abstract

A memory structure includes a substrate and a plurality of memory cells. The plurality of memory cells are stacked on the substrate. Each memory cell includes a first conductor layer, a first gate, a second gate, a second conductor layer, a channel layer, and a first charge storage layer. The first conductor layer, the first gate, the second gate, and the second conductor layer are sequentially stacked. The first conductor layer and the first gate are electrically insulated from each other. The first gate and the second gate are electrically insulated from each other. The second gate and the second conductor layer are electrically insulated from each other. The channel layer is located at a side of the first conductor layer, a side of the first gate, a side of the second gate, and a side of the second conductor layer. The first gate and the second gate are electrically insulated by the channel layer. The first conductor layer and the second conductor layer are electrically connected to the channel layer. The first charge storage layer is located between the first gate and the channel layer.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor structure, and more particularly to a memory structure. BACKGROUND

[0002] Non-volatile memory (e.g., flash memory) has become a widely used memory for personal computers and electronic devices because it can perform multiple data storage, reading and erasing operations, and has the advantages of not losing stored data when power supply is interrupted, short data access time, and low power consumption.

[0003] A three-dimensional NOR type flash memory (3D NOR flash memory) has been developed, which uses a channel hot electron (CHE) injection method for programming operation. However, how to improve the programming efficiency of the three-dimensional NOR type flash memory is the current goal. SUMMARY

[0004] The present application provides a semiconductor structure, which can effectively improve the programming efficiency.

[0005] The present application provides a memory structure, which includes a substrate and a plurality of memory cells. The plurality of memory cells are stacked on the substrate. Each memory cell includes a first conductor layer, a first gate, a second gate, a second conductor layer, a channel layer and a first charge storage layer. The first conductor layer, the first gate, the second gate and the second conductor layer are sequentially stacked. The first conductor layer and the first gate are electrically insulated from each other. The first gate and the second gate are electrically insulated from each other. The second gate and the second conductor layer are electrically insulated from each other. The channel layer is located at one side of the first conductor layer, one side of the first gate, one side of the second gate and one side of the second conductor layer. The first gate and the second gate are electrically insulated from the channel layer. The first conductor layer and the second conductor layer are electrically connected to the channel layer. The first charge storage layer is located between the first gate and the channel layer.

[0006] In an embodiment according to the application, in the memory structure, each memory cell further comprises a first dielectric layer, a second dielectric layer, a third dielectric layer, a fourth dielectric layer, a fifth dielectric layer, and a sixth dielectric layer. The first dielectric layer is between the first charge storage layer and the channel layer and between the first gate and the first conductor layer. The second dielectric layer is between the first gate and the first charge storage layer. The third dielectric layer is between the first conductor layer and the channel layer, between the first dielectric layer and the channel layer, between the second gate and the channel layer, and between the second conductor layer and the channel layer. The fourth dielectric layer is between the first gate and the second gate. The fifth dielectric layer is between the second gate and the second conductor layer. The sixth dielectric layer is between the first dielectric layer and the first conductor layer. The first conductor layer can be electrically connected to the channel layer by dielectric breakdown of the third dielectric layer between the first conductor layer and the channel layer. The second conductor layer can be electrically connected to the channel layer by dielectric breakdown of the third dielectric layer between the second conductor layer and the channel layer.

[0007] In an embodiment according to the application, in the memory structure, the third dielectric layer can be a continuous structure on a side of the first conductor layer, on a side of the first gate, on a side of the second gate, and on a side of the second conductor layer.

[0008] In an embodiment according to the application, in the memory structure, each memory cell further comprises a first dielectric layer, a second dielectric layer, a third dielectric layer, a fourth dielectric layer, a fifth dielectric layer, and a sixth dielectric layer. The first dielectric layer is between the first charge storage layer and the channel layer and between the first gate and the first conductor layer. The second dielectric layer is between the first gate and the first charge storage layer. The third dielectric layer is between the second gate and the channel layer. The fourth dielectric layer is between the first gate and the second gate. The fifth dielectric layer is between the second gate and the second conductor layer. The sixth dielectric layer is between the first dielectric layer and the first conductor layer.

[0009] In an embodiment according to the application, in the memory structure, the first conductor layer can directly contact the channel layer, and the second conductor layer can directly contact the channel layer.

[0010] In an embodiment according to the application, in the memory structure, the third dielectric layer can further be between the second gate and the fourth dielectric layer and between the second gate and the fifth dielectric layer.

[0011] In an embodiment according to the application, in the memory structure, each memory cell further comprises a second charge storage layer. The second charge storage layer is between the second gate and the channel layer.

[0012] According to an embodiment of the present application, in the memory structure, each memory cell further comprises a first dielectric layer, a second dielectric layer, a third dielectric layer, a fourth dielectric layer, a fifth dielectric layer, a sixth dielectric layer, and a seventh dielectric layer. The first dielectric layer is between the first charge storage layer and the channel layer, between the first gate and the first conductor layer, and between the first gate and the second gate. The second dielectric layer is between the first gate and the first charge storage layer. The third dielectric layer is between the second charge storage layer and the channel layer, between the second gate and the second conductor layer, and between the second gate and the first gate. The fourth dielectric layer is between the second gate and the second charge storage layer. The fifth dielectric layer is between the first dielectric layer and the third dielectric layer between the first gate and the second gate. The sixth dielectric layer is between the first dielectric layer and the first conductor layer. The seventh dielectric layer is between the third dielectric layer and the second conductor layer.

[0013] According to an embodiment of the present application, in the memory structure, the first conductor layer directly contacts the channel layer, and the second conductor layer directly contacts the channel layer.

[0014] According to an embodiment of the present application, in the memory structure, two adjacent memory cells share the first conductor layer.

[0015] According to an embodiment of the present application, in the memory structure, the components in the two adjacent memory cells sharing the first conductor layer have a symmetric configuration.

[0016] According to an embodiment of the present application, in the memory structure, two adjacent memory cells share the second conductor layer.

[0017] According to an embodiment of the present application, in the memory structure, the components in the two adjacent memory cells sharing the second conductor layer have a symmetric configuration.

[0018] According to an embodiment of the present application, in the memory structure, the materials of the first conductor layer, the second gate, and the second conductor layer are, for example, doped polysilicon. The material of the first gate is, for example, metal.

[0019] According to an embodiment of the present application, in the memory structure, the materials of the first conductor layer and the second conductor layer are, for example, doped polysilicon. The materials of the first gate and the second gate are, for example, metal.

[0020] According to an embodiment of the present application, in the memory structure, the material of the channel layer is, for example, semiconductor material.

[0021] According to an embodiment of the present application, in the memory structure, the semiconductor material is, for example, polysilicon.

[0022] According to an embodiment of the present application, in the memory structure, the material of the first charge storage layer is, for example, a charge trapping material.

[0023] According to an embodiment of the present application, in the memory structure, the charge trapping material is, for example, silicon nitride.

[0024] According to an embodiment of the present application, in the memory structure, the memory structure can be a three-dimensional NAND or NOR flash memory structure.

[0025] Based on the above, in the memory structure according to the present application, a plurality of memory cells are stacked on a substrate, each memory cell has a first conductor layer, a first gate, a second gate and a second conductor layer stacked in sequence, and a first charge storage layer is located between the first gate and a channel layer. Therefore, the memory structure according to the present application can use a source side injection (SSI) method to perform programming operation on the memory cells, thereby improving programming efficiency. In addition, since the memory cells can have an auxiliary gate, the design of the memory cells is more flexible.

[0026] In order to make the above features and advantages of the present application more apparent, specific embodiments are described below in detail, and are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 A cross-sectional view of a memory structure according to an embodiment of the present application;

[0028] Figure 2 A cross-sectional view of a memory structure according to another embodiment of the present application;

[0029] Figure 3 A cross-sectional view of a memory structure according to another embodiment of the present application.

[0030] SYMBOL DESCRIPTION

[0031] 10, 20, 30: memory structure

[0032] 100, 200, 300: substrate

[0033] 102, 108, 202, 208, 302, 308: conductor layer

[0034] 104, 106, 204, 206, 304, 306: gate

[0035] 110, 210, 310: channel layer

[0036] 112, 212, 312, 314: charge storage layer

[0037] 114, 116, 118, 120, 122, 123, 124, 126, 214, 216, 218, 220, 222, 223, 224, 226, 316, 318, 320, 322, 324, 325, 326, 327, 328: dielectric layer

[0038] MC1, MC2, MC3: memory cell DETAILED DESCRIPTION

[0039] Figure 1 A cross-sectional view of a memory structure according to an embodiment of the present application.

[0040] Reference will now be made to Figure 1 The memory structure 10 includes a substrate 100 and a plurality of memory cells MC1. The memory structure 10 can be a three-dimensional NAND or NOR flash memory structure. The substrate 100 can be a semiconductor substrate, such as a silicon substrate. In addition, depending on product design requirements, desired doped regions (not shown) can be formed in the substrate 100.

[0041] The plurality of memory cells MC1 are stacked on the substrate 100. Each memory cell MC1 includes a conductor layer 102, a gate 104, a gate 106, a conductor layer 108, a channel layer 110, and a charge storage layer 112. The conductor layer 102, the gate 104, the gate 106, and the conductor layer 108 are stacked in order. The conductor layer 102 and the gate 104 are electrically insulated from each other. The gate 104 and the gate 106 are electrically insulated from each other. The gate 106 and the conductor layer 108 are electrically insulated from each other. The materials of the conductor layer 102, the gate 106, and the conductor layer 108 are, for example, doped polysilicon. The material of the gate 104 is, for example, a metal, such as tungsten.

[0042] The channel layer 110 is located at one side of the conductor layer 102, at one side of the gate 104, at one side of the gate 106, and at one side of the conductor layer 108. In some embodiments, the channel layer 110 can have a cross-sectional shape similar to a U shape. The material of the channel layer 110 is, for example, a semiconductor material. In some embodiments, the semiconductor material is, for example, polysilicon. The gate 104 and the gate 106 are electrically insulated from the channel layer 110. The conductor layer 102 and the conductor layer 108 are electrically connected to the channel layer 110.

[0043] The charge storage layer 112 is located between the gate 104 and the channel layer 110. The charge storage layer 112 can also be located between the gate 104 and the conductor layer 102 and between the gate 104 and the gate 106. The charge storage layer 112 can be used to store electric charges. In some embodiments, the charge storage layer 112 can have an insulating effect. In some embodiments, the charge storage layer 112 can have a cross-sectional shape similar to a U shape. The material of the charge storage layer 112 is, for example, a charge-trapping material. In some embodiments, the charge-trapping material is, for example, silicon nitride.

[0044] In addition, each memory cell MC1 can further include a dielectric layer 114, a dielectric layer 116, a dielectric layer 118, a dielectric layer 120, a dielectric layer 122, and a dielectric layer 123. The dielectric layer 114 is located between the charge storage layer 112 and the channel layer 110, and between the gate 104 and the conductor layer 102. The dielectric layer 114 can also be located between the gate 104 and the gate 106. The dielectric layer 114 can serve as a tunneling dielectric layer. The dielectric layer 114 can electrically insulate the conductor layer 102 and the gate 104 from each other. The dielectric layer 114 can electrically insulate the gate 104 and the channel layer 110 from each other. The dielectric layer 114 can electrically insulate the gate 104 and the gate 106 from each other. In some embodiments, the dielectric layer 114 can have a U-shaped cross-sectional shape. The material of the dielectric layer 114 is, for example, silicon oxide.

[0045] The dielectric layer 116 is located between the gate 104 and the charge storage layer 112. The dielectric layer 116 can serve as a blocking dielectric layer. The dielectric layer 116 can electrically insulate the conductor layer 102 and the gate 104 from each other. The dielectric layer 116 can electrically insulate the gate 104 and the channel layer 110 from each other. The dielectric layer 116 can electrically insulate the gate 104 and the gate 106 from each other. In some embodiments, the dielectric layer 116 can have a U-shaped cross-sectional shape. The material of the dielectric layer 116 is, for example, silicon oxide.

[0046] The dielectric layer 118 is located between the conductor layer 102 and the channel layer 110, between the dielectric layer 114 and the channel layer 110, between the gate 106 and the channel layer 110, and between the conductor layer 108 and the channel layer 110. The dielectric layer 118 can electrically insulate the gate 104 and the channel layer 110 from each other. The dielectric layer 118 can electrically insulate the gate 106 and the channel layer 110 from each other. On the other hand, before operating the memory cell MC1, a large voltage can be applied to the conductor layer 102 and the conductor layer 108, so that the conductor layer 102 can be electrically connected to the channel layer 110 through dielectric breakdown of the dielectric layer 118 located between the conductor layer 102 and the channel layer 110, and the conductor layer 108 can be electrically connected to the channel layer 110 through dielectric breakdown of the dielectric layer 118 located between the conductor layer 108 and the channel layer 110. In addition, the dielectric layer 118 can be a continuous structure located on one side of the conductor layer 102, on one side of the gate 104, on one side of the gate 106, and on one side of the conductor layer 108.

[0047] A dielectric layer 120 is between the gate 104 and the gate 106. For example, the dielectric layer 120 can be between the dielectric layer 114 and the gate 106. The dielectric layer 120 can electrically insulate the gate 104 and the gate 106 from each other. The material of the dielectric layer 120 is, for example, silicon oxide.

[0048] A dielectric layer 122 is between the gate 106 and the conductor layer 108. The dielectric layer 122 can electrically insulate the gate 106 and the conductor layer 108 from each other. The material of the dielectric layer 122 is, for example, silicon oxide.

[0049] A dielectric layer 123 is between the dielectric layer 114 and the conductor layer 102. The dielectric layer 123 can electrically insulate the conductor layer 102 and the gate 104 from each other. The material of the dielectric layer 123 is, for example, silicon oxide.

[0050] In some embodiments, the memory structure 10 can further include at least one of a dielectric layer 124 and a dielectric layer 126. The dielectric layer 124 is on the channel layer 110. The material of the dielectric layer 124 is, for example, silicon oxide. The dielectric layer 126 is between the memory cell MC1 and the substrate 100. The material of the dielectric layer 126 is, for example, silicon oxide.

[0051] In the present embodiment, two adjacent memory cells MC1 can share the conductor layer 102. The components in the two adjacent memory cells MC1 sharing the conductor layer 102 can have a symmetrical configuration relationship. In the present embodiment, two adjacent memory cells MC1 can share the conductor layer 108. The components in the two adjacent memory cells MC1 sharing the conductor layer 108 can have a symmetrical configuration relationship.

[0052] Based on the above embodiments, in the memory structure 10, a plurality of memory cells MC1 are stacked on the substrate 100, each memory cell MC1 has the conductor layer 102, the gate 104, the gate 106 and the conductor layer 108 stacked in sequence, and the charge storage layer 112 is between the gate 104 and the channel layer 110. When the memory cell MC1 is operated, the gate 104 can be used as a control gate, the gate 106 can be used as an auxiliary gate, the conductor layer 102 can be electrically connected to a bit line, and the conductor layer 108 can be electrically connected to a source line. Therefore, the memory cell MC1 can be programmed by using a source side injection method, so that the programming efficiency can be improved. In addition, since the memory cell MC1 can have an auxiliary gate, the design of the memory cell MC1 is more flexible.

[0053] Figure 2 A cross-sectional view of a memory structure according to another embodiment of the present application.

[0054] Please refer to Figure 2The memory structure 20 includes a substrate 200 and a plurality of memory cells MC2. The memory structure 20 can be a three-dimensional NAND or NOR flash memory structure. The substrate 200 can be a semiconductor substrate, such as a silicon substrate. In addition, depending on product design requirements, desired doped regions (not shown) can be formed in the substrate 200.

[0055] The plurality of memory cells MC2 are stacked on the substrate 200. Each memory cell MC2 includes a conductor layer 202, a gate 204, a gate 206, a conductor layer 208, a channel layer 210, and a charge storage layer 212. The conductor layer 202, the gate 204, the gate 206, and the conductor layer 208 are stacked in order. The conductor layer 202 and the gate 204 are electrically insulated from each other. The gate 204 and the gate 206 are electrically insulated from each other. The gate 206 and the conductor layer 208 are electrically insulated from each other. The materials of the conductor layer 202, the gate 206, and the conductor layer 208 are, for example, doped polysilicon. The material of the gate 204 is, for example, a metal, such as tungsten.

[0056] The channel layer 210 is located at one side of the conductor layer 202, one side of the gate 204, one side of the gate 206, and one side of the conductor layer 208. In some embodiments, the channel layer 210 can have a cross-sectional shape similar to a U shape. The material of the channel layer 210 is, for example, a semiconductor material. In some embodiments, the semiconductor material is, for example, polysilicon. The gate 204 and the gate 206 are electrically insulated from the channel layer 210. The conductor layer 202 and the conductor layer 208 are electrically connected to the channel layer 210. In this embodiment, the conductor layer 202 can directly contact the channel layer 210, and the conductor layer 208 can directly contact the channel layer 210.

[0057] The charge storage layer 212 is located between the gate 204 and the channel layer 210. The charge storage layer 212 can also be located between the gate 204 and the conductor layer 202, and between the gate 204 and the gate 206. The charge storage layer 212 can be used to store electric charges. In some embodiments, the charge storage layer 212 can have an insulating effect. In some embodiments, the charge storage layer 212 can have a cross-sectional shape similar to a U shape. The material of the charge storage layer 212 is, for example, a charge-trapping material. In some embodiments, the charge-trapping material is, for example, silicon nitride.

[0058] In addition, each memory cell MC2 can also include a dielectric layer 214, a dielectric layer 216, a dielectric layer 218, a dielectric layer 220, a dielectric layer 222, and a dielectric layer 223. The dielectric layer 214 is between the charge storage layer 212 and the channel layer 210, and between the conductor layer 202 and the gate 204. The dielectric layer 214 can also be between the gate 204 and the gate 206. The dielectric layer 214 can function as a tunneling dielectric layer. The dielectric layer 214 can electrically insulate the conductor layer 202 and the gate 204 from each other. The dielectric layer 214 can electrically insulate the gate 204 and the channel layer 210 from each other. The dielectric layer 214 can electrically insulate the gate 204 and the gate 206 from each other. In some embodiments, the dielectric layer 214 can have a U-shaped cross-sectional shape. The material of the dielectric layer 214 is, for example, silicon oxide.

[0059] The dielectric layer 216 is between the gate 204 and the charge storage layer 212. The dielectric layer 216 can function as a blocking dielectric layer. The dielectric layer 216 can electrically insulate the conductor layer 202 and the gate 204 from each other. The dielectric layer 216 can electrically insulate the gate 204 and the channel layer 210 from each other. The dielectric layer 216 can electrically insulate the gate 204 and the gate 206 from each other. In some embodiments, the dielectric layer 216 can have a U-shaped cross-sectional shape. The material of the dielectric layer 216 is, for example, silicon oxide.

[0060] The dielectric layer 218 is between the gate 206 and the channel layer 210. The dielectric layer 218 can also be between the gate 206 and the dielectric layer 220, and between the gate 206 and the dielectric layer 222. The dielectric layer 218 can electrically insulate the gate 206 and the channel layer 210 from each other. The dielectric layer 218 can electrically insulate the gate 206 and the gate 204 from each other. The dielectric layer 218 can electrically insulate the gate 206 and the conductor layer 208 from each other. In some embodiments, the dielectric layer 218 can have a U-shaped cross-sectional shape. The material of the dielectric layer 218 is, for example, silicon oxide.

[0061] The dielectric layer 220 is between the gate 204 and the gate 206. For example, the dielectric layer 220 can be between the dielectric layer 214 and the dielectric layer 218. The dielectric layer 220 can electrically insulate the gate 204 and the gate 206 from each other. The material of the dielectric layer 220 is, for example, silicon oxide.

[0062] The dielectric layer 222 is between the gate 206 and the conductor layer 208. For example, the dielectric layer 222 can be between the dielectric layer 218 and the conductor layer 208. The dielectric layer 222 can electrically insulate the gate 206 and the conductor layer 208 from each other. The material of the dielectric layer 222 is, for example, silicon oxide.

[0063] The dielectric layer 223 is between the dielectric layer 214 and the conductor layer 202. The dielectric layer 223 can electrically insulate the conductor layer 202 and the gate 204 from each other. The material of the dielectric layer 223 is, for example, silicon oxide.

[0064] In some embodiments, the memory structure 20 can further include at least one of a dielectric layer 224 and a dielectric layer 226. The dielectric layer 224 is located on the channel layer 210. The material of the dielectric layer 224 is, for example, silicon oxide. The dielectric layer 226 is located between the memory cell MC2 and the substrate 200. The material of the dielectric layer 226 is, for example, silicon oxide.

[0065] In the present embodiment, two adjacent memory cells MC2 can share the conductor layer 202. The components in the two adjacent memory cells MC2 sharing the conductor layer 202 can have a symmetric configuration relationship. In the present embodiment, two adjacent memory cells MC2 can share the conductor layer 208. The components in the two adjacent memory cells MC2 sharing the conductor layer 208 can have a symmetric configuration relationship.

[0066] Based on the above embodiments, in the memory structure 20, a plurality of memory cells MC2 are stacked on the substrate 200, each memory cell MC2 has the conductor layer 202, the gate 204, the gate 206 and the conductor layer 208 stacked in sequence, and the charge storage layer 212 is located between the gate 204 and the channel layer 210. When the memory cell MC2 is operated, the gate 204 can be used as a control gate, the gate 206 can be used as an auxiliary gate, the conductor layer 202 can be electrically connected to a bit line, and the conductor layer 208 can be electrically connected to a source line. Therefore, the source side injection method can be used for programming operation of the memory cell MC2, thereby improving the programming efficiency. In addition, since the memory cell MC2 can have an auxiliary gate, the design of the memory cell MC2 is more flexible.

[0067] Figure 3 A cross-sectional view of a memory structure according to another embodiment of the present application.

[0068] Please refer to Figure 3 The memory structure 30 includes a substrate 300 and a plurality of memory cells MC3. The memory structure 30 can be a three-dimensional NAND type flash memory structure. The substrate 300 can be a semiconductor substrate, such as a silicon substrate. In addition, according to product design requirements, the required doped regions (not shown) can be formed in the substrate 300.

[0069] A plurality of memory cells MC3 are disposed in a stack on the substrate 300. Each memory cell MC3 includes a conductor layer 302, a gate 304, a gate 306, a conductor layer 308, a channel layer 310, and a charge storage layer 312. The conductor layer 302, the gate 304, the gate 306, and the conductor layer 308 are disposed in a stack. The conductor layer 302 and the gate 304 are electrically insulated from each other. The gate 304 and the gate 306 are electrically insulated from each other. The gate 306 and the conductor layer 308 are electrically insulated from each other. The materials of the conductor layer 302 and the conductor layer 308 are, for example, doped polysilicon. The materials of the gate 304 and the gate 306 are, for example, metal, such as tungsten.

[0070] The channel layer 310 is disposed on a side of the conductor layer 302, on a side of the gate 304, on a side of the gate 306, and on a side of the conductor layer 308. In some embodiments, the channel layer 310 can have a cross-sectional shape similar to a U-shape. The material of the channel layer 310 is, for example, a semiconductor material. In some embodiments, the semiconductor material is, for example, polysilicon. The gate 304 and the gate 306 are electrically insulated from the channel layer 310. The conductor layer 302 and the conductor layer 308 are electrically connected to the channel layer 310. In this embodiment, the conductor layer 302 can directly contact the channel layer 310, and the conductor layer 308 can directly contact the channel layer 310.

[0071] The charge storage layer 312 is disposed between the gate 304 and the channel layer 310. The charge storage layer 312 can also be disposed between the gate 304 and the conductor layer 302, and between the gate 304 and the gate 306. The charge storage layer 312 can be used to store electric charge. In some embodiments, the charge storage layer 312 can have an insulating effect.

[0072] In some embodiments, the charge storage layer 312 can have a cross-sectional shape similar to a U-shape. The material of the charge storage layer 312 is, for example, a charge-trapping material. In some embodiments, the charge-trapping material is, for example, silicon nitride.

[0073] In addition, each memory cell MC3 can also include a charge storage layer 314. The charge storage layer 314 is disposed between the gate 306 and the channel layer 310. The charge storage layer 314 can also be disposed between the gate 306 and the conductor layer 308, and between the gate 306 and the gate 304. The charge storage layer 314 can be used to store electric charge. In some embodiments, the charge storage layer 314 can have an insulating effect. In some embodiments, the charge storage layer 314 can have a cross-sectional shape similar to a U-shape. The material of the charge storage layer 314 is, for example, a charge-trapping material. In some embodiments, the charge-trapping material is, for example, silicon nitride.

[0074] In addition, each memory cell MC3 can also include a dielectric layer 316, a dielectric layer 318, a dielectric layer 320, a dielectric layer 322, a dielectric layer 324, a dielectric layer 325, and a dielectric layer 327. The dielectric layer 316 is located between the charge storage layer 312 and the channel layer 310, between the conductor layer 302 and the gate 304, and between the gate 304 and the gate 306. The dielectric layer 316 can function as a tunneling dielectric layer. The dielectric layer 316 can electrically insulate the conductor layer 302 and the gate 304 from each other. The dielectric layer 316 can electrically insulate the gate 304 and the channel layer 310 from each other. The dielectric layer 316 can electrically insulate the gate 304 and the gate 306 from each other. In some embodiments, the dielectric layer 316 can have a U-shaped cross-sectional shape. The material of the dielectric layer 316 is, for example, silicon oxide.

[0075] The dielectric layer 318 is located between the gate 304 and the charge storage layer 312. The dielectric layer 318 can function as a blocking dielectric layer. The dielectric layer 318 can electrically insulate the conductor layer 302 and the gate 304 from each other. The dielectric layer 318 can electrically insulate the gate 304 and the channel layer 310 from each other. The dielectric layer 318 can electrically insulate the gate 304 and the gate 306 from each other. In some embodiments, the dielectric layer 318 can have a U-shaped cross-sectional shape. The material of the dielectric layer 318 is, for example, silicon oxide.

[0076] The dielectric layer 320 is located between the charge storage layer 314 and the channel layer 310, between the conductor layer 308 and the gate 306, and between the gate 306 and the gate 304. The dielectric layer 320 can function as a tunneling dielectric layer. The dielectric layer 320 can electrically insulate the gate 306 and the conductor layer 308 from each other. The dielectric layer 320 can electrically insulate the gate 306 and the channel layer 310 from each other. The dielectric layer 320 can electrically insulate the gate 304 and the gate 306 from each other. In some embodiments, the dielectric layer 320 can have a U-shaped cross-sectional shape. The material of the dielectric layer 320 is, for example, silicon oxide.

[0077] The dielectric layer 322 is located between the gate 306 and the charge storage layer 314. The dielectric layer 322 can function as a blocking dielectric layer. The dielectric layer 322 can electrically insulate the gate 306 and the conductor layer 308 from each other. The dielectric layer 322 can electrically insulate the gate 306 and the channel layer 310 from each other. The dielectric layer 322 can electrically insulate the gate 304 and the gate 306 from each other. In some embodiments, the dielectric layer 322 can have a U-shaped cross-sectional shape. The material of the dielectric layer 322 is, for example, silicon oxide.

[0078] The dielectric layer 324 is located between the dielectric layer 316 and the dielectric layer 320 between the gate 304 and the gate 306. The dielectric layer 324 can electrically insulate the gate 304 and the gate 306 from each other. The material of the dielectric layer 324 is, for example, silicon oxide.

[0079] A dielectric layer 325 is located between the dielectric layer 316 and the conductor layer 302. The dielectric layer 325 can electrically insulate the conductor layer 302 and the gate 304 from each other. The material of the dielectric layer 325 is, for example, silicon oxide.

[0080] A dielectric layer 327 is located between the dielectric layer 320 and the conductor layer 308. The dielectric layer 327 can electrically insulate the gate 306 and the conductor layer 308 from each other. The material of the dielectric layer 327 is, for example, silicon oxide.

[0081] In some embodiments, the memory structure 30 can further include at least one of a dielectric layer 326 and a dielectric layer 328. The dielectric layer 326 is located on the channel layer 310. The material of the dielectric layer 326 is, for example, silicon oxide. The dielectric layer 328 is located between the memory cell MC3 and the substrate 300. The material of the dielectric layer 328 is, for example, silicon oxide.

[0082] In the present embodiment, two adjacent memory cells MC3 can share the conductor layer 302. The components in the two adjacent memory cells MC3 sharing the conductor layer 302 can have a symmetrical configuration relationship. In the present embodiment, two adjacent memory cells MC3 can share the conductor layer 308. The components in the two adjacent memory cells MC3 sharing the conductor layer 308 can have a symmetrical configuration relationship.

[0083] Based on the above-described embodiments, in the memory structure 30, a plurality of memory cells MC3 are stacked on the substrate 300, each memory cell MC3 has the conductor layer 302, the gate 304, the gate 306, and the conductor layer 308 stacked in sequence, and the charge storage layer 312 is located between the gate 304 and the channel layer 310. In addition, each memory cell MC3 can further include the charge storage layer 314, and the charge storage layer 314 is located between the gate 306 and the channel layer 310. Since the memory cell MC3 has the charge storage layer 312 and the charge storage layer 314 separated from each other, the memory cell MC3 can include a first bit using the charge storage layer 312 to store charges and a second bit using the charge storage layer 314 to store charges, thereby improving the bit density.

[0084] When operating the first bit in the memory cell MC3, the gate 304 can be used as a control gate, the gate 306 can be used as an auxiliary gate, the conductor layer 302 can be electrically connected to a bit line, and the conductor layer 308 can be electrically connected to a source line. Thus, the first bit in the memory cell MC3 can be programmed by using a source side injection method, thereby improving programming efficiency. In addition, when operating the second bit in the memory cell MC3, the gate 304 can be used as an auxiliary gate, the gate 306 can be used as a control gate, the conductor layer 302 can be electrically connected to a source line, and the conductor layer 308 can be electrically connected to a bit line. Thus, the second bit in the memory cell MC3 can be programmed by using a source side injection method, thereby improving programming efficiency. On the other hand, since the memory cell MC3 can have an auxiliary gate, the design of the memory cell MC3 is more flexible.

[0085] In summary, in the memory structure of the above embodiments, a plurality of memory cells are stacked on a substrate. Since each memory cell has a control gate and an auxiliary gate, the memory cell can be programmed by using a source side injection method, thereby improving programming efficiency.

[0086] Although the present application has been disclosed in connection with the above embodiments, it will be apparent to those skilled in the art that modifications and / or additions can be made without departing from the spirit and scope of the application. Therefore, the scope of the application should be determined by the following claims.

Claims

1. A memory structure, comprising: Base; as well as Multiple storage cells are stacked on the substrate, wherein each storage cell includes: A first conductor layer, a first gate, a second gate, and a second conductor layer are stacked in sequence. The first conductor layer and the first gate are electrically insulated from each other, the first gate and the second gate are electrically insulated from each other, and the second gate and the second conductor layer are electrically insulated from each other. A channel layer is located on one side of the first conductor layer, one side of the first gate, one side of the second gate, and one side of the second conductor layer, wherein the first gate and the second gate are electrically insulated from the channel layer, and the first conductor layer and the second conductor layer are electrically connected to the channel layer. as well as A first charge storage layer is located between the first gate and the channel layer.

2. The memory structure of claim 1, wherein each of the memory cells further comprises: A first dielectric layer is located between the first charge storage layer and the channel layer, and between the first gate and the first conductor layer; The second dielectric layer is located between the first gate and the first charge storage layer; The third dielectric layer is located between the first conductor layer and the channel layer, between the first dielectric layer and the channel layer, between the second gate and the channel layer, and between the second conductor layer and the channel layer; The fourth dielectric layer is located between the first gate and the second gate; A fifth dielectric layer is located between the second gate and the second conductor layer; and The sixth dielectric layer is located between the first dielectric layer and the first conductor layer, wherein The first conductor layer is electrically connected to the channel layer through dielectric layer breakdown of the third dielectric layer located between the first conductor layer and the channel layer, and The second conductor layer is electrically connected to the channel layer through dielectric layer breakdown of the third dielectric layer located between the second conductor layer and the channel layer.

3. The memory structure as described in claim 2, wherein the third dielectric layer is a continuous structure located on one side of the first conductor layer, one side of the first gate, one side of the second gate, and one side of the second conductor layer.

4. The memory structure of claim 1, wherein each of the memory cells further comprises: A first dielectric layer is located between the first charge storage layer and the channel layer, and between the first gate and the first conductor layer; The second dielectric layer is located between the first gate and the first charge storage layer; The third dielectric layer is located between the second gate and the channel layer; The fourth dielectric layer is located between the first gate and the second gate; A fifth dielectric layer is located between the second gate and the second conductor layer; and The sixth dielectric layer is located between the first dielectric layer and the first conductor layer.

5. The memory structure of claim 4, wherein the first conductor layer directly contacts the channel layer, and the second conductor layer directly contacts the channel layer.

6. The memory structure of claim 4, wherein the third dielectric layer is further located between the second gate and the fourth dielectric layer and between the second gate and the fifth dielectric layer.

7. The memory structure of claim 1, wherein each of the memory cells further comprises: The second charge storage layer is located between the second gate and the channel layer.

8. The memory structure of claim 7, wherein each of the memory cells further comprises: A first dielectric layer is located between the first charge storage layer and the channel layer, between the first gate and the first conductor layer, and between the first gate and the second gate; The second dielectric layer is located between the first gate and the first charge storage layer; The third dielectric layer is located between the second charge storage layer and the channel layer, between the second gate and the second conductor layer, and between the second gate and the first gate; The fourth dielectric layer is located between the second gate and the second charge storage layer; The fifth dielectric layer is located between the first dielectric layer and the third dielectric layer, which are situated between the first gate and the second gate. The sixth dielectric layer is located between the first dielectric layer and the first conductor layer; as well as The seventh dielectric layer is located between the third dielectric layer and the second conductor layer.

9. The memory structure of claim 8, wherein the first conductor layer directly contacts the channel layer, and the second conductor layer directly contacts the channel layer.

10. The memory structure of claim 1, wherein two adjacent memory cells share the first conductor layer.

11. The memory structure of claim 10, wherein the components in two adjacent memory cells sharing the first conductor layer have a symmetrical configuration.

12. The memory structure of claim 1, wherein two adjacent memory cells share the second conductor layer.

13. The memory structure of claim 12, wherein the components in two adjacent memory cells sharing the second conductor layer have a symmetrical configuration.

14. The memory structure of claim 1, wherein the materials of the first conductor layer, the second gate and the second conductor layer comprise doped polysilicon, and the material of the first gate comprises metal.

15. The memory structure of claim 1, wherein the materials of the first conductor layer and the second conductor layer comprise doped polysilicon, and the materials of the first gate and the second gate comprise metal.

16. The memory structure of claim 1, wherein the material of the channel layer comprises a semiconductor material.

17. The memory structure of claim 16, wherein the semiconductor material comprises polycrystalline silicon.

18. The memory structure of claim 1, wherein the material of the first charge storage layer comprises a charge trapping material.

19. The memory structure of claim 18, wherein the charge trapping material comprises silicon nitride.

20. The memory structure of claim 1, wherein the memory structure includes a three-dimensional inverse-OR flash memory structure.

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