Memory device and method of manufacturing the same

Abstract

The present disclosure provides a memory device and a method of fabricating the same. The memory device includes a stack and a plurality of memory strings. The stack is disposed on a substrate, and includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings pass through the stack along a first direction, wherein a first memory string of the memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar respectively extend along the first direction and are separated from each other. The channel layer is disposed between the first conductive pillar and the second conductive pillar. The memory structure surrounds the second conductive pillar, wherein the memory structure includes a resistive memory material.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a memory device, and more particularly, to a three-dimensional memory device and a method of fabricating the same. BACKGROUND

[0002] Recently, as the demand for more superior memory devices has gradually increased, various three-dimensional (3D) memory devices have been provided. However, most of the three-dimensional memory devices still have some electrical problems. Therefore, there is still a need to provide an improved three-dimensional memory device and a method of fabricating the same.

[0003] SUMMARY

[0004] The present disclosure relates to a memory device and a method of fabricating the same. In the memory device of the present disclosure, the contact area between the memory structure and the channel layer is small, so some of the existing electrical problems can be overcome.

[0005] According to an embodiment of the present disclosure, a memory device is provided. The memory device includes a stack and a plurality of memory strings. The stack is disposed on a substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The plurality of memory strings pass through the stack along a first direction, wherein a first memory string of the plurality of memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar respectively extend along the first direction and are separated from each other. The channel layer is disposed between the first conductive pillar and the second conductive pillar. The memory structure surrounds the second conductive pillar, wherein the memory structure includes a resistive memory material.

[0006] According to an embodiment of the present disclosure, a method of fabricating a memory device is provided. The method includes the following steps. First, a stack structure disposed on a substrate is provided. The stack structure includes a plurality of sacrificial layers and a plurality of insulating layers alternately stacked along a first direction. Next, a plurality of openings passing through the stack structure are formed; a portion of the sacrificial layers is removed to form a plurality of recesses between the sacrificial layers, the insulating layers, and the openings; a channel material layer is formed in the recesses, wherein the channel material layer includes a first side and a second side, and the first side and the second side are opposite to each other; a vertical hole extending along the first direction is formed on the first side of the channel material layer; a conductive material is filled in the vertical hole to form a first conductive pillar; an extension hole extending along the first direction is formed on the second side of the channel material layer, and the channel material layer becomes a channel layer; a memory material and a conductive material are sequentially filled in the extension hole to form a memory structure and a second conductive pillar, respectively, wherein the memory structure surrounds the second conductive pillar and includes a resistive memory material. Thereafter, the sacrificial layers are removed, and the conductive material is filled in the positions where the sacrificial layers are removed to form a plurality of conductive layers.

[0007] For a better understanding of the above-described and other aspects of the present application, one preferred embodiment will be described in detail herein below with reference to the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figures 1-9D Schematic diagram of a memory device and its manufacturing flow according to an embodiment of the present application;

[0009] Figures 10A-13D Schematic diagram of a memory device and its manufacturing flow according to another embodiment of the present application;

[0010] Figure 14A Circuit diagram of a memory device according to an embodiment of the present application;

[0011] Figure 14B Circuit diagram of a memory device according to another embodiment of the present application; and

[0012] Figure 14C Circuit diagram of a memory device according to an embodiment of the present application.

[0013] REFERENCE NUMERALS

[0014] 10, 20, 30: Memory device

[0015] 100: Substrate

[0016] 100s: Upper surface

[0017] 112: Opening

[0018] 114: Insulating pillar

[0019] 116: Oxide layer

[0020] 116': Oxide material layer

[0021] 118a, 218a: First conductive pillar

[0022] 118b, 218b: Second conductive pillar

[0023] 118c, 218c: Third conductive pillar

[0024] 118t, 218t: Vertical hole

[0025] 120: Channel layer

[0026] 120': Channel material layer

[0027] 120b: Backside channel layer

[0028] 120f: Frontside channel layer

[0029] 120t: Trench

[0030] 122, 222: memory structure

[0031] 122t, 222t: extended hole

[0032] 218d: fourth conductive pillar

[0033] 1201-1206: channel portion

[0034] A, A', B, B': profile line end point

[0035] BL: bit line

[0036] CL: conductive layer

[0037] E1: first side

[0038] E2: second side

[0039] IL: insulating layer

[0040] L1, L2: length

[0041] MS: memory string

[0042] MS1: first memory string

[0043] MS2: second memory string

[0044] p1, p2: path

[0045] R: resistive memory

[0046] s1: inner surface

[0047] s2: outer surface

[0048] SAL: sacrificial layer

[0049] SL: source line

[0050] ST: stack

[0051] ST': stack structure

[0052] T: transistor

[0053] TL: cover layer

[0054] WL: word line DETAILED DESCRIPTION

[0055] The present application relates to a three-dimensional memory device. In particular, the memory device (e.g., memory device 10 and 20) according to any embodiment of the present application can be applied to a three-dimensional "resistive memory device". In the present application, "resistive memory device" means any memory related to resistance change, such as transition metal oxide resistive random-access memory (TMO ReRAM), conductive bridging random access memory (CBRAM), phase change memory (PCM), magnetoresistive random access memory (MRAM), or other suitable resistive memory. In addition, the memory device (e.g., memory device 10 and 20) according to any embodiment of the present application can be applied to three-dimensional and memory (3DAND memory), and the present application is not limited thereto.

[0056] Figures 1-9D A schematic diagram of a memory device 10 according to an embodiment of the present application and a manufacturing process thereof.

[0057] Referring to Figure 1 , which is a cross-sectional view taken along a first direction (e.g., the Z direction) and a third direction (e.g., the X direction), the first direction and the third direction can be staggered with respect to each other, such as perpendicular to each other, but the present application is not limited thereto. First, a substrate 100 is provided, and a stack structure ST' is formed on an upper surface 100s of the substrate 100. The stack structure ST' includes a plurality of sacrificial layers SAL and a plurality of insulating layers IL alternately stacked along the first direction (e.g., the Z direction, or the normal direction of the upper surface 100s of the substrate 100).

[0058] In some embodiments, the substrate 100 is, for example, a dielectric layer (e.g., a silicon oxide layer). The insulating layer IL can be, for example, a silicon oxide layer, which includes, for example, silicon dioxide. The sacrificial layer SAL can be, for example, a silicon nitride layer. In the present embodiment, the topmost layer and the bottommost layer of the stack structure ST' are insulating layers IL, and seven insulating layers IL and six sacrificial layers SAL are shown, but the present application is not limited thereto. The number and arrangement of the insulating layers IL and the sacrificial layers SAL can be adjusted as needed.

[0059] Thereafter, referring to Figures 2A-2C , Figure 2A , which is a cross-sectional view taken along the first direction (e.g., the Z direction) and the third direction (e.g., the X direction), correspondingFigure 2B and 2C a cross-section along the A-A' line of Figure 2B a top view along the second direction (e.g. Y direction) and the third direction (e.g. X direction), corresponding to a plane of the sacrificial layer SAL; Figure 2C a top view along the second direction (e.g. Y direction) and the third direction (e.g. X direction), corresponding to a plane of the insulating layer IL.

[0060] As shown in Figures 2A-2C , a plurality of openings 112 are formed through the stack structure ST' along the first direction (e.g. Z direction) by an etching process. Each opening 112 passes through a portion of the bottommost insulating layer IL, and a bottom of the opening 112 can expose the bottommost insulating layer IL. In the present embodiment, the openings 112 have a circular cross-section in a top view along the Figure 2B and 2C , but the present application is not limited thereto. The cross-section of the openings 112 in a top view along the Figure 2B and 2C may be elliptical or other suitable geometric shapes. In some embodiments, the openings 112 can be referred to as vertical trench openings.

[0061] Next, please refer to Figures 3A-3C , Figure 3A a cross-section along the first direction (e.g. Z direction) and the third direction (e.g. X direction), corresponding to Figure 3B and 3C a cross-section along the A-A' line of Figure 3B a top view along the second direction (e.g. Y direction) and the third direction (e.g. X direction), corresponding to a plane of the sacrificial layer SAL; Figure 3C a top view along the second direction (e.g. Y direction) and the third direction (e.g. X direction), corresponding to a plane of the insulating layer IL.

[0062] As shown in Figures 3A-3C , a portion of the sacrificial layer SAL is removed by an etching process to form a plurality of recesses 120t between the sacrificial layer SAL, the insulating layer IL and the openings 112. The recesses 120t and the openings 112 can be in communication with each other. The etching process of this step is, for example, a wet etching process or a dry etching process. The etchant of the wet etching process is, for example, phosphoric acid (H3PO4), and the etching process is, for example, a reactive-ion etching (RIE).

[0063] Thereafter, please refer to Figures 4A-4C , Figure 4Aa cross-sectional view taken along a line A-A' of Figure 4B and 4C ; Figure 4B a top view taken along a line B-B' of Figure 4C a top view taken along a line B-B' of

[0064] As shown in Figures 4A-4C , an oxide material layer 116' and a channel material layer 120' can be formed in the recess 120t in sequence. The oxide material layer 116' can be formed by an oxidation process, such as in-situ steam generation oxidation (ISSG oxidation). The material of the oxide material layer 116' is, for example, an oxide of silicon, a high-k material, or other suitable material. After the oxide material layer 116' is formed, a channel material can be filled in the opening 112 and the recess 120t, and then a channel material in the opening 112 is removed by an etch-back process, and the channel material in the recess 120t is retained to close the recess 120t, so that the channel material layer 120' surrounded by the oxide material layer 116' is formed. The material of the channel material layer 120' is, for example, undoped polysilicon. Figure 4A From the perspective of Figure 4B , the oxide material layer 116' has a similar C-shaped cross-section, i.e., the oxide material layer 116' covers the upper surface, the lower surface, and a side surface of the channel material layer 120'. From the perspective of , the channel material layer 120' surrounds the opening 112, and the oxide material layer 116' surrounds the channel material layer 120'. In the second and third directions, the thickness of the channel material layer 120' can be greater than the thickness of the oxide material layer 116'.

[0065] Thereafter, please refer to Figures 5A-5C , Figure 5A a cross-sectional view taken along a line A-A' of Figure 5B and 5C ; Figure 5B a top view taken along a line B-B' of Figure 5C a top view taken along a line B-B' of

[0066] As shown in Figures 5A-5CAs shown, insulating material is filled in the opening 112 to form an insulating pillar 114. Thereafter, a planarization process, such as a chemical-mechanical planarization (CMP), can be performed. The material of the insulating pillar 114 can be an oxide, such as silicon dioxide.

[0067] Thereafter, please refer to Figures 6A-6C , Figure 6A the cross-sectional view formed by the first direction (e.g., the Z direction) and the third direction (e.g., the X direction), corresponding to the plane of the insulating layer IL; Figure 6B and 6C the cross-sectional view formed by the A-A' line of Figure 6B the top view formed by the second direction (e.g., the Y direction) and the third direction (e.g., the X direction), corresponding to the plane of the sacrificial layer SAL; Figure 6C the top view formed by the second direction (e.g., the Y direction) and the third direction (e.g., the X direction), corresponding to the plane of the insulating layer IL.

[0068] As shown in Figures 6A-6C , two adjacent channel material layers 120' form a group of channel material layers 120'. Each channel material layer 120' includes a first side E1 and a second side E2 opposite to each other, and the first side E1 is closer to the other channel material layer 120' than the second side E2. In this embodiment, the first side E1 is, for example, the inner side of each channel material layer 120' in the group of channel material layers 120', and the second side E2 is, for example, the outer side of each channel material layer 120' in the group of channel material layers 120'. After forming a vertical hole 118t extending along the first direction at the first side E1 of the channel material layer 120', a deposition process is performed to fill a conductive material in the vertical hole 118t to form a first conductive pillar 118a, wherein the conductive material is, for example, doped polysilicon. That is, the vertical hole 118t is formed between the adjacent two insulating pillars 114, and is formed, for example, by removing part of the insulating pillar 114, the channel material layer 120', the insulating layer IL, and the sacrificial layer SAL (i.e., removing part of the stack structure ST'). Thereafter, a planarization process, such as a chemical-mechanical planarization, can be performed. The shape and size of the vertical hole 118t are not particularly limited, as long as it is sufficient to connect the adjacent two channel material layers 120'. In some embodiments, the first side E1 can be referred to as a source side, and the second side E2 can be referred to as a drain side.

[0069] Thereafter, please refer to Figures 7A-7C , Figure 7A the cross-sectional view formed by the first direction (e.g., the Z direction) and the third direction (e.g., the X direction), corresponding to the plane of the insulating layer IL; Figure 7B and 7CThe cross-section formed by the line connecting A-A'; Figure 7B The top view formed by the second direction (e.g., the Y direction) and the third direction (e.g., the X direction) corresponds to the plane of the sacrificial layer SAL; Figure 7C The top view formed by the second direction (e.g., the Y direction) and the third direction (e.g., the X direction) corresponds to the plane of the insulating layer IL.

[0070] like Figures 7A-7C As shown, an extended via 122t extending along a first direction is formed on the second side E2 (e.g., the outer side) of the channel material layer 120'. The extended via 122t is formed, for example, by removing portions of the insulating pillar 114, oxide material layer 116', channel material layer 120', insulating layer 11, and sacrificial layer SAL (i.e., the stacked structure ST' with the removed portions) through an etching process. After forming the extended via 122t, the oxide material layer 116' and the channel material layer 120' become oxide layer 116 and channel layer 120, respectively. In this embodiment, the width of the vertical via 118t in the third direction (X direction) may be greater than the width of the extended via 122t in the third direction (X direction), but the invention is not limited thereto.

[0071] After that, please refer to the following: Figures 8A-8C , Figure 8A This is a cross-sectional view formed by a first direction (e.g., the Z direction) and a third direction (e.g., the X direction), corresponding to... Figure 8B and 8C The cross-section formed by the line connecting A-A'; Figure 8B The top view formed by the second direction (e.g., the Y direction) and the third direction (e.g., the X direction) corresponds to the plane of the sacrificial layer SAL; Figure 8C The top view formed by the second direction (e.g., the Y direction) and the third direction (e.g., the X direction) corresponds to the plane of the insulating layer IL.

[0072] like Figures 8A-8C As shown, a memory structure 122 is formed by sequentially filling an extended cavity 122t with memory material and conductive material through a deposition process, thereby forming a second conductive pillar 118b, a third conductive pillar 118c, and memory structures 122 surrounding the second conductive pillar 118b and the third conductive pillar 118c, respectively. Subsequently, a planarization process, such as chemical mechanical planarization, can be performed. The memory material may include resistive memory materials, such as transition metal oxides, bridge memory materials, phase-change memory materials, magnetoresistive memory materials, or other suitable materials. For example, the memory material may be hafnium oxide (HfO). X), germanium-antimony-tellurium is an alloy (Ge-Sb-Te alloy) or other suitable material. The second conductive pillar 118b and the third conductive pillar 118c can be a multi-layer structure, such as titanium nitride / tungsten (TiN / W), tantalum nitride / tungsten (TaN / W), titanium / titanium nitride / tungsten (Ti / TiN / W), or other suitable structure.

[0073] In this embodiment, the memory structure 122 has a U-shaped profile, as shown in Figure 8A , but the present disclosure is not limited thereto. In other embodiments, the memory structure 122 can have a ring-shaped profile, i.e., the memory structure 122 extends only on the sidewalls of the extended hole 122t and does not have a bottom portion that is continuous along the second direction and the third direction, but exposes the bottom portion of the extended hole 122t.

[0074] Thereafter, please refer to Figures 9A-9D , Figure 9A , the cross-sectional view taken along the first direction (e.g., the Z direction) and the third direction (e.g., the X direction); Figure 9B , the cross-sectional view taken along the first direction (e.g., the Z direction) and the second direction (e.g., the Y direction); Figure 9C , the top view taken along the second direction (e.g., the Y direction) and the third direction (e.g., the X direction), corresponding to the plane of the conductive layer CL; Figure 9D , the top view taken along the second direction (e.g., the Y direction) and the third direction (e.g., the X direction), corresponding to the plane of the cap layer TL. Figure 9A , and 9B correspond to the cross-sections taken along the A-A line and the B-B line of Figure 9C , respectively.

[0075] As shown in Figures 9A-9D , after the sacrificial layer SAL is removed, the conductive material is filled in the positions where the sacrificial layer SAL is removed to form the plurality of conductive layers CL, i.e., the stack ST in which the conductive layers CL and the insulating layers IL are alternately stacked along the first direction. Thereafter, a cap layer TL is formed on the stack ST. For example, the sacrificial layer SAL can be removed by a selective etching process, leaving the insulating layers IL. In this way, a plurality of memory strings MS are formed through the stack ST, and the memory strings MS can include a first memory string MS1 and a second memory string MS2, wherein the first conductive pillar 118a, the second conductive pillar 118b, the channel layer 120, and the memory structure 122 can correspond to the first memory string MS1. In some embodiments, a barrier layer (not shown) can be deposited in the positions where the sacrificial layer SAL is removed before the conductive material is filled. The material of the barrier layer can be an oxide material or a dielectric material. The barrier layer can electrically isolate the conductive layer CL and the memory structure 122, and can serve as a gate oxide of the channel layer 120.

[0076] Based on the above steps, the following is formed: Figures 9A-9D The memory device 10 shown includes a stacked layer ST, a plurality of memory serial lines MS, and a cover layer TL disposed on a substrate 100. The stacked layer ST includes a plurality of conductive layers CL and a plurality of insulating layers IL alternately stacked along a first direction. The substrate 100 has an upper surface 100s, on which the stacked layer ST is formed. The conductive layers CL and the insulating layers IL extend along a second direction and a third direction, respectively, and the first, second, and third directions are interleaved (for example, they are perpendicular to each other, but the invention is not limited thereto). The memory serial lines MS pass through the stacked layer ST along the first direction (e.g., the Z direction). The cover layer TL is disposed on the stacked layer ST.

[0077] Please refer to Figure 9C Two adjacent memory serial lines (MS) form a group of memory serial lines (MS), and the two adjacent memory serial lines (MS) are connected to each other. Each group of memory serial lines (MS) may include a first memory serial line (MS1) and a second memory serial line (MS2). The first memory serial line (MS1) includes a first conductive post 118a, a second conductive post 118b, an oxide layer 116, an insulating post 114, a channel layer 120, and a memory structure 122. The first conductive post 118a and the second conductive post 118b may extend along a first direction and be separated from each other. The channel layer 120 is disposed between the first conductive post 118a and the second conductive post 118b. The oxide layer 116 is disposed between the conductive layer CL and the channel layer 120. The memory structure 122 surrounds the second conductive post 118b, but does not surround the channel layer 120, the oxide layer 116, and the first conductive post 118a (i.e., the channel layer 120, the oxide layer 116, and the first conductive post 118a are exposed). Furthermore, the memory structure 122 has an inner surface s1 and an outer surface s2. The inner surface s1 is in direct contact with the second conductive post 118b, and the outer surface s2 is in direct contact with the channel layer 120, such that the second conductive post 118b and the channel layer 120 are separated by the memory structure 122. In other words, the memory structure 122 extends along a first direction (Z direction) and is disposed between the second conductive post 118b and the channel layer 120, between the second conductive post 118b and the insulating post 114, and between the second conductive post 118b and the stacked layers ST (including the conductive layer CL and the insulating layer SL).

[0078] In such Figure 9CIn the cross-sectional view shown, the channel layer 120 is separated by the first conductive pillar 118a and the second conductive pillar 118b into a front-side channel layer 120f and a back-side channel layer 120b. The front-side channel layer 120f and the back-side channel layer 120b provide two current paths pi and p2. In one embodiment, the first conductive pillar 118a serves as a source of the first memory string MS1, the second conductive pillar 118b serves as a drain of the first memory string MS1, the conductive layer CL can serve as a word line, and a bit line (not shown) is electrically connected to the second conductive pillar 118b. When a current flows into the second conductive pillar 118b through the bit line (not shown), the current can flow from the second conductive pillar 118b to the memory structure 122, and then the current can be transferred from the memory structure 122 to the front-side channel layer 120f and / or the back-side channel layer 120b, and then to the first conductive pillar 118a through the front-side channel layer 120f and / or the back-side channel layer 120b. That is, the current can flow through the path pi and / or the path p2.

[0079] Please refer to Figure 9B In the second direction (Y direction), the length LI of the conductive layer CL is less than the length L2 of the insulating layer IL. In this embodiment, the total length of the conductive layer CL, the oxide layer 116, and the channel layer 120 in the second direction is equal to the length of the insulating layer IL in the second direction. A plurality of trenches 120t is provided between the conductive layer CL, the insulating layer IL, and the insulating pillar 114, and the channel layer 120 is disposed in the trenches 120t. More specifically, each layer of the conductive layer CL corresponds to a trench 120t, and the channel layer 120 is disposed between two adjacent insulating layers IL, insulating pillars 114, and corresponding conductive layers CL. Furthermore, the channel layer 120 includes a plurality of channel portions 1201-1206, which correspond to different layers of the conductive layer CL and are separated from each other. In this embodiment, the channel portions 1201-1206 of different layers are respectively confined in the trenches 120t and are not connected to each other, but the present application is not limited thereto. In other embodiments, the channel layer can extend outside the trenches, so that the channel portions of different layers can be connected to each other.

[0080] According to one embodiment of the present application, the memory structure 122 includes a resistive memory material. The resistive memory material can be, for example, a transition metal oxide, a conductive bridge memory material, a phase change memory material, a magnetoresistive memory material, or other suitable material. For example, the memory material can be hafnium oxide (HfO XThe material of the oxide layer 116 is, for example, an oxide of silicon, a high-dielectric-constant material, or another suitable material. The material of the first conductive pillar 118a may include doped polycrystalline silicon. The second conductive pillar 118b may be a multilayer structure, such as titanium nitride / tungsten (TiN / W), tantalum nitride / tungsten (TaN / W), titanium / titanium nitride / tungsten (Ti / TiN / W), or another suitable structure. The material of the channel layer 120 is, for example, doped polycrystalline silicon. The conductive layer CL is, for example, a titanium nitride / tungsten (TiN / W) bilayer structure. The material of the insulating layer IL may include oxides, such as silicon dioxide.

[0081] In this embodiment, the second memory serial unit MS2 is adjacent to and connected to the first memory serial unit MS1, and the first memory serial unit MS1 and the second memory serial unit MS2 share the first conductive post 118a, such as... Figure 9C As shown. The second memory array MS2 includes a first conductive post 118a, a third conductive post 118c, an oxide layer 116, an insulating post 114, a channel layer 120, and a memory structure 122. The first conductive post 118a can serve as the common source of the first memory array MS1 and the second memory array MS2. The second memory array MS2 is mirror-symmetrical to the first memory array MS1 about an axis of symmetry that passes through the center of the first conductive post 118a and extends along a second direction. The third conductive post 118c has the same material, structure, and function as the second conductive post 118b, and the third conductive post 118c can serve as the drain in the second memory array MS2. That is, after current is applied to the third conductive post 118c, it can be sequentially transmitted to the first conductive post 118a through the memory structure 122 and the channel layer 120. Other components in the second memory array MS2 use the same component symbols as other components in the first memory array MS1. These components also have the same material, structure, and function, and will not be described again here.

[0082] In this embodiment, the first conductive post 118a may have an elliptical cross-section, and the second conductive post 118b and the third conductive post 118c may have circular cross-sections, such as... Figure 9C As shown, the present invention is not limited thereto. In other embodiments, the cross-section of the first conductive post 118a may be circular or other suitable shape, and the cross-sections of the second conductive post 118b and the third conductive post 118c may be elliptical or other suitable shape. Those skilled in the art can make adjustments according to their needs.

[0083] Compared to comparative examples where the memory structure surrounds the channel layer, the memory structure 122 of this invention only surrounds the second conductive post 118b or the third conductive post 118c and does not surround the channel layer 120, thus the contact area between the memory structure 122 and the channel layer 120 is smaller. Furthermore, compared to comparative examples where the channel layer is not formed in a groove or where the channel layer extends continuously along a first direction, the channel layer 120 according to an embodiment of this invention is formed in a groove 120t, and the channel portions 1201 to 1206 corresponding to different conductive layers CL are not interconnected, thus the contact area between the memory structure 122 and the channel layer 120 is smaller. That is, in the memory device 10 of an embodiment of this disclosure, the memory structure 122 and the channel layer 120 can have a smaller contact area, thereby significantly reducing the risk of leakage current and reducing the operating voltage.

[0084] Figures 10A-13D This is a schematic diagram of a memory device 20 and its manufacturing process according to another embodiment of the present invention.

[0085] First, proceed as follows Figures 1-5C The formation steps shown are followed by the following steps: Figures 10A-10C The formation steps are shown. Please also refer to... Figures 10A-10C , Figure 10A This is a cross-sectional view formed by a first direction (e.g., the Z direction) and a third direction (e.g., the X direction), corresponding to... Figure 10B and 10C A cross-sectional view of the line connecting A-A'; Figure 10B The top view formed by the second direction (e.g., the Y direction) and the third direction (e.g., the X direction) corresponds to the plane of the sacrificial layer SAL; Figure 10C The top view formed by the second direction (e.g., the Y direction) and the third direction (e.g., the X direction) corresponds to the plane of the insulating layer IL.

[0086] like Figures 10A-10CAs shown, 2 adjacent channel material layers 120' along the third direction (e.g. X direction) are taken as a group of channel material layers 120', each channel material layer 120' includes a first side E1 and a second side E2, the first side E1 and the second side E2 are opposite to each other, and the first side E1 is closer to the other channel material layer 120' than the second side E2. In this embodiment, the first side E1 is, for example, the inner side of each channel material layer 120' in the group of channel material layers 120', and the second side E2 is, for example, the outer side of each channel material layer 120' in the group of channel material layers 120'. After forming the vertical holes 218t extending along the first direction on the first side E1 of the channel material layer 120', the vertical holes 218t are filled with a conductive material, for example, doped polysilicon, by a deposition process to form the first conductive pillars 218a and the third conductive pillars 218c. That is, 2 adjacent vertical holes 218t are formed between 2 adjacent insulating pillars 114, and are formed, for example, by removing part of the insulating pillars 114, the channel material layers 120', the insulating layers IL and the sacrificial layers SAL (i.e. removing part of the stack structure ST') by an etching process. Then, a planarization process, for example, chemical mechanical planarization, can be performed. In some embodiments, the first side E1 can be referred to as the source side, and the second side E2 can be referred to as the drain side. As shown in FIG. 1G, the first conductive pillars 218a are arranged on the right side of the connected channel material layers 120', and the third conductive pillars 218c are arranged on the left side of the connected channel material layers 120', that is, the first conductive pillars 218a and the third conductive pillars 218c are arranged on different sides (e.g. left and right sides) of the connected channel material layers 120', but the present application is not limited thereto, in other embodiments, the first conductive pillars 218a can be arranged on the right side of the connected channel material layers 120', and the third conductive pillars 218c can also be arranged on the right side of the connected channel material layers 120', that is, the first conductive pillars 218a and the third conductive pillars 218c can be arranged on the same side (e.g. both right sides) of the connected channel material layers 120'. Figure 10B As shown, the first conductive pillars 218a are arranged on the right side of the connected channel material layers 120', and the third conductive pillars 218c are arranged on the left side of the connected channel material layers 120', that is, the first conductive pillars 218a and the third conductive pillars 218c are arranged on different sides (e.g. left and right sides) of the connected channel material layers 120', but the present application is not limited thereto, in other embodiments, the first conductive pillars 218a can be arranged on the right side of the connected channel material layers 120', and the third conductive pillars 218c can also be arranged on the right side of the connected channel material layers 120', that is, the first conductive pillars 218a and the third conductive pillars 218c can be arranged on the same side (e.g. both right sides) of the connected channel material layers 120'.

[0087] Please also refer to Figures 11A-11C , Figure 11A the cross-sectional view of the A-A' line of FIG. 1F; Figure 11B and 11C the cross-sectional view of the A-A' line of FIG. 1F; Figure 11B the top view of the second direction (e.g. Y direction) and the third direction (e.g. X direction), corresponding to the plane of the sacrificial layers SAL; Figure 11C the top view of the second direction (e.g. Y direction) and the third direction (e.g. X direction), corresponding to the plane of the insulating layers IL.

[0088] As shown in FIG. 1G, the first conductive pillars 218a are arranged on the right side of the connected channel material layers 120', and the third conductive pillars 218c are arranged on the left side of the connected channel material layers 120', that is, the first conductive pillars 218a and the third conductive pillars 218c are arranged on different sides (e.g. left and right sides) of the connected channel material layers 120', but the present application is not limited thereto, in other embodiments, the first conductive pillars 218a can be arranged on the right side of the connected channel material layers 120', and the third conductive pillars 218c can also be arranged on the right side of the connected channel material layers 120', that is, the first conductive pillars 218a and the third conductive pillars 218c can be arranged on the same side (e.g. both right sides) of the connected channel material layers 120'. Figures 11A-11CAs shown, an extended hole 222t extending along the first direction is formed at the second side E2 (e.g. the outer side) of the channel material layer 120'. The extended hole 222t is formed by removing part of the insulating pillar 114, the oxide material layer 116', the channel material layer 120', the insulating layer IL and the sacrificial layer SAL (i.e. removing part of the stack structure ST') by an etching process. After forming the extended hole 222t, the oxide material layer 116' and the channel material layer 120' become the oxide layer 116 and the channel layer 120, respectively.

[0089] Thereafter, please refer to Figures 12A-12C , Figure 12A for a cross-sectional view formed along the first direction (e.g. the Z direction) and the third direction (e.g. the X direction), which corresponds to the cross-sectional view along the A-A' line of Figure 12B and 12C ; Figure 12B for a top view formed along the second direction (e.g. the Y direction) and the third direction (e.g. the X direction), which corresponds to the planar view of the sacrificial layer SAL; Figure 12C for a top view formed along the second direction (e.g. the Y direction) and the third direction (e.g. the X direction), which corresponds to the planar view of the insulating layer IL.

[0090] As shown in Figures 12A-12C , the memory material and the conductive material are sequentially filled in the extended hole 222t by a deposition process to form a second conductive pillar 218b, a fourth conductive pillar 218d and a memory structure 222 surrounding the second conductive pillar 218b and the fourth conductive pillar 218d, respectively. Thereafter, a planarization process, such as a chemical mechanical planarization, can be performed. The memory material can include a resistive memory material, such as a transition metal oxide, a conductive bridge memory material, a phase change memory material, a magnetoresistive memory material or other suitable material. For example, the memory material can be hafnium oxide (HfO X ), a germanium-antimony-tellurium alloy (Ge-Sb-Te alloy) or other suitable material. The second conductive pillar 218b and the fourth conductive pillar 218d can be a multi-layer structure, such as titanium nitride / tungsten (TiN / W), tantalum nitride / tungsten (TaN / W), titanium / titanium nitride / tungsten (Ti / TiN / W) or other suitable structure.

[0091] In the present embodiment, the cross-section of the memory structure 222 is a U-shaped structure, as shown in Figure 12A , but the present application is not limited thereto. In other embodiments, the memory structure 222 can be a ring-shaped structure, i.e. the memory structure 222 only extends on the sidewall of the extended hole 222t and does not have a continuous bottom portion extending along the second direction and the third direction, but exposes the bottom portion of the extended hole 222t.

[0092] Thereafter, please refer to Figures 13A-13D , Figure 13A a cross-sectional view taken along a first direction (e.g., Z direction) and a third direction (e.g., X direction); Figure 13B a cross-sectional view taken along a first direction (e.g., Z direction) and a second direction (e.g., Y direction); Figure 13C a top view taken along a second direction (e.g., Y direction) and a third direction (e.g., X direction), corresponding to a plane of the conductive layers CL; Figure 13D a top view taken along a second direction (e.g., Y direction) and a third direction (e.g., X direction), corresponding to a plane of the cap layer TL. Figure 13A and 13B correspond to cross-sections along the A-A' line and the B-B' line of Figure 13C , respectively.

[0093] As shown in Figures 13A-13D , after the sacrificial layers SAL are removed, conductive material is filled in the locations where the sacrificial layers SAL are removed to form a plurality of conductive layers CL, i.e., to form a stack ST in which the conductive layers CL and the insulating layers IL are alternately stacked along the first direction. Thereafter, a cap layer TL is formed on the stack ST. For example, the sacrificial layers SAL can be removed by a selective etching process that leaves the insulating layers IL. In this way, a plurality of memory strings MS are formed through the stack ST, which can include a first memory string MS1 and a second memory string MS2, where the first conductive pillar 218a, the second conductive pillar 218b, the channel layer 120, and the memory structure 222 can form the first memory string MS1. In some embodiments, a barrier layer (not shown) can be deposited in the locations where the sacrificial layers SAL are removed before the conductive material is filled in. The barrier layer can be an oxide material or a dielectric material. The barrier layer can electrically isolate the conductive layers CL from the memory structure 222 and can serve as a gate oxide for the channel layer 120.

[0094] According to the above steps, a memory device 20 is formed as shown in Figures 13A-13D . The memory device 20 includes a stack ST, a plurality of memory strings MS, and a cap layer TL disposed on a substrate 100. The stack ST includes a plurality of conductive layers CL and a plurality of insulating layers IL alternately stacked along a first direction. The substrate 100 has an upper surface 100s on which the stack ST is formed, and the conductive layers CL and the insulating layers IL extend along a second direction and a third direction, respectively, which are interlaced with the first direction (e.g., the first, second, and third directions are perpendicular to each other, but the present disclosure is not limited thereto). The memory strings MS pass through the stack ST along the first direction (e.g., the Z direction). The cap layer TL is disposed on the stack ST.

[0095] Please refer toFigure 13C Two adjacent memory strings MS along a third direction (e.g., the X direction) form a group of memory strings MS, and these two adjacent memory strings MS are separated from each other. Each group of memory strings MS may include a first memory string MS1 and a second memory string MS2. The first memory string MS1 includes a first conductive post 218a, a second conductive post 218b, an oxide layer 116, an insulating post 114, a channel layer 120, and a memory structure 222. The first conductive post 218a and the second conductive post 218b may extend along a first direction and are separated from each other. The channel layer 120 is disposed between the first conductive post 218a and the second conductive post 218b. The oxide layer 116 is disposed between the conductive layer CL and the channel layer 120. The memory structure 222 surrounds the second conductive post 218b, but does not surround it (i.e., the channel layer 120, the oxide layer 116, and the first conductive post 218a are exposed). Furthermore, the memory structure 222 has an inner surface s1 and an outer surface s2. The inner surface s1 is in direct contact with the second conductive post 218b, and the outer surface s2 is in direct contact with the channel layer 120, such that the second conductive post 218b and the channel layer 120 are separated by the memory structure 222. In other words, the memory structure 222 extends along a first direction (Z direction) and is disposed between the second conductive post 218b and the channel layer 120, between the second conductive post 218b and the insulating post 114, and between the second conductive post 218b and the stack ST (including the conductive layer CL and the insulating layer SL).

[0096] In such Figure 13C In the cross-section shown, the channel layer 120 is separated into a front channel layer 120f and a rear channel layer 120b by a first conductive post 218a and a second conductive post 218b. The front channel layer 120f and the rear channel layer 120b provide two current paths p1 and p2. In one embodiment, the first conductive post 218a serves as the source of the first memory serial cell MS1, and the second conductive post 218b serves as the drain of the first memory serial cell MS1. A bit line (not shown) is electrically connected to the second conductive post 218b, and the conductive layer CL can serve as a word line. When current flows into the second conductive post 218b via the bit line (not shown), the current can flow from the second conductive post 218b into the memory structure 222. Subsequently, the current can be transferred from the memory structure 222 to the front channel layer 120f and / or the rear channel layer 120b, and then from the front channel layer 120f and / or the rear channel layer 120b back to the first conductive post 218a. That is, the current can flow through path p1 and / or path p2.

[0097] Please refer to Figure 13BIn the second direction (Y direction), the length LI of the conductive layer CL is smaller than the length L2 of the insulating layer IL. In this embodiment, the total length of the conductive layer CL, the oxide layer 116, and the channel layer 120 in the second direction is equal to the length of the insulating layer IL in the second direction. A plurality of recesses 120t is provided between the conductive layer CL and the insulating layer IL, and the channel layer 120 is provided in the recesses 120t. More specifically, each layer of the conductive layer CL corresponds to a recess 120t, and the channel layer 120 is provided between the two adjacent insulating layers IL and the corresponding conductive layers CL. Furthermore, the channel layer 120 includes a plurality of channel portions 1201-1206, which correspond to the different layers of the conductive layer CL and are separated from each other. In this embodiment, the channel portions 1201-1206 of the different layers are respectively confined in the recesses 120t and are not connected to each other, but the present application is not limited thereto, and in other embodiments, the channel layer can extend outside the recesses, so that the channel portions of the different layers can be connected to each other.

[0098] According to an embodiment of the present application, the memory structure 222 includes a resistive memory material. The resistive memory material is, for example, a transition metal oxide, a conductive bridge memory material, a phase change memory material, a magnetoresistive memory material, or other suitable material. For example, the memory material can be hafnium oxide (HfO X ), a germanium-antimony-tellurium alloy (Ge-Sb-Te alloy), or other suitable material. The material of the oxide layer 116 is, for example, an oxide of silicon, a high dielectric constant material, or other suitable material. The material of the first conductive pillar 218a can include doped polysilicon. The second conductive pillar 218b can be a multi-layer structure, for example, titanium nitride / tungsten (TiN / W), tantalum nitride / tungsten (TaN / W), titanium / titanium nitride / tungsten (Ti / TiN / W), or other suitable structure. The material of the channel layer 120 is, for example, doped polysilicon. The conductive layer CL is, for example, a double-layer structure of titanium nitride / tungsten (TiN / W). The material of the insulating layer IL can include an oxide, for example, silicon dioxide.

[0099] In this embodiment, the second memory string MS2 is adjacent to the first memory string MS1 and separated from the first memory string MS1, as shown in FIG. 1. The second memory string MS2 includes a plurality of memory structures 222, which are arranged in a stack along the second direction Y. The memory structures 222 are arranged in the same manner as the memory structures 222 of the first memory string MS1. Figure 13CThe second memory string MS2 includes a third conductive pillar 218c, a fourth conductive pillar 218d, the oxide layer 116, the insulating pillar 114, the channel layer 120, and the memory structure 122. The first memory string MS1 and the second memory string MS2 have a center point C, and the second memory string MS2 is mirror-symmetrical to the first memory string MS1 with a symmetry axis passing through the center point C and extending along a second direction. The third conductive pillar 218c and the fourth conductive pillar 218d have the same material, structure, and function as the first conductive pillar 218a and the second conductive pillar 218b, respectively. The third conductive pillar 218c can serve as a source of the second memory string MS2, and the fourth conductive pillar 218d can serve as a drain of the second memory string MS2. That is, after current is applied to the fourth conductive pillar 218d, the current can sequentially pass through the memory structure 222 and the channel layer 120 to the third conductive pillar 218c. Other elements in the second memory string MS2 use the same element symbols as those in the first memory string MS1, and these elements also have the same material, structure, and function, which will not be repeatedly described herein.

[0100] In the present embodiment, the first conductive pillar 218a (e.g., a source) is disposed on the right side of the first memory string MS1, the second conductive pillar 218b (e.g., a drain) and the connected memory structure 222 are disposed on the left side of the first memory string MS1, the third conductive pillar 218c (e.g., a source) is disposed on the left side of the second memory string MS2, and the fourth conductive pillar 218d (e.g., a drain) and the connected memory structure 222 are disposed on the right side of the second memory string MS2, that is, the first conductive pillar 218a and the third conductive pillar 218c are disposed on different sides (i.e., left and right sides) of the first memory string MS1 and the second memory string MS2, respectively, as shown in FIG. 13C. However, the present application is not limited thereto, and in other embodiments, the first conductive pillar 218a (e.g., a source) can be disposed on the right side of the first memory string MS1, the second conductive pillar 218b (e.g., a drain) and the connected memory structure 222 can be disposed on the left side of the first memory string MS1, the third conductive pillar 218c (e.g., a source) can be disposed on the right side of the second memory string MS2, and the fourth conductive pillar 218d (e.g., a drain) and the connected memory structure 222 can be disposed on the left side of the second memory string MS2, that is, the first conductive pillar 218a and the third conductive pillar 218c can be disposed on the same side (e.g., the right side) of the first memory string MS1 and the second memory string MS2, respectively, and the second conductive pillar 218b, the fourth conductive pillar 218d, and the connected memory structure 222 can be disposed on the same side (e.g., the left side) of the first memory string MS1 and the second memory string MS2, respectively. Such a structure can correspond to subsequent Figure 14C A circuit diagram of the memory device 30 is shown.

[0101] In this embodiment, the first conductive pillar 218a, the second conductive pillar 218b, the third conductive pillar 218c and the fourth conductive pillar 218d can have a circular cross section, as shown in FIG. 2B, but the present application is not limited thereto. The cross section of the first conductive pillar 218a, the second conductive pillar 218b, the third conductive pillar 218c and the fourth conductive pillar 218d can be elliptical or other suitable shape, which can be adjusted by those skilled in the art according to requirements. Figure 13C

[0102] Compared with the comparative example in which the memory structure surrounds the channel layer, since the memory structure 222 of the present application only surrounds the second conductive pillar 218b or the fourth conductive pillar 218d without surrounding the channel layer 120, the contact area between the memory structure 222 and the channel layer 120 is smaller. Compared with the comparative example in which the channel layer is not formed in the recess or the channel layer continuously extends along the first direction, since the channel layer 120 of the present application is formed in the recess 120t and the channel portions 1201-1206 corresponding to different conductive layers CL are not connected to each other, the contact area between the memory structure 222 and the channel layer 120 is smaller. That is, in the memory device 20 of an embodiment of the present application, the memory structure 222 and the channel layer 120 can have a smaller contact area, so that the risk of leakage current can be greatly reduced, and the operating voltage can be reduced.

[0103] Figure 14A The circuit diagram of the memory device 10 according to an embodiment of the present application (i.e., the memory device 10 shown in FIG. 2A) is shown in FIG. 3. Figures 9A-9D The circuit diagram of the memory device 20 according to another embodiment of the present application (i.e., the memory device 20 shown in FIG. 2B) is shown in FIG. 4. Figure 14B The circuit diagram of the memory device 30 according to an embodiment of the present application is shown in FIG. 5. Figures 13A-13D The circuit diagram of the memory device 20 according to another embodiment of the present application (i.e., the memory device 20 shown in FIG. 2B) is shown in FIG. 4. Figure 14C The circuit diagram of the memory device 30 according to an embodiment of the present application is shown in FIG. 5.

[0104] Please refer to Figure 14A ​The conductive layer CL serves as a word line WL, the first conductive post 118a is electrically connected to a source line SL, the second conductive post 118b and the third conductive post 118c are electrically connected to a bit line BL, the memory structure 122 surrounds the second conductive post 118b and the third conductive post 118c, respectively, and a resistive random-access memory (RRAM) R and a transistor T are electrically connected to the corresponding word line WL, bit line BL and source line SL. That is, the interleaved position of each memory structure 122 and the conductive layer CL can form a memory cell unit including a resistive random-access memory R and a transistor T (1T1R). In this embodiment, the memory device 10 is a common-source AND memory array structure, and the first memory string MS1 and the second memory string MS2 share a source line SL.

[0105] Please refer to Figure 14B The conductive layer CL serves as a word line WL, the first conductive post 218a is electrically connected to a source line SL, the second conductive post 218b is electrically connected to a bit line BL, the third conductive post 218c is electrically connected to a source line SL, and the fourth conductive post 218d is electrically connected to a bit line BL, the memory structure 222 surrounds the second conductive post 218b and the fourth conductive post 218d, respectively, and a resistive random-access memory R and a transistor T are electrically connected to the corresponding word line WL, bit line BL and source line SL. That is, the interleaved position of each memory structure 222 and the conductive layer CL can form a memory cell unit including a resistive random-access memory R and a transistor T (1T1R). In this embodiment, the memory device 20 is an AND memory array structure.

[0106] Figure 14C The memory device 30 shown is similar to the memory device 20, except for the arrangement of the third conductive post, the fourth conductive post and the connected memory structure in the second memory string MS2. Please refer to Figure 14CThe conductive layer CL serves as a word line WL, the first conductive pillar is electrically connected to a source line SL, the second conductive pillar is electrically connected to a bit line BL, the third conductive pillar is electrically connected to the source line SL, and the fourth conductive pillar is electrically connected to the bit line BL. The first conductive pillar is located between the second conductive pillar and the fourth conductive pillar, the fourth conductive pillar is located between the first conductive pillar and the third conductive pillar, and the memory structure surrounds the second conductive pillar and the fourth conductive pillar, respectively. The resistive memory R and the transistor T are electrically connected to the corresponding word line WL, bit line BL, and source line SL. That is, the interleaved position of each memory structure and the conductive layer CL can form a memory cell including a resistive memory R and a transistor T (1T1R). In this embodiment, the memory device 30 is an AND memory array structure.

[0107] According to an embodiment, a memory device and a method of manufacturing the same are provided. The memory device includes a stack and a plurality of memory strings. The stack is disposed on a substrate, and includes a plurality of conductive layers and a plurality of insulating layers that are alternately stacked. The plurality of memory strings passes through the stack along a first direction, wherein a first memory string of the plurality of memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar extend along the first direction and are separated from each other, respectively. The channel layer is disposed between the first conductive pillar and the second conductive pillar. The memory structure surrounds the second conductive pillar, wherein the memory structure includes a resistive memory material.

[0108] Compared with the comparative example in which the memory structure surrounds the channel layer, since the memory structure of the present disclosure only surrounds the second conductive pillar (i.e., does not surround the channel layer), the contact area between the memory structure and the channel layer is small, thereby greatly reducing the risk of leakage current and reducing the operating voltage, so that some known electrical problems can be overcome.

[0109] In summary, although the present application has been disclosed as above with embodiments, it is not intended to limit the present application. Those skilled in the art, without departing from the spirit and scope of the present application, can make various modifications and decorations. Therefore, the protection scope of the present application shall be subject to the scope defined by the appended claims.

Claims

1. A memory device, comprising: a stack disposed on a substrate, the stack comprising a plurality of conductive layers and a plurality of insulating layers alternately stacked; and a plurality of memory strings traversing the stack along a first direction, wherein a first memory string of the memory strings comprises: a first conductive pillar and a second conductive pillar each extending along the first direction and separated from each other; a channel layer disposed between the first conductive pillar and the second conductive pillar; and a memory structure surrounding the second conductive pillar, wherein the memory structure comprises a resistive memory material.

2. The memory device of claim 1, wherein the memory structure is disposed between the second conductive pillar and the channel layer.

3. The memory device of claim 1, wherein the memory structure has an inner surface and an outer surface, the inner surface opposite to the outer surface, the inner surface directly contacting the second conductive pillar, the outer surface directly contacting the channel layer, such that the second conductive pillar and the channel layer are separated by the memory structure.

4. The memory device of claim 1, wherein the substrate has an upper surface, the stack is formed on the upper surface, the conductive layers and the insulating layers each extend along a second direction, the second direction being staggered with the first direction, in the second direction, lengths of the conductive layers are less than lengths of the insulating layers.

5. The memory device of claim 1, further comprising a plurality of recesses disposed between the conductive layers and the insulating layers, wherein the channel layer is disposed in the recesses.

6. The memory device of claim 1, wherein the channel layer comprises a plurality of channel portions corresponding to the conductive layers of different layers, and the channel portions are separated from each other.

7. The memory device of claim 1, wherein the memory strings further comprise a second memory string adjacent to the first memory string, and the first memory string and the second memory string share the first conductive pillar.

8. The memory device of claim 1, wherein the memory strings further comprise a second memory string adjacent to the first memory string and separated from the first memory string.

9. A method of manufacturing a memory device, comprising providing a stack structure disposed on a substrate, the stack structure comprising a plurality of sacrificial layers and a plurality of insulating layers alternately stacked along a first direction; forming a plurality of openings traversing the stack structure; removing portions of the sacrificial layers to form a plurality of recesses between the sacrificial layers, the insulating layers, and the openings; forming a channel material layer in the recesses, wherein the channel material layer comprises a first side and a second side, the first side and the second side opposite to each other; forming a vertical hole extending along the first direction on the first side of the channel material layer; filling a conductive material in the vertical hole to form a first conductive pillar; forming an extended hole extending along the first direction on the second side of the channel material layer, and the channel material layer becomes a channel layer; a memory material and a conductive material are sequentially filled in the extended hole to form a memory structure and a second conductive pillar, respectively, wherein the memory structure surrounds the second conductive pillar and comprises a resistive memory material; and the sacrificial layers are removed, and conductive material is filled in locations where the sacrificial layers are removed to form conductive layers.

10. The method of claim 9, further comprising forming oxide material layers in the recesses before forming the channel material layer.

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