A system and method for testing pre-processing generation

Abstract

The present disclosure relates to a system for generating test pre-processing and related methods. The system includes a test device and a storage device including a user data block and a system block. The test device reads a stored initial system data snapshot from the system block, and the initial system data snapshot erases the system block and the user data block, writes data to a selected user data block, generates a system table associated with the erasure and writing of the selected user data block, replaces the initial system data snapshot with the system table, writes the replaced system table to the system block, and performs one or more tests on the storage device.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a testing system. Background Technology

[0002] The computing environment paradigm has shifted to ubiquitous computing systems that can be used anytime, anywhere. Consequently, the use of portable electronic devices such as mobile phones, digital cameras, and laptops has increased rapidly. These portable electronic devices typically use memory systems with memory devices, also known as data storage devices. The data storage device serves as either the main memory or auxiliary memory in the portable electronic device.

[0003] Because memory devices have no moving parts, memory systems using them offer excellent stability, durability, high data access speeds, and low power consumption. Examples of memory systems with these advantages include Universal Serial Bus (USB) memory devices, memory cards with various interfaces such as Universal Flash Memory (UFS), and solid-state drives (SSDs). Various testing tools can be used to test memory systems. Summary of the Invention

[0004] Aspects of the present invention include a system and method for generating test preconditions based on factory formatted states of a data storage device.

[0005] In one aspect of the invention, a test system includes a test apparatus and a storage device, the storage device including a plurality of system blocks and a plurality of user data blocks, the system blocks being configured to store an initial system data snapshot. The test apparatus is configured to: read the initial system data snapshot from the system blocks of the storage device, the initial system data snapshot being stored in the system blocks of the storage device and representing the factory format of the storage device; erase the system blocks and user data blocks; preprocess the storage device by writing data to one or more user data blocks selected from the user data blocks based on a set preprocessing; generate one or more system tables associated with the erasure and writing of the selected user data blocks; replace the initial system data snapshot with the system tables associated with the erasure and writing of the selected user data blocks; write the replaced system tables to the system blocks; and perform one or more tests on the preprocessed storage device to determine whether errors exist at least when writing data to the storage device.

[0006] In another aspect of the invention, a method for testing a storage device including a plurality of system blocks and a plurality of user data blocks, the system blocks storing an initial system data snapshot, the method comprising: reading the initial system data snapshot from the system blocks of the storage device, the initial system data snapshot being stored in the system blocks of the storage device and representing the factory format of the storage device; erasing the system blocks and user data blocks; preprocessing the storage device by writing data to one or more user data blocks selected from the user data blocks based on a set preprocessing; generating one or more system tables associated with the erasure and writing of the selected user data blocks; replacing the initial system data snapshot with the system tables associated with the erasure and writing of the selected user data blocks; writing the replaced system tables to the system blocks; and performing one or more tests on the preprocessed storage device to determine whether errors exist at least when writing data to the storage device.

[0007] Other aspects of the invention will become apparent from the following description. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating a data processing system according to an embodiment of the present invention.

[0009] Figure 2 This is a block diagram illustrating a memory system according to another embodiment of the present invention.

[0010] Figure 3 This is a circuit diagram illustrating a memory block of a memory device according to yet another embodiment of the present invention.

[0011] Figure 4 This is a diagram illustrating the state distribution of different types of cells in a memory device according to an embodiment of the present invention.

[0012] Figure 5 This is a diagram illustrating a test system according to another embodiment of the present invention.

[0013] Figure 6 This is a diagram illustrating a memory device according to yet another embodiment of the present invention.

[0014] Figure 7 This is a diagram illustrating the preprocessing and testing process of a storage device according to yet another embodiment of the present invention.

[0015] Figure 8 This is a diagram illustrating an example of test preprocessing for generating a storage device according to an embodiment of the present invention.

[0016] Figure 9 This is a diagram illustrating the operation of test preprocessing for generating a storage device according to another embodiment of the present invention.

[0017] Figure 10 This is a diagram illustrating an operational example of updating the address mapping table of a storage device according to yet another embodiment of the present invention. Detailed Implementation

[0018] Various embodiments of the invention are described in more detail below with reference to the accompanying drawings. However, the invention may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will convey the scope of the invention to those skilled in the art. Furthermore, references herein to “embodiment,” “another embodiment,” etc., are not necessarily directed to only one embodiment, and different references to any such phrases are not necessarily directed to the same embodiment. The term “embodiment” as used herein does not necessarily refer to all embodiments. Throughout this disclosure, the same reference numerals refer to the same parts in the drawings and embodiments of the invention.

[0019] This invention can be implemented in many ways, including: processes; apparatus; systems; computer program products implemented on computer-readable storage media; and / or processors, such as processors adapted to execute instructions stored on and / or provided by memory linked to the processor. In this specification, these embodiments or any other forms in which the invention may take place can be referred to as techniques. Generally, the order of operation of the disclosed processes can be varied within the scope of this invention. Unless otherwise stated, components such as processors or memory described as suitable for performing tasks can be implemented as general-purpose means or circuit components configured or otherwise programmed to perform tasks at a given time, or as specific means or circuit components manufactured to perform tasks. As used herein, the term "processor," etc., refers to one or more means, circuits, and / or processing cores suitable for processing data such as computer program instructions.

[0020] The methods, processes, and / or operations described herein can be executed by code or instructions to be run by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device can be those described herein or those other than the elements described herein. Because the algorithm (or operation of the computer, processor, controller, or other signal processing device) upon which the method is based is described in detail, the code or instructions for implementing the methods can transform a computer, processor, controller, or other signal processing device into a dedicated processor for executing the methods herein.

[0021] If implemented at least in part as software, the controller, processor, device, module, unit, multiplexer, generator, logic circuit, interface, decoder, driver, and other signal generation and signal processing functional components may include, for example, a memory or other storage device for storing, for example, code or instructions to be executed by a computer, processor, microprocessor, controller, or other signal processing device.

[0022] The following provides a detailed description of embodiments of the invention, along with accompanying drawings illustrating various aspects of the invention. The invention is described in conjunction with these embodiments, but is not limited to any particular embodiment. The invention includes many alternatives, modifications, and equivalents. Numerous specific details are set forth in the following description to provide a thorough understanding of the invention. These details are provided for illustrative purposes; the invention may be practiced without some or all of these specific details, as described in the claims. For clarity, known technical materials in the art related to the invention have not been described in detail so as not to unnecessarily obscure the invention.

[0023] Figure 1 This is a block diagram illustrating a data processing system 2 according to an embodiment of the present invention.

[0024] Reference Figure 1 The data processing system 2 may include a host device 5 and a memory system 10. The memory system 10 may receive requests from the host device 5 and operate in response to the received requests. For example, the memory system 10 may store data to be accessed by the host device 5.

[0025] The host device 5 can be implemented using any of a variety of electronic devices. In various embodiments, the host device 5 can be an electronic device such as a desktop computer, workstation, 3D television, smart television, digital audio recorder, digital audio player, digital picture recorder, digital picture player, and / or digital video recorder and digital video player. In various embodiments, the host device 5 can be a portable electronic device such as a mobile phone, smartphone, e-book reader, MP3 player, portable multimedia player (PMP), and / or portable game console.

[0026] The memory system 10 can be implemented using any of a variety of storage devices such as solid-state drives (SSDs) and memory cards. In various embodiments, the memory system 10 can be configured as a component of a variety of electronic devices such as: computers, ultra-mobile personal computers (PCs) (UMPCs), workstations, netbook computers, personal digital assistants (PDAs), portable computers, network tablet PCs, wireless phones, mobile phones, smartphones, e-book readers, portable multimedia players (PMPs), portable gaming devices, navigation devices, black boxes, digital cameras, digital multimedia broadcasting (DMB) players, 3D televisions, smart televisions, digital audio recorders, digital audio players, digital picture recorders, digital picture players, digital video recorders, digital video players, data center storage devices, devices capable of receiving and transmitting information in a wireless environment, radio frequency identification (RFID) devices, and a variety of electronic devices for home networks, a variety of electronic devices for computer networks, a variety of electronic devices for telematics networks, or a variety of components for computing systems.

[0027] The memory system 10 may include a controller 100 and a memory device 200. The controller 100 can control the overall operation of the memory device 200.

[0028] The memory device 200 can perform one or more erase, program, and read operations under the control of the controller 100. The memory device 200 can receive commands (CMD), addresses (ADDR), and data (DATA) via input / output lines. The memory device 200 can receive power (PWR) via power lines and control signals (CTRL) via control lines. Depending on the design and configuration of the memory system 10, the control signal CTRL may include, for example, a command latch enable signal, an address latch enable signal, a chip enable signal, a write enable signal, a read enable signal, and other operation signals.

[0029] The controller 100 and memory device 200 can be integrated into a single semiconductor device such as a solid-state drive (SSD). The SSD may include a storage device for storing data therein. In one embodiment of the invention, when the memory system 10 is used in an SSD, the performance of host devices coupled to the memory system 10 (e.g., Figure 1 The operating speed of the main unit 5).

[0030] The controller 100 and memory device 200 can be integrated into a single semiconductor device such as a memory card. For example, the controller 100 and memory device 200 can be integrated to configure PC cards, compact flash memory (CF) cards, smart media (SM) cards, memory sticks, multimedia cards (MMC), reduced-size multimedia cards (RS-MMC), micro-sized versions of MMC (micro MMC), secure digital cards (SD cards), mini secure digital cards (mini SD cards), micro secure digital cards (micro SD cards), high-capacity secure digital cards (SDHC), and / or universal flash memory (UFS).

[0031] Figure 2 This is a block diagram illustrating a memory system according to another embodiment of the present invention. For example, Figure 2 The memory system can be described Figure 1 The memory system 10 shown.

[0032] Reference Figure 2 The memory system 10 may include a controller 100 and a memory device 200. The memory system 10 can respond to requests from a host device (e.g., from...). Figure 1 The host device 5 operates upon request and, in particular, stores data to be accessed by the host device.

[0033] The memory device 200 can store data to be accessed by the host device.

[0034] The memory device 200 may be implemented using volatile memory devices such as dynamic random access memory (DRAM) and / or static random access memory (SRAM) or non-volatile memory devices such as read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric random access memory (FRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM) and / or resistive RAM (RRAM).

[0035] The controller 100 can control the storage of data in the memory device 200. For example, the controller 100 can control the memory device 200 in response to a request from a host device. The controller 100 can provide the host device with data read from the memory device 200, and can store the data provided by the host device into the memory device 200.

[0036] The controller 100 may include a storage device 110 connected via a bus 160, a control component 120 which may be implemented as a processor such as a central processing unit (CPU), an error correction code (ECC) component 130, a host interface (I / F) 140, and a memory interface (I / F) 150.

[0037] Storage device 110 can be used as working memory for memory system 10 and controller 100, and storage device 110 can store data for driving memory system 10 and controller 100. When controller 100 controls the operation of memory device 200, storage device 110 can store data used by controller 100 and memory device 200 for operations such as read operations, write operations, programming operations and erase operations.

[0038] Storage device 110 may be implemented using volatile memory such as static random access memory (SRAM) or dynamic random access memory (DRAM). As described above, storage device 110 can store data used by the host device in storage device 200 for read and write operations. To store data, storage device 110 may include program memory, data memory, write buffer, read buffer, mapping buffer, etc.

[0039] Control component 120 can control the general operation of memory system 10 and, in response to write or read requests from host device, control write or read operations on memory device 200. Control component 120 can drive firmware or other program instructions, which may be referred to as a flash translation layer (FTL), to control the operation of memory system 10. For example, FTL can perform operations such as logical-to-physical (L2P) mapping, wear leveling, garbage collection, and / or bad block handling. L2P mapping is referred to as logical block addressing (LBA).

[0040] ECC component 130 can detect and correct errors in data read from memory device 200 during a read operation. In one embodiment, when the number of error bits is greater than or equal to a threshold number of correctable error bits, ECC component 130 may not correct the error bits, but instead outputs an error correction failure signal indicating that the correction of error bits has failed.

[0041] In various embodiments, the ECC component 130 may perform error correction operations based on coded modulation such as low-density parity-check (LDPC) codes, Bosch-Chadhury-Hokungam (BCH) codes, turbo codes, turbo product codes (TPC), Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), or block-coded modulation (BCM). However, error correction is not limited to these techniques. Thus, the ECC component 130 may include any and all circuitry, systems, or devices suitable for error correction operations.

[0042] The host interface 140 can communicate with the host device through one or more of the following communication standards or interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), High-Speed ​​Peripheral Component Interconnect (PCI-e or PCIe), Small Computer System Interface (SCSI), Serial SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Enhanced Small Disk Interface (ESDI), and Electronic Integrated Drive (IDE).

[0043] Memory interface 150 can provide an interface between controller 100 and memory device 200, allowing controller 100 to control memory device 200 in response to requests from host device. Memory interface 150 can generate control signals for memory device 200 and process data under the control of control component 120. In one embodiment, when memory device 200 is flash memory such as NAND flash memory, memory interface 150 can generate control signals for that flash memory and process data under the control of control component 120.

[0044] For example Figure 2 The memory device 200 shown may include a memory cell array 210, control circuitry 220, voltage generation circuitry 230, row decoder 240, page buffer 250 (which may be an array of page buffers), column decoder 260, and input / output (I / O) circuitry 270. The memory cell array 210 may include multiple memory blocks 211 capable of storing data. The voltage generation circuitry 230, row decoder 240, page buffer 250, column decoder 260, and I / O circuitry 270 may form peripheral circuitry for the memory cell array 210. The peripheral circuitry may perform programming, reading, or erasing operations on the memory cell array 210. The control circuitry 220 may control the peripheral circuitry.

[0045] The voltage generation circuit 230 can generate operating voltages of various levels. For example, in an erase operation, the voltage generation circuit 230 can generate operating voltages of various levels, such as erase voltage and pass voltage.

[0046] The line decoder 240 can communicate electrically with the voltage generation circuit 230 and a plurality of memory blocks 211. The line decoder 240 can select at least one memory block among the plurality of memory blocks 211 in response to a line address generated by the control circuit 220, and transmit the operating voltage provided by the voltage generation circuit 230 to the selected memory block.

[0047] Page buffer 250 can be accessed via bit line BL ( Figure 3 (As shown) is connected to the memory cell array 210. The page buffer 250 can precharge the bit line BL with a positive voltage during programming and reading operations, transfer data to and receive data from the selected memory block, or temporarily store the transferred data in response to a page buffer control signal generated by the control circuit 220.

[0048] The column decoder 260 can transmit data to and receive data from the page buffer 250, or it can transmit data to and receive data from the input / output circuit 270.

[0049] Input / output circuit 270 can input from external devices (e.g., Figure 1 The controller 100 receives commands and addresses and transmits them to the control circuit 220, which transmits data from the external device to the column decoder 260, or outputs data from the column decoder 260 to the external device via the input / output circuit 270.

[0050] The control circuit 220 can control the peripheral circuits in response to commands and addresses.

[0051] Figure 3 This is a circuit diagram illustrating a memory block of a semiconductor memory device according to another embodiment of the present invention. For example, Figure 3 The storage block can be Figure 2 Any one of the storage blocks 211 in the memory cell array 210 shown.

[0052] Reference Figure 3 Storage block 211 may include multiple word lines WL0 to WLn-1, drain select line DSL, and source select line SSL connected to line decoder 240. These lines may be arranged in parallel with multiple word lines between DSL and SSL.

[0053] The memory block 211 may further include multiple cell strings 221 respectively connected to bit lines BL0 to BLm-1. Each column of cell strings may include one or more drain-select transistors (DSTs) and one or more source-select transistors (SSTs). In the illustrated embodiment, each cell string has one DST and one SST. In the cell string, multiple memory cells or memory cell transistors MC0 to MCn-1 may be connected in series between the drain-select transistors (DSTs) and source-select transistors (SSTs). Each of the memory cells may be formed as multiple layer cells. For example, each of the memory cells may be formed as a single-layer cell (SLC) storing 1 bit of data. Each of the memory cells may be formed as a multi-layer cell (MLC) storing 2 bits of data. Each of the memory cells may be formed as a three-layer cell (TLC) storing 3 bits of data. Each of the memory cells may be formed as a four-layer cell (QLC) storing 4 bits of data.

[0054] The source of each SST in a cell string can be connected to the common source line CSL, and the drain of each DST can be connected to the corresponding bit line. The gate of an SST in a cell string can be connected to SSL, and the gate of a DST in a cell string can be connected to DSL. The gates of memory cells spanning cell strings can be connected to the corresponding word lines. That is, the gate of memory cell MC0 is connected to the corresponding word line WL0, the gate of memory cell MC1 is connected to the corresponding word line WL1, and so on. A group of memory cells connected to a specific word line can be called a physical page. Therefore, the number of physical pages in memory block 211 can correspond to the number of word lines.

[0055] Page buffer 250 may include multiple page buffers 251 connected to bit lines BL0 to BLm-1. Page buffers 251 may operate in response to page buffer control signals. For example, during a read operation or a verification operation, page buffers 251 may temporarily store data received through bit lines BL0 to BLm-1 or sense the voltage or current of the bit lines.

[0056] In various embodiments of the invention, memory block 211 may include NAND flash memory cells. However, memory block 211 is not limited to this cell type, but may include NOR flash memory cells. Memory cell array 210 may be implemented as a hybrid flash memory combining two or more types of memory cells, or as a 1-NAND flash memory with the controller embedded within the memory chip.

[0057] Figure 4 This is a diagram illustrating the state distribution or programming voltage (PV) level distribution of different types of cells in a memory device according to an embodiment of the present invention.

[0058] Reference Figure 4 Each memory cell can be implemented using a specific type of cell, such as a single-level cell (SLC) for storing 1 bit of data, a multi-level cell (MLC) for storing 2 bits of data, a three-level cell (TLC) for storing 3 bits of data, or a four-level cell (QLC) for storing 4 bits of data. Typically, all memory cells in a particular memory device are of the same type, but this is not required.

[0059] An SLC can include two states, P0 and P1. P0 can represent the erase state, and P1 can represent the programmable state. Because an SLC can be set to one of two different states, each SLC can be programmed or store one bit according to a set encoding method. An MLC can include four states, P0, P1, P2, and P3. Among these states, P0 can represent the erase state, and P1 through P3 can represent the programmable state. Because an MLC can be set to one of four different states, each MLC can be programmed or store two bits according to a set encoding method. A TLC can include eight states, P0 through P7. Among these states, P0 can represent the erase state, and P1 through P7 can represent the programmable state. Because a TLC can be set to one of eight different states, each TLC can be programmed or store three bits according to a set encoding method. A QLC can include 16 states, P0 through P15. Among these states, P0 can represent the erase state, and P1 through P15 can represent the programmable state. Because a QLC can be set to one of sixteen different states, each QLC can be programmed or store four bits according to the set encoding method.

[0060] Re-reference Figure 2 and Figure 3 The memory device 200 may include a plurality of memory cells (e.g., NAND flash memory cells). The memory cells are arranged as follows: Figure 3The array arrangement of rows and columns is shown. Cells in each row are connected to word lines (e.g., WL0), while cells in each column are connected to bit lines (e.g., BL0). These word lines and bit lines are used for read and write operations. During a write operation, when the word line is asserted, the data to be written ("1" or "0") is provided to the bit line. During a read operation, the word line is asserted again, and the threshold voltage for each cell can then be obtained from the bit line. Multiple pages can share memory cells belonging to (i.e., connected to) the same word line. When the memory cell is implemented using MLC, the multiple pages include a most significant bit (MSB) page and a least significant bit (LSB) page. When the memory cell is implemented using TLC, the multiple pages include an MSB page, a middle significant bit (CSB) page, and an LSB page. When the memory cell is implemented using QLC, the multiple pages include an MSB page, a middle most significant bit (CMSB) page, a middle least significant bit (CLSB) page, and an LSB page. For example, an encoding scheme (e.g., Gray encoding) can be used to program memory cells in order to increase the capacity of a memory system 10 such as an SSD.

[0061] Figure 5 This is a diagram illustrating a test system 2 according to another embodiment of the present invention.

[0062] Reference Figure 5 The test system 500 may include a test device 510 and a storage device 520. In various embodiments of the present invention, the test device 510 may be a real host device communicatively connected to the storage device 520 (e.g., Figure 1 5) host device or virtual host device (i.e., host emulator).

[0063] Storage device 520 may include controller 100 and memory device 200. Memory device 200 may include multiple memory cells (e.g., NAND flash memory cells). Figure 3 As shown, memory cells in memory device 200 are arranged in an array of rows and columns. Cells in a specific row are connected to word lines (e.g., WL0), while cells in a specific column are connected to bit lines (e.g., BL0). These word lines and bit lines are used for read and write operations. During a write operation, when the word line is activated, data to be written ("1" or "0") is provided at the bit line. During a read operation, the word line is reactivated, and the threshold voltage for each cell can then be obtained from the bit line. Multiple pages can share memory cells belonging to (i.e., connected to) the same word line.

[0064] The controller 100 may include firmware (FW) or other program instructions that define specific categories of software for controlling various operations of the memory device 200 (e.g., read operations, write operations, and erase operations). In various embodiments of the invention, the firmware may reside in the storage device 110 and may be... Figure 2 The control component 120 executes the firmware. The firmware may include a host interface layer (HIL) for controlling communication with the test device 510, a flash translation layer (FTL) for controlling communication between the test device 510 and the memory device 200, and a flash interface layer (FIL) for controlling communication with the memory device 200.

[0065] Storage device 520 can be tested using various testing methods, such as black-box testing, white-box testing, and unit testing. The storage device 520 used for testing can be a hardware (HW) platform (i.e., a real storage device) or an emulator (i.e., a personal computer (PC)). Testing storage device 520 may include sending commands from test device 510 to storage device 520 and checking the expected results.

[0066] In various embodiments of the invention, storage device 520 may be a solid-state drive (SSD) implemented using a NAND flash memory device. The capacity of NAND flash memory devices has become so large that creating preprocessing in a simulated environment using only a scheme that runs arbitrary I / O workloads (i.e., commands) would take a considerable amount of time. For example, writing to the full capacity of a NAND flash memory device could take hours or days.

[0067] Optionally, a preprocessing generation scheme can be used for storage device 520. Generating and preparing preprocessing for testing means transforming storage device 520 into a specific predefined state. This preprocessing generation scheme can make preprocessing creation time independent of preprocessing complexity. However, firmware can be so complex that it is difficult to support all of its data structures. Therefore, embodiments of the present invention provide a scheme for efficiently creating preprocessing for testing storage devices. In particular, embodiments of the present invention provide a test system for generating test preprocessing for storage devices based on their factory formatting state.

[0068] Refer to the return Figure 5The testing device 510 can generate test preprocessing for the storage device 520 and provide the generated test preprocessing to the storage device 520, thereby preprocessing the storage device 520 (e.g., memory device 200) based on the test preprocessing. Further, the testing device 510 can run (execute) one or more tests on the preprocessed storage device 520. Specifically, the testing device 510 can generate preprocessing based on the state after the factory format including data structures of the storage device 520 has been dumped to the storage device 520. In one embodiment of the invention, the preprocessing can be generated for use in a simulation system (i.e., a NAND flash memory device simulator), and the entire preprocessing process can be executed on a virtual platform as described below.

[0069] Figure 6 This is a diagram illustrating a memory device 200 of a memory device 520 according to another embodiment of the present invention.

[0070] Reference Figure 6 The memory device 200 may include a plurality of system blocks 610 and a plurality of user data blocks 620. The plurality of user data blocks 620 may include blocks for storing user data (e.g., writing data). The plurality of system blocks 610 may include one or more firmware blocks 612, one or more system data blocks 614 for storing system data, and one or more system table blocks 616 for storing system tables.

[0071] Figure 7 This is a diagram illustrating the preprocessing and testing process of the storage device 520 according to another embodiment of the present invention.

[0072] Reference Figure 7 Preprocessing and testing procedures can be performed on storage device 520 (e.g., NAND flash memory device). These procedures can be performed by testing device 510. In one embodiment of the invention, testing device 510 can be a real host device or a virtual host device.

[0073] First, the NAND flash memory device 520 can be in an empty state (710). Second, a factory formatting process (715) can be performed on the NAND flash memory device 520 in an empty state. This factory formatting process may occur under factory conditions before the NAND flash memory device 520 reaches the user. A specific FW code can be used for factory formatting. The same FW code for factory formatting can be used on an emulator platform for the same purpose as it is used on a hardware platform.

[0074] As a result of the factory formatting process, an initial snapshot (i.e., version) of the system data structure (hereinafter referred to as the initial system data snapshot) may appear in the NAND flash memory device 520 (720), and therefore the state of the NAND flash memory device 520 may change. For example, Figure 8 Snapshot 810 shows the state of the NAND flash memory device 520 after the factory formatting process. In the example shown, the user data block may still be empty.

[0075] Test apparatus 510 can obtain an initial system data snapshot. In various embodiments of the invention, an initial system data snapshot can be obtained in a simulated environment using the raw FW code of the factory formatting process. Alternatively, an initial system data snapshot can be obtained from a hardware platform. In this embodiment where an initial system data snapshot is obtained from a hardware platform, test apparatus 510 may include a specific method for obtaining NAND content (i.e., the initial system data snapshot) from a real NAND flash memory device 520. For example, a vendor unique command (VUC) may be used to extract NAND content from the NAND flash memory device 520 (e.g., an SSD) to test apparatus 510.

[0076] The test apparatus 510 can generate test preprocessing (725) based on an initial system data snapshot and provide the generated test preprocessing to the NAND flash memory device 520. The storage device 520 can be preprocessed (730) based on the test preprocessing. For example, Figure 8 Snapshot 820 shows the state of the pre-processed NAND flash memory device 520. Test device 510 can run one or more tests (e.g., black-box test, white-box test, and cell test) on the pre-processed memory device 520 (735).

[0077] Figure 8 This is a diagram illustrating an example of generating test preprocessing for storage device 520 according to an embodiment of the present invention.

[0078] exist Figure 8 In the diagram, 810 represents the state (or snapshot) of storage device (e.g., NAND flash memory device) 520 after a factory formatting process. In the example shown, firmware block 612, system data block 614, and system table block 616 of storage device 520 can be written to have specific default settings (715) through a factory formatting process. System data block 614 may include N system data blocks. System table block 616 may include K system table blocks. Each system table block may include (M+1) mapping table groups, erase count tables, read count tables, and other system tables. Mapping table groups may be address mapping tables that store the mapping between logical block addresses (LBAs) and physical block addresses (PBAs). LBAs may be from... Figure 1 The host device 5 or Figure 5 The test device 510 receives an address associated with a specific operation (e.g., a write operation) of the memory device 200. The PBA may be an address indicating a specific memory region (e.g., a page) of the user data block 620 in the memory device 200.

[0079] Figure 8 820 in the diagram represents the state (or snapshot) of storage device 520 after preprocessing (725). In the example shown, some system table blocks 616 and some user data blocks 620 of storage device 520 can be preprocessed to have a specific state as shown in 820. In the first system table block, (M+1) mapping table groups and an erase count table can be preprocessed. Figure 8 As shown, state 820 indicates that 15 user data blocks in user data block 620 are preprocessed.

[0080] Figure 9 This is a diagram illustrating the operation of generating test preprocessing for storage device 520 according to another embodiment of the present invention. Figure 9 The operation can be performed by Figure 5 The test device 510 is used for testing.

[0081] Reference Figure 9 The testing device 510 can be used for, for example Figure 8 One or more system table blocks of the system block shown generate test preprocessing. When user data is in the user data block, the system table can be written to storage device 520. Because, as... Figure 8 An initial snapshot of the system table shown in 810 is already in storage device 520, therefore test device 510 can update the system table according to the read-modify-write procedure. The read-modify-write procedure can only be applied to system data, because user data is written to empty (erase) user data blocks. The read-modify-write procedure is described below.

[0082] exist Figure 9 In the example 910, test device 510 can read all system blocks from system block 610 to obtain an initial system data snapshot. In one embodiment of the invention, test device 510 can obtain the initial system data snapshot from a PC (if using a simulation environment) or a hardware platform (if using a real NAND flash memory device). The read system blocks (i.e., the initial system data snapshot) can be stored in memory (e.g., random access memory (RAM)).

[0083] Then, the test apparatus 510 can allocate a system table in memory. In various embodiments of the invention, the test apparatus 510 can allocate an address mapping table, an erase count table, and a read count table. Furthermore, the test apparatus 510 can erase system blocks and user data blocks.

[0084] exist Figure 9 In the 920 section, the test device 510 can preprocess the storage device 520 by writing data to one or more user data blocks 620 selected from the user data blocks based on a set preprocessing type. Logical block addresses (LBAs) can be distributed across the user data blocks based on the desired preprocessing type (or data write preprocessing). In various embodiments of the invention, the set preprocessing type may include sequential preprocessing for storage devices with sequential writes, random preprocessing for storage devices with random writes, and persistent preprocessing for storage devices in a persistent state. A persistent state means that the entire capacity of the storage device 520 has been written many times, such that the write amplification index (WAI) becomes stable without significant changes. After the LBAs are distributed across the user data blocks, system tables, such as address mapping tables and other system tables, may be populated.

[0085] In one embodiment, for sequential preprocessing, test device 510 may write user data blocks 620 with sequentially increasing LBAs. That is, test device 520 may write data sequentially to user data blocks 620, which are selected sequentially based on sequential preprocessing. In another embodiment, for random / continuous preprocessing, test device 510 may write user data blocks 620 with random LBAs and write some invalid data. That is, test device 520 may write data randomly to user data blocks 620, which are randomly selected based on random / continuous preprocessing. For random / continuous preprocessing, all valid data in a user data block may be at the beginning of the user data block, and all invalid data may be at the end of the user data block, thus not affecting garbage collection (GC). In some embodiments, for random / continuous preprocessing, each user block may not be written with 100% valid pages. For example, each user block may be written with 90% valid data and 10% invalid (dummy) data. Optionally, valid and invalid data may be uniformly mixed within a user data block.

[0086] exist Figure 9 In configuration 930, test apparatus 510 can generate one or more system tables associated with the erasure and writing of user data blocks. In one embodiment, test apparatus 510 can generate an address mapping table. For example... Figure 10As shown, after writing user data block N to a specific page (e.g., physical address (N, M)) associated with a specific logical block address (e.g., LBA X), the mapping information between logical and physical addresses in the address mapping table can be stored (updated). In another embodiment, test apparatus 510 can generate chipkill parity associated with the encoding of each mapping table block. For example, chipkill parity can be generated by performing an XOR operation on the bits of each mapping table block. Furthermore, when the written data has a regular structure for sequential preprocessing, the address mapping table can be generated without performing an XOR operation. In another embodiment, test apparatus 510 can generate an erase count table associated with the erasure of user data blocks.

[0087] exist Figure 9 In step 940, test apparatus 510 can replace the obtained system table (i.e., the initial system data snapshot) with the system table generated in memory. That is, the initial system data snapshot can be modified. In one embodiment, the initial erase count snapshot can be replaced by the generated erase count table data. For sequential / random preprocessing, the erase counter for all written user data blocks can be set to a specific value (e.g., "1"). For continuous preprocessing, the erase counter for all written user data blocks can be set to a predefined value depending on overprovisioning (OP) or any other (arbitrary) value. In another embodiment, the initial map table snapshot can be replaced by the generated map table data. As described above, chip-based parity checking can generate the map table data.

[0088] exist Figure 9 In the 950, test device 510 can write the modified system table (i.e., the initial system data snapshot) into system block 610.

[0089] The above read-modify-write process can be performed on a single FTL. If multiple FTL instances exist, operations 920 to 950 can be repeated for each FTL. After performing the above read-modify-write process, test device 510 can run one or more tests using the generated preprocessing.

[0090] Experiments were conducted to measure the performance of the preprocessing generation scheme and the direct scheme (without using the preprocessing generation scheme) described in embodiments of the present invention. A 1TB 3D TLC 8CH SSD simulator was used for the experiments. The results show that the preprocessing generation scheme of the present invention can shorten the preprocessing generation time compared with the direct scheme, as shown in Table 1.

[0091] Table 1

[0092]

[0093] As described above, embodiments of the present invention provide a scheme for generating test preprocessing based on the factory formatting state of a data storage device. This scheme can reduce the generation time of test preprocessing for testing data storage devices.

[0094] While the foregoing embodiments have been shown and described in considerable detail for clarity and understanding, the invention is not limited to the details provided. As those skilled in the art will understand from the foregoing disclosure, many alternative ways of carrying out the invention exist. Therefore, the disclosed embodiments are illustrative and not restrictive. The invention covers all modifications and alternatives. Furthermore, embodiments may be combined to form additional embodiments.

Claims

1. A test system comprising: a storage device including a plurality of system blocks and a plurality of user data blocks, the system blocks storing an initial system data snapshot; and a test device communicatively coupled to the storage device and the test device: reads the initial system data snapshot from the system blocks of the storage device, the initial system data snapshot stored in the system blocks of the storage device and representing a factory format of the storage device; erases the system blocks and the user data blocks; writes data to one or more user data blocks selected from among the user data blocks based on a set pre-processing, thereby pre-processing the storage device; generates one or more system tables associated with the erasing and writing of the selected user data blocks; replaces the initial system data snapshot with the system tables associated with the erasing and writing of the selected user data blocks; writes the replaced system tables to the system blocks; and performs one or more tests on the pre-processed storage device to determine whether there are errors at least when the data is written to the storage device.

2. The test system of claim 1, wherein the initial system data snapshot includes factory default settings stored in the storage device by the factory format.

3. The test system of claim 1, wherein the initial system data snapshot includes at least one of an initial address mapping table snapshot and an initial erase count table snapshot.

4. The test system of claim 3, wherein the system tables include an address mapping table storing mapping relationships between one or more logical block addresses and one or more physical block addresses of data blocks associated with the writing of the user data blocks and an erase count table storing erase counts of the user data blocks according to the erasing of the user data blocks.

5. The test system of claim 1, wherein the set pre-processing includes one of a sequential pre-processing, a random pre-processing, and a continuous pre-processing.

6. The test system of claim 5, wherein the test device writes the data sequentially to user data blocks, the user data blocks being sequentially selected based on the sequential pre-processing.

7. The test system of claim 5, wherein the test device writes the data randomly to the user data blocks, the user data blocks being randomly selected based on the random pre-processing.

8. The test system of claim 5, wherein the test device writes valid data to user data blocks among the plurality of user data blocks at a set beginning portion and invalid data to user data blocks among the plurality of user data blocks at a set end portion, the beginning portion and the end portion being selected based on the random pre-processing and the continuous pre-processing, or the test device writes a first percentage of valid data and a second percentage of invalid data to each user data block based on the random pre-processing and the continuous pre-processing, the first percentage being greater than the second percentage. ​ 9. The test system of claim 1, wherein the test device replaces the initial system data snapshot with the system table by: storing the read initial system data snapshot in a memory; and replacing the stored initial system data snapshot with the system table.

10. A method of testing a storage device, the storage device comprising a plurality of system blocks and a plurality of user data blocks, the system blocks storing an initial system data snapshot, the method comprising: reading the initial system data snapshot from the system blocks of the storage device, the initial system data snapshot stored in the system blocks of the storage device and representing a factory format of the storage device; erasing the system blocks and the user data blocks; writing data to one or more user data blocks selected from among the user data blocks based on a set pre-processing, thereby pre-processing the storage device; generating one or more system tables associated with the erasing and writing of the selected user data blocks; replacing the initial system data snapshot with the system tables associated with the erasing and writing of the selected user data blocks; writing the replaced system tables to the system blocks; and performing one or more tests on the pre-processed storage device to determine whether there are errors at least when the data is written to the storage device.

11. The method of claim 10, wherein the initial system data snapshot comprises factory default settings stored in the storage device by the factory format.

12. The method of claim 10, wherein the initial system data snapshot comprises at least one of an initial address mapping table snapshot and an initial erase count table snapshot.

13. The method of claim 12, wherein the system tables comprise an address mapping table storing mapping relationships between one or more logical block addresses and one or more physical block addresses of data blocks associated with the writing of the user data blocks and an erase count table storing erase counts of the user data blocks according to the erasing of the user data blocks.

14. The method of claim 10, wherein the set pre-processing comprises one of a sequential pre-processing, a random pre-processing, and a continuous pre-processing.

15. The method of claim 14, wherein writing data to the one or more user data blocks comprises writing the data sequentially to user data blocks, the user data blocks being sequentially selected based on the sequential pre-processing.

16. The method of claim 14, wherein writing data to the one or more user data blocks comprises writing the data randomly to user data blocks, the user data blocks being randomly selected based on the random pre-processing. ​ 17. The method of claim 14, wherein writing data to the one or more user data blocks comprises writing valid data to user data blocks at a set beginning portion of the plurality of user data blocks and writing invalid data to user data blocks at a set end portion of the plurality of user data blocks, the beginning portion and the end portion selected based on the random pre-processing and the persistent pre-processing, or writing data to the one or more user data blocks comprises writing a first percentage of valid data and a second percentage of invalid data to each user data block based on the random pre-processing and the persistent pre-processing, the first percentage greater than the second percentage.

18. The method of claim 10, wherein replacing the initial system data snapshot with the system table comprises: storing the read initial system data snapshot in memory; and replacing the stored initial system data snapshot with the system table.

19. A method of testing a storage device, the storage device having a plurality of system blocks and a plurality of user data blocks, the method comprising: generating an initial system data snapshot showing a state of the system blocks and the user data blocks based on factory default settings; erasing the system blocks and the user data blocks; pre-processing the storage device by writing data to one or more user data blocks of the storage device using a data write pre-processing that distributes logical block addresses among different user data blocks; and performing one or more tests on the pre-processed storage device to determine whether there are errors at least at the time the data is written to the storage device.

20. The method of claim 19, wherein the data write pre-processing comprises one of a sequential pre-processing, a random pre-processing, and a persistent pre-processing.

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