Integrated circuit interconnect structure

Abstract

The invention relates to an interconnect structure of an integrated circuit. A method of manufacturing an interconnect structure of an integrated circuit, which interconnect structure is intended to be encapsulated in an encapsulation resin in contact with a first surface of a protective layer. The protective layer is located on a first surface of the interconnect structure. The interconnect structure comprises a copper interconnect element, which extends at least partially through an insulating layer and is flush with the first surface of the interconnect structure. The manufacturing method comprises a structuring step of the protective layer or a step of forming the protective layer by structuring. The structuring step or the forming step is adapted to structure the first surface of the protective layer in the form of ridges and grooves alternating with each other.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to French patent application number 2108802, filed on August 20, 2021, entitled “Structure d'interconnexion d'uncircuit Intégré”, which is incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] This disclosure generally relates to integrated circuits, and more specifically to integrated circuit interconnect structures and methods of manufacturing such interconnect structures. Specifically, this disclosure relates to integrated circuit interconnect structures intended for encapsulation in an electronic package using resin. Background Technology

[0004] An integrated circuit includes electronic components formed inside and / or on top of a semiconductor layer (or substrate). The integrated circuit also includes interconnect structures located on the semiconductor layer. The interconnect structures include insulating layers having interconnect elements disposed therein, such as conductive vias, conductive tracks, and / or conductive pads. Vias pass through one or more insulating layers of the interconnect structure to electrically couple conductive tracks and / or circuit components and / or conductive pads formed on the upper layer of the interconnect structure (i.e., the layer furthest from the substrate).

[0005] Vias, conductive tracks, and especially conductive pads formed on the upper layers of interconnect structures can be made of copper, which is increasingly replacing aluminum in electronic circuits. In fact, copper is a better conductor than aluminum; copper interconnects can be smaller than aluminum interconnects and require less energy to conduct electricity.

[0006] Copper (Cu) interconnects, especially vias or conductive pads, are typically formed using a so-called "dotted" method, which includes:

[0007] - A step of performing photolithography on an insulating layer to form a resin pattern capable of forming an etching mask on the upper surface of the layer;

[0008] - The step of etching from the upper surface of an insulating layer covered with a resin pattern to form trenches and / or holes in the insulating layer;

[0009] - The step of depositing a copper layer to fill trenches and / or holes with copper; and

[0010] - A step of polishing (or "planarizing") the upper surface of the interconnect structure to make the copper pads flush with the upper surface of the insulating layer.

[0011] Because of this polishing step, the upper surface of the interconnect structure is planar, which makes it more difficult to encapsulate such integrated circuits in resin for integration into electronic packages. For example, an undesirable phenomenon of resin delamination at the level of contact with the interconnect structure may occur. Summary of the Invention

[0012] It is hoped that this packaging problem can be overcome in resins containing integrated circuits with this interconnect structure.

[0013] One embodiment overcomes all or some of the disadvantages of known interconnect structures.

[0014] One embodiment provides a method for manufacturing an interconnect structure for an integrated circuit, the interconnect structure of which is intended to be encapsulated in an encapsulating resin in contact with a first surface of a protective layer located on the first surface of the interconnect structure, the interconnect structure including copper interconnect elements that extend at least partially through an insulating layer and are flush with the first surface of the interconnect structure.

[0015] The manufacturing method includes a structuring step of the protective layer or a step of forming the protective layer by structuring, wherein the structuring step or forming step is adapted to structure the first surface of the protective layer in the form of alternating ridges and grooves.

[0016] The second side of the protective layer (corresponding to the side opposite the first side of the protective layer), for example, contacts the first side of the interconnect structure, thereby contacting the copper interconnect element that is flush with the first side of the interconnect structure.

[0017] Furthermore, the structure of the protective layer is specified to be formed from the first surface of the protective layer, which does not penetrate the protective layer, and therefore does not form an opening in the protective layer.

[0018] According to one embodiment, the structuring step includes:

[0019] - A photolithography step, suitable for forming a resin pattern on the first surface of the protective layer, wherein the formed resin pattern is in the form of a series of protrusions separated by openings; then

[0020] - An etching step from the first surface of the protective layer, wherein the etching step is adapted to etch at least a portion of the protective layer and is performed by forming a resin pattern of an etching mask to form ridges separated by grooves in the protective layer. According to the example, the protrusions are substantially rectangular.

[0021] According to a specific embodiment, the width of the groove is in the range of 50 nm to 5 μm, preferably in the range of 50 nm to 200 nm, and / or the height of the groove is in the range of 50 nm to 500 nm, preferably in the range of 100 nm to 200 nm.

[0022] According to one embodiment, the structuring step includes a step of chemically and mechanically polishing a first surface of the protective layer, the polishing step being adapted to form a roughness greater than or equal to 5 nanometers on the first surface of the protective layer, the roughness being defined by the root mean square height of the ridges of the surface relative to an average level defined for the surface.

[0023] According to a specific embodiment, the polishing step includes a slurry polishing solution containing abrasive balls.

[0024] According to an embodiment, the step of forming a protective layer through structuring includes:

[0025] - The step of etching a first surface of an insulating layer from a first surface of an interconnect structure, the etching step being performed between interconnect elements to form trenches in the insulating layer between interconnect elements, such that at least a portion of the interconnect element protrudes above the etched first surface of the insulating layer.

[0026] - The step of forming a protective layer in the trench and on the protruding parts of the interconnecting elements;

[0027] The etching and forming steps are adapted to structure the first surface of the protective layer in the form of alternating ridges and grooves.

[0028] According to a specific embodiment, the width of the trench is greater than or equal to 2 μm and / or the height of the trench is in the range of 20 to 300 nm, preferably 150 to 250 nm.

[0029] According to a specific embodiment, the height of the trench is in the range of 20 to 100 nm, preferably in the range of 25 to 75 nm.

[0030] According to one embodiment, the step of forming a protective layer by structuring includes, prior to the step of etching the insulating layer:

[0031] - Photolithography step, suitable for forming a resin pattern on the first surface of the interconnect structure, wherein the formed resin pattern is in the form of a series of protrusions separated by openings;

[0032] The etching of the insulating layer is performed by forming a resin pattern on an etching mask, with protrusions positioned to at least mask interconnect elements. According to the example, the protrusions are substantially rectangular.

[0033] According to one embodiment, the protective layer is formed by chemical vapor deposition technology, for example, by plasma-enhanced chemical vapor deposition.

[0034] One embodiment provides an integrated circuit including an interconnect structure located on a semiconductor layer. The integrated circuit is intended to be encapsulated in an encapsulating resin in contact with a first surface of a protective layer located on the first surface of the interconnect structure. The interconnect structure includes interconnect elements that at least partially extend through an insulating layer and are flush with the first surface of the interconnect structure. The first surface of the protective layer is configured in the form of alternating ridges and grooves.

[0035] The following embodiments can be applied to manufacturing methods and integrated circuits.

[0036] According to one embodiment, the root mean square height of the ridges formed on the first surface of the protective layer relative to a defined average level of the first surface is greater than or equal to 5 nm.

[0037] According to one embodiment, the interconnect element includes a copper conductive via.

[0038] According to one embodiment, the interconnect element further includes at least one copper conductive pad.

[0039] According to one embodiment, the integrated circuit includes a metallization layer formed in a trench in a protective layer and extending to a conductive pad, wherein the metallization layer forms an extension on a first surface of the protective layer.

[0040] According to one embodiment, the protective layer includes:

[0041] - A first nitride layer, for example, is made of silicon nitride or silicon carbonitride on a first surface of the interconnect structure;

[0042] - An oxide layer, for example, made of silicon oxide on the first nitride layer;

[0043] - A second nitride layer, for example, is made of silicon nitride or silicon carbonitride on an oxide layer.

[0044] According to a specific embodiment, alternating ridges and grooves are formed in the second nitride layer. Attached Figure Description

[0045] The above-described features and advantages, as well as others, will be described in detail in the following description of specific embodiments given by way of illustration rather than limitation with reference to the accompanying drawings, in which:

[0046] Figure 1 The interconnect structure of the integrated circuit is shown;

[0047] Figure 2 It is an image of an integrated circuit encapsulated in resin, for example Figure 1 Integrated circuits;

[0048] Figure 3A , Figure 3B , Figure 3C and Figure 3DThis is a cross-sectional view showing the interconnect structure at the end of successive steps of an example of a manufacturing method according to an embodiment;

[0049] Figure 4A , Figure 4B , Figure 4C and Figure 4D This is a cross-sectional view showing the interconnect structure at the end of successive steps in another example of the manufacturing method according to an embodiment;

[0050] Figure 5A , Figure 5B , Figure 5C and Figure 5D This is a cross-sectional view showing the interconnect structure at the end of successive steps in another example of the manufacturing method according to an embodiment;

[0051] Figure 6A , Figure 6B , Figure 6C and Figure 6D This is a cross-sectional view showing the interconnect structure at the end of successive steps of another example of the manufacturing method according to an embodiment. Detailed Implementation

[0052] In different figures, the same features are designated by the same labels. Specifically, common structural and / or functional features in various embodiments may have the same labels and may be provided with the same structure, dimensions, and material properties.

[0053] For clarity, the steps and elements useful for understanding the embodiments described herein have been detailed and described in detail. Specifically, the figures show the upper layer of the interconnect structure, i.e., the layer furthest from the semiconductor layer (substrate) having the interconnect structure. Furthermore, the figures show vias and conductive pads extending in the insulating layer of the upper layer, although the insulating layer may include one or more conductive tracks and / or other insulating layers. The interconnect structure also typically includes other layers below the upper layer, in which other interconnect elements are arranged.

[0054] Vias and conductive pads can typically be designated as “interconnect elements”, where interconnect elements may also include conductive tracks.

[0055] By convention, the protective layer is considered part of the interconnect structure in the following description. The upper surface of the interconnect structure before the protective layer is deposited can be designated as the "upper surface" of the interconnect structure. The upper surface of the interconnect structure coated with the protective layer can be designated as the "passivated upper surface" of the interconnect structure. The interconnect structure coated with the protective layer can be designated as the "passivated interconnect structure".

[0056] For clarity, the substrate with electronic components formed inside and / or on top of it is not shown in the accompanying drawings.

[0057] Unless otherwise stated, when referring to two elements connected together, it means there is no direct connection of any intermediate element other than a conductor, and when referring to two elements coupled together, it means that the two elements can be connected, or they can be coupled through one or more other elements.

[0058] In the following disclosure, unless otherwise stated, when referring to absolute position qualifiers such as the terms “front,” “back,” “up,” “down,” “left,” “right,” etc., or relative position qualifiers such as the terms “upper,” “lower,” “superior,” “subordinate,” etc., or directional qualifiers such as “horizontal,” “vertical,” etc., refer to the orientation shown in the figure.

[0059] When referring to the upper layer, horizontal, side, or surface, the layer, horizontal, side, or surface that is furthest from the substrate compared to another layer, horizontal, side, or surface that is closer to the substrate is being referred to.

[0060] In this specification, height and thickness represent dimensions along the vertical direction (the Z direction identified in the figures), and width represents dimensions along the X direction identified in the figures. The Y direction is not shown in the figures, but it corresponds to the direction perpendicular to both the X and Z directions. The X and Y directions form the XY plane, which is designated as the main plane of the integrated circuit.

[0061] Unless otherwise stated, “approximately,” “estimated,” “basically,” and “on the order of magnitude” mean within 10%, preferably within 5%.

[0062] Figure 1 The diagram shows the upper layer 1101 of an interconnect structure 110 of an integrated circuit 100. The upper layer includes conductive vias 112 and conductive pads 114, which pass through an insulating layer 116 and a first nitride layer 118. The first nitride layer 118 is disposed below the insulating layer 116. The vias and pads are flush with the upper surface 110A of the interconnect structure 110 (corresponding to the upper surface of the upper layer 1101 of the interconnect structure) and extend in depth within the insulating layer 116 at least until they reach the lower surface of the first nitride layer 118.

[0063] The interconnect structure 110 is coated with a protective layer 120, which includes:

[0064] - A second nitride layer 122 is disposed on the upper surface 110A of the interconnect structure 110;

[0065] - An oxide layer 124 is disposed on the second nitride layer 122;

[0066] - A third nitride layer 126 is disposed on the oxide layer 124.

[0067] Above the conductive pad 114, the protective layer 120 has been etched over its entire thickness, i.e., etched all the way down to the pad, to form a trench. A metallization layer 130 is then formed in the trench to contact the pad. This on-pad metallization, referred to as "OPM," forms an outgrowth protruding from the passivated upper surface 120A of the interconnect structure 110.

[0068] Vias 112 and pads 114 are made of copper (Cu). As described below, they are formed by a damascene method that includes polishing the upper surface of the integrated circuit so that the vias and copper pads are flush with the passivated upper surface 120A of the interconnect structure. In effect, due to this polishing step, the upper surface 110A of the interconnect structure is planar. Therefore, the protective layer 120 deposited on this planar upper surface also has a planar upper surface 120A.

[0069] The inventors have observed that such a planar surface makes it more difficult to encapsulate the integrated circuit in resin when assembling it in an electronic package: delamination of the encapsulating resin can be observed at the interface between the resin and the interconnect structure. This is in Figure 2 As can be seen in the image, Figure 2 Integrated circuit 100 is shown, for example Figure 1 The integrated circuit 100 includes an interconnect structure 110 on a substrate 150, the integrated circuit is encapsulated in a resin 160, and a layer 170 between the interconnect structure 110 and the resin 160 can be observed.

[0070] The solution to this delamination phenomenon is to form an interface layer suitable for adhesion to both the integrated circuit and the encapsulating resin, such as a polyimide layer. However, this solution involves annealing the polyimide layer to crosslink the polyimide material, which includes heating the integrated circuit / interface layer / resin assembly. This can be problematic or even incompatible when the substrate of the integrated circuit includes certain components, such as phase-change memory (PCM).

[0071] The inventors have provided an improved interconnect structure that overcomes all or part of the above-mentioned disadvantages of interconnect structures, and in particular, eliminates the annealing step.

[0072] Examples of interconnect structures and methods for manufacturing such interconnect structures will be described below. These examples are non-limiting, and various modifications will be made by those skilled in the art based on the instructions of this disclosure.

[0073] Figures 3A to 3D An example of an interconnect structure manufacturing method according to an embodiment is shown, along with the resulting interconnect structure.

[0074] Figure 3AThe initial structure is shown. The initial structure includes an upper layer 2101 of an integrated circuit interconnect structure 210. The upper layer includes vias 212 and pads 214 (e.g., ...). Figure 3D The vias and pads are conductive and pass through the insulating layer 216 and the first nitride layer 218. The first nitride layer 218 is located below the insulating layer 216 and can form a diffusion barrier layer and an etch stop layer.

[0075] The insulating layer 216 is used in an example made of silicon dioxide (SiO2). The first nitride layer 218 is used in an example made of silicon nitride (SiN) or silicon carbonitride (SiCN).

[0076] Vias 212 and pads 214 are flush with the upper surface 210A of interconnect structure 210 (corresponding to the upper surface of the upper layer 2101 of interconnect structure) and extend, for example, downwards to the insulating layer 216, at least downwards to the lower surface of the first nitride layer 218, as shown. All or part of the vias and / or pads may contact other vias in interconnect structure 210 in a lower layer (not shown). The vias and pads are made of copper (Cu).

[0077] Interconnect structure 210 is coated with a protective layer 220, shown as a multilayer structure, including:

[0078] - A second nitride layer 222, such as silicon nitride (SiN), is disposed on the upper surface 210A of the interconnect structure 210;

[0079] - An oxide layer 224, for example made of silicon oxide (SiO2), is disposed on the second nitride layer 222;

[0080] - A third nitride layer 226, for example made of silicon nitride (SiN), is disposed on the oxide layer 224.

[0081] The thickness of the second nitride layer 222 can be in the range of approximately 10 to 40 nm, for example, approximately 20 nm. The thickness of the oxide layer 224 can be in the range of approximately 400 to 600 nm, for example, approximately 500 nm. The thickness of the third nitride layer 226 can be in the range of approximately 300 to 700 nm, for example, approximately 500 nm.

[0082] For example, oxide layer 224 forms a so-called "getter" layer for capturing basic ions. Nitride layers 222 and 226, for example, can form a physical barrier against the diffusion of basic ions. Protective layer 220 is suitable for protecting integrated circuits, especially interconnect structures.

[0083] Different layers of the protective layer can be formed using chemical vapor deposition (CVD) technology, particularly plasma-enhanced chemical vapor deposition (PECVD) technology.

[0084] Figure 3B The structure obtained at the end of a photolithography step performed on the upper surface 220A of the protective layer 220 is shown, in which a resin pattern 240 is formed on the protective layer. In a cross-sectional view, as shown, the pattern 240 can take the form of a series of rectangular protrusions 242 separated by openings 244.

[0085] This pattern can be obtained through a traditional photolithography process, namely:

[0086] - The deposition includes at least one resin layer comprising at least one resist layer;

[0087] - A resist layer is exposed to radiation using a mask, which is formed of opaque and transparent areas and is defined to obtain the desired pattern in the resist; and

[0088] - A portion of the resist layer is dissolved in a specific aqueous or organic solution, called a developer, to develop the pattern.

[0089] The pattern shown is obtained, for example, using a positive resist. The resist portions exposed to radiation (through the transparent areas of the mask) become soluble in the developing solution, while the unexposed resist portions (through the opaque areas of the mask) remain insoluble in the developing solution. As a variation, the resist may be negative. Then, the resist portions exposed to radiation become insoluble in the developing solution, while the unexposed resist portions remain soluble in the developing solution.

[0090] At least one resin layer may be a single layer or have a multilayer structure including stacked resin layers, wherein at least one resin layer is photosensitive. According to an example embodiment, the resist layer is a multilayer structure including a carbon resin layer, an anti-reflective resin layer, and a resist layer. An opening 244 is then defined by these three resin layers.

[0091] Figure 3C The interconnect structure 210 obtained at the end of a subsequent step, in which the upper surface 220A of the protective layer 220 is etched downwards to a depth h1, is shown. In the example shown, the upper layer of the protective layer, namely the third nitride layer 226, is etched, and it is preferably partially etched, i.e., etched to a depth less than the thickness of the third nitride layer. Etching is performed by forming a resin pattern 240 that forms an etching mask, such that the etching occurs substantially at the openings 244 of the pattern and in the areas not covered by the pattern. The etching forms trenches 229 in the upper layer 226.

[0092] The etching of the third nitride layer 226 can be dry etching, for example, by implementing fluorine plasma.

[0093] Then, for example, by dry etching, a step to remove the resin pattern is performed, such as by applying oxygen plasma.

[0094] At the end of the etching of the third nitride layer 226 and the removal of the pattern 240, the upper surface 220A of the protective layer 220 has a serrated topology 227 (which may be specified by the more general term "ridge") separated by trenches 229 (which may be specified by the more general term "groove").

[0095] According to the example, each trench 229 may have a width l1 in the range of approximately 50 nm to 5 μm, preferably in the range of approximately 50 nm to 200 nm, for example, equal to approximately 100 nm, and / or a height h1 in the range of approximately 50 nm to 500 nm, preferably in the range of approximately 100 nm to 200 nm, for example, equal to approximately 150 nm. The width of each trench is defined by the width of the opening 244 in the resin pattern 240. The height of the trench is defined by the etching depth.

[0096] The trench structure on the passivated upper surface of the interconnect structure enables the bonding of the encapsulation resin 260 during integrated circuit assembly in the package, such as... Figure 3D As shown, the aforementioned delamination effect is reduced or even eliminated. Furthermore, the disclosed manufacturing method eliminates the annealing step, thereby limiting the thermal stress experienced by electronic components, particularly temperature-sensitive components, within the substrate.

[0097] Figure 3D This is a wider view of the interconnect structure 210 of integrated circuit 200, showing copper pads 214. During the etching steps described above, the third nitride layer 226 was etched to the same depth in the area around the copper pads 214 that was not masked by the resin pattern 240. Therefore, the upper surface of the protective layer 220 is substantially planar around the pads 214. The resin layer 260 bonded to the upper surface 220A of the protective layer has been shown.

[0098] Furthermore, a protective layer 220 has been etched across its entire thickness, extending down to the copper pad 214, to form a complementary trench. This complementary etching can be dry etching, for example, performed using fluorine plasma. A metallization layer is then typically formed in the complementary trench by chemical growth. This on-pad metallization 230 (OPM) contacts the copper pad 214 and forms an extension protruding from the passivated upper surface 220A of the interconnect structure. The metallization layer 230 is thus suitable for electrically coupling integrated circuit 200 to another integrated circuit. For example, the on-pad metallization 230 may comprise nickel, palladium, and / or gold, or any other suitable metal or metal alloy.

[0099] Figures 4A to 4D Another example of an interconnect structure manufacturing method according to an embodiment is shown, along with the resulting interconnect structure.

[0100] This alternative method example differs from the previous one primarily in that it does not include... Figure 3B and Figure 3C The photolithography and etching steps involved, which were replaced by polishing steps, resulted in interconnect structures that differed primarily from the topology of the protective layer, which exhibited roughness on its upper surface rather than having serrated edges separated by trenches.

[0101] Figure 4A It shows the relationship with Figure 3A The initial structure is similar to the one shown. Therefore, the initial structure includes an upper layer 3101 of the interconnect structure 310 of the integrated circuit. The upper layer 3101 shown includes copper vias 312 and copper pads 314, which pass through an insulating layer 316 and a first nitride layer 318 disposed beneath the insulating layer 316. The interconnect structure 310 is coated with a protective layer 320, which is shown as a multilayer structure, including:

[0102] - A second nitride layer 322 is disposed on the upper surface 310A of the interconnect structure 310;

[0103] -Oxide layer 324 disposed on second nitride layer 322;

[0104] - A third nitride layer 326 is disposed on the oxide layer 324.

[0105] Preferably, the third nitride layer 326 has an initial thickness greater than the thickness required at the end of the polishing step. For example, the initial thickness of the third nitride layer 316 is defined such that at the end of the polishing step, it is substantially equal to the root mean square (RMS) of approximately 500 nm at the level of the trench (defined below). For example, the initial thickness of the third nitride layer 326 may be approximately 600 nm.

[0106] Figure 4B The structure obtained at the end of the chemical mechanical polishing step of the third nitride layer 326 is shown. This polishing is adapted to create roughness on the upper surface of the third nitride layer. The roughness is preferably greater than about 5 nm.

[0107] As illustrated in the example, for a given surface, roughness is defined by the root mean square height of the surface's highest points (ridges) relative to the average level defined for the surface, a definition known under the abbreviation RMS. The average level of the surface is determined by the average height of the ridges and depressions (grooves) on the surface. For example, the values ​​of the ridges and depressions (grooves) are measured using atomic force microscopy, abbreviated as AFM.

[0108] Such a roughness value can be obtained by using a slurry polishing solution that includes abrasive balls. In the example, the diameter of the abrasive balls is selected to obtain the roughness value shown above.

[0109] Therefore, at the end of the polishing step, the upper surface 320A of the protective layer 320 has a rough surface with ridges 327 and recesses 329 (grooves).

[0110] The next steps, such as Figure 4C and Figure 4D As shown, similar to Figure 3D Related descriptions. Therefore, as Figure 4C As shown, a protective layer 320 has been etched across its entire thickness, extending down to the copper pad 314, to form a trench 328. This etching could be, for example, dry etching performed using fluorine plasma. A metallization layer 330 is then typically formed in the trench 328 by growth. Figure 4D As shown, the on-pad metallization 330 (OPM) contacts the copper pad 314 and forms an elongation protruding from the passivated upper surface 320A of the interconnect structure 310. For example, the on-pad metallization 330 includes nickel, palladium and / or gold or any other suitable metal or metal alloy.

[0111] The formation of this minimum roughness on the passivated upper surface of the interconnect structure enables the bonding of the encapsulating resin 360, such as Figure 4D As shown, this reduces or even eliminates the aforementioned delamination effect, while also eliminating the annealing step. This alternative manufacturing method also has the advantage of simplicity, particularly by eliminating the photolithography and etching steps, but also eliminating the chemical removal of resin.

[0112] Figures 5A to 5D Another example of a method for manufacturing an interconnect structure according to an embodiment is shown, along with the resulting interconnect structure.

[0113] Figure 5A The initial structure is shown, for example, with... Figure 3A and Figure 4A The associated initial structure includes an upper layer 4101 of interconnect structure 410, the upper layer including a conductive via 412 passing through an insulating layer 416 and a first nitride layer 418. The conductive via 412 is flush with the upper surface 410A of interconnect structure 401, and for example, the conductive via 412 extends at least downward in the insulating layer 416 to the lower surface of the first nitride layer 418, as shown.

[0114] However, the initial structure and combination Figure 3A and Figure 4AThe difference in the described structure lies in that the upper surface 410A of the interconnect structure 410 is coated with a monolayer, such as a monolayer nitride layer 415, which is made of silicon nitride (SiN) or silicon carbonitride (SiCN). In other words, a protective layer has not yet been formed. The second nitride layer 415 can form an intermediate layer between the copper of the conductive via and the resin intended to be deposited in the next photolithography step. The intermediate layer forms a diffusion barrier layer and an etch stop layer, as well as a layer for protecting the copper from the environment (e.g., preventing air oxidation). Furthermore, it is preferable not to perform photolithography directly on the copper to avoid oxidation and / or corrosion of the copper, especially if the resin must be removed by wet cleaning.

[0115] Figure 5B The structure obtained at the end of a photolithography step performed on the second nitride layer 415, in which a resin pattern 440 is formed on the second nitride layer, is shown. In the cross-sectional view, the pattern 440 shown takes the form of continuous rectangular protrusions 442, which are perpendicularly arranged to the vias 412 and separated by openings 444. The photolithography step can be similar to... Figure 3B The steps described.

[0116] Figure 5C The structure obtained at the end of a subsequent step where the second nitride layer 415 and the insulating layer 416 are etched to depth h2 is shown. The insulating layer is preferably partially etched, i.e., etched to a depth less than the thickness of the insulating layer. Etching is performed via a resin pattern 440 forming an etching mask, such that the etching occurs substantially at the openings 444 of the pattern and in areas not covered by the pattern. The etching forms trenches 419 in the insulating layer 416.

[0117] The height h2 of trench 419 is defined by the etching depth. The height h2 of trench 419 can be in the range of about 20 nm to 300 nm, preferably in the range of about 150 nm to 250 nm, for example, equal to about 200 nm.

[0118] The width l2 of the groove 419 is preferably greater than or equal to about 2 μm in order to allow for the insertion of a protective layer, as described below.

[0119] The etching of insulating layer 416 is preferably selective so that copper is not etched. This etching of the insulating layer can be dry etching, for example, by applying fluorine plasma. According to the example, the etching time can be adjusted to etch down to a given depth.

[0120] Then, perform the step of removing the resin pattern, similar to... Figure 3C The relevant description.

[0121] Figure 5D The passivated interconnect structure 410 obtained at the end of the formation step of the protective layer 420 is shown, which is shown as a multilayer structure including:

[0122] - A third nitride layer 422 is disposed in the trench 419 and on the unetched portion of the second nitride layer 415;

[0123] -Oxide layer 424 disposed on third nitride layer 422;

[0124] - A fourth nitride layer 426 is disposed on the oxide layer 424.

[0125] Similar to Figure 3A According to related descriptions, different layers of the protective layer can be formed by CVD, especially by PECVD.

[0126] At the end of the step of forming the structured protective layer, the upper surface 420A of the protective layer 420 has a structured topology of serrations 427 (ridges) separated by trenches 429 (grooves). This structuring of the passivated upper surface of the interconnect structure enables the bonding of encapsulating resin 460, such as... Figure 5D As shown, the above-mentioned stratification effect is reduced or even eliminated, while the annealing step is cancelled.

[0127] Although not shown, the interconnect structure may include conductive pads and a metallization layer on the pads, similar to bonding. Figure 3D As described.

[0128] Figures 6A to 6D Another example of a method for manufacturing an interconnect structure according to an embodiment is shown, along with the resulting interconnect structure. This other method example is combined with... Figures 5A to 5D The main difference in the described method example is that it does not include a photolithography step. For example, it is not necessary to deposit a nitride layer on the upper surface of the interconnect structure.

[0129] Figure 6A An initial structure is shown, which includes an upper layer 5101 of interconnect structure 510, the upper layer including conductive vias 512 and conductive pads 514 (e.g., through insulating layer 516 and first nitride layer 518) passing through insulating layer 516 and first nitride layer 518. Figure 6D (As shown). The conductive via 512 is flush with the upper surface 510A of the interconnect structure 510 and extends along the depth into the insulating layer 516, for example, at least downward to the lower surface of the first nitride layer 518, as shown.

[0130] Figure 6B The structure obtained at the end of the subsequent step of etching the insulating layer 516 around the conductive via 512 and conductive pad 514 to a depth h3 is shown (e.g.) Figure 6D (As shown). The insulating layer is preferably partially etched, that is, etched to a depth less than the thickness of the insulating layer. This etching allows the insulating layer around the conductive via 512 and the conductive pad 514 to be completely recessed, thereby forming the copper protrusion 517 and the trench 519 between the protrusions.

[0131] The height of the trench is defined by the etching depth. The height h3 of the trench 519 can be in the range of about 20 nm to 100 nm, preferably in the range of about 25 nm to 75 nm, for example, equal to about 50 nm.

[0132] The width l3 of the trench 519 is defined by the distance between vias 512 or between vias 512 and pads 514.

[0133] The etching of the insulating layer 516 is preferably selective so that copper is not etched. The etching of the insulating layer can be dry etching, such as by performing a fluorine plasma etching, or it can be wet etching, specifically through a fluorinated acid solution, such as hydrofluoric acid. According to examples, the acid concentration in the solution and / or the etching time can be adjusted to etch down to a given depth.

[0134] Figure 6C The passivated interconnect structure 510 obtained at the end of the step of forming the protective layer 520 is shown. The protective layer 520 is shown as a multilayer structure, including:

[0135] - A second nitride layer 522 is disposed on the copper protrusion 517 and in the trench 519;

[0136] -Oxide layer 524 is disposed on second nitride layer 522;

[0137] - A third nitride layer 526 is disposed on the oxide layer 524.

[0138] With already combined Figure 3A or Figure 5D Similar to the description, different layers of the protective layer can be formed by CVD, specifically by PECVD.

[0139] At the end of the step of forming the structured protective layer, the upper surface 520A of the protective layer 520 has a structured topology of serrations 527 (ridges) separated by trenches 529 (grooves). This structuring of the passivated upper surface of the interconnect structure enables the bonding of encapsulating resin 560, such as... Figure 6D As shown, this reduces or even eliminates the aforementioned delamination effect, while also eliminating the annealing step. Another example of this manufacturing method also has the advantage of simplicity, particularly by eliminating the photolithography step, but also eliminating the chemical resin removal step.

[0140] Figure 6D This is a wider view of the interconnect structure 510 of integrated circuit 500, showing copper pads 514. Similar to... Figure 3D or Figure 4C and 4DAccording to the relevant description, the protective layer 520 has been etched over its entire thickness, i.e., all the way to the pads, to form complementary trenches, and then a metallization layer is formed in the complementary trenches. The on-pad metallization 530 (OPM) contacts the copper pad 514 and forms an elongation protruding from the passivated upper surface 520A of the interconnect structure 510. For example, the on-pad metallization 530 includes nickel, palladium, and / or gold, or any other suitable metal or metal alloy. Encapsulating resin 560 is deposited on the assembly.

[0141] The manufacturing methods and interconnect structures obtained according to different embodiments can be used in field applications with integrated circuits intended to be encapsulated in encapsulating resin, with associated delamination risks. These manufacturing methods and interconnect structures are particularly suitable for integrated circuits with integrated phase-change memory (PCM).

[0142] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations will emerge. Specifically, the interconnect structure may include multiple conductive pads and multiple pad-on-metallization (OPM). The protective layer may differ from the protective layer disclosed in the different embodiments, for example, comprising one or two layers, or even more than three layers, and / or each different layer may be made of a different material than described, while achieving similar functionality.

[0143] For example, the protective layer may include a fourth layer above or below the three layers. This fourth layer is made of an insulating or dielectric material, such as an alloy or compound comprising aluminum or hafnium: Al₂O₃, HfO₂, Hf i Al j O k AlN, Al i N j O k HfN i (where i, j, and k can be freely chosen by those skilled in the art).

[0144] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variations is within the capabilities of those skilled in the art.

[0145] The various embodiments disclosed herein provide a method for manufacturing interconnect structures (210, 310, 410, 510) for integrated circuits (200, 300, 400, 500). The interconnect structures are intended to be encapsulated in an encapsulating resin in contact with a first surface (220A, 320A, 420A, 520A) of a protective layer (220, 320, 420, 520). A second side of the protective layer is located on the first surface (210A, 310A, 410A, 510A) of the interconnect structure. The interconnect structure includes copper interconnect elements (212, 214, 312, 314, 412, 512, 514), which at least partially extend through an insulating layer (216, 316, 416, 516) and are flush with the first surface of the interconnect structure, such that the second side of the protective layer contacts the copper interconnect elements. The manufacturing method can be summarized as including a structuring step of a protective layer or a step of forming a protective layer by structuring, wherein the structuring step or the forming step is adapted to structure the first surface of the protective layer in the form of alternating ridges (227, 327, 427, 527) and grooves (229, 329, 429, 529).

[0146] The structuring steps may include:

[0147] - A photolithography step is used to form a resin pattern (240) on the first surface (220A) of the protective layer (220), the formed resin pattern being in the form of a series of protrusions (242) separated by openings (244); then

[0148] - An etching step from a first surface (220A) of a protective layer (220), said etching step being adapted to etch at least a portion of the protective layer and performed via a resin pattern (240) forming an etching mask to form ridges (227) separated by grooves (229) in the protective layer.

[0149] The width (l1) of the groove (229) can be in the range of 50 nm to 5 μm, preferably in the range of 50 nm to 200 nm, and / or the height (h1) of the groove (229) can be in the range of 50 nm to 500 nm, preferably in the range of 100 nm to 200 nm.

[0150] The structuring step may include a step of chemically mechanically polishing a first surface (320A) of the protective layer (320), the polishing step being adapted to form a roughness greater than or equal to 5 nm on the first surface of the protective layer, the roughness being defined by the root mean square height of the ridges of the surface relative to an average level defined for the surface.

[0151] The polishing step can be performed using a slurry polishing solution containing abrasive balls.

[0152] The step of forming a protective layer by structuring may include: - etching a first surface of an insulating layer (416, 516) from a first surface (410A, 510A) of an interconnect structure (410, 510), the etching step being performed between interconnect elements (412, 512, 514) to form trenches (419, 519) between the interconnect elements in the insulating layer, such that at least a portion of the interconnect elements protrudes above the etched first surface of the insulating layer;

[0153] - The step of forming a protective layer (420, 520) in the trenches (419, 519) and on the protrusions of the interconnecting elements; the etching and forming steps are adapted to structure the first surface (420A, 520A) of the protective layer in the form of alternating ridges (427, 527) and trenches (429, 529).

[0154] The width (l2) of the trench (419) is preferably greater than or equal to 2 μm and / or the height (h2) of the trench (419) is in the range of 20 nm to 300 nm, preferably in the range of 150 nm to 250 nm.

[0155] The height (h3) of the trench (519) can be in the range of 20nm to 100nm, preferably in the range of 25nm to 75nm.

[0156] The step of forming a protective layer by structuring may include, prior to the step of etching the insulating layer (416): - a photolithography step adapted to form a resin pattern (440) on a first surface (410A) of the interconnect structure (410), the formed resin pattern being in the form of a series of protrusions (442) separated by openings (444); the step of etching the insulating layer (416) is performed via the resin pattern (440) forming an etching mask, the protrusions (442) being positioned to at least cover the interconnect elements (412).

[0157] The protective layers (420, 520) can be formed using chemical vapor deposition techniques, such as plasma-enhanced chemical vapor deposition.

[0158] An integrated circuit (200, 300, 400, 500) can be summarized as including interconnect structures (210, 310, 410, 510) disposed on a semiconductor layer. The integrated circuit is intended to be encapsulated in an encapsulating resin in contact with a first surface (220A, 320A, 420A, 520A) of a protective layer (220, 320, 420, 520), wherein a second side of the protective layer is located on the first surface (220A, 320A, 420A, 520A) of the interconnect structure. A) The interconnect structure includes interconnect elements (212, 214, 312, 314, 412, 512, 514), which at least partially extend through the insulating layer (216, 316, 416, 516) and are flush with the first surface of the interconnect structure, such that the second side of the protective layer contacts the copper interconnect elements, and the first surface of the protective layer is structured in the form of alternating ridges (227, 327, 427, 527) and grooves (229, 329, 429, 529).

[0159] The average secondary height of the ridges (227, 327, 427, 527) formed on the first surface (220A, 320A, 420A, 520A) of the protective layer (220, 320, 420, 520) relative to a defined average level of the first surface can be greater than or equal to 5 nm.

[0160] Interconnect elements may include copper conductive vias (212, 312, 412, 512).

[0161] Interconnecting elements may also include at least one copper conductive pad (214, 314, 514).

[0162] The integrated circuit (200, 300, 500) may include a metallization layer (230, 330, 530) formed in a protective layer (220, 320, 520) and extending into a conductive pad (214, 314, 514) in a trench (328), the metallization layer forming an extension of a first surface (220A, 320A, 520A) of the protective layer.

[0163] The protective layer (220, 320, 420, 520) may include: a first nitride layer (222, 322, 422, 522), for example made of silicon nitride or silicon carbonitride, on the first surface (210A, 310A, 410A, 510A) of the interconnect structure (210, 310, 410, 510);

[0164] - An oxide layer (224, 324, 424, 524), for example made of silicon oxide, is placed on the first nitride layer (222, 322, 422, 522);

[0165] - A second nitride layer (226, 326, 426, 526), ​​for example made of silicon nitride or silicon carbonitride, is located on the oxide layer (224, 324, 424, 524).

[0166] Alternating ridges (227, 327, 426, 526) and grooves (229, 329, 429, 529) can be formed in the second nitride layer (226, 326, 426, 526).

[0167] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments based on the detailed description above. Generally, the terminology used in the appended claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of the equivalents to which these claims are entitled. Therefore, the claims are not limited by this disclosure.

Claims

1. A method comprising: An interconnect structure for manufacturing integrated circuits, the interconnect structure including an insulating layer and conductive interconnect elements extending through the insulating layer, each of the conductive interconnect elements having a first surface coplanar with a first surface of the insulating layer; as well as A protective layer is formed on the interconnect structure, the protective layer comprising a first nitride layer, a second insulating layer, and a second nitride layer, the second insulating layer being between the first nitride layer and the second nitride layer, the first nitride layer being on a first surface of the conductive interconnect element and on a first surface of the insulating layer, and the second nitride layer comprising alternating ridges and grooves.

2. The method according to claim 1, wherein forming the protective layer comprises: A resin pattern is formed on the first surface of the protective layer by photolithography, the resin pattern being a series of protrusions separated by openings; as well as The ridges separated by the grooves are formed in the protective layer by etching from the first surface of the protective layer, the etching including etching at least a portion of the protective layer using the resin pattern as an etching mask.

3. The method of claim 2, wherein the width of the groove is in the range of 50 nm to 5 µm, and the height of the groove is in the range of 50 nm to 500 nm.

4. The method according to claim 1, wherein forming the protective layer comprises: The first surface of the protective layer is chemically and mechanically polished, the polishing comprising forming a roughness greater than or equal to 5 nm on the first surface of the protective layer, the roughness being defined by the root mean square height of the ridges of the surface relative to an average level defined for the surface.

5. The method of claim 4, wherein the polishing comprises applying a slurry polishing solution, the slurry polishing solution comprising abrasive balls.

6. The method of claim 1, wherein forming the protective layer comprises: A trench is formed between the interconnecting elements in the insulating layer such that at least a protruding portion of the interconnecting element protrudes above a first surface of the insulating layer. The formation of the trench includes etching the first surface of the insulating layer from the first surface of the interconnecting structure, the etching being performed between the interconnecting elements. as well as The protective layer is formed in the trench and on the protruding portion of the interconnecting element.

7. The method of claim 6, wherein the width of the trench is greater than or equal to 2µm, and the height of the trench is in the range of 20nm to 300nm.

8. The method of claim 6, wherein the height of the trench is in the range of 20 nm to 100 nm.

9. The method of claim 6, wherein forming the protective layer comprises, prior to etching the first surface of the insulating layer: A resin pattern is formed on the first surface of the interconnect structure by photolithography. The resin pattern includes a series of protrusions separated by openings. Etching of the first surface of the insulating layer is performed via the resin pattern forming an etching mask. The protrusions are positioned to at least shield the interconnect elements.

10. The method of claim 6, wherein the protective layer is formed by chemical vapor deposition.

11. The method according to claim 1, further comprising: An encapsulating resin is formed in contact with the first surface of the protective layer.

12. An integrated circuit, comprising: Semiconductor layer; The interconnect structure on the semiconductor layer includes an insulating layer and interconnect elements, the interconnect elements extending at least partially through the insulating layer and flush with a first surface of the interconnect structure; A protective layer on the first surface of the interconnect structure, the first surface of the protective layer being an alternation of ridges and grooves.

13. The integrated circuit of claim 12, wherein the average secondary height of the ridge formed on the first surface of the protective layer relative to a defined average level of the first surface is greater than or equal to 5 nm.

14. The integrated circuit of claim 12, wherein the interconnect element comprises a copper conductive via.

15. The integrated circuit of claim 14, wherein the interconnect element comprises at least one copper conductive pad.

16. The integrated circuit according to claim 15, further comprising: A metallization layer, formed in the trenches of the protective layer and extending into the conductive pads, forms an extension of the first surface of the protective layer.

17. The integrated circuit of claim 12, wherein the protective layer comprises: A first nitride layer on the first surface of the interconnect structure; An oxide layer on the first nitride layer; A second nitride layer on the oxide layer.

18. The integrated circuit of claim 17, wherein the alternation of the ridges and the trenches is formed in the second nitride layer.

19. The integrated circuit according to claim 12, further comprising: Encapsulating resin in contact with the first surface of the protective layer.

20. A method comprising: Forming an interconnect structure on a substrate, the formation of the interconnect structure comprising: The first nitride layer is formed; An insulating layer is formed on the first nitride layer; Interconnect elements are formed extending through the first nitride layer and the insulating layer, each interconnect element having a first surface coplanar with the first surface of the insulating layer; A protective layer is formed on the interconnect structure, the formation of the protective layer comprising: A second nitride layer is formed on the interconnect structure, and the second nitride layer is in contact with the first surface of the insulating layer and the first surface of the interconnect element; An oxide layer is formed on the second nitride layer; and A third nitride layer is formed on the oxide layer; A groove is formed in the third nitride layer; and Encapsulation material is formed on the protective layer and in the grooves in the third nitride layer.

21. The method of claim 20, wherein forming the groove comprises forming a trench in the third nitride layer.

22. The method of claim 20, wherein, The formation of the groove includes creating a roughness greater than or equal to 5 nm in the third nitride layer through chemical mechanical polishing, and The roughness is defined by the root mean square height of the ridges of the surface relative to the average level defined for the surface.

23. The method of claim 20, wherein, The formation of the groove includes forming a trench in the insulating layer; The second nitride layer is formed on the insulating layer and in the trench; The oxide layer is formed on the second nitride layer and in the trench; The third nitride layer is formed on the oxide layer and in the trench; as well as The encapsulation material is formed on the third nitride layer and in the trench.

Images