Shared memory interconnection device, arbitration method and arbitration circuit

By designing a hierarchical interconnect network and a distributed arbitration module, the high hardware complexity and high latency of traditional shared memory interconnect architectures are solved, achieving low latency and high-efficiency data transmission, which is suitable for shared memory access in artificial intelligence accelerator chips.

CN122086648AActive Publication Date: 2026-05-26MOFFETT AI TECHNOLOGY SHENZHEN CO LTD
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Patent Information

Application Number
CN202610535153.9
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2026-04-22
Publication Date
2026-05-26
Estimated Expiration
2046-04-22

AI Technical Summary

Technical Problem

Traditional shared memory interconnect architectures in artificial intelligence chips suffer from high hardware complexity, large area overhead, high power consumption, and high latency, making it difficult to meet the requirements of low-latency intensive access.

Method used

A hierarchical interconnection network and a distributed arbitration module are adopted, including an outer routing network and an inner switching network. Data routing and arbitration are performed through butterfly switching units and cross-connect switching modules. The arbitration module handles conflicts based on port weights, realizing dynamic arbitration and weight management.

Benefits of technology

While reducing hardware area overhead, it ensures local bandwidth and low latency, solves the interconnection problem of shared memory in large-scale AI chips, and improves data transmission efficiency.

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Abstract

The invention provides a shared memory interconnection device, an arbitration method and an arbitration circuit, and relates to the technical field of integrated circuit interconnection, the implementation scheme is as follows: a hierarchical interconnection network comprises an outer layer routing network and an inner layer switching network, the outer layer routing network comprises a multi-stage switching network consisting of a plurality of butterfly switching units, and the inner layer switching network comprises a plurality of butterfly switching units; the routing module is used for routing data flow packets of the input port to a plurality of subgroups of an inner-layer switching network, and the inner-layer switching network comprises a plurality of crossbar switch switching modules and is used for performing local non-blocking switching; the arbitration module is used for maintaining the weight of each input port, determining an arbitration result among the ports with conflicts based on the weight, progressively increasing the weight of the corresponding port by a preset increment when the arbitration is not passed, and recovering the weight of the corresponding port to an initial value when the arbitration is passed, the arbitration result of each port is determined by cascading and transmitting the arbitration state among the ports with conflicts, so that the local bandwidth and low delay can be ensured while the hardware area overhead can be greatly reduced.
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