Bit-Loading-Based HPLC Signal Processing Method

Abstract

This invention discloses a bit-loading-based HPLC signal processing method, belonging to the field of power line carrier communication technology. The bit-loading-based HPLC signal processing method includes: reading bit data from a channel interleaving module and sequentially writing it into a first bit buffer queue according to a preset number of bits to be read from the channel interleaving module; in bit-loading mode, determining the target number of bits to be filled for each subcarrier based on the modulation scheme corresponding to each subcarrier; different modulation schemes correspond to different target bit numbers; sequentially reading the target number of bits from the first bit buffer queue according to the writing order, and mapping the read-out bit data to the corresponding subcarrier for modulation and transmission. This invention achieves efficient rate matching for data processing in bit-loading mode and data transmission without subcarriers crossing physical blocks.

Description

Technical Field

[0001] This invention belongs to the field of power line carrier communication technology, and particularly relates to an HPLC signal processing method based on bit loading. Background Technology

[0002] In the field of high-speed power line communication (HPLC), in order to cope with complex channel environments and improve transmission efficiency, communication systems typically employ multi-carrier modulation technology. In the new generation of technology, a bit loading mode has been introduced. This technology can dynamically allocate appropriate modulation methods according to the channel quality of each subcarrier, thereby significantly improving spectrum utilization.

[0003] In bit-loading mode, the modulation order of each subcarrier is different, resulting in inconsistent bit counts carried by each subcarrier at the same transmission time. Meanwhile, in existing signal processing links, some processing stages still perform data processing with fixed bit granularity or fixed timing. When these two processing methods are superimposed on the same data path, inconsistent data timing can easily occur, leading to waiting, blocking, or reduced throughput during data processing, thus affecting the overall system transmission efficiency. Summary of the Invention

[0004] This invention aims to at least solve one of the technical problems existing in the prior art. To this end, this invention proposes a bit-loading-based HPLC signal processing method to achieve efficient matching of data processing rates in bit-loading mode.

[0005] In a first aspect, the present invention provides a bit-loading-based HPLC signal processing method applied at a signal transmitting end; the signal transmitting end includes, in processing order, a channel interleaving module, a first bit buffer queue, and a bit mapping module; the method includes:

[0006] Bit data is read from the channel interleaving module and written into the first bit buffer queue in sequence according to the preset number of bits to be read from the channel interleaving module;

[0007] In bit loading mode, the target number of bits to be filled for each subcarrier is determined based on the modulation scheme corresponding to each subcarrier; the target number of bits is different for different modulation schemes.

[0008] The target number of bits are read sequentially from the first bit buffer queue in the order of writing, and the read-out bits are mapped to the corresponding subcarriers for modulation and transmission.

[0009] According to one embodiment of the present invention, the maximum number of cached bits in the first bit buffer queue is greater than or equal to the maximum value among the target number of bits required to fill each subcarrier.

[0010] According to one embodiment of the present invention, when the number of bits cached in the first bit buffer queue is less than the target number of bits corresponding to the current subcarrier, reading bit data from the first bit buffer queue is paused until the number of bits cached in the first bit buffer queue reaches the target number of bits.

[0011] According to one embodiment of the present invention, the writing and reading of the first bit buffer queue are performed based on the same clock signal.

[0012] Secondly, the present invention provides a bit-loading-based HPLC signal processing method applied at a signal receiving end; the signal receiving end includes, in the order of processing, a demapping module, a second bit buffer queue, a storage module, and a deinterleaving module; the method includes:

[0013] In bit loading mode, the bit data carried by each subcarrier is written into the second bit buffer queue in sequence according to the target number of bits corresponding to the modulation scheme of each subcarrier.

[0014] The second bit buffer queue is controlled to write bit data into the storage module according to the bit data writing order and the first preset rule, so that the storage module can read out bit data with the second target number of bits.

[0015] The storage module is controlled to read bit data at the second target number of bits, and the deinterleaving module is controlled to perform deinterleaving processing on the bit data read from the bit buffer queue at the second target number of bits.

[0016] According to one embodiment of the present invention, the first preset rule includes writing bit data to the storage module with a first target number of bits; the row width of the storage module is an integer multiple of the least common multiple of the first target number of bits and the second target number of bits; when the remaining writable bits of the physical block are less than or equal to the first target number of bits, the remaining writable bits of the physical block are read from the second bit cache queue, and the remaining writable bits of the physical block are written to the storage module.

[0017] Thirdly, the present invention provides a bit-loading-based HPLC signal processing method applied to a signal receiving end; the signal receiving end, in the order of processing, includes a demapping module, a third bit buffer queue, two parallel deinterleaving modules, and a storage module; the method includes:

[0018] In bit loading mode, the bit data carried by each subcarrier is written into the third bit buffer queue in sequence according to the target number of bits corresponding to the modulation scheme of each subcarrier.

[0019] The third bit buffer queue is controlled to distribute the bit data in parallel to one or two deinterleaving modules for deinterleaving processing according to the bit data writing order and the second preset rule.

[0020] The processed bit data is read from one or two deinterleaving modules respectively, and then written to the storage module.

[0021] According to one embodiment of the present invention, bit data is distributed in parallel to one or two deinterleaving modules for deinterleaving processing according to a second preset rule. Specifically, this includes: reading bit data with a third target number of bits, distributing the bit data of the third target number of bits in parallel to two deinterleaving modules, and controlling the two deinterleaving modules to perform deinterleaving processing with a first target number of bits respectively; when the remaining writable bits of the physical block are less than or equal to the third target number of bits, reading out a number of bit data corresponding to the remaining writable bits, and distributing the bit data of the remaining writable bits in parallel to one or two deinterleaving modules for deinterleaving processing.

[0022] According to one embodiment of the present invention, whenever the bit data stored in the storage module meets the number of bits of a physical block, the corresponding number of bit data is read from the storage module for decoding processing.

[0023] According to one embodiment of the present invention, the storage module is a single-port storage module.

[0024] Fourthly, the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the bit-loading-based HPLC signal processing method as described in the first, second, or third aspects above.

[0025] Fifthly, the present invention provides a non-transitory computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the bit-loading-based HPLC signal processing method as described in the first, second, or third aspects above.

[0026] In a sixth aspect, the present invention provides a chip including a processor and a communication interface, the communication interface being coupled to the processor, the processor being used to run programs or instructions to implement the bit-load-based HPLC signal processing method as described in the first, second, or third aspects above.

[0027] In a seventh aspect, the present invention provides a computer program product, including a computer program that, when executed by a processor, implements the bit-loading-based HPLC signal processing method as described in the first, second, or third aspects above.

[0028] The above-described one or more technical solutions in the embodiments of the present invention have at least one of the following technical effects:

[0029] The control channel interleaving module reads out bit data and writes it sequentially into the first bit buffer queue according to the preset number of bits to be read out by the channel interleaving module. This decouples the fixed-bit-granularity channel interleaving process from the variable bit mapping process corresponding to the subcarrier modulation method in the same processing link, thereby effectively avoiding data backlog and throughput bottlenecks caused by data processing rate mismatch. In bit loading mode, different target bit numbers required to fill each subcarrier are determined for different modulation methods corresponding to each subcarrier, realizing adaptive optimization of modulation method and bit allocation, maximizing spectral efficiency and system transmission performance in complex power line environments. Then, the target number of bits is read out from the first bit buffer queue in the writing order, and the bit data read out on demand is mapped to the corresponding subcarrier for modulation and transmission. The sequential reading and mapping according to the target number of bits required by the subcarrier not only achieves accurate matching of bit supply, but also effectively solves the problem of subcarrier data crossing physical block boundaries caused by bit number mismatch. At the same time, it simplifies the data processing scheduling logic and improves the overall modulation efficiency of the signal transmitter in bit loading mode.

[0030] In summary, this invention reduces hardware complexity and chip area overhead while achieving data processing rate matching in high-speed power line carrier communication. Furthermore, it eliminates the need for subcarrier data to cross data physical block boundaries for mapping, effectively ensuring high throughput, low latency, and high reliability of the signal modulation process in bit loading mode.

[0031] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0032] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0033] Figure 1 This is a schematic diagram of the channel interleaver provided in some embodiments of the present invention;

[0034] Figure 2 This is a schematic diagram of the structure of the signal transmitting end provided in some embodiments of the present invention;

[0035] Figure 3 This is a schematic flowchart of a bit-loading-based HPLC signal processing method provided in some embodiments of the present invention;

[0036] Figure 4This is a schematic diagram of the payload data modulation process provided in some embodiments of the present invention;

[0037] Figure 5 This is a schematic diagram of the first bit cache queue caching bit data provided in some embodiments of the present invention;

[0038] Figure 6 This is a schematic diagram of the structure of a signal receiving end provided in some embodiments of the present invention;

[0039] Figure 7 This is a schematic flowchart of a bit-loading-based HPLC signal processing method provided in other embodiments of the present invention;

[0040] Figure 8 This is a schematic diagram of the structure of a signal receiving end provided in some other embodiments of the present invention;

[0041] Figure 9 This is a flowchart illustrating the bit-loading-based HPLC signal processing method provided in some other embodiments of the present invention;

[0042] Figure 10 This is a schematic diagram of the structure of an electronic device provided in some embodiments of the present invention. Detailed Implementation

[0043] The technical solutions of the embodiments of the present invention will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention are within the scope of protection of the present invention.

[0044] The terms "first," "second," etc., used in the specification and claims of this invention are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0045] To address the issue of inconsistent data clock cycles under bit-loading conditions, related technologies typically mitigate this problem by adding parallel processing units or improving memory access capabilities. However, such solutions often rely on more complex hardware structures and scheduling control logic, significantly increasing hardware resource consumption and power consumption. Furthermore, when subcarrier data crosses physical processing boundaries, the scheduling control difficulty further increases, leading to higher system implementation complexity. Therefore, under the current technological conditions, balancing the flexibility of bit loading with the efficiency of the signal processing chain without significantly increasing hardware overhead remains a pressing problem for HPLC systems.

[0046] Furthermore, in high-speed power line carrier communication systems, Orthogonal Frequency Division Multiplexing (OFDM) technology is typically used to modulate signals to improve multipath interference resistance and spectrum utilization efficiency. OFDM divides a broadband signal into multiple mutually orthogonal subcarriers for parallel transmission, enabling the communication system to maintain good transmission stability in the frequency-selective power line channel environment. However, in the OFDM system, each subcarrier exists in parallel within the same symbol period, and its modulation method and the number of bits carried are directly related to the channel state of the subcarrier.

[0047] Therefore, when OFDM technology is combined with the bit loading mechanism, the difference in bit carrying capacity between different subcarriers is further amplified, making the problem of inconsistent bit granularity more prominent in the signal processing process, and placing higher demands on the timing matching and overall throughput of related processing links in the system.

[0048] In traditional HPLC communication systems, the transmission and processing of OFDM signals typically requires rearranging and mapping the encoded bit sequence to enhance the system's anti-interference capability in complex power line channel environments and provide a basic data organization for subsequent modulation processing. This rearrangement process is generally achieved through channel interleaving, and the interleaved bit data further participates in bit mapping to complete subcarrier modulation. Therefore, to facilitate understanding of the organization of bit data in the channel interleaving stage of existing systems and its impact on subsequent modulation processing, a typical channel interleaver structure and its read / write method are described below with reference to the accompanying figures.

[0049] Figure 1 This is a schematic diagram of the channel interleaver provided in some embodiments of the present invention. For example... Figure 1As shown, the channel interleaver is a storage matrix with a fixed structure. Numbers 1 to 28 within the matrix represent the storage location indices of the bits. Bit data is written sequentially along the column direction indicated by the write arrows, with four bits written at a time. For example, positions 1, 2, 3, and 4 in the diagram represent a set of bits written sequentially. Subsequently, the channel interleaver reads data sequentially along the row direction indicated by the read arrows, also reading four bits at a time. For example, positions 1, 8, 15, and 22 in the diagram constitute a set of data read row by row.

[0050] It should be noted that in power line carrier communication systems, the power line channel environment is complex, characterized by impulse noise, narrowband interference, and frequency-selective fading, making it highly susceptible to continuous burst errors during transmission. If these erroneous bits occur in a concentrated manner, they will exceed the error correction capability of the channel coding, leading to data loss. The role of channel interleaving is to combat such burst errors. By rearranging the order of the encoded bit sequence, the erroneous bits that were originally continuous in the time or frequency domain are dispersed into different coding blocks or time positions after deinterleaving. This transforms concentrated burst errors into discrete random errors, thereby improving the error correction success rate of subsequent channel decoding. It is one of the key technologies to ensure high-reliability transmission of power line communication even in harsh channel environments.

[0051] After channel interleaving is completed, the bit mapping module fills the processed bit data onto each subcarrier for subsequent modulation and transmission. In the HPLC system, the subcarriers typically employ a uniform and fixed modulation scheme, such as Binary Phase Shift Keying (BPSK), Quadrature Phase Shift Keying (QPSK), or 16-Quadrature Amplitude Modulation (16QAM), with each subcarrier capable of carrying 1, 2, and 4 bits respectively. Since the channel interleaver typically reads 4 bits at a time, which is an integer multiple of the fixed number of bits required by the subcarrier (1, 2, or 4 bits), the bit data stream can be processed continuously and in a matched manner, preventing subcarrier data from crossing physical block (PB) boundaries.

[0052] However, next-generation power line carrier communication protocols have introduced bit-loaded signal modulation methods, such as 64-Quadrature Amplitude Modulation (64QAM), where each subcarrier can carry 6 bits. Furthermore, in bit-loaded mode, the number of bits required to fill each subcarrier can dynamically change, i.e., it could be 1 bit, 2 bits, 4 bits, or 6 bits. In this case, the original channel interleaver, which fixed its read / write operations in 4-bit units, experiences a rate mismatch with the variable bit mapping requirements of the backend.

[0053] For example, when the total number of bits in a physical block is not an integer multiple of the number of subcarrier bits (such as 6 bits), the data required for a single subcarrier may come from two different physical blocks, which creates a "cross-physical-block" data transmission problem. This not only disrupts the continuous processing flow based on physical blocks, but also causes complex scheduling problems in actual hardware implementation. If solutions such as dual-port storage are adopted, although the data transmission rate pressure can be alleviated to some extent, it will significantly increase the chip area, power consumption and control logic complexity, and the cross-physical-block scheduling of critical subcarriers is still extremely cumbersome.

[0054] In view of this, embodiments of the present invention provide an HPLC signal processing method based on bit loading, which aims to solve the problems of rate mismatch and subcarrier transmission across physical blocks in high-speed power line communication systems under bit loading mode. By introducing a bit buffer queue for rate adaptation and buffering of data processing, efficient rate matching of data processing under bit loading mode and data transmission without subcarrier transmission across physical blocks are achieved with almost no increase in hardware overhead and processing complexity.

[0055] The bit-loading-based HPLC signal processing method provided by the present invention will be described in detail below with reference to the accompanying drawings and through specific embodiments and application scenarios.

[0056] The bit-loaded HPLC signal processing method provided by this invention can be applied to a bit-loaded HPLC signal processing system. The bit-loaded HPLC signal processing system includes a signal transmitting device and a signal receiving device, wherein the signal transmitting device is used to transmit a carrier signal, and the signal receiving device is used to receive the carrier signal transmitted by the signal transmitting device.

[0057] The signal transmitting and receiving devices can be, for example, electronic devices, such as power line communication terminals, concentrators, smart meters, communication module embedded devices, or communication test terminals. Alternatively, the electronic devices can also be devices with computing capabilities or intelligent robots, used to perform the signal acquisition, processing, and synchronization steps in the embodiments of the present invention.

[0058] It should be noted that the signal transmitting end and the signal receiving end correspond to each other and work together in the overall communication link. The bit organization and modulation method adopted by the transmitting end and the demodulation and recovery process of the receiving end are logically consistent and complementary.

[0059] To facilitate the explanation of the signal processing mechanism involved in the embodiments of the present invention, the following will first describe the processing process of the signal transmitting end as an example.

[0060] Figure 2 This is a schematic diagram of the structure of a signal transmitting end provided in some embodiments of the present invention. For example... Figure 2 As shown, the signal transmitting end includes a channel interleaving module, a first bit buffer queue, and a bit mapping module. The channel interleaving module is used to read the encoded and buffered bit data from the upstream storage module at a fixed rate (e.g., 4 bits at a time) and perform channel interleaving on it.

[0061] The first bit buffer queue is located between the channel interleaving module and the bit mapping module. It is used to receive the output data from the channel interleaving module in a fixed rate (e.g., 4 bits) sequence, and read out the corresponding number of bits of data from its own buffer queue in the order of writing as needed.

[0062] The bit mapping module is used to determine the modulation scheme and target padding bit number corresponding to each subcarrier in bit loading mode, and to map the corresponding number of bit data read from the first bit buffer queue to the corresponding OFDM subcarrier for subsequent modulation and transmission.

[0063] It should be noted that writing in the order of writing means that each data unit from the channel interleaving module is stored sequentially in the physical storage space of the first bit buffer queue according to the time sequence in which it was processed. This ensures that the data generated earlier occupies a higher storage position, thus maintaining the temporal order of the data stream at the physical level. Reading in the order of writing means that when reading data, the first bit buffer queue starts from the earliest written data unit among all currently stored data and reads continuously in strict accordance with the writing order.

[0064] The first bit buffer queue with the pipelined access mechanism with strict write and read timing can effectively avoid data out of order during storage, so that the logical order of the signal can still be intact after a series of processes such as interleaving, buffering, and mapping.

[0065] Furthermore, the bit buffer queue in this embodiment of the invention is fundamentally different from the general-purpose memory used for random access and the random access memory (RAM) used for regular data access in the system. This is because general-purpose memory provides a universal storage space where addresses can be arbitrarily assigned and data can be accessed randomly and repeatedly; its access order depends entirely on complex external address management logic, making management complex. In contrast, the bit buffer queue strictly follows the timing of data writing for non-skipped sequential reading. This characteristic makes it suitable for processing continuous data streams from the channel interleaving module to the bit mapping module.

[0066] In hardware circuit implementation, bit buffer queues differ significantly from RAM and other memory types. Specifically, bit buffer queues do not directly access arbitrary specified locations via external address lines. Instead, they do not provide external read / write address lines; data position advancement is entirely achieved through automatic incrementing of internal read / write pointers, offering advantages such as a simple interface and convenient control. The hardware circuit consists of numerous independent functional modules interconnected via specific control and data signals. When there are differences in data processing speeds between interconnected modules (i.e., clock mismatch), the faster module must wait for the slower module. This waiting mechanism essentially achieves data flow synchronization and smoothing through buffering, and bit buffer queues effectively address this type of data caching requirement.

[0067] In this embodiment of the invention, the first bit buffer queue is configured to write in fixed units of a preset number of bits (e.g., 4 bits) for the channel interleaving module, and to read out dynamically adapt to the target number of bits required by each subcarrier (e.g., 1, 2, 4, or 6 bits). This "fixed bit write, dynamic bit read" working mode makes it act as both a "bit data rate adapter" and a "bit data length shaper," thereby solving the mismatch between fixed processing time and dynamic bit requirements with a simple architecture and avoiding the additional overhead caused by using a complex parallel storage architecture.

[0068] Figure 3 This is a schematic flowchart of a bit-loading-based HPLC signal processing method provided in some embodiments of the present invention. For example... Figure 3 As shown, the bit-load-based HPLC signal processing method includes steps 310 to 330.

[0069] Step 310: Read bit data from the channel interleaving module and write it into the first bit buffer queue in sequence according to the preset number of bits to be read from the channel interleaving module.

[0070] The preset readout bit count of the channel interleaving module refers to the fixed number of bits that the channel interleaving module reads from its internal storage matrix in each working cycle. Typically, the preset readout bit count of the channel interleaving module is 4 bits.

[0071] Specifically, the signal transmitting device reads a fixed number of bits from the channel interleaving module and writes the bits into the first bit buffer queue in the order in which they are read.

[0072] In some implementations, the signal transmitting device further includes a turbo coding (Turbo) module before reading bit data from the channel interleaving module to further improve the transmission reliability of the HPLC system. Figure 4 This is a schematic diagram of the payload data modulation process provided in some embodiments of the present invention. For example... Figure 4 As shown, in the Turbo encoding module, the signal transmitting device performs Turbo encoding on the input payload data in physical blocks. Turbo encoding is a forward error correction coding technique that combines recursive system convolutional codes with an interleaver, providing excellent error correction performance close to the Shannon limit. The encoded physical blocks generate a corresponding multiple of encoded bits according to a set code rate (e.g., 1 / 2, 2 / 3, etc.). In other modes, the encoded bitstream is written to a storage module, then undergoes channel interleaving processing via a channel interleaving module. A diversity copy module is set after the channel interleaving module. The interleaved bit data (at a fixed rate, such as 4 bits) read from the channel interleaving module is sent to the diversity copy module. The diversity copy module copies the input bit data according to the number of copies configured for the HPLC system (e.g., one or more times) to generate redundancy in the frequency or time domain, enhancing the signal's robustness in fading channels. In bit loading mode, the interleaved bit data (at a fixed rate, such as 4 bits) read from the channel interleaving module is written into the first bit buffer queue, where rate adaptation and buffering are performed. Subsequently, the bit mapping module reads the corresponding number of bits from the first bit buffer queue as needed, based on the modulation scheme and target bit number (1 bit, 2 bits, 4 bits, or 6 bits) determined by the channel quality of each subcarrier, and directly maps them to the corresponding OFDM subcarrier, thereby completing the modulation and transmission of the signal.

[0073] Step 320: In bit loading mode, determine the target number of bits to be filled for each subcarrier according to the modulation scheme corresponding to each subcarrier; the target number of bits is different for different modulation schemes.

[0074] The target number of bits refers to the number of bits required to fill a specific subcarrier within the current symbol period. Its value is determined by the modulation scheme allocated to that subcarrier. For example, BPSK corresponds to 1 bit, QPSK corresponds to 2 bits, 16QAM corresponds to 4 bits, and 64QAM corresponds to 6 bits.

[0075] Specifically, after entering bit loading mode, the signal transmitting device determines a suitable modulation scheme for each subcarrier based on real-time channel estimation results or pre-configured channel quality indication information. Subsequently, by querying a preset "modulation scheme-bit number" mapping table, it determines the target number of bits required to fill each subcarrier at the current transmission time.

[0076] In some implementations, the signal transmitting device can determine the corresponding modulation scheme for each subcarrier based on channel measurement results, thereby obtaining the corresponding target number of bits. Specifically, the signal transmitting device first obtains the channel quality index of each subcarrier under the current channel environment through channel estimation. For example, the channel quality index may be the signal-to-noise ratio (SNR). Afterward, the signal transmitting device compares the channel quality index of each subcarrier with a preset set of modulation thresholds, thereby selecting the most optimized modulation scheme under the current transmission conditions (e.g., the highest rate while meeting a certain bit error rate requirement).

[0077] For example, subcarriers with good channel quality can be assigned 64QAM modulation (with a target number of 6 bits), subcarriers with medium quality can be assigned 16QAM modulation (with a target number of 4 bits), while subcarriers with poor quality may be assigned QPSK (with a target number of 2 bits) or BPSK (with a target number of 1 bit). Ultimately, each subcarrier determines the target number of bits it needs to fill in the current symbol period based on its assigned modulation scheme, thus forming an adaptive bit allocation mapping table.

[0078] Step 330: Read out the target number of bits from the first bit buffer queue in the order of writing, and map the read-out bits to the corresponding subcarriers for modulation and transmission.

[0079] The writing order refers to the order in which bit data enters the first bit buffer queue. In other words, the first bit buffer queue follows the first-in-first-out principle, reading out the earliest written bit data first.

[0080] The signal transmitting device generates a corresponding read request based on the target number of bits required to fill each subcarrier as determined in step 320, and reads the corresponding number of bits from the first bit buffer queue in the order in which the bit data was written. After reading, the signal transmitting device accurately allocates the obtained bit data to its corresponding target subcarrier for subsequent symbol modulation and signal transmission.

[0081] In bit loading mode, the target number of bits required by each subcarrier changes dynamically. If the number of bits in the bit buffer queue is less than the maximum possible target number of bits (e.g., 6 bits), when a subcarrier needs to read 6 bits of data, the mapping operation of that subcarrier may not be completed in one read cycle due to insufficient data in the queue. It will be necessary to wait for multiple write cycles to gather enough data, and this waiting will disrupt the continuity of data processing.

[0082] Based on this, in some embodiments, the maximum number of cached bits in the first bit buffer queue is greater than or equal to the maximum value among the target number of bits required to fill each subcarrier.

[0083] The signal transmitting device determines the target bit set based on the modulation scheme supported by the bit loading mode, and selects the maximum value (e.g., 6 bits) from it. Subsequently, the signal transmitting device sets the maximum number of bits that can be stored in the first bit buffer queue to be greater than or equal to this maximum value.

[0084] For example, the maximum number of buffer bits in the first bit buffer queue can be set to an integer multiple of this maximum value. When the maximum number of target bits to be filled in each subcarrier is 6 bits, the maximum number of buffer bits in the first bit buffer queue can be, for example, 12 bits.

[0085] By configuring the maximum number of cached bits in the first bit buffer queue to be no less than the maximum target number of bits, the single data requirement of any modulation subcarrier can be met, avoiding multiple reads caused by insufficient cache capacity of the first bit buffer queue, thereby maintaining high throughput and low latency continuous data processing in the bit loading mode of the data processing link.

[0086] Furthermore, in actual operation, since the write rate of the channel interleaving module is fixed, while the data requests of the subcarrier are dynamic and may occur continuously, there may still be brief moments when the amount of bit data currently in the first bit buffer queue is insufficient to meet the larger bit demand of the current subcarrier. For example, if there are only 4 bits in the first bit buffer queue, but the current subcarrier needs 6 bits, forcing an incomplete read at this time will lead to incorrect bit data mapping. If a complex logical mapping process is split into multiple cycles, it will increase the scheduling complexity and latency.

[0087] Therefore, in some embodiments, when the number of bits cached in the first bit buffer queue is less than the target number of bits corresponding to the current subcarrier, reading bit data from the first bit buffer queue is paused until the number of bits cached in the first bit buffer queue reaches the target number of bits.

[0088] For example, Figure 5 This is a schematic diagram illustrating the first bit cache queue caching bit data provided in some embodiments of the present invention. For example... Figure 5 As shown, let rd_data be the effective data quantity indication signal output by the first bit buffer queue, and req_size be the bit number request signal issued by the bit mapping module. The first bit buffer queue receives bit data from the channel interleaving module, and the signal transmitting device compares these two values ​​in real time. When rd_data is less than req_size, the signal transmitting device pauses the read operation. During this period, the channel interleaving module continues to write data to the first bit buffer queue, and rd_data increases accordingly. When rd_data is not less than req_size, the signal transmitting device performs the operation of reading the target number of bits.

[0089] The waiting mechanism ensures that each readout operation fully satisfies the subcarrier's bit requirements, guaranteeing the correctness and completeness of the mapped data and preventing mapping errors due to insufficient bit data. It's important to note that while the waiting mechanism may introduce a time delay, the existence of the first bit buffer queue means this process only occurs between the first bit buffer queue and the bit mapping module, and does not affect the continuous operation of the upstream channel interleaving module. Therefore, the overall data flow throughput remains unaffected, achieving error-free and highly efficient data supply under dynamic and irregular data requests.

[0090] It should be noted that the first bit buffer queue read and write operations can be based on synchronous or asynchronous clocks. However, if an asynchronous clock design is used, that is, the read and write sides use clock signals of different frequencies or phases, although it can improve the flexibility of bit data processing to a certain extent, it usually requires additional synchronizer circuitry to prevent metastability, and may lead to a decrease in data throughput, an increase in design verification difficulty, and additional chip area overhead.

[0091] Therefore, in some embodiments, the writing and reading of the first bit buffer queue are performed based on the same clock signal. The output write enable of the channel interleaving module, the read enable of the bit mapping module, and the read and write pointer update logic inside the first bit buffer queue are all connected to and driven by the same global working clock signal. The read and write operations are triggered and completed on a specific edge (such as the rising edge) of this clock signal. The corresponding control logic (such as determining whether the amount of buffered data meets the read condition) is also completed within the same clock domain, without the need for cross-clock domain signal synchronization.

[0092] By adopting a synchronous design based on the same clock signal, the timing and control logic of the entire rate adaptation process can be effectively simplified, reducing the metastability risk caused by cross-clock domains and improving the reliability of data transmission. Furthermore, since no complex synchronization circuits need to be added, it helps to save chip area and reduce power consumption. It achieves alignment of read and write operations on the time base, making the control loop delay from writing and status judgment to reading deterministic and controllable. As a result, the data stream processing in the first bit buffer queue stage has high determinism, high stability and high predictability.

[0093] According to the bit-loading-based HPLC signal processing method provided by the embodiments of the present invention, bit data is read out by controlling the channel interleaving module and written into the first bit buffer queue in sequence according to the preset number of bits read out by the channel interleaving module. This decouples the fixed-bit-granularity channel interleaving processing from the variable bit mapping process corresponding to the subcarrier modulation mode in the same processing link, thereby effectively avoiding data backlog and throughput bottlenecks caused by data processing rate mismatch. In bit-loading mode, different target bit numbers required to fill each subcarrier are determined for different modulation modes corresponding to each subcarrier, realizing adaptive optimization of modulation mode and bit allocation, maximizing spectral efficiency and system transmission performance in complex power line environments. Then, the target number of bit data is read out from the first bit buffer queue in the writing order, and the bit data read out on demand is mapped to the corresponding subcarrier for modulation and transmission. The sequential reading and mapping according to the target number of bits required by the subcarrier not only achieves accurate matching of bit supply, but also effectively solves the problem of subcarrier data crossing physical block boundaries caused by bit number mismatch. At the same time, it simplifies the data processing scheduling logic and improves the overall modulation efficiency of the signal transmitter in bit-loading mode.

[0094] After explaining the relevant processing flow at the signal transmitting end, the signal processing flow at the signal receiving end in bit-loaded mode will be described below. It should be noted that the processing flow at the signal receiving end corresponds functionally to that at the signal transmitting end; its purpose is to recover and reconstruct the signal transmitted via the power line channel to obtain data content consistent with the original bit sequence at the transmitting end. Figure 6 This is a schematic diagram of the structure of a signal receiving end provided in some embodiments of the present invention. For example... Figure 6 As shown, the signal receiving end includes, in the order of processing, a demapping module, a second bit buffer queue, a storage module, and a deinterleaving module.

[0095] The demapping module is used to demodulate the corresponding number of bits of data from each subcarrier in the received OFDM symbol according to the modulation scheme of each subcarrier in bit loading mode, and output them in subcarrier order.

[0096] The second bit buffer queue is located between the demapping module and the storage module. It is used to receive and buffer the bit data stream with dynamically changing bit count from the demapping module.

[0097] The storage module is used to receive and store bit data read from the second bit buffer queue. In some implementations, the storage module is a single-port memory.

[0098] The deinterleaving module is used to deinterleave the bit data read from the storage module according to the inverse rule corresponding to the channel interleaving rule, so as to restore the original order of the bit data for subsequent data decoding and other processing.

[0099] Figure 7 This is a schematic flowchart of a bit-loading-based HPLC signal processing method provided in other embodiments of the present invention. For example... Figure 7 As shown, the bit-load-based HPLC signal processing method includes steps 710 to 730.

[0100] Step 710: In bit loading mode, according to the target number of bits corresponding to the modulation scheme of each subcarrier, write the bit data carried by each subcarrier into the second bit buffer queue in sequence.

[0101] Specifically, in bit-loading mode, the signal receiving device controls the demapping module to demodulate the corresponding number of bits (i.e., the target number of bits) from the received OFDM symbols according to the modulation scheme corresponding to each subcarrier. Subsequently, the signal receiving device writes the demodulated bit data sequentially into the third bit buffer queue according to the transmission order of the subcarriers.

[0102] By reorganizing the bit data originally scattered on different subcarriers into a sequentially arranged, continuously input bit data stream and writing it into a second bit buffer queue for buffering, the bit data can be collected and temporarily stored in an orderly and complete manner even when the number of bits on the subcarriers changes dynamically, thereby maintaining the continuity and stability of the data link at the signal receiver.

[0103] Step 720: Control the second bit buffer queue to write the bit data into the storage module according to the bit data writing order and the first preset rule.

[0104] The writing order refers to the order in which bit data enters the bit cache queue, and the first preset rule refers to the rule that controls the reading of data from the bit cache queue and writing it to the storage module.

[0105] For example, the first preset rule may be configured to align the write format of the storage module with the fixed read rules of subsequent processing units (such as deinterleaving modules).

[0106] In some implementations, the first preset rule is to write bit data to the storage module with a first target number of bits; the row width of the storage module is an integer multiple of the least common multiple of the first target number of bits and the second target number of bits; if the remaining writable bits of the physical block are less than or equal to the first target number of bits, the remaining writable bits of the physical block are read from the second bit cache queue and the remaining writable bits of the physical block are written to the storage module.

[0107] The first target number of bits refers to the fixed number of bits used by the second bit buffer queue when writing bit data to the storage module.

[0108] For example, the first target number of bits could be 6 bits.

[0109] Specifically, the signal receiving device calculates the number of bits already written to the current physical block and then calculates the remaining writable bits. Typically, when the remaining writable bits of the physical block are greater than or equal to the first target number of bits, the signal receiving device controls the second bit buffer queue to perform read and write operations for the first target number of bits. When the remaining writable bits of the physical block are less than the first target number of bits, the signal receiving device controls the second bit buffer queue to perform a single read and write operation for the remaining writable bits of the physical block, thus completing the filling of the current physical block. Afterward, the signal receiving device resets the count to zero and begins the writing process for the next physical block.

[0110] It should be noted that the first preset rule is the core scheduling logic controlling the writing of bit data from the second bit cache queue to the storage module. Its main function is to solve the access efficiency and data alignment problems caused by the mismatch between the bit data stream and the fixed storage structure. Specifically, the first preset rule can effectively handle cross-storage row writing of bit data. By aligning the bit data written each time with the width of the storage row, a single write operation is completed within a single storage row, avoiding multi-cycle cross-row access, thereby improving storage bandwidth efficiency and simplifying control. In addition, the first preset rule can align the fixed input bit data (such as the first number of bits) of subsequent data processing units, so that each subsequent read of the storage module can obtain a regular physical block with naturally aligned boundaries. This provides ready-to-use input for data processing such as deinterleaving, reduces data reorganization overhead, realizes data organization on a physical block basis, controls the rhythm and boundaries of data writing, and thus allows the data of a complete physical block to be continuously and alignedly stored in a continuous area of ​​the storage space, facilitating the triggering and management of subsequent processing on a physical block basis.

[0111] In the above embodiments, by writing data at the physical block boundary according to the remaining number of bits, the data of each physical block can be completely and aligned, which facilitates subsequent decoding processing on a physical block basis. This avoids the problem of data being stored across physical blocks or storage line boundaries, reduces the complex scheduling and additional access latency caused by storing data across physical block boundaries, and ensures that the entire bit data receiving link can still maintain an efficient and reliable processing flow in bit loading mode.

[0112] The second target number of bits refers to the fixed number of bits that the storage module reads in each operation. This value is usually preset according to the HPLC system architecture and the input requirements of the processing unit.

[0113] For example, the second target bit count can be 4 bits to match the fixed input width of the deinterleaving module.

[0114] Specifically, the signal receiving device detects the state of the second bit buffer queue (such as the amount of buffered data) and controls the second bit buffer queue to read data sequentially in the form of specific data blocks according to the first preset rule. Then, the data is written to the storage module, so that the storage module can efficiently and alignedly read the data in the future with a fixed second target number of bits.

[0115] By reorganizing and batch-writing bit data into the storage module according to predetermined rules, data with a uniform format and easy access is prepared for subsequent processing steps such as deinterleaving. This enables the storage module to efficiently and alignedly read data with a fixed second target number of bits, thereby avoiding the blocking or efficiency reduction problems of downstream processing units (such as deinterleavers) that may be caused by input data format mismatch.

[0116] Step 730: Control the storage module to read bit data with the second target number of bits, and control the deinterleaving module to perform deinterleaving processing on the bit data read from the second bit buffer queue with the second target number of bits.

[0117] Deinterleaving refers to the process of rearranging the input bit sequence according to a predetermined deinterleaving rule (for example, reversing the interleaving operation of writing by row and reading by column to writing by column and reading by row).

[0118] The signal receiving device controls the storage module to read out the stored bit data in units of a fixed second target number of bits and send it to the deinterleaving module. The storage module is a single-port storage module. The deinterleaving module receives this fixed number of bits in each working clock cycle and rearranges these bits in real time according to the built-in or configured deinterleaving mapping rules to restore the original bit order before interleaving.

[0119] By restoring the bit sequence that may have been scattered due to interleaving during channel transmission into a coherent data stream that conforms to the original coding order, the data arrangement disturbance introduced by the signal transmitter to combat channel burst errors is effectively eliminated. This provides correct and continuous data input for subsequent decoding and other processing stages. By processing with a fixed second target number of bits, the data processing of the deinterleaving module is stable and efficient, and a good rate match is achieved with the preceding and following modules.

[0120] In some implementations, the storage module is positioned before the deinterleaving module, and a Turbo decoding module is positioned after the deinterleaving module. Furthermore, a single-port storage module and a single deinterleaving module are used to save chip area. Specifically, the storage module's row width is configured to 12 bits, and the maximum number of cached bits in the second bit buffer queue is also 12 bits. The second bit buffer queue receives data from the demapping module with dynamically changing bit counts, and reads are performed in fixed 6-bit units. Since the storage module's row width is an integer multiple of the bit buffer queue's read unit (6 bits), continuous writes in 6-bit units do not cause cross-row access issues, effectively reducing scheduling complexity. The deinterleaving module writes and reads data in fixed 4-bit units, and the storage module's row width (12 bits) is also an integer multiple of 4 bits. Similarly, cross-row operations are avoided when reading data from storage and writing data to the deinterleaving module.

[0121] Furthermore, since Turbo decoding is performed on a physical block basis, in some implementations, whenever the number of bits stored in the storage module meets the bit count of a physical block, the corresponding number of bits are read from the storage module for decoding. Specifically, when the storage module is full of data for a physical block, the signal receiving device initiates the subsequent deinterleaving and decoding process. A physical block contains multiple OFDM symbols, and there is an inherent time interval between OFDM symbols. The processing time for storage, deinterleaving, and other processes can be accommodated within this interval. Therefore, from a system perspective, the signal processing flow remains continuous.

[0122] In the above embodiments, when the stored bit data meets the bit count of a physical block, the corresponding number of bits are read from the storage module for decoding, ensuring the integrity and correctness of data processing and achieving high efficiency and good timing in bit data processing. Simultaneously, the single-port storage module saves chip area and hardware overhead, resulting in simpler layout and wiring, simplified drive circuitry, effectively reducing system power consumption, simplifying control logic and scheduling complexity, and improving system stability.

[0123] According to the bit-loading-based HPLC signal processing method provided by the present invention, in bit-loading mode, the bit data carried by each subcarrier is sequentially written into the second bit buffer queue according to the target number of bits corresponding to the modulation mode of each subcarrier. This effectively buffers the discrete bit data stream output by the demapping module, allowing the demapping process to proceed continuously and avoiding bit data backlog or loss due to rate mismatch. The second bit buffer queue is controlled to write the bit data into the storage module according to the bit data writing order and a first preset rule, so that the storage module reads the bit data with the second target number of bits. This allows the bit data to be adaptively adjusted at the physical block boundary, reorganizing the input data into an aligned storage format. This effectively solves the problem of storing subcarrier data across physical block boundaries, enabling the storage module to efficiently and alignedly read the bit data with a fixed second target number of bits. The deinterleaving module is controlled to deinterleave the bit data read from the second bit buffer queue with the second target number of bits. Utilizing the data alignment foundation achieved in the previous steps, the deinterleaving module can operate efficiently at a fixed rate, restoring a coherent bit data stream that conforms to the original order, providing basic data for subsequent decoding, and avoiding data processing blockage caused by input bit data mismatch.

[0124] In summary, the bit-load-based HPLC signal processing method provided by the embodiments of the present invention effectively solves the problems of rate mismatch and data transmission across physical blocks in the bit-load mode at the signal receiving end. By introducing a second bit buffer queue and an adapted control mechanism, it replaces the complex parallel architecture that relies on dual-port storage and multiple deinterleaving modules. While significantly saving chip area, reducing power consumption and simplifying control logic, it ensures that the signal receiving link has high throughput, low latency and high reliability data processing capabilities.

[0125] When processing signals in 64QAM modulation mode at the receiving end, the demapping module outputs a 6-bit data stream, while the subsequent deinterleaving module typically requires a fixed number of bits (e.g., 4 bits) as input, resulting in a significant rate mismatch. In scenarios with high data throughput or stringent real-time requirements, a non-single path can be used to further improve the overall deinterleaving processing efficiency.

[0126] However, if a dual-port storage module and two independent deinterleaving modules are deployed in pursuit of higher processing speeds, along with complex scheduling logic, the data throughput can be improved, but the chip area, power consumption and control complexity will be significantly increased. In particular, the scheduling difficulty increases sharply when the carrier crosses the physical block boundary, which leads to a decrease in the actual feasibility and cost-effectiveness of the solution.

[0127] Based on the above design concept, this embodiment of the invention improves the data throughput of bit data processing by adding parallel deinterleaving modules without increasing the number of storage module ports. The following will describe the signal processing process in bit loading mode for an architecture with a single-port storage module and two parallel deinterleaving modules at the signal receiver. Figure 8 This is a schematic diagram of the structure of a signal receiving end provided in other embodiments of the present invention. For example... Figure 8 As shown, the signal receiver, in the order of processing, includes a demapping module, a third bit buffer queue, two parallel deinterleaving modules, namely deinterleaving module 1 and deinterleaving module 2, and a storage module.

[0128] Figure 9 This is a schematic flowchart of a bit-loading-based HPLC signal processing method provided in some other embodiments of the present invention. For example... Figure 9 As shown, the bit-load-based HPLC signal processing method includes steps 910 to 930.

[0129] Step 910: In bit loading mode, according to the target number of bits corresponding to the modulation scheme of each subcarrier, write the bit data carried by each subcarrier into the third bit buffer queue in sequence.

[0130] Specifically, in bit-loading mode, the signal receiving device controls the demapping module to demodulate the corresponding number of bits (i.e., the target number of bits) from the received OFDM symbols according to the modulation scheme corresponding to each subcarrier. Subsequently, the signal receiving device writes the demodulated bit data sequentially into the third bit buffer queue according to the transmission order of the subcarriers.

[0131] By reorganizing the bit data originally scattered on different subcarriers into a sequentially arranged, continuously input bit data stream and writing it into a third bit buffer queue for buffering, the bit data can be collected and temporarily stored in an orderly and complete manner even when the number of bits on the subcarriers changes dynamically, thereby maintaining the continuity and stability of the data link at the signal receiver.

[0132] Step 920: Control the third bit buffer queue to distribute the bit data in parallel to one or two deinterleaving modules for deinterleaving processing according to the bit data writing order and the second preset rule.

[0133] The second preset rule refers to the data allocation and control rules designed to adapt to the input of two parallel deinterleaving modules. Its core is to allocate data to one or two deinterleaving modules based on factors such as the number of bits of the current data to be processed and the physical block boundary position. Parallel allocation refers to the process of simultaneously inputting bit data from the third bit buffer queue to one or two deinterleaving modules according to the second preset rule.

[0134] In some implementations, bit data is distributed in parallel to one or two deinterleaving modules for deinterleaving processing according to a second preset rule. Specifically, this includes: distributing bit data of a third target number of bits in parallel to two deinterleaving modules, and controlling the two deinterleaving modules to perform deinterleaving processing with a first target number of bits respectively; when the remaining writable bits of the physical block are less than or equal to the third target number of bits, reading out a number of bit data corresponding to the remaining writable bits, and distributing the remaining writable bits in parallel to one or two deinterleaving modules for deinterleaving processing.

[0135] The third target bit count refers to the number of bits contained in the smallest data unit read from the third bit buffer queue and prepared for parallel allocation.

[0136] For example, the third target bit number could be, for instance, 8 bits.

[0137] For example, when the third bit buffer queue has sufficient data, the signal receiving device controls the third bit buffer queue to read 8 bits of data and splits it into two 4-bit data packets, which are then sent to the two deinterleaving modules respectively. When it is detected that the remaining bits of the current physical block are less than or equal to 8 bits (e.g., only 5 bits remain), the signal receiving device controls the third bit buffer queue to read these 5 bits of data. Subsequently, according to a preset mapping rule, these 5 bits of data are appropriately allocated to the two deinterleaving modules for processing, ensuring that the current physical block is processed accurately and completely.

[0138] For example, the preset mapping rule could be that when the number of remaining bits in a physical block is less than or equal to 4 bits, the remaining bit data is allocated to one of the two parallel deinterleaving modules; when the number of remaining bits in a physical block is greater than 4 bits and less than the third target number of bits, the remaining bit data in the physical block is split into 4 bits and less than 4 bits, and allocated to the two parallel deinterleaving modules.

[0139] Specifically, the signal receiving device continuously monitors the data status of the third bit buffer queue and generates a control signal according to the second preset rule. The control signal controls the third bit buffer queue to read data in the order in which the bit data was written, in the form of a specific number of bits, and allocates these data to one deinterleaving module or two deinterleaving modules simultaneously for parallel deinterleaving processing according to the second preset rule, thereby constructing a scalable parallel deinterleaving processing architecture.

[0140] It should be noted that the second preset rule is the core scheduling logic that controls the allocation of bit data from the third bit buffer queue to one or two parallel deinterleaving modules. Its main function is to solve the problems of efficient load distribution, order preservation, and boundary alignment of dynamic bit streams in parallel processing architectures. Specifically, the second preset rule can effectively convert the serial bit data stream into regular data blocks suitable for parallel processing, and through a preset allocation strategy, ensure that the bit data is evenly and orderly distributed to each deinterleaving module. In addition, the second preset rule can effectively handle the remaining data at the physical block boundaries, dynamically adjusting the allocation target and data volume according to the real-time changes in the number of writable bits, so that each physical block can be processed completely and continuously, avoiding the destruction of the logical integrity of the data or the introduction of processing idle periods due to parallel splitting.

[0141] By presetting a second pre-defined rule, the distribution and load balancing of bit data streams between deinterleaving channels are realized, effectively improving the overall processing capacity and throughput of the deinterleaving process, and adapting to the needs of higher data rates. At the same time, its rule-based distribution mechanism ensures the correct order of data processing and effectively solves the cross-physical block problem that may occur in bit loading mode.

[0142] Step 930: Read the processed bit data from one or two deinterleaving modules respectively, and write the processed bit data into the storage module.

[0143] The storage module refers to a functional unit used to temporarily store the deinterleaved and recovered bit data for subsequent decoding processing. In some implementations, the storage module is a single-port storage module, that is, a memory that supports only a single read or write within the same clock cycle.

[0144] Specifically, the signal receiving device reads the deinterleaved bit data from the outputs of one or two deinterleaving modules according to the processing completion status of the deinterleaving modules. Then, the signal receiving device writes this bit data into the storage module through the storage interface in a specific organized order.

[0145] For example, the organization order may be one or more of the following: the order in which deinterleaving is completed or based on logical addresses within physical blocks.

[0146] In some implementations, the signal receiving device reads processed bit data from a deinterleaving module and writes the data into a storage module. This corresponds to a working mode in which, under certain circumstances, such as when the amount of remaining data at the physical block boundary is small, the bit data is allocated to a single deinterleaving module for processing according to a second preset rule.

[0147] The above implementation method, using only a single deinterleaving module, single-port storage, and a third bit cache queue in coordination, can effectively solve the rate matching and data alignment problems in bit loading mode through cache scheduling and rule control, while maximizing chip area savings, reducing power consumption, and simplifying control logic.

[0148] In other embodiments, the signal receiving device reads the processed bit data from the two deinterleaving modules and writes the data into the storage module after necessary sorting or merging. This corresponds to the working mode in which data is distributed in parallel to the two deinterleaving modules according to a second preset rule to improve processing throughput under normal circumstances.

[0149] The above implementation method effectively improves the data processing capability of the deinterleaving process through appropriate parallelization, which helps to meet the requirements of higher real-time performance and data rate.

[0150] In some embodiments, whenever the number of bits stored in the storage module meets the bit count of a physical block, the signal receiving device reads the corresponding number of bits from the storage module to initiate subsequent data processing. This ensures that the decoder can obtain the complete physical block for processing each time, effectively guaranteeing the correctness and efficiency of decoding. Furthermore, since the processing time of a physical block can usually be accommodated within the OFDM symbol interval, the entire receiving process remains continuous for the HPLC system.

[0151] In other embodiments, the storage module is a single-port storage module. Although the theoretical peak bandwidth of a single-port storage module is lower than that of a dual-port storage module, through the coordinated design with the preceding third-bit cache queue and the optimized configuration of the storage row width (such as setting it to an integer multiple of the subsequent processing bit width), the actual access efficiency of single-port storage can meet the continuous pipeline requirements of the system. This can greatly save chip area and power consumption, significantly simplify the storage control logic and scheduling complexity, and avoid the internal interference that may be caused by dual-port access, thereby improving the stability and reliability of the system.

[0152] According to the bit-loading-based HPLC signal processing method provided in this embodiment of the invention, in bit-loading mode, the bit data carried by each subcarrier is sequentially written into the third bit buffer queue according to the target number of bits corresponding to the modulation mode of each subcarrier. This effectively buffers the discrete bit data stream output by the demapping module, allowing the demapping process to proceed continuously and avoiding bit data backlog or loss due to rate mismatch. The third bit buffer queue is controlled to distribute the bit data in parallel to one or two deinterleaving modules for deinterleaving processing according to the bit data writing order and a second preset rule. This achieves an effective combination of dynamic load allocation and parallel processing capabilities. While improving the deinterleaving throughput through dual-path parallel processing in regular data segments, it can also switch under special circumstances such as physical block boundaries, ensuring the integrity and correct order of the bit data physical blocks. The processed bit data is read from one or two deinterleaving modules and written into the storage module, achieving a smooth transition from parallel processing to centralized storage. This provides a complete, orderly, and reliable data foundation for subsequent decoding stages and supports batch, high-efficiency decoding scheduling based on physical blocks.

[0153] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0154] In some embodiments, Figure 10 These are schematic diagrams of the structure of an electronic device provided in some embodiments of the present invention. For example... Figure 10 As shown, this embodiment of the invention also provides an electronic device 1000, including a processor 1001, a memory 1002, and a computer program stored in the memory 1002 and executable on the processor 1001. When the program is executed by the processor 1001, it implements the various processes of the above-described bit-load-based HPLC signal processing method embodiment and achieves the same technical effect. To avoid repetition, it will not be described again here.

[0155] This invention provides a non-transitory computer-readable storage medium storing a computer program. When executed by a processor, the computer program implements the various processes of the bit-load-based HPLC signal processing method described above, and achieves the same technical effect. To avoid repetition, it will not be described again here.

[0156] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable media, such as computer read-only memory (ROM), random-access memory (RAM), magnetic disks, or optical disks.

[0157] The computer-readable storage medium may include: read-only memory (ROM), random-access memory (RAM), magnetic disk or optical disk, etc.

[0158] This invention provides a computer program product, including a computer program that, when executed by a processor, implements the bit-load-based HPLC signal processing method described above.

[0159] This invention provides a chip that includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the above-described bit-load-based HPLC signal processing method embodiments and achieve the same technical effects. To avoid repetition, it will not be described again here.

[0160] It should be understood that the chip mentioned in the embodiments of the present invention may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0161] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of the present invention is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0162] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the related technology, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0163] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of the present invention.

[0164] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0165] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A bit-loading based HPLC signal processing method, characterized in that, The method is applied to a signal transmitting end; the signal transmitting end includes, in processing order, a channel interleaving module, a first bit buffer queue, and a bit mapping module; the method includes: Bit data is read from the channel interleaving module and written into the first bit buffer queue in sequence according to the preset number of bits read from the channel interleaving module; the maximum number of buffered bits in the first bit buffer queue is greater than or equal to the maximum value among the target number of bits required to fill each subcarrier; In bit loading mode, for each subcarrier's modulation scheme, the target number of bits to be filled for each subcarrier is determined; the target number of bits is different for different modulation schemes; when the number of bits cached in the first bit buffer queue is less than the target number of bits corresponding to the current subcarrier, reading bit data from the first bit buffer queue is paused until the number of bits cached in the first bit buffer queue reaches the target number of bits; The target number of bits are read sequentially from the first bit buffer queue in the order of writing, and the read-out bits are mapped to the corresponding subcarriers for modulation and transmission.

2. The bit-loading-based HPLC signal processing method of claim 1, wherein, The writing and reading of the first bit buffer queue are performed based on the same clock signal.

3. A bit-loading based HPLC signal processing method, characterized in that, The method is applied to a signal receiving end; the signal receiving end, in the order of processing, includes a demapping module, a second bit buffer queue, a storage module, and a deinterleaving module; the method includes: In bit loading mode, the bit data carried by each subcarrier is written into the second bit buffer queue in sequence according to the target number of bits corresponding to the modulation scheme of each subcarrier. The second bit buffer queue is controlled to write bit data into the storage module according to the writing order of the bit data, with a first target number of bits. If the remaining writable bits of a physical block are less than or equal to the first target number of bits, the remaining writable bits of the physical block are read from the second bit cache queue and written to the storage module. The storage module is controlled to read bit data at a second target number of bits, and the deinterleaving module is controlled to perform deinterleaving processing on the bit data read by the storage module at the second target number of bits; the row width of the storage module is an integer multiple of the least common multiple of the first target number of bits and the second target number of bits.

4. A bit-loading based HPLC signal processing method, characterized in that, The method is applied to a signal receiving end; the signal receiving end includes, in the order of processing, a demapping module, a third-bit buffer queue, two parallel deinterleaving modules, and a storage module; the method includes: In bit loading mode, the bit data carried by each subcarrier is sequentially written into the third bit buffer queue according to the target number of bits corresponding to the modulation scheme of each subcarrier. The third bit buffer queue is controlled to read out bit data in the order of writing the bit data, with a third target number of bits. The bit data of the third target number of bits is distributed in parallel to the two deinterleaving modules, and the two deinterleaving modules are controlled to perform deinterleaving processing with a first target number of bits respectively. If the remaining writable bits of the physical block are less than or equal to the third target number of bits, read out the number of bits corresponding to the remaining writable bits, and distribute the remaining writable bits in parallel to one or two deinterleaving modules for deinterleaving processing. Processed bit data is read from one or two deinterleaving modules and written into the storage module; wherein, whenever the bit data stored in the storage module meets the number of bits of a physical block, the corresponding number of bits are read from the storage module for decoding.

5. The bit-loading-based HPLC signal processing method of claim 3, wherein, The method further includes: Whenever the number of bits stored in the storage module meets the number of bits in a physical block, the corresponding number of bits are read from the storage module for decoding.

6. The bit-loading-based HPLC signal processing method according to claim 3 or 4, characterized in that, The storage module is a single-port storage module.

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