Signal processing methods and signal processors

Abstract

A signal processing method includes the following steps: receiving an input signal through a signal receiving circuit and parsing the input signal to generate multiple bit codes; temporarily storing the multiple bit codes of the first part according to a time sequence through a shift register, and starting a decoder when the shift register is full; when the multiple bit codes of the first part conform to the decoding table rules and boundary detection rules, performing boundary calibration through the decoder based on the multiple bit codes of the first part.

Description

Technical Field

[0001] The embodiments described in this disclosure relate to a signal processing method and a signal processor, and more particularly to a signal processing method and a signal processor for decoding boundary calibration. Background Technology

[0002] In the 10BASE-T1S specification, the physical layer converts the 4B symbols to be transmitted into 5B symbols using 4B / 5B encoding. Then, the 5B symbols undergo Differential Manchester Encoding (DME) to convert each bit into a DME symbol, and the data is transmitted sequentially between the two parties. However, during data transmission, due to factors such as channel effects and radio frequency interference, the receiver may lose or miss DME symbols at the beginning of data reception, resulting in 5B boundary detection errors. Therefore, a 5B boundary detection strategy is needed to solve this problem. Summary of the Invention

[0003] Some embodiments of this disclosure relate to a signal processing method, comprising the following steps: receiving an input signal through a signal receiving circuit and parsing the input signal to generate multiple bit codes; temporarily storing the multiple bit codes of the first part according to a time sequence through a shift register, and starting a decoder when the shift register is full; when the multiple bit codes of the first part conform to the decoding table rules and the boundary detection rules, performing boundary calibration through the decoder based on the multiple bit codes of the first part.

[0004] Some embodiments of this disclosure relate to a signal processor, including a signal receiving circuit, a shift register, and a decoder. The signal receiving circuit receives an input signal and parses the input signal to generate multiple bit codes. The shift register temporarily stores a first portion of the multiple bit codes according to a time sequence. The decoder is activated when the shift register is full and performs boundary calibration based on the first portion of the multiple bit codes when the first portion of the multiple bit codes conforms to the decoding table rules and boundary detection rules.

[0005] In summary, the signal processing method and signal processor disclosed herein enable users to perform 5B boundary detection strategies based on combinations of multiple 5B symbols set by themselves. They can flexibly adjust the boundary detection rules to be more stringent or relaxed according to different situations, and can effectively avoid misjudgments of SSD(H) or BEACON(N) in the 10BASE-T1S specification, thereby effectively improving the accuracy of 5B boundary detection. Attached Figure Description

[0006] To make the above and other objects, features, advantages and embodiments of this disclosure more apparent and understandable, the accompanying drawings are described below:

[0007] Figure 1 This is a schematic diagram of a signal processor depicted according to some embodiments of the present disclosure;

[0008] Figure 2 This is a flowchart depicting a signal processing method according to some embodiments of the present disclosure;

[0009] Figure 3 This is a 4B / 5B coding comparison diagram depicted according to some embodiments of this disclosure;

[0010] Figure 4 This is an operational schematic diagram of a signal processing method described in accordance with some embodiments of the present disclosure;

[0011] Figure 5 These are schematic diagrams illustrating the operation of a signal processing method according to some embodiments of this disclosure; and

[0012] Figure 6 This is a schematic diagram illustrating a data format according to some embodiments of the present disclosure. Detailed Implementation

[0013] As used herein, the term "coupled" may also refer to "electrical coupling," and the term "connection" may also refer to "electrical connection." "Coupled" and "connection" may also refer to the cooperation or interaction of two or more components.

[0014] refer to Figure 1 . Figure 1 This is a schematic diagram of a signal processor 100 depicted according to some embodiments of the present disclosure. Figure 1 For example, signal processor 100 includes signal receiving circuitry 110, shift register 130, and decoder 150. In terms of connectivity, signal receiving circuitry 110 is coupled to shift register 130, and shift register 130 is coupled to decoder 150.

[0015] The configuration of the signal processor 100 described above is for illustrative purposes only, and all configurations of the signal processor 100 are within the scope of this disclosure. Detailed operation of the signal processor 100 will be explained below. Figure 2 This will be explained together.

[0016] Please refer to Figure 2 . Figure 2 This is a flowchart illustrating a signal processing method 200 according to some embodiments of the present disclosure. The signal processing method 200 can be applied to, for example... Figure 1Signal processor 100. Please refer to the following as well. Figure 1 as well as Figure 2 .

[0017] Please refer to this first. Figure 3 . Figure 3 This is a 4B / 5B coding comparison diagram depicted according to some embodiments of this disclosure. In some embodiments, the present invention... Figure 1 signal processors and Figure 2 Signal processing methods are applicable to, for example Figure 3 The diagram depicting the 4B / 5B coding comparison.

[0018] For example, the 4B code corresponding to symbol name 0 is 0000, and the 5B code corresponding to symbol name 0 is 11110. The rest follow the same pattern. It should be noted that in some embodiments, when receiving or transmitting bit codes, the least significant bit (LSB) is transmitted. That is, when the 5B code corresponding to symbol name 0 is 11110, the signal receiving circuit 110 receives the bits in the order 0, 1, 1, 1, 1. The rest follow the same pattern.

[0019] Please continue to refer to this. Figure 2 In step S210, the input signal is received and parsed by a signal receiving circuit to generate multiple bit codes. In some embodiments, the input signal is transmitted by a signal transmitter (not shown) and processed by a signal receiver such as... Figure 1 The signal received by the signal receiving circuit 110 shown. In some embodiments, after receiving the input signal, the signal receiving circuit 110 parses the Manchester encoded symbols in the input signal to generate multiple bit codes, and then sequentially transmits the multiple bit codes to the shift register 130 for temporary storage.

[0020] In step S230, multiple bit codes are temporarily stored in a shift register according to a time sequence, and the decoder is started when the multiple temporary storage spaces of the shift register are full of multiple bit codes. In some embodiments, such as Figure 1 The shift register 130 shown temporarily stores multiple bit codes according to a time sequence. In some embodiments, such as... Figure 1 The shift register 130 shown temporarily stores multiple bit codes according to a time sequence. When the temporary storage space of the shift register 130 is full, as follows: Figure 1 The decoder 150 shown is started. In some embodiments, if a new bit code is received before the decoder 150 decodes the 5B boundary, the decoder 150 updates the shift register 130 and excludes the oldest bit code.

[0021] Please refer to this as well. Figure 4 . Figure 4 This is a schematic diagram illustrating the operation of a signal processing method 200 described according to some embodiments of the present disclosure. In some embodiments, Figure 4 It is based on Figure 1 The operation diagram of the signal processing method 200 depicted by the shift register 130 is shown below. Figure 4 As shown, at time T, as Figure 1 The signal receiving circuit 110 shown receives the input signal, which includes the bit code 0001100011001000010011011.

[0022] like Figure 4 As shown, in some embodiments, when encoded with 5-bit codes, such as Figure 1 The shift register 130 shown contains three 5-code temporary storage spaces 132A, 132B, and 132C. For example... Figure 4 As shown, sub-shift registers 132A to 132C each contain 5 temporary storage cells that can temporarily store 5 bit codes.

[0023] like Figure 4 As shown, shift register 130 temporarily stores the bit codes of the input signal according to the time sequence.

[0024] At time T+15t, the temporary storage spaces 132A to 132C of shift register 130 are full of bit code 110000110010000. At this time, as... Figure 1 The decoder 150 shown is started. On the other hand, between time T and time T+15t, the decoder 150 is not started because the shift register 130 has not yet been filled with bit codes.

[0025] Please continue to refer to this. Figure 2 In step S240, it is determined whether the multiple bit codes temporarily stored in the shift register conform to the decoding table rules and boundary detection rules. In some embodiments, step S240 is performed as follows: Figure 1 The decoder 150 shown is used for this purpose.

[0026] In some embodiments, the boundary detection rules are set by the user.

[0027] When it is determined in step S240 that the multiple bit codes temporarily stored in the shift register conform to the decoding table rules and the boundary detection rules, step S250 is executed. In step S250, the decoder performs boundary calibration based on the multiple bit codes temporarily stored in the shift register.

[0028] On the other hand, when it is determined in step S240 that multiple bit codes temporarily stored in the shift register do not conform to the decoding table rules and boundary detection rules, the process returns to step S230, as follows: Figure 1 The decoder 150 shown waits for the shift register 130 to continuously update the bit codes until the multiple bit codes temporarily stored in the shift register 130 conform to the decoding table rules and the boundary detection rules.

[0029] Please refer to Figure 5 . Figure 5 This is a schematic diagram illustrating the operation of another signal processing method 200 described according to some embodiments of the present disclosure. In some embodiments, Figure 5 It is based on Figure 1 The operation diagram of the signal processing method 200 depicted by the shift register 130 is shown below. Figure 5 As shown, at time T, in step S210, as Figure 1 The signal receiving circuit 110 shown receives the input signal. The input signal contains bit code zzz1100011001000010011011, where z is the corrupted data.

[0030] In some embodiments, when a bit code with data corruption is detected, the decoder 150 identifies the corrupted bit code as SILENCE(I), and the corresponding symbol name is I.

[0031] For example, please refer to Figure 5 At time T+15t, the bit code temporarily stored in temporary storage space 132A is zzz11, the bit code temporarily stored in temporary storage space 132B is 00011, and the bit code temporarily stored in temporary storage space 132C is 00100. Decoder 150 follows the... Figure 3 The decoding table 300 shown determines that the symbol name corresponding to the 5-bit code stored in the temporary storage space 132A is I, the symbol name corresponding to the 5-bit code stored in the temporary storage space 132B is J, and the symbol name corresponding to the 5-bit code stored in the temporary storage space 132C is H.

[0032] In some embodiments, the decoder 150 is also used to determine whether the bit code temporarily stored in the shift register 130 conforms to the boundary detection rules. The boundary detection rules will be explained below.

[0033] In some embodiments, a specific symbol name includes symbol name J, symbol name H, symbol name N, and symbol name T. In some embodiments, symbol name J is SYNC(J) (synchronization J), symbol name H is SSD(H) (data stream start separator H), symbol name N is BEACO(N) (beacon N), and symbol name T is HB(T) (heartbeat T).

[0034] Please refer to Figure 6 . Figure 6 This is a schematic diagram illustrating a data format according to some embodiments of the present disclosure. Figure 6The diagram illustrates four common 5B-encoded data formats. The first is Packet Header Type 1, consisting of multiple symbolic names J followed by two symbolic names H, and then the data type. The second is Packet Header Type 2, consisting of multiple symbolic names J followed by symbolic names T, and then symbolic names R. The third is the PLCA Command, consisting of five symbolic names N. The fourth is the Heartbeat Command, consisting of five symbolic names T.

[0035] Depend on Figure 6 It can be seen that the symbol name J is followed by another symbol name J, symbol name H, or symbol name T. In some embodiments, when... Figure 1 The decoder 150 shown determines the following: Figure 4 When the symbol name corresponding to the multiple bit codes temporarily stored in the temporary storage space 132A is J, the decoder 150 locks the decoding boundary based on the multiple bit codes temporarily stored in the shift register 130 to perform decoding.

[0036] Because both symbol names H and N have only one code value of 1 in 5B encoding, consecutive combinations of symbol names H and N can easily lead to confusion and incorrect judgment. Figure 6 It can be seen that, according to the 10BASE-TIS specification and transmission format, the symbol name H will only appear twice, followed by data from symbol names 0 to F. Therefore, using three shift registers 130 with a temporary storage space of 5 bits each can avoid confusion between symbol name H and symbol name N.

[0037] In some embodiments, when as Figure 1 The decoder 150 shown determines the following: Figure 4 When the symbol name corresponding to the multiple bit codes temporarily stored in the temporary storage space 132A shown is H, the decoder 150 determines as follows: Figure 4 The multiple bit codes temporarily stored in the temporary storage space 132B shown are based on the following... Figure 3 The rule shown in decoding table 300 determines whether the corresponding symbol name is H after decoding.

[0038] When the temporary storage space 132B stores multiple bit codes according to, Figure 3 When the symbol name H is decoded according to the rules of the decoding table 300 shown, the decoder 150 locks the decoding boundary based on the multiple bit codes temporarily stored in the shift register 130 to perform decoding. That is, when two consecutive symbol names H appear, the decoder 150 locks the decoding boundary.

[0039] Please continue to refer to this. Figure 6 Since the symbol name N appears five times consecutively, even with the loss of 10 bits of information, there are still three instances of the symbol name N. Therefore, a boundary detection rule is set to address this characteristic and prevent confusion with the symbol name H. Specifically, when three consecutive instances of the symbol name H are detected, the decoding boundary is locked.

[0040] In some embodiments, when as Figure 1 The decoder 150 shown determines the following: Figure 4 When the symbol name corresponding to the multiple bit codes temporarily stored in the temporary storage space 132A shown is N, the decoder 150 determines the multiple bit codes temporarily stored in the temporary storage space 132B based on the following criteria: Figure 3 After decoding according to the rules of the decoding table 300 shown, it is determined whether the symbol name is N. Furthermore, the decoder 150 determines the multiple bit codes temporarily stored in the temporary storage space 132C based on the following... Figure 3 After decoding according to the rules of the decoding table 300 shown, is it the symbol name N?

[0041] When multiple bit codes temporarily stored in temporary storage space 132B are based on, as follows Figure 3 The decoding table 300 shown is decoded into the symbol name N, and the multiple bit codes temporarily stored in the temporary storage space 132C are based on the following... Figure 3 When the symbol name N is obtained after decoding according to the rules of the decoding table 300 shown, the decoder 150 locks the decoding boundary according to the multiple bit codes temporarily stored in the shift register 130 to perform decoding.

[0042] In addition, such as Figure 6 As described, since the symbol name T appears five times consecutively, even with the loss of 10 bits of information, three symbol names T still exist. Therefore, a boundary detection rule is set based on this characteristic to avoid confusion with the symbol name H. That is, when it is determined that three consecutive symbol names T appear, the decoding boundary is locked.

[0043] In some embodiments, when as Figure 1 The decoder 150 shown determines the following: Figure 4 When the symbol name corresponding to the multiple bit codes temporarily stored in the temporary storage space 132A shown is T, the decoder 150 determines the multiple bit codes temporarily stored in the temporary storage space 132B based on the following criteria: Figure 3 The rules in the decoding table 300 shown indicate whether the decoded result is the symbol name T. Furthermore, the decoder 150 determines the multiple bit codes temporarily stored in the temporary storage space 132C based on the following... Figure 3 After decoding according to the rules of the decoding table 300 shown, is it the symbol name T?

[0044] When multiple bit codes temporarily stored in temporary storage space 132B are based on, as follows Figure 3The decoding table 300 shown is decoded into the symbol name T, and the multiple bit codes temporarily stored in the temporary storage space 132C are based on the following... Figure 3 When the symbol name T is obtained after decoding according to the rules of the decoding table 300 shown, the decoder 150 locks the decoding boundary according to the multiple bit codes temporarily stored in the shift register 130 to perform decoding.

[0045] In some other embodiments, the boundary detection rule may also take the symbol name I into consideration to increase flexibility in use. The boundary detection rules described above are for illustrative purposes only, and the implementation of the present invention is not limited thereto.

[0046] In summary, this disclosure provides a signal processing method and a signal processor. The mechanism of judging by combining multiple 5B symbol names can not only avoid misjudgment, but also has more flexibility to adjust the judgment boundary detection rules according to different situations, so as to effectively improve the accuracy of judging 5B boundaries.

[0047] In some embodiments, the decoder 150 may be a server or other device. In some embodiments, the decoder 150 may be a server, circuit, central processing unit (CPU), microcontroller (MCU), or other device with equivalent functions, possessing functions such as temporary storage, computation, data reading, receiving signals or information, and transmitting signals or information. In some embodiments, the shift register 130 may be a circuit with signal temporary storage or similar functions. The signal receiving circuit 110 may be a component with signal receiving functions or similar functions.

[0048] Furthermore, the examples above include sequential exemplary steps, but these steps need not be performed in the order shown. Performing these steps in different orders is within the scope of this disclosure. Within the spirit and scope of the embodiments of this disclosure, these steps may be added, substituted, changed in order, and / or omitted as appropriate.

[0049] Although this disclosure has been described above with reference to embodiments, it is not intended to limit this disclosure. Any person skilled in the art can make various changes and improvements without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the appended claims.

[0050] Explanation of reference numerals in the attached figures:

[0051] 100: Signal Processor

[0052] 110: Signal receiving circuit

[0053] 130: Shift Register

[0054] 150: Decoder

[0055] 200: Signal Processing Methods

[0056] S210, S230, S240, S250: Steps

[0057] 300: Decoding Table

[0058] 132A, 132B, 132C: Temporary storage space

Claims

1. A signal processing method, comprising: The input signal is received by a signal receiving circuit, and the input signal is parsed to generate multiple bit codes; The first part of these bit codes is temporarily stored in a shift register according to the time sequence, and the decoder is started when the shift register is full; When the bit codes of the first part conform to the decoding table rules and the boundary detection rules, the decoder performs boundary calibration based on the bit codes of the first part. in, The boundary detection rule includes: when the bit codes of the first part correspond to a symbol name J, followed by multiple symbol names H, followed by multiple symbol names N, or followed by multiple symbol names T, the decoder locks the decoding boundary based on the bit codes of the first part.

2. The signal processing method as claimed in claim 1, wherein the shift register includes multiple temporary storage spaces, and each of these shift registers includes 5 temporary storage cells, wherein the shift register is encoded using 5-code.

3. The signal processing method as described in claim 2, wherein the boundary detection rule includes whether the bit codes of the portion temporarily stored in the first temporary space of these temporary spaces conform to one of a plurality of specific symbol names after being decoded according to the decoding table rule.

4. The signal processing method as described in claim 3, wherein the boundary detection rule further comprises: When one of these specific symbol names is symbol name J, the decoder locks the decoding boundary based on the bit codes temporarily stored in the shift register.

5. The signal processing method as described in claim 3, wherein the boundary detection rule further comprises: When one of these specific symbol names is symbol name H, the decoder determines whether the bit codes in the portion temporarily stored in the second temporary space of these temporary spaces, after being decoded according to the decoding table rules, are symbol name H; and When the bit codes in the portion temporarily stored in the second temporary storage space are decoded into a symbol name H according to the decoding table rules, the decoder locks the decoding boundary based on the bit codes in the portion temporarily stored in the shift register.

6. The signal processing method of claim 3, wherein the boundary detection rule further comprises: When one of these specific symbol names is symbol name N, the decoder determines whether the bit codes of the part temporarily stored in the second temporary space of these temporary spaces are symbol name N after being decoded according to the decoding table rules; The decoder determines whether the bit codes in the third temporary space among these temporary spaces are symbol names N after being decoded according to the decoding table rules; as well as When the bit codes in the second temporary storage space are decoded into symbol name N according to the decoding table rules, and the bit codes in the third temporary storage space are decoded into symbol name N according to the decoding table rules, the decoder locks the decoding boundary based on the bit codes in the shift register.

7. The signal processing method as described in claim 3, wherein the boundary detection rule further comprises: When one of these specific symbol names is a symbol name T, the decoder determines whether the bits in the part temporarily stored in the second temporary space of these temporary spaces are symbol names T after being decoded according to the decoding table rules; The decoder determines whether the bit codes in the third temporary space among these temporary spaces are symbol names T after being decoded according to the decoding table rules; as well as When the bit codes in the second temporary storage space are decoded into symbol name T according to the decoding table rules, and the bit codes in the third temporary storage space are decoded into symbol name T according to the decoding table rules, the decoder locks the decoding boundary based on the bit codes in the shift register.

8. A signal processor, comprising: A signal receiving circuit is used to receive an input signal and parse the input signal to generate multiple bit codes; A shift register temporarily stores these bits from the first part according to the time sequence; and The decoder is activated when the shift register is full and is used to perform boundary calibration based on the bit codes of the first part when the bit codes of the first part conform to the decoding table rules and the boundary detection rules. in, The boundary detection rule includes: when the bit codes of the first part correspond to a symbol name J, followed by multiple symbol names H, followed by multiple symbol names N, or followed by multiple symbol names T, the decoder locks the decoding boundary based on the bit codes of the first part.

9. The signal processor of claim 8, wherein when the bit codes of the first part do not conform to the decoding table rules and the boundary detection rules, the shift register is updated to temporarily store the bit codes of the second part, and the decoder is further used to determine whether the bit codes of the second part conform to the decoding table rules and the boundary detection rules.

10. The signal processor of claim 9, wherein the bit codes of the second portion are composed of the bit codes of the first portion shifted by one bit.

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