A sorting control method, device and medium for a DCS control system

Abstract

The present invention discloses a sorting control method for a DCS control system. The upstream logic triggers the input pins of the queuing function block to activate the corresponding output pins. The corresponding output pins are activated in ascending or descending order for the triggered input pins; it is also necessary to determine whether there is overlapping control for multiple simultaneously activated output pins; and to determine whether the number of multiple simultaneously activated output pins reaches a preset threshold. The present invention supports a large sorting volume and greatly improves the sorting capacity. It unifies ascending and descending sorting and supports both ascending and descending sorting. And it has built-in priority processing. Regardless of ascending or descending sorting, the smaller the channel number, the higher the priority in the same cycle. It does not occupy the global array and liberates system resources. It has dual queries of the timing table and the channel table, which is convenient for program editing and data reference. It supports the insertion sequence function, and any valid channel can be inserted to any valid position, as well as the insertion sequence protection function, which can protect the existing output results from being affected by the insertion sequence function.

Description

Technical Field

[0001] The present invention belongs to the field of industrial control, and particularly relates to a sorting control method, device and medium for a DCS control system. Background Art

[0002] DCS: The full name is "Distributed Control System", which can also be directly translated as "Distributed Control System" or "Distributed Computer Control System". It is a new generation of instrument control system based on microprocessors, adopting the design principle of decentralized control functions, centralized display and operation, and taking into account decentralized autonomy and comprehensive coordination. It adopts a multi-layer hierarchical and cooperative autonomous structure form, and its main feature is its centralized management and decentralized control. DCS has been extremely widely used in various industries such as electric power, metallurgy, and petrochemical.

[0003] The existing DCS in the prior art has the following technical problems: Capacity: Generally only supports 8 channels, 16 channels, 32 channels, 64 channels for queuing, with the problem of small capacity. Sequence: Generally only supports positive sequences and does not support reverse sequences. Priority: Generally, the smaller the channel number, the higher the priority in the same cycle. Global array: Generally occupies, and is likely to occupy above 32 channels, occupying system resources. Timing table, channel table: Generally only has a timing table or its prototype, without the cooperation of the timing table and the channel table, which is not conducive to fast query. Insertion order: Generally only supports insertion in the second execution order, does not support arbitrary insertion order, and has no insertion order protection function. Maximum output configuration: Generally does not have, is hard-coded, and the value is 1, and does not support maximum output configuration. Summary of the Invention

[0004] The technical objective of the present invention is to provide a sorting control method, device and medium for a DCS control system to solve the technical problems of small sorting quantity, non-support for reverse sequences, occupation of system resources, non-conduciveness to fast query, non-support for arbitrary insertion order, no insertion order protection function, and non-support for maximum output configuration.

[0005] To solve the above problems, the technical solution of the present invention is as follows:

[0006] A sorting control method for a DCS control system includes the following steps:

[0007] The input pins of the queuing function block are triggered by the upstream logic to activate the output pins of the corresponding queuing function block. Among them, the queuing function block is connected with a Boolean data, which is used to convert the Boolean data into an electrical signal of 0 - 24VDC or 0 - 220VAC to drive an external device connected to the output pin.

[0008] Specifically, controlling and activating the output pins of the corresponding queuing function block by the queuing function block includes the following steps:

[0009] Under the same priority, for the triggered input pins, the corresponding output pins are activated in the positive sequence or the reverse sequence; it is judged whether there is overlapping control among the multiple simultaneously activated output pins. If there is, only one of the overlapping output pins is activated in the positive sequence or the reverse sequence; it is judged whether the number of the multiple simultaneously activated output pins reaches a preset threshold. If it reaches the preset threshold, the output pins with the number of the preset threshold are activated, and the remaining output pins are in an unactivated state.

[0010] Among them, the queuing function block includes 96 input pins and 96 output pins, the maximum sorting quantity is 96, the input pins are respectively named as IN1, IN2, …, IN96 according to the serial numbers, the output pins are respectively named as OUT1, OUT2, …, OUT96 according to the serial numbers, and the input pins and the output pins with the same serial number are mutually associated.

[0011] Specifically, under the same priority,

[0012] for the triggered input pins, the corresponding output pins are activated in the positive sequence, and the corresponding output pins are activated in the same order as the upstream logic input order;

[0013] for the triggered input pins, the corresponding output pins are activated in the reverse sequence, and the corresponding output pins are activated in the reverse order of the upstream logic input order.

[0014] Among them, a single input pin and a periodic pin group composed of several input pins are under the same priority, and the corresponding output pins are activated following the positive sequence or the reverse sequence;

[0015] In the same periodic pin group, the input pins use the serial numbers as the activation priorities, and the input pins are used to activate the corresponding output pins in ascending order of the serial numbers.

[0016] Specifically, when the corresponding output pins are activated, the activated output pins are recorded in real time through a channel table or a timing table;

[0017] The arrangement of the table cells of the channel table represents the channel serial number, which is the serial number of the input pin or the output pin, and the number in the table cell of the channel table is the sorting of the activated corresponding output pin;

[0018] The arrangement of the table cells of the timing table represents the sorting of the activated corresponding output pin, and the number in the table cell of the channel table represents the channel serial number, which is the serial number of the input pin or the output pin.

[0019] Preferably, an insertion sequence function is also supported, and any valid channel is inserted into a valid position;

[0020] The valid channel is the input pin triggered by the upstream logic and the corresponding activated or to-be-activated output pin;

[0021] The valid position is that the valid channels are sorted in the maximum sorting quantity of the queuing function block.

[0022] Preferably, when inserting the sequence, it is also necessary to determine whether to start the insert sequence protection;

[0023] If the insert sequence protection is enabled, the activated output pins are not affected by the insert sequence;

[0024] If the insert sequence protection is not enabled, the insert sequence is completed regardless of the activated output pins.

[0025] An electronic device includes a processor and a memory. A computer instruction that can run on the processor is stored on the memory. The processor is used to call the computer instruction in the memory to execute the sorting control method for the DCS control system as described in any one of the above.

[0026] A storage medium is used to store computer instructions. When the computer instructions run, the device where the storage medium is located is controlled to execute the sorting control method for the DCS control system as described in any one of the above.

[0027] Due to the adoption of the above technical solutions, the present invention has the following advantages and positive effects compared with the prior art:

[0028] The present invention supports a large sorting quantity, can support 96-channel sorting, and can greatly improve the sorting capacity. It has unified forward and reverse sorting, supporting forward sorting and reverse sorting. And it has built-in priority processing. Regardless of forward or reverse sorting, the smaller the channel number, the higher the priority in the same cycle. It does not occupy the global array, liberating system resources. It has dual queries of the timing table and the channel table, which is convenient for program editing and data reference. It supports the insert sequence function, and any valid channel can be inserted to any valid position to achieve arbitrary insert sequence and insert sequence protection; the built-in insert sequence protection function can protect the existing output results from being affected by the insert sequence function. The present invention also has a built-in maximum output configuration, and the output quantity can be configured. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] By reading the following detailed description of the preferred embodiments, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the present invention.

[0030] Figure 1 It is the external shape diagram of the queuing function block of the present invention;

[0031] Figures 2 to 4 It is the internal attribute diagram of the queuing function block of the present invention;

[0032] Figure 5 It is the structural diagram of the timing table or the channel table of the present invention;

[0033] Figures 6 to 18This is the specific implementation diagram of the present invention. Specific implementation manner

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the specific implementation manners of the present invention will be described below with reference to the accompanying drawings. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings, and other implementation manners can also be obtained.

[0035] To make the drawings concise, only the parts related to the present invention are schematically shown in each drawing, and they do not represent the actual structure of the product. In addition, to make the drawings concise and easy to understand, in some drawings, parts with the same structure or function are only schematically shown for one of them, or only one of them is marked. In this article, "one" not only means "only this one", but also means "more than one" situation.

[0036] The following further describes in detail a sorting control method, device and medium for a DCS control system proposed by the present invention with reference to the accompanying drawings and specific embodiments. According to the following description and the claims, the advantages and features of the present invention will be clearer.

[0037] Embodiment

[0038] Embodiment

[0039] Refer to Figures 1 to 18 , this embodiment provides a sorting control method for a DCS control system, including the following steps:

[0040] The input pins of the queuing function block are triggered by the upstream logic to activate the output pins of the corresponding queuing function block. Specifically, refer to Figure 1 , the queuing function block supports at most 96 boolean input pins and 96 boolean output pins. The input pins are named IN1, IN2,..., IN96 in sequence, and the output pins are named OUT1, OUT2,..., OUT96 in sequence. Each group of input pins and output pins with the same serial number are associated with each other. Boolean data can be connected upstream of the input pins and downstream of the output pins. At this time, in this embodiment, the boolean data is converted into electrical signals such as 0-24VDC and 0-220VAC to drive external field devices.

[0041] Specifically, controlling and activating the output pins of the corresponding queuing function block through the queuing function block includes the following steps:

[0042] At the same priority level, for the triggered input pins, the corresponding output pins are activated in the forward sequence or reverse sequence. Specifically, at the same priority level, for the triggered input pins, the corresponding output pins are activated in the forward sequence, activating the corresponding output pins in the same order as the upstream logic input; for the triggered input pins, the corresponding output pins are activated in the reverse sequence, activating the corresponding output pins in the reverse order of the upstream logic input. Whether it is IN1, IN2, IN3 or IN2, IN3, IN1 or IN2, IN1, IN3 that are triggered successively, the output logic always follows the principle of first come, first served (forward sequence) or last come, first served (reverse sequence), and is activated and output in the set order.

[0043] However, not all input pins are at the same priority level. For example, a periodic pin group composed of several input pins and other independent input pins are at the same priority level, and the periodic pin group as a whole follows the forward sequence or reverse sequence to activate the corresponding output pins. In the same periodic pin group, the input pins use the serial number as the activation priority, and the input pins are activated in ascending order of the serial number to activate the corresponding output pins. For example, IN1, IN2, and IN3 are in the same periodic pin group and are triggered simultaneously. Since the number of outputs is limited, there is a concept of priority for pins within the same period. The smaller the pin serial number, the higher the priority within the same period. Therefore, for 3 objects connected to 3 pins, it is best to connect the important objects to the pins with smaller serial numbers. This has been processed internally, whether it is the forward sequence or the reverse sequence.

[0044] In addition, it is also necessary to determine whether there is overlapping control for multiple output pins activated simultaneously. If so, only one of the overlapping output pins is activated in the forward sequence or reverse sequence. For example, there are ten logic segments that need to control different devices, but there is a common device. To avoid mistakes, only one logic segment can control this common device at the same time. However, the running times of these ten logic segments may overlap. To avoid simultaneous control, a queuing function is required.

[0045] In addition, it is also necessary to determine whether the number of multiple output pins activated simultaneously reaches a preset threshold. If it reaches the preset threshold, the output pins with the preset threshold number are activated, and the remaining output pins are in an unactivated state. Since the total power on-site is fixed, for example, if only 20 large devices can operate simultaneously, exceeding this number will pose a risk of tripping. To ensure normal operation on-site, queuing is required, and the excess beyond 20 needs to be restricted. Only when any one of the first 20 devices ends can the subsequent devices be activated and conduct this embodiment to achieve operation.

[0046] In addition, for on-line maintenance of equipment, that is, maintenance while the equipment is working, assuming that 15 devices can be maintained simultaneously and the maintenance time is 24 hours, the longer the maintenance time, the lower the failure rate. Detected by a certain detection mechanism, when a certain quantity is reached, it enters the on-line maintenance mode to ensure that the 15 devices under maintenance are all the devices with the highest failure rate.

[0047] Preferably, this embodiment does not occupy the global array, liberating system resources.

[0048] Specifically, referring to Figure 5 , while activating the corresponding output pins, the activated output pins are recorded in real time through a channel table or a timing table. Now, the channel table and the timing table are described as follows:

[0049] The channel table is a table obtained by arranging the execution order according to the channel numbers, which can be mutually converted with the timing table and is used to quickly find the execution sequence corresponding to a certain channel number. The arrangement of the table cells in the channel table represents the channel serial number, which is the serial number of the input pin or output pin, and the number in the table cell of the channel table is the sorting of activating the corresponding output pin.

[0050] Specifically, each row of the channel table is set with a maximum of 32 numbers. Therefore, for 96-channel sorting, it is converted into a table of 3 rows * 32 columns. From left to right in the first row of the channel table, it represents the current sorting of channels 1-32. From left to right in the second row, it represents the current sorting of channels 33-64. From left to right in the third row, it represents the current sorting of channels 65-96. The channel number is the serial number of the input pin.

[0051] Current channel = row number * 32 + column number + 1. For example, [0][0] represents channel 1, and [2]

[31] represents channel 96. The intersection of the row and the column determines the sorting where a channel is located, that is, the number in the figure. The query result of the channel table is a sorting number.

[0052] If the IN1 pin is set to ON due to upstream logic while the other pins are all OFF, then at this time [0][0] = 1, meaning that channel 1 is ranked first, and at the same time the OUT1 output is set to ON, transmitting a boolean quantity information. Other logics can make corresponding changes when detecting this change. If this information represents the start signal of the first of ten mutually exclusive units, then unit 1 will start accordingly. If in the next cycle, the IN5 pin is also set to ON, then [0][4] = 2, meaning that channel 5 is ranked second. However, the OUT5 output will not be set to ON. Only when IN1 is set to OFF and IN5 is still ON, the OUT5 will be set to ON. When [0][4] = 1, unit 5 will start at this time.

[0053] The timing table is a table obtained by arranging channel numbers in the execution order, which can be mutually converted with the channel table and is used to quickly find the channel number corresponding to a certain execution sequence. The arrangement of the table cells in the timing table represents the sorting for activating the corresponding output pins, and the numbers in the table cells of the channel table represent the channel numbers, which are the numbers of input pins or output pins.

[0054] Specifically, similar to the channel table, at most 32 numbers are set in each row of the timing table. Therefore, for 96-channel sorting, it is converted into a table of 3 rows * 32 columns. From left to right in the first row of the timing table, it represents the current channels of sequences 1 - 32; from left to right in the second row, it represents the current channels of sequences 33 - 64; from left to right in the third row, it represents the current channels of sequences 65 - 96.

[0055] Current serial number = row number * 32 + column number + 1; for example, [0][0] represents sequence 1, and [2]

[31] represents sequence 96. The intersection of the row and the column determines the channel where a serial number is located, that is, the blue number in the figure. That is, the query result of the timing table is a channel number.

[0056] If the IN1 pin is set to ON due to upstream logic while the other pins are all OFF, then at this time [0][0] = 1, meaning that serial number 1 is channel 1, and at the same time the OUT1 output is set to ON, transmitting a boolean quantity information. Other logics can make corresponding changes when detecting this change. If this information represents the start signal of the first of ten mutually exclusive units, then unit 1 will start accordingly. If in the next control cycle, the IN5 pin is also set to ON, then [0][1] = 5, meaning that sorting 2 is channel 5. However, the OUT5 output will not be set to ON. Only when IN1 is set to OFF and IN5 is still ON, will OUT5 be set to ON, because at this time [0][0] = 5 (when the previous serial number channel is set to OFF, the subsequent serial numbers are automatically filled in), and then unit 5 will start.

[0057] Next, the control cycle is generally 500MS. As long as there is a change within 500MS, the value at that moment will be transmitted into the DCS system during the next acquisition, and thus enter the input pins IN1 - IN96. If both IN1 and IN5 are set to ON within 500MS while the other channels are all OFF, then the output OUT1 = ON, OUT5 = OFF. If IN2 and IN6 are also set to ON in the next cycle, then at this time serial number 1 is channel 1, serial number 2 is channel 5, serial number 3 is channel 2, and serial number 4 is channel 6.

[0058] See Figures 6 to 18 for a detailed description of the specific implementation of this embodiment.

[0059] Specifically, see Figures 6 to 9, due to the existence of built-in priority processing, regardless of positive or reverse sorting, within the same cycle pin group, the smaller the channel number, the higher the priority. Figure 6 For positive sorting, the maximum output is 1. Channels 2, 3, and 4 have not been activated simultaneously, and the timing table is all 0. Then in Figure 7 , channels 2, 3, and 4 are activated simultaneously. Since the smaller the number, the higher the priority, they are sorted as 2, 3, and 4 in the timing table. And the maximum output is 1, so channel 2, that is, OUT2, successfully outputs. Figure 8 For reverse sorting, the maximum output is 2. Channels 13, 14, and 15 have not been activated simultaneously, so the timing table is all 0. Then in Figure 9 , channels 13, 14, and 15 are activated simultaneously. Since the smaller the number, the higher the priority, they are sorted as 13, 14, and 15 in the timing table. And the maximum output is 2, so channels 13 and 14, that is, OUT13 and OUT14, successfully output.

[0060] Specifically, refer to Figures 10 to 13 for the upstream logic to illustrate the control processes of positive sorting and reverse sorting for channels with the same priority. Figure 10 For positive sorting, the maximum output is 1. Channels 7, 5, 11, and 9 are activated successively, and the timing table is also arranged as 7, 5, 11, and 9. Since the maximum output is 1, only channel 7 at the [0, 0] position in the timing table is successfully conducted. Figure 11 For positive sorting, the maximum output is 1. After channels 7, 5, 11, and 9 are activated successively and then channels 7 and 11 are deactivated, at this time, the timing table is arranged as 5 and 9. Since the maximum output is 1, only channel 5 at the [0, 0] position is in the conducting state. Figure 12 For reverse sorting, the maximum output is 2. Channels 7, 5, 11, and 9 are activated successively, and the timing table is set in reverse as 9, 11, 5, and 7. Since the maximum output is 2, channels 9 and 11 at the [0, 0] and [0, 1] positions in the timing table are successfully conducted. Figure 13 Also for reverse sorting, the maximum output is 2. After channels 7, 5, 11, and 9 are activated successively and then channels 7 and 11 are deactivated, at this time, the timing table is set in reverse as 9 and 5 after removing 7 and 11. Since the maximum output is 2, both channels 9 and 5 at the [0, 0] and [0, 1] positions are successfully conducted.

[0061] Specifically, refer to Figure 14 and Figure 15 to illustrate the differences between the timing table and the channel table. Taking Figure 14 as an example, for positive sorting, channels 6, 10, 8, and 12 are activated successively. At this time, the numbers 6, 10, 8, and 12 are filled in the first row of the timing table from left to right in sequence, and the numbers represent the channel numbers. Taking Figure 15 as an example, for positive sorting, and the activation order of channels is the same as that in Figure 14The same. At this time, in the channel table, [0, 5], i.e., channel 6, is marked with the number 1; [0, 9], i.e., channel 10, is marked with the number 2; [0, 7], i.e., channel 8, is marked with the number 3; [0, 11], i.e., channel 12, is marked with the number 4. The numbers represent the sorting numbers.

[0062] Preferably, referring to Figure 4 , Figures 16 to 18 , this embodiment also supports the function of inserting sequences, and any valid channel can be inserted into a valid position. There are 4 operation parameters for inserting sequences. Fill in the channel that needs to insert the sequence at CX_IN. As Figure 16 shown, select channel 12. CX_TGT is the target serial number for inserting the sequence. As Figure 16 shown, it is to be inserted into the 2nd position. After the successful insertion of the sequence, as Figure 17 shown, the sorting of the timing table changes from 6, 10, 8, 12 to 6, 12, 10, 8, indicating the successful insertion of the sequence. CX_PRO is whether to enable the protection for inserting the sequence. If it is enabled, the serial number with the output OUT of the channel being ON cannot be directly inserted. If 1 is filled in at ON_MAX to enable the protection for inserting the sequence, the serial number cannot be directly inserted into the 1st position because this will cause a sudden change in the output signal. If each channel represents a unit, the starting unit will be immediately changed, which may have an impact on the life of the unit, etc. If CX_CMD is set to ON, a sequence insertion is completed, and the result is as Figure 18 shown, which is to insert channel 12 into the position of the 1st sequence.

[0063] Furthermore, this embodiment also provides an electronic device. The electronic device includes a processor and a memory. A computer instruction that can run on the processor is stored on the memory. The processor is used to call the computer instruction in the memory to execute the sorting control method for the DCS control system as described above.

[0064] In addition, this embodiment also provides a storage medium. The storage medium is used to store computer instructions. Among them, when the computer instructions run, the device where the storage medium is located is controlled to execute the sorting control method for the DCS control system as described above.

[0065] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Even if various changes are made to the present invention, provided that these changes fall within the scope of the claims of the present invention and their equivalent technologies, they still fall within the protection scope of the present invention.

Claims

1. A sorting control method for a DCS control system, characterized in that, It includes the following steps: The input pins of the queuing function block are triggered by the upstream logic to activate the output pins corresponding to the queuing function block. Among them, the queuing function block is connected with Boolean data, which is used to convert the Boolean data into electrical signals of 0 - 24VDC or 0 - 220VAC to drive external devices connected to the output pins; Specifically, the control and activation of the output pins corresponding to the queuing function block through the queuing function block include the following steps: Under the same priority, the output pins corresponding to the triggered input pins are activated in ascending or descending order; during the activation process, it is judged whether the number of the activated output pins reaches a preset threshold. If it reaches the preset threshold, the preset threshold number of the output pins are activated, and the remaining output pins are in an unactivated state. After the activated output pins are deactivated, they are activated in turn according to the queuing order; at the same time, it is judged whether there is overlapping control for the multiple output pins to be activated. If so, only one of the overlapping output pins is activated in ascending or descending order, and the remaining output pins enter the queue; Among them, overlapping control is defined as that the output logics of multiple output pins control the same common device, resulting in overlapping of the response time of the same common device to the above logics, that is, device overlapping control occurs.

2. The sorting control method for a DCS control system according to claim 1, characterized in that, The queuing function block includes 96 input pins and 96 output pins, and the maximum sorting quantity is 96. The input pins are respectively named IN1, IN2, …, IN96 according to the serial numbers, and the output pins are respectively named OUT1, OUT2, …, OUT96 according to the serial numbers. The input pins and the output pins with the same serial number are mutually associated.

3. The sorting control method for a DCS control system according to claim 2, wherein Under the same priority, For the triggered input pins, the corresponding output pins are activated in ascending order, and the corresponding output pins are activated in the same order as the upstream logic input; For the triggered input pins, the corresponding output pins are activated in descending order, and the corresponding output pins are activated in the reverse order of the upstream logic input.

4. The sorting control method for a DCS control system according to claim 3, characterized in that, A single input pin and a periodic pin group composed of several input pins are under the same priority, and the corresponding output pins are activated following the ascending or descending order; In the same periodic pin group, the input pins use the serial number as the activation priority, and the input pins are activated in ascending order of the serial number to activate the corresponding output pins in turn.

5. The sorting control method for a DCS control system according to claim 2, characterized in that, While activating the corresponding output pins, the activated output pins are recorded in real time through a channel table or a timing table; The arrangement of the table cells of the channel table represents the channel serial number, which is the serial number of the input pin or the output pin, and the number in the table cell of the channel table is the sorting of the activated corresponding output pin; The arrangement of the table cells of the timing table represents the sorting of the activated corresponding output pin, and the number in the table cell of the channel table represents the channel serial number, which is the serial number of the input pin or the output pin.

6. The sorting control method for a DCS control system according to claim 2, characterized in that Further preferably, it also supports the function of inserting order, and any valid channel can be inserted into a valid position; The effective channel is the input pin triggered by the upstream logic and the corresponding output pin that is activated or to be activated; The effective position is that the effective channel is sorted in the maximum sorting quantity of the queuing function block.

7. The sorting control method for a DCS control system according to claim 6, wherein Further preferably, it is also necessary to judge whether to start the insertion protection during the insertion sequence; If the insertion protection is enabled, the activated output pins are not affected by the insertion sequence; If the insertion protection is not enabled, the insertion sequence is completed regardless of the activated output pins.

8. An electronic device, characterized in that, The electronic device includes a processor and a memory, and the memory stores computer instructions that can run on the processor, and the processor is used to call the computer instructions in the memory to execute the sorting control method for the DCS control system according to any one of claims 1-7.

9. A storage medium, characterized in that, The storage medium is used to store computer instructions, wherein, when the computer instructions run, the device where the storage medium is located is controlled to execute the sorting control method for the DCS control system according to any one of claims 1-7.

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