Chip interconnect structure, its fabrication method, and chip packaging structure

Abstract

This application relates to a chip interconnect structure, its fabrication method, and a chip packaging structure. The chip interconnect structure includes a semiconductor layer and a first wiring layer. The semiconductor layer has a first side facing the chip and a second side opposite to the first side. A first electrode extending from the first side to the second side is provided within the semiconductor layer. The first wiring layer is located on the first side of the semiconductor layer and includes a plurality of electrically isolated first wirings and a plurality of second wirings, each second wiring corresponding to a first electrode. The first wirings are used to electrically connect first chip pins of two chips. The second chip pins of each chip are electrically connected to external circuits through corresponding second wirings and corresponding first electrodes. This design can increase the power supply path area and avoid insufficient power supply to the chip.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a chip interconnect structure, its fabrication method, and a chip packaging structure. Background Technology

[0002] In related technologies, semiconductor processes are used to fabricate interconnect lines on silicon wafers in chip packaging structures. These interconnect lines connect chips with different functions to the same silicon wafer, thereby achieving signal interconnection between chips with different functions. However, traditional chip packaging structures suffer from insufficient power supply from external power sources to the chips. Summary of the Invention

[0003] Therefore, it is necessary to address the problem of insufficient external power supply to the chip in traditional chip packaging structures by providing a chip interconnect structure, its fabrication method, and a chip packaging structure.

[0004] According to a first aspect of this application, a chip interconnect structure is provided for connecting two chips, wherein each chip includes a plurality of first chip pins and a plurality of second chip pins, and the chip interconnect structure includes:

[0005] A semiconductor layer has a first side facing the chip and a second side disposed opposite to the first side, wherein a first electrode is provided within the semiconductor layer extending from the first side to the second side; and

[0006] A first wiring layer is disposed on a first side of the semiconductor layer and includes a plurality of first wirings and a plurality of second wirings electrically isolated from each other, wherein each second wiring corresponds to a first electrode.

[0007] Wherein, the first wiring is used to electrically connect the first chip pins of the two chips;

[0008] The second chip pin of each chip is electrically connected to an external circuit through the corresponding second wiring and the corresponding first electrode.

[0009] In one embodiment, the semiconductor layer has a through-hole extending from the first side to the second side;

[0010] The first electrode includes a dielectric layer and a conductive structure. The dielectric layer is disposed on the sidewall of the via and surrounds the sidewall of the conductive structure.

[0011] In one embodiment, the via extends from the first side to the second side along the thickness direction of the semiconductor layer.

[0012] In one embodiment, the chip interconnect structure further includes a second wiring layer disposed on the second side of the semiconductor layer, the side of the second wiring layer opposite to the semiconductor layer being provided with a plurality of first external connector pins corresponding to the first electrodes, and the second wiring layer being provided with a plurality of third wirings corresponding to the first external connector pins.

[0013] The first electrode is electrically connected to the external circuit through the corresponding third wiring and the corresponding first external connector pin.

[0014] According to a second aspect of this application, a chip packaging structure is provided, including the chip interconnect structure described above.

[0015] In one embodiment, the chip further includes a plurality of third chip pins spaced apart;

[0016] The chip packaging structure also includes a plurality of second electrodes corresponding one-to-one with the pins of the third chip. The plurality of second electrodes surround the periphery of the chip interconnect structure and are electrically isolated from each other.

[0017] The third chip pin of the chip is electrically connected to an external circuit via the corresponding second electrode.

[0018] In one embodiment, the chip package structure further includes a dielectric intermediate layer that surrounds the periphery of the chip interconnect structure and fills the spaces between the second electrodes to electrically isolate the second electrodes and the chip interconnect structure from each other.

[0019] In one embodiment, the chip package structure further includes a third wiring layer disposed between the chip and the dielectric intermediate layer, the third wiring layer including a first lead corresponding to the first chip pin, a second lead corresponding to the second chip pin, and a third lead corresponding to the third chip pin;

[0020] The first chip pins of the two chips are electrically connected through the corresponding first lead and the corresponding first wiring.

[0021] The second chip pin of the chip is electrically connected to an external circuit through the corresponding second lead and the corresponding first electrode;

[0022] The third chip pin of the chip is electrically connected to an external circuit via the corresponding third lead and the corresponding second electrode.

[0023] In one embodiment, the chip packaging structure further includes a substrate disposed on the side of the dielectric intermediate layer opposite to the chip;

[0024] The substrate includes a device layer, in which a plurality of third electrodes corresponding one-to-one with the first electrode and a plurality of fourth electrodes corresponding one-to-one with the second electrode are disposed through the device layer;

[0025] The first electrode is electrically connected to the external circuit via the corresponding third electrode;

[0026] The second electrode is electrically connected to the external circuit via the corresponding fourth electrode.

[0027] According to a third aspect of this application, a method for fabricating a chip interconnect structure is provided. The chip interconnect structure is used to connect two chips, each chip including a plurality of first chip pins and a plurality of second chip pins. The fabrication method includes:

[0028] A semiconductor layer is provided, the semiconductor layer having a first side;

[0029] A first electrode is formed extending from the first side into the semiconductor layer;

[0030] A first wiring layer is formed on the first side of the semiconductor layer;

[0031] The surface of the semiconductor layer facing away from the first side is thinned to expose the surface of the first electrode away from the first side.

[0032] The first wiring layer includes a plurality of first wirings and a plurality of second wirings that are electrically isolated from each other, and the second wirings correspond one-to-one with the first electrodes;

[0033] The first wiring is used to electrically connect the first chip pins of the two chips;

[0034] The second chip pin of each chip is electrically connected to an external circuit through the corresponding second wiring and the corresponding first electrode.

[0035] The aforementioned chip interconnect structure, its fabrication method, and chip packaging structure utilize the first wiring layer to flexibly achieve electrical connection with the first chip pin at any location on the chip. This facilitates the redistribution of the electrical signals of the first chip pin on the first wiring layer. On the one hand, this allows the electrical signals on one chip to be transmitted to another bare chip over a shorter distance. On the other hand, the electrical signals on the chip can also be transmitted to external circuits over a shorter distance. External circuits, such as external power supplies, can also provide power to the chip through the first electrode and the second wiring. Considering that the first electrode extends from the first side to the second side, and the first wiring layer is located on the first side facing the chip, it can be understood that the current direction provided to the chip by the external circuit, such as the external power supply, can be approximately parallel to the direction from the first side to the second side. This allows the external circuit, such as the external power supply, to provide power to the chip from bottom to top through the first electrode and the second wiring, thereby expanding the power supply path area and preventing insufficient power supply to the chip. Attached Figure Description

[0036] Figure 1 A schematic diagram of a chip packaging structure according to an embodiment of this application is shown;

[0037] Figure 2 A schematic diagram of a chip interconnect structure according to an embodiment of this application is shown;

[0038] Figures 3a-3f A schematic diagram illustrating the fabrication process of a chip interconnect structure according to an embodiment of this application is shown;

[0039] Figure 4 A schematic flowchart illustrating a method for fabricating a chip interconnect structure according to an embodiment of this application is shown;

[0040] Figures 5a-5h A schematic diagram illustrating the fabrication process of a chip packaging structure according to an embodiment of this application is shown;

[0041] Figure 6 A schematic flowchart illustrating a method for fabricating a chip packaging structure according to an embodiment of this application is shown.

[0042] In the diagram: 10, Chip packaging structure; 100, Chip interconnect structure; 110, Semiconductor layer; 111, First side; 112, Second side; 113, First electrode; 114, Through-hole; 120, First wiring layer; 121, First wiring; 122, Second wiring; 130, Second wiring layer; 131, First external lead; 132, Third wiring; 210, Second electrode; 220, Dielectric intermediate layer; 300, Third wiring layer; 310, First lead; 320, Third lead; 400, Substrate; 410, Device layer; 420, Third electrode; 430, Fourth electrode; 440, Second external lead; 450, Third external lead; 500, Fourth wiring layer; 510, Fourth external lead; 520, Fifth external lead; 600, Carrier board; 20, Chip; 21, First chip lead; 22, Second chip lead; 23, Third chip lead. Detailed Implementation

[0043] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0044] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0045] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0046] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0047] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0048] It should be noted that when an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or there may be an intervening element. When an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only possible implementation.

[0049] In related technologies, semiconductor processes are used to fabricate interconnect lines on silicon wafers in chip packaging structures. These interconnect lines connect chips with different functions to the same silicon wafer, thereby achieving signal interconnection between chips with different functions. However, traditional chip packaging structures suffer from insufficient power supply from external power sources to the chips.

[0050] The applicant discovered through research that in the relevant technology, it is impossible to directly supply power from below the connection structure of different chips, resulting in a long power supply path from the external power source to the chip, which in turn leads to insufficient power supply.

[0051] To address the problem of insufficient power supply from external power sources in traditional chip packaging structures, the applicant has designed a chip interconnect structure. The chip interconnect structure includes a first electrode. An external circuit, such as an external power source, can be electrically connected to the first electrode at the bottom of the chip interconnect structure and supply power to the corresponding chip through the first electrode, achieving a bottom-up power supply effect and avoiding insufficient power supply to the chip.

[0052] Figure 1 A schematic diagram of a chip packaging structure according to an embodiment of this application is shown. Figure 2 A schematic diagram of a chip interconnect structure according to an embodiment of this application is shown.

[0053] Please see Figure 1 and Figure 2 An embodiment of this application provides a chip interconnect structure 100 for connecting two chips 20. Each chip 20 includes a plurality of first chip pins 21 and a plurality of second chip pins 22, which are spaced apart from each other and electrically isolated from one another.

[0054] The chip interconnect structure 100 includes a semiconductor layer 110 and a first wiring layer 120. The semiconductor layer 110 has a first side 111 facing the chip 20 and a second side 112 disposed opposite to the first side 111. A first electrode 113 is provided in the semiconductor layer 110, extending from the first side 111 to the second side 112.

[0055] The first electrode 113 can penetrate the semiconductor layer 110 in the direction from the first side 111 to the second side 112, and the direction from the first side 111 to the second side 112 can be parallel to the thickness direction of the semiconductor layer 110.

[0056] The first wiring layer 120 is disposed on the first side 111 of the semiconductor layer 110, and the first wiring layer 120 includes a plurality of first wirings 121 and a plurality of second wirings 122 that are electrically isolated from each other, and the second wirings 122 correspond one-to-one with the first electrode 113.

[0057] "A plurality of first wires 121 and a plurality of second wires 122 that are electrically isolated from each other", wherein any two first wires 121 are electrically isolated from each other, any two second wires 122 are electrically isolated from each other, and any first wire 121 and any second wire 122 are electrically isolated from each other.

[0058] The first wiring 121 is used to electrically connect the first chip pins 21 of the two chips 20. That is, the first chip pins 21 of the two chips 20 are electrically connected through the corresponding first wiring 121 so as to realize the signal interconnection of the two chips 20.

[0059] The second chip pin 22 of each chip 20 is electrically connected to the external circuit through the corresponding second wiring 122 and the corresponding first electrode 113.

[0060] Thus, the first wiring layer 120 can flexibly achieve electrical connection with the first chip pin 21 at any location on the chip 20, thereby facilitating the redistribution of the electrical signals of the first chip pin 21 on the first wiring layer 120. On the one hand, this allows the electrical signals on one chip 20 to be transmitted to another bare chip 20 over a shorter distance; on the other hand, the electrical signals on the chip 20 can also be transmitted to external circuits over a shorter distance. External circuits, such as external power supplies, can also supply power to the chip 20 through the first electrode 113 and the second wiring layer 122. The chip 20 provides power. With the first electrode 113 extending from the first side 111 to the second side 112, and the first wiring layer 120 located on the first side 111 facing the chip 20, it can be understood that the direction of the current supplied to the chip 20 by the external circuit (external power supply) can be approximately parallel to the direction from the first side 111 to the second side 112. This allows the external circuit (external power supply) to supply power to the chip 20 from bottom to top via the first electrode 113 and the second wiring layer 122, thereby expanding the power supply path area and preventing insufficient power supply to the chip 20.

[0061] In some embodiments, the semiconductor layer 110 has a through-hole 114 extending from a first side 111 to a second side 112. The first electrode 113 includes a dielectric layer and a conductive structure. The dielectric layer is disposed on the sidewall of the through-hole 114 and surrounds the sidewall of the conductive structure. The dielectric layer electrically isolates the semiconductor layer 110 from the conductive structure, and external circuits (such as external power supplies) can supply power to the chip 20 from bottom to top via the conductive structure of the first electrode 113 and the second wiring 122, thereby improving the reliability of power supply to the chip 20 by external circuits (such as external power supplies).

[0062] In some embodiments, the via 114 extends from the first side 111 to the second side 112 along the thickness direction of the semiconductor layer 110.

[0063] It is understandable that the conductive structure of the first electrode 113 filling the via 114 can also extend along the thickness direction of the semiconductor layer 110. This makes it easier for external circuits (external power supply) to supply power to the chip 20 from bottom to top by means of the conductive structure of the first electrode 113 and the second wiring 122.

[0064] In some embodiments, the conductive structure can be a copper pillar, and the depth of the through hole 114 can be 100 micrometers.

[0065] In some embodiments, the chip interconnect structure 100 further includes a second wiring layer 130 disposed on the second side 112 of the semiconductor layer 110. The side of the second wiring layer 130 facing away from the semiconductor layer 110 is provided with a plurality of first external connector pins 131 corresponding to the first electrode 113. The second wiring layer 130 is provided with a plurality of third wirings 132 corresponding to the first external connector pins 131. The first electrode 113 is electrically connected to an external circuit through the corresponding third wirings 132 and the corresponding first external connector pins 131.

[0066] The third wiring 132 enables electrical signals on chip 20 to be transmitted to external circuits over a shorter distance, thereby optimizing signal fan-out position, controlling impedance, reducing crosstalk between signals, and enhancing power supply.

[0067] In some embodiments, the first wiring layer 120 may include one or more first sub-wiring layers, each of which may have the same or different thickness, area, and shape. Adjacent first sub-wiring layers may be electrically connected using copper vias. The structure and material of the second wiring layer 130 may be the same as or different from those of the first wiring layer 120.

[0068] One embodiment of this application provides a chip packaging structure 10 including the chip interconnect structure 100 described above.

[0069] In some embodiments, the chip 20 further includes a plurality of third chip pins 23 spaced apart, wherein any two third chip pins 23 are electrically isolated from each other, any first chip pin 21 and any third chip pin 23 are electrically isolated from each other, and any second chip pin 22 and any third chip pin 23 are electrically isolated from each other.

[0070] The chip package structure 10 also includes a plurality of second electrodes 210 corresponding one-to-one with the third chip pin 23. The plurality of second electrodes 210 surround the periphery of the chip interconnect structure 100 and are electrically isolated from each other. The third chip pin 23 of the chip 20 is electrically connected to the external circuit through the corresponding second electrodes 210.

[0071] In other words, on the one hand, external circuits such as (external power supply) can supply power to chip 20 from bottom to top through the first electrode 113 and the second wiring 122. On the other hand, external circuits such as (external power supply) can also supply power to chip 20 through the second electrode 210. Since the second electrode 210 and the chip interconnect structure 100 are electrically isolated from each other, mutual interference between the second electrode 210 and the chip interconnect structure 100 is avoided. This can expand the power supply path area, realize impedance control, reduce crosstalk between signals, and enhance power supply.

[0072] In some embodiments, the chip package structure 10 further includes a dielectric intermediate layer 220, which surrounds the periphery of the chip interconnect structure 100 and fills the spaces between the second electrodes 210 to electrically isolate the second electrodes 210 and the chip interconnect structure 100 from each other.

[0073] The dielectric intermediate layer 220 can be formed using silicon interposer technology or resin filling process, without specific limitations. On the one hand, the dielectric intermediate layer 220 can electrically isolate the second electrode 210 and the chip interconnect structure 100 from each other; on the other hand, the dielectric intermediate layer 220 provides protection for the second electrode 210 and the chip interconnect structure 100.

[0074] In some embodiments, the chip package structure 10 further includes a third wiring layer 300 disposed between the chip 20 and the dielectric intermediate layer 220. The third wiring layer 300 includes a first lead 310 corresponding to the first chip pin 21, a second lead corresponding to the second chip pin 22, and a third lead 320 corresponding to the third chip pin 23.

[0075] The first chip pins 21 of the two chips 20 are electrically connected through the corresponding first lead 310 and the corresponding first wiring 121 to realize signal communication between the two chips 20.

[0076] The second chip pin 22 of chip 20 is electrically connected to the external circuit through the corresponding second lead and the corresponding first electrode 113, and the third chip pin 23 of chip 20 is electrically connected to the external circuit through the corresponding third lead 320 and the corresponding second electrode 210.

[0077] In this way, the electrical signals of the chip 20 can be redistributed using the third wiring layer 300, wherein a portion of the signal of one chip 20 flows through the first chip pin 21 to the corresponding first lead 310 and the corresponding first wiring 121, and finally flows into the first chip pin 21 of another chip 20, so as to realize the electrical signal interconnection of the two chips 20.

[0078] Another portion of the signal from chip 20 flows to the external circuit via the second chip pin 22 through the corresponding second lead and the corresponding first electrode 113. Yet another portion of the signal from chip 20 flows to the external circuit via the third chip pin 23 through the corresponding third lead 320 and the corresponding second electrode 210. Of course, the external circuit (such as an external power supply) can also provide power to chip 20 through the first electrode 113 and the second electrode 210 respectively.

[0079] Understandably, the third wiring layer 300 enables electrical signals on one chip 20 to be transmitted to another chip 20 or external circuits over a shorter distance, thereby optimizing signal fan-out position, controlling impedance, reducing crosstalk between signals, and enhancing power supply.

[0080] In some embodiments, the chip package structure 10 further includes a substrate 400, which is disposed on the side of the dielectric intermediate layer 220 away from the chip 20. The substrate 400 includes a device layer 410, in which a plurality of third electrodes 420 corresponding to the first electrode 113 and a plurality of fourth electrodes 430 corresponding to the second electrode 210 are disposed. The first electrode 113 is electrically connected to an external circuit through the corresponding third electrode 420, and the second electrode 210 is electrically connected to an external circuit through the corresponding fourth electrode 430.

[0081] An external circuit (such as an external power supply) can be electrically connected to the second chip pin 22 on the chip 20 via the corresponding third electrode 420 and the corresponding first electrode 113. The external circuit (such as an external power supply) can also be electrically connected to the third chip pin 23 on the chip 20 via the corresponding fourth electrode 430 and the corresponding second electrode 210. In this way, the external circuit (such as an external power supply) can provide power to the chip 20 from bottom to top, which can expand the power supply path area and avoid insufficient power supply to the chip 20.

[0082] The substrate 400 has a plurality of second external connector pins 440 and a plurality of third external connector pins 450 on the side opposite to the dielectric intermediate layer 220. The second external connector pins 440 correspond one-to-one with the third electrode 420 and are electrically connected to the corresponding third electrode 420 and the external circuit, respectively. The third external connector pins 450 correspond one-to-one with the fourth electrode 430 and are electrically connected to the corresponding fourth electrode 430 and the external circuit, respectively.

[0083] In some embodiments, the chip package structure 10 further includes a fourth wiring layer 500 located between the dielectric intermediate layer 220 and the substrate 400. The fourth wiring layer 500 has a fourth external connector 510 corresponding to the first electrode 113 on the side facing the substrate 400, and a plurality of fifth external connectors 520 corresponding to the second electrode 210. The fourth external connector 510 is electrically connected to the corresponding first electrode 113 through the corresponding first external connector 131 and the corresponding third wiring 132, and the fifth external connector 520 is electrically connected to the corresponding second electrode 210.

[0084] The following section will focus on the fabrication method of the chip interconnect structure 100.

[0085] Figures 3a-3f A schematic diagram illustrating the fabrication process of the chip interconnect structure 100 is shown. Figure 4A schematic flowchart illustrating the fabrication method of the chip interconnect structure 100 is shown.

[0086] Please refer to Figure 3 and Figure 4 A method for fabricating a chip interconnect structure 100 includes the following steps:

[0087] S10, please refer to Figure 3a A semiconductor layer 110 is provided, the semiconductor layer 110 having a first side 111.

[0088] S20, please refer to Figure 3b A first electrode 113 is formed, extending from the first side 111 into the semiconductor layer 110.

[0089] S30, please refer to Figure 3c A first wiring layer 120 is formed on the first side 111 of the semiconductor layer 110. Specifically, the first wiring layer 120 can be fabricated on the first side 111 of the semiconductor layer 110 using processes such as photolithography and electroplating.

[0090] S40, please refer to Figure 3d The surface of the semiconductor layer 110 facing away from the first side 111 is thinned to expose the surface of the first electrode 113 away from the first side 111. A grinding process can be used to thin the surface of the semiconductor layer 110 facing away from the first side 111, so that the first electrode 113 in the semiconductor layer 110 is exposed, or the second side 112 of the semiconductor layer 110 can be exposed.

[0091] The first wiring layer 120 includes multiple first wirings 121 and multiple second wirings 122 that are electrically isolated from each other. Each second wiring 122 corresponds one-to-one with a first electrode 113. The first wirings 121 are used to electrically connect the first chip pins 21 of two chips 20. The second chip pins 22 of each chip 20 are electrically connected to an external circuit through the corresponding second wiring 122 and the corresponding first electrode 113. Both the first wirings 121 and the multiple second wirings 122 can be copper wires.

[0092] In some embodiments, step S20 of forming a first electrode 113 extending from the first side 111 into the semiconductor layer 110 specifically includes:

[0093] A via 114 is formed on the first side 111 of the semiconductor layer 110, and a first electrode 113 is formed within the via 114 in a filled manner. Specifically, the via 114 can be formed on the first side 111 of the semiconductor layer 110 using an ion etching process (see reference). Figure 3b (For understanding), the depth of the through hole 114 can be 100 micrometers.

[0094] In some embodiments, the method for fabricating the chip interconnect structure 100 further includes:

[0095] S50, please refer to Figure 3e A second wiring layer 130 is formed on the second side 112 of the semiconductor layer 110, and a plurality of first external leads 131 corresponding one-to-one with the first electrode 113 are formed on the side of the second wiring layer 130 away from the semiconductor layer 110. The second wiring layer 130 and the first external leads 131 can be fabricated on the second side 112 of the semiconductor layer 110 using processes such as photolithography and electroplating.

[0096] In some embodiments, such as Figures 3a-3f First, follow steps S10-S50 to form an overall structure including multiple chip interconnect structures 100, and then cut the overall structure to obtain multiple chip interconnect structures 100.

[0097] The fabrication process of the chip packaging structure 10 is described below.

[0098] Figures 5a-5h A schematic diagram illustrating the fabrication process of the chip package structure 10 is shown. Figure 6 A flowchart illustrating the fabrication method of the chip package structure 10 is shown.

[0099] S100, please refer to Figure 5a A carrier plate 600 is provided, which can be made of glass.

[0100] S200, please refer to Figure 5b A fourth wiring layer 500 is formed on a carrier 600. The fourth wiring layer 500 is fabricated on a glass carrier using photolithography, electroplating and other processes. The fourth wiring layer 500 can be a copper circuit layer.

[0101] S300, please refer to Figure 5c Multiple second electrodes 210 are formed on the fourth wiring layer 500. Multiple second electrodes 210 can be formed on the fourth wiring layer 500 using processes such as photolithography and electroplating, and the second electrodes 210 can be copper pillars.

[0102] S400, please refer to Figure 5d The chip interconnect structure 100 is formed on the fourth wiring layer 500, and a plurality of second electrodes 210 surround the periphery of the chip interconnect structure 100. The chip interconnect structure 100 can be attached to the fourth wiring layer 500 using a flip chip bonding process.

[0103] S500, please refer to Figure 5eA dielectric intermediate layer 220 is formed on the fourth wiring layer 500 to electrically isolate the second electrode 210 and the chip interconnect structure 100. The dielectric intermediate layer 220 surrounds the periphery of the chip interconnect structure 100 and fills the spaces between the second electrode 210 and between the second electrode 210 and the chip interconnect structure 100. The dielectric intermediate layer 220 can be formed on the fourth wiring layer 500 using a resin filling process. The dielectric intermediate layer 220 can be an insulating resin.

[0104] S600, please refer to Figure 5f A third wiring layer 300 is formed on the dielectric middle layer 220. The third wiring layer 300 can be fabricated on the dielectric middle layer 220 using processes such as photolithography and electroplating. The third wiring layer 300 can be a copper circuit layer, that is, the first lead 310, the second lead and the third lead 320 can be copper wires.

[0105] S700, please refer to Figure 5g This allows the two chips 20 to be placed on the third wiring layer 300, and the two chips 20 can be attached to the third wiring layer 300 using flip chip bonding technology.

[0106] S800, please refer to Figure 5h Remove the carrier board 600 and fabricate the fourth external connector pin 510 and the fifth external connector pin 520 on the exposed fourth wiring layer 500.

[0107] S900, please refer to Figure 1 The fourth external connector pin 510 and the fifth external connector pin 520 are connected to the substrate 400 (using flip chip bonding technology) to obtain the chip package structure 10.

[0108] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0109] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A chip interconnect structure, characterized in that, The chip interconnect structure is used to connect two chips. Each chip includes multiple first chip pins and multiple second chip pins. The chip interconnect structure includes: A semiconductor layer has a first side facing the chip and a second side disposed opposite to the first side, wherein a first electrode is provided within the semiconductor layer extending from the first side to the second side; and A first wiring layer is disposed on a first side of the semiconductor layer and includes a plurality of first wirings and a plurality of second wirings electrically isolated from each other, wherein each second wiring corresponds to a first electrode. Wherein, the first wiring is used to electrically connect the first chip pins of the two chips; The second chip pin of each chip is electrically connected to an external circuit through the corresponding second wiring and the corresponding first electrode; The chip interconnect structure further includes a second wiring layer disposed on the second side of the semiconductor layer. The side of the second wiring layer away from the semiconductor layer is provided with a plurality of first external connector pins corresponding to the first electrodes. The second wiring layer is provided with a plurality of third wirings corresponding to the first external connector pins. The first electrode is electrically connected to the external circuit through the corresponding third wiring and the corresponding first external connector pin.

2. The chip interconnect structure according to claim 1, characterized in that, The semiconductor layer has a through-hole extending from the first side to the second side; The first electrode includes a dielectric layer and a conductive structure. The dielectric layer is disposed on the sidewall of the via and surrounds the sidewall of the conductive structure.

3. The chip interconnect structure according to claim 2, characterized in that, The via extends from the first side to the second side along the thickness direction of the semiconductor layer.

4. A chip packaging structure, characterized in that, Includes the chip interconnect structure as described in any one of claims 1-3; The chip also includes a plurality of third chip pins spaced apart; The chip packaging structure also includes a plurality of second electrodes corresponding one-to-one with the pins of the third chip. The plurality of second electrodes surround the periphery of the chip interconnect structure and are electrically isolated from each other. The third chip pin of the chip is electrically connected to an external circuit via the corresponding second electrode.

5. The chip packaging structure according to claim 4, characterized in that, The chip package structure further includes a dielectric intermediate layer that surrounds the periphery of the chip interconnect structure and fills the spaces between the second electrodes to electrically isolate the second electrodes and the chip interconnect structure from each other.

6. The chip packaging structure according to claim 5, characterized in that, The chip packaging structure further includes a third wiring layer disposed between the chip and the dielectric intermediate layer. The third wiring layer includes a first lead corresponding to the first chip pin, a second lead corresponding to the second chip pin, and a third lead corresponding to the third chip pin. The first chip pins of the two chips are electrically connected through the corresponding first lead and the corresponding first wiring. The second chip pin of the chip is electrically connected to an external circuit through the corresponding second lead and the corresponding first electrode; The third chip pin of the chip is electrically connected to an external circuit via the corresponding third lead and the corresponding second electrode.

7. The chip packaging structure according to claim 5, characterized in that, The chip packaging structure also includes a substrate, which is disposed on the side of the dielectric intermediate layer opposite to the chip; The substrate includes a device layer, in which a plurality of third electrodes corresponding one-to-one with the first electrode and a plurality of fourth electrodes corresponding one-to-one with the second electrode are disposed through the device layer; The first electrode is electrically connected to the external circuit via the corresponding third electrode; The second electrode is electrically connected to the external circuit via the corresponding fourth electrode.

8. A method for fabricating a chip interconnect structure, characterized in that, The chip interconnect structure is used to connect two chips, each chip including multiple first chip pins and multiple second chip pins, and the fabrication method includes: A semiconductor layer is provided, the semiconductor layer having a first side and a second side disposed opposite to the first side; A first electrode is formed extending from the first side into the semiconductor layer; A first wiring layer is formed on the first side of the semiconductor layer; The surface of the semiconductor layer facing away from the first side is thinned to expose the surface of the first electrode away from the first side. The first wiring layer includes a plurality of first wirings and a plurality of second wirings that are electrically isolated from each other, and the second wirings correspond one-to-one with the first electrodes; The first wiring is used to electrically connect the first chip pins of the two chips; The second chip pin of each chip is electrically connected to an external circuit through the corresponding second wiring and the corresponding first electrode; The chip interconnect structure further includes a second wiring layer disposed on the second side of the semiconductor layer. The side of the second wiring layer away from the semiconductor layer is provided with a plurality of first external connector pins corresponding to the first electrodes. The second wiring layer is provided with a plurality of third wirings corresponding to the first external connector pins. The first electrode is electrically connected to the external circuit through the corresponding third wiring and the corresponding first external connector pin.

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