Light-emitting control circuit and display panel

Abstract

The present invention discloses a light-emitting control circuit and a display panel, wherein the light-emitting control circuit comprises: a first output module, a second output module, a clamping module, a first control module, a second control module and a writing module; the first control module is used to respond to a first clock signal, a second clock signal and the potential of a first node, and transmit the first potential signal to the second node; the first node is connected to the second control module, and the second node is connected to the control end of the first output module; the second control module is used to respond to the first clock signal and the potential of a third node, and transmit the second potential signal to the first node, and the third node is connected to the control end of the second output module; the writing module is used to respond to the second clock signal and transmit the start signal to the third node; the clamping module is used to respond to the first potential signal of the third node and control the signal of the second node to be the second potential signal. The circuit of this embodiment can realize providing a light-emitting control signal to a pixel circuit of full NTFT.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a light emitting control circuit and a display panel. Background Art

[0002] In recent years, many types of display devices have been developed at home and abroad, such as liquid crystal display devices, plasma display devices, electrowetting display devices, electrophoretic display devices, organic light-emitting display devices, etc. Among them, organic light-emitting display devices use the recombination of electron-hole pairs in specific materials to emit light of a specific wavelength to display images, and have the advantages of fast response, low power consumption, thinness, and wide color gamut.

[0003] An organic light-emitting display device includes: a plurality of pixels for displaying images; a pixel circuit for applying a data voltage to the pixel to drive the pixel to emit light; and a light-emitting control circuit for applying a light-emitting control signal to the pixel to control the pixel to emit light in a light-emitting phase. The light-emitting phase is a period of time during which the pixel needs to emit light in a frame of display.

[0004] The pixel circuit includes multiple transistors. The existing light emitting control circuits use P-type transistors or mixed N-type and P-type transistors to serve the pixel circuits. As the market demand for large-size organic light emitting display devices increases, pixel circuits based on indium gallium zinc oxide, that is, all transistors are N-type transistors, are gradually being used. At the same time, the light emitting control circuits that transmit light emitting control signals to the pixel circuits that are all N-type transistors also need to be updated. Summary of the invention

[0005] The present invention provides a light emitting control circuit and a display panel, which provide a light emitting control signal to a pixel circuit including N-type transistors, so as to adapt to a large-sized display panel.

[0006] According to one aspect of the present invention, there is provided a light emitting control circuit, comprising: a first output module, a second output module, a clamping module, a first control module, a second control module and a writing module;

[0007] The first control module is used to respond to the first clock signal, the second clock signal and the potential of the first node, and transmit the first potential signal to the second node; wherein the first node is connected to the second control module, and the second node is connected to the control end of the first output module;

[0008] The second control module is used to respond to the first clock signal and the potential of the third node, transmit the second potential signal to the first node, and the third node is connected to the control end of the second output module;

[0009] The writing module is used for transmitting a start signal to the third node in response to the second clock signal;

[0010] The clamping module is used for controlling the signal of the second node to be the second potential signal in response to the first potential signal of the third node;

[0011] The first output module is used to control the second potential signal to be transmitted to the output end of the light emitting control circuit according to the potential of the second node;

[0012] The second output module is used to control the first potential signal to be transmitted to the output end of the light emitting control circuit according to the potential of the third node.

[0013] Optionally, the first control module includes a storage unit, a first control subunit and a second control subunit, the first end of the storage unit is connected to the first potential signal, the second end of the storage unit is connected to the first node, and the storage unit is used to store the potential of the first node;

[0014] The first terminal of the first control subunit is connected to the first potential signal, the second terminal of the first control subunit is connected to the first node, the control terminal of the first control subunit is connected to the second clock signal, and the first control subunit is used to respond to the second clock signal and transmit the first potential signal to the first node;

[0015] The first end of the second control subunit is connected to the first end of the first control subunit, the second end of the second control subunit is connected to the second node, the first control end of the second control subunit is connected to the first node, the second control end of the second control subunit is connected to the first clock signal, and the second control subunit is used to respond to the first clock signal and the potential of the first node, and transmit the first potential signal to the second node.

[0016] Optionally, the storage unit includes a first capacitor, the first control subunit includes a first transistor, and the second control subunit includes a second transistor and a third transistor;

[0017] The first end of the first capacitor is connected to the first potential signal, and the second end of the first capacitor is connected to the first node;

[0018] A first electrode of the first transistor is connected to the first potential signal, a second electrode of the first transistor is connected to the first node, and a gate of the first transistor is connected to the second clock signal;

[0019] The first electrode of the second transistor is connected to the first electrode of the first transistor, the second electrode of the second transistor is connected to the first electrode of the third transistor, the gate of the second transistor is connected to the first node, the second electrode of the third transistor is connected to the second node, and the gate of the third transistor is connected to the first clock signal.

[0020] Optionally, the first end of the second control module is connected to the second potential signal, the second end of the second control module is connected to the first node, the first control end of the second control module is connected to the first clock signal, and the second control end of the second control module is connected to the third node;

[0021] Optionally, the second control module includes a fourth transistor and a fifth transistor, the first electrode of the fourth transistor is connected to the second potential signal, the second electrode of the fourth transistor is connected to the first electrode of the fifth transistor, the gate of the fourth transistor is connected to the first clock signal, the second electrode of the fifth transistor is connected to the first node, and the gate of the fifth transistor is connected to the third node.

[0022] Optionally, the first end of the writing module is connected to the start signal, the second end of the writing module is connected to the third node, and the control end of the writing module is connected to the second clock signal;

[0023] Optionally, the writing module includes a sixth transistor, a first electrode of the sixth transistor is connected to the start signal, a second electrode of the sixth transistor is connected to the third node, and a gate of the sixth transistor is connected to the second clock signal.

[0024] Optionally, the first end of the clamping module is connected to the second potential signal, the second end of the clamping module is connected to the second node, and the control end of the clamping module is connected to the third node.

[0025] Optionally, the clamping module includes a seventh transistor, a first electrode of the seventh transistor is connected to the second potential signal, a second electrode of the seventh transistor is connected to the second node, and a gate of the seventh transistor is connected to the third node.

[0026] Optionally, the first end of the first output module is connected to the second potential signal, the second end of the first output module is connected to the output end of the light emitting control circuit, and the control end of the first output module is connected to the second node;

[0027] The first terminal of the second output module is connected to the first potential signal, the second terminal of the second output module is connected to the output terminal of the light emitting control circuit, and the control terminal of the second output module is connected to the third node.

[0028] Optionally, the first output module includes a second capacitor and an eighth transistor, the first electrode of the eighth transistor is connected to the second potential signal, the second electrode of the eighth transistor is connected to the output end of the light-emitting control circuit, the gate of the eighth transistor is connected to the second node, the first end of the second capacitor is connected to the first electrode of the eighth transistor, and the second end of the second capacitor is connected to the gate of the eighth transistor.

[0029] Optionally, the second output module includes a third capacitor and a ninth transistor, the first electrode of the ninth transistor is connected to the first potential signal, the second electrode of the ninth transistor is connected to the output end of the light-emitting control circuit, the gate of the ninth transistor is connected to the third node, the first end of the third capacitor is connected to the second electrode of the ninth transistor, and the second end of the third capacitor is connected to the gate of the ninth transistor.

[0030] Optionally, the light-emitting control circuit also includes: a boost module, which is connected to the third node, and is used to write a transition voltage difference into the third node when the first clock signal connected to the boost module jumps from the second potential signal to the first potential signal, wherein the transition voltage difference is the difference between the first potential signal and the second potential signal.

[0031] Optionally, the first end of the boost module is connected to the first clock signal, and the second end of the boost module is connected to the third node;

[0032] Optionally, the boost module includes a tenth transistor and a fourth capacitor, the first electrode of the tenth transistor is connected to the first clock signal, the second electrode of the tenth transistor is connected to the first end of the fourth capacitor, the gate of the tenth transistor is connected to the second end of the fourth capacitor, and the second end of the fourth capacitor is connected to the third node.

[0033] According to another aspect of the present invention, a display panel is provided, comprising any one of the above-mentioned light emitting control circuits.

[0034] The light-emitting control circuit provided by the embodiment of the present invention includes: a first output module, a second output module, an embedding module, a first control module, a second control module and a writing module; the first control module is used to respond to a first clock signal, a second clock signal and the potential of the first node, and transmit the first potential signal to the second node; wherein the first node is connected to the second control module, and the second node is connected to the control end of the first output module; the second control module is used to respond to the first clock signal and the potential of the third node, and transmit the second potential signal to the first node, and the third node is connected to the control end of the second output module; the writing module is used to respond to the second clock signal and transmit the start signal to the third node; the embedding module is used to respond to the first potential signal of the third node and control the signal of the second node to be the second potential signal; the first output module is used to control the second potential signal to be transmitted to the output end of the light-emitting control circuit according to the potential of the second node; the second output module is used to control the first potential signal to be transmitted to the output end of the light-emitting control circuit according to the potential of the third node. In this embodiment, the potential of the third node is controlled by the writing module, and the potential of the second node is controlled by the first control module, the second control module and the clamping module, so that at a time, at most one of the first output module and the second output module is turned on to transmit the first potential signal or the second potential signal to the output end of the light-emitting control circuit. The signal output by the output end of the light-emitting control circuit is the light-emitting control signal, thereby controlling the pixel circuit including transistors that are all N-type transistors to emit light in the light-emitting stage. The circuit provided in this embodiment can be used to drive the pixel circuit including transistors that are all N-type transistors, thereby realizing the application of large-size display panels.

[0035] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 It is a schematic diagram of the structure of a full PTFT pixel circuit;

[0038] Figure 2 It is the driving timing diagram of the full PTFT pixel circuit;

[0039] Figure 3 It is a schematic diagram of the structure of a full NTFT pixel circuit;

[0040] Figure 4 It is the driving timing diagram of the pixel circuit of full NTFT;

[0041] Figure 5 is a structural schematic diagram of a light emitting control circuit provided by an embodiment of the present invention;

[0042] Figure 6 is a driving timing diagram of a light emitting control circuit provided by an embodiment of the present invention;

[0043] Figure 7 is a structural schematic diagram of another light emitting control circuit provided by an embodiment of the present invention;

[0044] Figure 8 is a structural schematic diagram of another light emitting control circuit provided by an embodiment of the present invention;

[0045] Fig. 9 It is a schematic diagram of the working process of a light emitting control circuit provided by an embodiment of the present invention in the first stage;

[0046] Fig.10 It is a schematic diagram of the working process of a light emitting control circuit in the second stage provided by an embodiment of the present invention;

[0047] Fig.11 It is a schematic diagram of the working process of a light emitting control circuit provided by an embodiment of the present invention in the third stage;

[0048] Fig.12 It is a schematic diagram of the working process of a light emitting control circuit provided by an embodiment of the present invention in the fourth stage;

[0049] Fig.13 It is a schematic diagram of the working process of a light emitting control circuit provided by an embodiment of the present invention in the fifth stage;

[0050] Fig.14 It is a schematic diagram of the working process of a light emitting control circuit provided by an embodiment of the present invention in the sixth stage;

[0051] Fig.15 It is a schematic diagram of the working process of a light emitting control circuit provided by an embodiment of the present invention in the seventh stage;

[0052] Fig.16 It is a schematic diagram of the working process of a light emitting control circuit provided by an embodiment of the present invention in the eighth stage;

[0053] Fig.17 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0054] Fig.18 It is a simulation result diagram of a display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0055] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0056] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0057] As described in the background technology, the existing light-emitting control circuits are all for pixel circuits in which all transistors are P-type transistors (full PTFT) or a mixture of N-type transistors and P-type transistors (LTPO). However, for pixel circuits in which all transistors are N-type transistors (NTFT), the above-mentioned light-emitting control circuits are no longer applicable. The inventors have found that the reason for the above-mentioned problem is that, taking the full PTFT pixel circuit as an example, the required light-emitting control signal is mostly at a low level within a frame. However, the light-emitting control signal required for the full NTFT pixel circuit is mostly at a high level within a frame. For details, please refer to Figure 1-Figure 4 ,in, Figure 1 It is a schematic diagram of the structure of the full PTFT pixel circuit. Figure 2 This is the driving timing diagram of the full PTFT pixel circuit. Figure 3 It is a schematic diagram of the structure of the pixel circuit of full NTFT. Figure 4 This is the driving timing diagram of the full NTFT pixel circuit. It is worth noting that Figure 1 and Figure 3 Only part of the structure of the pixel circuit is shown, that is, only the first transistor, the second transistor T2, the third transistor T3 and the light-emitting device LD are shown. The first transistor, the second transistor T2, the third transistor T3 and the light-emitting device LD are connected between the first power supply VDD and the second power supply VSS, and the gates of the second transistor T2 and the third transistor T3 are connected to the light-emitting control signal EM. Figure 2 In a frame t0, the light emitting control signal EM is at a low level for most of the time period, so as to control the second transistor T2 and the third transistor T3 to be turned on, so that the driving current generated by the first transistor T1 according to the voltage between its gate and the first electrode is transmitted to the light emitting device LD, so as to drive the light emitting device LD to emit light. Figure 4 In a frame t0, the light emitting control signal EM is at a high level for most of the time period, and the second transistor T2 and the third transistor T3 are turned on, so that the driving current generated by the first transistor T1 according to the voltage of its gate and the first electrode is transmitted to the light emitting device LD to drive the light emitting device LD to emit light. Therefore, the light emitting control signals of the pixel circuit of the NTFT and the pixel circuit of the PTFT are different, and the light emitting control circuit connected to the pixel circuit of the PTFT is no longer applicable to the pixel circuit of the NTFT.

[0058] In view of the above problems, an embodiment of the present invention provides a novel light emitting control circuit suitable for a full NTFT pixel circuit. Figure 5 A schematic diagram of a light emitting control circuit according to an embodiment of the present invention is provided. Figure 5 , the light emitting control circuit comprises:

[0059] A first output module 1, a second output module 2, a clamping module 3, a first control module 4, a second control module 5 and a writing module 6;

[0060] The first control module 4 is used to transmit the first potential signal VGH to the second node N2 in response to the first clock signal CK1, the second clock signal CK2 and the potential of the first node N1; wherein the first node N1 is connected to the second control module 5, and the second node N2 is connected to the control end of the first output module 1;

[0061] The second control module 5 is used to respond to the first clock signal CK1 and the potential of the third node N3, transmit the second potential signal VGL to the first node N1, and the third node N3 is connected to the control end of the second output module 2;

[0062] The writing module 6 is used for transmitting the start signal SIN to the third node N3 in response to the second clock signal CK2;

[0063] The clamping module 3 is used for responding to the first potential signal VGH of the third node N3 and controlling the signal of the second node N2 to be the second potential signal VGL;

[0064] The first output module 1 is used for controlling the second potential signal VGL to be transmitted to the output terminal OUT of the light emitting control circuit according to the potential of the second node N2;

[0065] The second output module 2 is used for controlling the first potential signal VGH to be transmitted to the output terminal OUT of the light emitting control circuit according to the potential of the third node N3.

[0066] Exemplarily, when the potentials of the first clock signal CK1, the second clock signal CK2 and the first node N1 are all on-potentials, the first control module 4 is controlled to be on, so as to transmit the first potential signal VGH to the second node N2. At least one of the first clock signal CK1, the second clock signal CK2 and the first node N1 is off-potential, and the first control module 4 is controlled to be off, so that the first potential signal VGH cannot be transmitted to the second node N2. Wherein, the on-potential described here and below is the potential for turning on the corresponding module, which may be the first potential signal VGH in this embodiment, and the off-potential is the potential for turning off the corresponding module, which may be the second potential signal VGL in this embodiment, and exemplarily, the first potential signal VGH may be a high level, and the second potential signal VGL may be a low level. When the potentials of the first clock signal CK1 and the third node N3 are all on-potentials, the second control module 5 is controlled to be on, so as to transmit the second potential signal VGL to the first node N1. When at least one of the first clock signal CK1 and the potential of the third node N3 is the off potential, the second control module 5 is turned off so that the second potential signal VGL cannot be transmitted to the first node N1. When the second clock signal CK2 is the on potential, the write module 6 is controlled to be turned on to transmit the start signal SIN to the third node N3. When the second clock signal CK2 is the off potential, the write module 6 is controlled to be turned off so that the start signal cannot be transmitted to the third node N3. When the potential of the third node N3 is the first potential signal VGH, the clamping module 3 is controlled to be turned on to transmit the second potential signal VGL to the second node N2, thereby controlling the signal of the second node N2 to be the second potential signal VGL. When the potential of the third node N3 is the second potential signal VGL, the clamping module 3 is controlled to be turned off so that the second potential signal VGL cannot be transmitted to the second node N2. When the potential of the second node N2 is the on potential, the first output module 1 is controlled to be on, so that the second potential signal VGL is transmitted to the output terminal OUT of the light emitting control circuit. When the potential of the second node N2 is the off potential, the first output module 1 is controlled to be off, so that the second potential signal VGL cannot be transmitted to the output terminal OUT of the light emitting control circuit. When the potential of the third node N3 is the on potential, the second output module 2 is controlled to be on, so that the first potential signal VGH is transmitted to the output terminal OUT of the light emitting control circuit. When the potential of the third node N3 is the off potential, the second output module 2 is controlled to be off, so that the first potential signal VGH cannot be transmitted to the output terminal OUT of the light emitting control circuit. Optionally, the first control module 4 is further used to respond to the second clock signal CK2 and transmit the first potential signal VGH to the first node N1.

[0067] Figure 6 A driving timing diagram of a light emitting control circuit provided by an embodiment of the present invention, Figure 6 The drive timing shown is applicable to Figure 5 The light control circuit shown in the reference Figure 5 and Figure 6 The working process of the light emitting control circuit in one frame may include eight stages from the first stage P1 to the eighth stage P8, and the specific working process is as follows:

[0068] In the first stage P1, the start signal SIN is at a high level, the first clock signal CK1 is at a low level, and the second clock signal CK2 is at a high level. The first control module 4 transmits the first potential signal VGH to the first node N1 in response to the second clock signal CK2, so that the first node N1 is the first level signal VGH, that is, a high level. Because the first clock signal CK1 is at a low level, the first control module 4 and the second control module 5 are controlled to be turned off. After the second control module 4 is turned off, the second potential signal VGL cannot be transmitted to the first node N1, thereby avoiding interference with the first potential signal VGH of the first node N1. The second clock signal CK2 controls the writing module 6 to be turned on, and the turned-on writing module 6 transmits the start signal SIN to the third node N3, thereby making the potential of the third node N3 a high level. The potential control clamping module 3 of the third node N3 is turned on, and the turned-on clamping module 3 transmits the second potential signal VGL, that is, a low level, to the second node N2, so that the potential of the second node N2 is a low level. The potential of the second node N2 controls the first output module 1 to be turned off, and the potential of the third node N3 controls the second output module 2 to be turned on. The turned-on second output module 2 transmits the first potential signal VGH to the output terminal OUT of the light emitting control circuit.

[0069] In the second stage P2, the start signal SIN is at a high level, the first clock signal CK1 is at a high level, and the second clock signal CK2 is at a low level. The second clock signal CK2 controls the write module 6 to turn off, and the potential of the third node N3 maintains the high level of the previous stage, i.e., the first stage P1. The potential of the third node N3 controls the clamping module 3 to turn on, so as to transmit the second potential signal VGL to the second node N2, so that the potential of the second node N2 is at a low level. The potential of the third node N3 and the first clock signal CK1 control the second control module 5 to turn on, and the turned-on second control module 5 transmits the second potential signal VGL to the first node N1, so that the potential of the first node N1 is at a low level. The potential of the first node N1 and the second clock signal CK2 control the first control module 4 to turn off, so that the first potential signal VGH cannot be transmitted to the second node N2, avoiding the influence on the low level of the second node N2. The potential of the second node N2 controls the first output module 1 to turn off, and the potential of the third node N3 controls the second output module 2 to turn on, and the turned-on second output module 2 transmits the first potential signal VGH to the output terminal OUT of the light-emitting control circuit.

[0070] In the third stage P3, the start signal SIN is at a low level, the first clock signal CK1 is at a low level, and the second clock signal CK2 is at a high level. The second clock signal CK2 controls the writing module 6 to be turned on, and the turned-on writing module 6 transmits the start signal SIN to the third node N3, so that the potential of the third node N3 is at a low level. Because the second clock signal CK2 is at a high level, the first control module VGH is controlled to transmit the first potential signal VGH to the first node N1, so that the potential of the first node N1 is at a high level. The potential of the third node N3 and the first clock signal CK1 control the second control module 5 to be turned off, so that the second potential signal VGL cannot be transmitted to the first node N1, avoiding the influence on the high level of the first node N1. The first clock signal CK1 controls the first control module 4 to be turned off, so that the first potential signal VGH cannot be transmitted to the second node N2. At the same time, the potential control clamping module 3 of the third node N3 is turned off, so that the second potential signal VGL cannot be transmitted to the second node N2, and the second node N2 maintains the low level of the previous stage, i.e., the second stage P2. The potential of the second node N2 controls the first output module 1 to be turned off, and the potential of the third node N3 controls the second output module 2 to be turned off. Therefore, the potential of the output terminal OUT of the light emitting control circuit maintains the high level of the previous stage, ie, the second stage P2.

[0071] In the fourth stage P4, the start signal SIN is at a low level, the first clock signal CK1 is at a high level, and the second clock signal CK2 is at a low level. The second clock signal CK2 controls the write module 6 to turn off, so that the low level of the start signal SIN cannot be transmitted to the third node N3, and the potential of the third node N3 maintains the low level of the previous stage. The potential of the third node N3 controls the second control module 5 to turn off, so that the second potential signal VGL cannot be transmitted to the first node N1. The second clock signal CK2 controls the first control module 4 to be unable to transmit the first potential signal VGH to the first node N1, and the first node N1 maintains the high level of the previous stage. The first control module responds to the high level of the first node N1 and the first clock signal CK1, and transmits the first potential signal VGH to the second node N2. The potential of the third node N3 controls the clamping module 3 to turn off, so that the second potential signal VGL cannot be transmitted to the second node N2, and the potential of the third node N3 controls the second control module 5 to turn off, so that the second potential signal VGL cannot be transmitted to the second node N2, avoiding the influence on the high level of the second node N2. The potential of the third node N3 controls the second output module 2 to be turned off, and the potential of the second node N2 controls the first output module 1 to be turned on. The turned-on first output module 1 transmits the second potential signal VGL to the output terminal OUT of the light emitting control circuit.

[0072] In the fifth stage P5, the start signal SIN is at a low level, the first clock signal CK1 is at a low level, and the second clock signal CK2 is at a high level. The second clock signal CK2 controls the writing module 6 to be turned on so that the start signal SIN is transmitted to the third node N3, so that the potential of the third node N3 is at a low level. The potential of the first clock signal CK1 and the third node N3 controls the second control module 5 to be turned off so that the second potential signal VGL cannot be transmitted to the first node N1. Although the first clock signal CK1 controls the first control module 4 to be turned off and the first potential signal VGH cannot be transmitted to the second node N2, the first control module 4 can transmit the first potential signal VGH to the first node N1 in response to the potential of the second clock signal CK2, so that the potential of the first node N1 is at a high level. The potential of the third node N3 controls the clamping module 6 to be turned off so that the second potential signal VGL cannot be transmitted to the second node N2, and the potential of the second node N2 maintains the high level of the previous stage, i.e., the fourth stage P4. The potential of the third node N3 controls the second output module 2 to be turned off, and the potential of the second node N2 controls the first output module 1 to be turned on. The turned-on first output module 1 transmits the second potential signal VGL to the output terminal OUT of the light emitting control circuit.

[0073] In the sixth stage P6, the start signal SIN is at a high level, the first clock signal CK1 is at a high level, and the second clock signal CK2 is at a low level. The second clock signal CK2 controls the write module 6 to turn off, so that the start signal SIN cannot be transmitted to the third node N3, and the potential of the third node N3 maintains the low level of the previous stage, i.e., the fifth stage P5. The potential of the third node N3 controls the second control module 5 to turn off, so that the second potential signal VGL cannot be transmitted to the first node N1, and the first node N1 maintains the high level of the previous stage. Although the second clock signal CK2 is at a low level and controls the first control module 4 to turn off, the first control module 4 responds to the high level of the first node N1 and the high level of the first clock signal CK1, and can transmit the first potential signal VGH to the second node N2, so that the potential of the second node N2 is a high level. The potential of the third node N3 controls the clamping module 6 to turn off, so that the second potential signal VGL cannot be transmitted to the second node N2, avoiding the influence on the high level of the second node N2. The potential of the third node N3 controls the second output module 2 to be turned off, and the potential of the second node N2 controls the first output module 1 to be turned on. The turned-on first output module 1 transmits the second potential signal VGL to the output terminal OUT of the light emitting control circuit.

[0074] In the seventh stage P7, the start signal SIN is at a high level, the first clock signal CK1 is at a low level, and the second clock signal CK2 is at a high level. The second clock signal CK2 controls the writing module 6 to turn on, so that the start signal SIN is transmitted to the third node N3, so that the potential of the third node N3 is at a high level. The potential of the third node N3 and the first clock signal CK1 control the second control module 5 to turn off, so that the second potential signal VGL cannot be transmitted to the first node N1. Although the first clock signal CK1 controls the first control module 4 to turn off, the first control module 4 responds to the second clock signal CK2 and transmits the first potential signal VGH to the first node N1, so that the potential of the first node N1 is at a high level. The third node N3 controls the clamping module 3 to turn on, so that the second potential signal VGL is transmitted to the second node N2, so that the potential of the second node N2 is at a low level. The potential of the second node N2 controls the first output module 1 to turn off, and the potential of the third node N3 controls the second output module 2 to turn on, so as to transmit the first potential signal VGH to the output terminal OUT of the light emitting control circuit.

[0075] In the eighth stage P8, the start signal SIN is at a high level, the first clock signal CK1 is at a high level, and the second clock signal CK2 is at a low level. The second clock signal CK2 controls the write module 6 to turn off, so that the start signal SIN cannot be transmitted to the third node N3, and the potential of the third node N3 maintains the high level of the previous stage, i.e., the seventh stage P7. The potential of the third node N3 controls the clamping module 3 to turn on, so that the second potential signal VGL is transmitted to the second node N2, so that the potential of the second node N2 is a low level. The potential of the third node N3 and the first clock signal CK1 control the second control module 5 to turn on, so as to transmit the second potential signal VGL to the first node N1, so that the potential of the first node N1 is a low level. The second clock signal and the potential of the first node N1 control the first control module 4 to turn off, so that the first potential signal VGH cannot be transmitted to the second node N2, avoiding the influence on the low level of the second node N2. The potential of the second node N2 controls the first output module 1 to turn off, and the potential of the third node N3 controls the second output module 2 to turn on, so as to transmit the first potential signal VGH to the output terminal OUT of the light-emitting control circuit.

[0076] After the eighth stage P8 ends, the light emitting control circuit further includes a cycle stage, in which the seventh stage P7 and the eighth stage P8 are repeated until one frame ends.

[0077] In this embodiment, the potential of the third node is controlled by the writing module, and the potential of the second node is controlled by the first control module, the second control module and the clamping module, so that at a time, at most one of the first output module and the second output module is turned on to transmit the first potential signal or the second potential signal to the output end of the light-emitting control circuit. The signal output by the output end of the light-emitting control circuit is the light-emitting control signal, thereby controlling the pixel circuit including transistors that are all N-type transistors to emit light in the light-emitting stage. The circuit provided in this embodiment can be used to drive the pixel circuit including transistors that are all N-type transistors, thereby realizing the application of large-size display panels.

[0078] Figure 7 A schematic diagram of another light emitting control circuit provided by an embodiment of the present invention, referring to Figure 7 Optionally, the first control module 4 includes a storage unit 41, a first control subunit 42 and a second control subunit 43, the first end of the storage unit 41 is connected to the first potential signal VGH, the second end of the storage unit 41 is connected to the first node N1, and the storage unit 41 is used to store the potential of the first node N1;

[0079] The first terminal of the first control subunit 42 is connected to the first potential signal VGH, the second terminal of the first control subunit 42 is connected to the first node N1, the control terminal of the first control subunit 42 is connected to the second clock signal CK2, and the first control subunit 42 is used to respond to the second clock signal CK2 and transmit the first potential signal VGH to the first node N1;

[0080] The first end of the second control subunit 43 is connected to the first end of the first control subunit 42, the second end of the second control subunit 43 is connected to the second node N2, the first control end of the second control subunit 43 is connected to the first node N1, the second control end of the second control subunit 43 is connected to the first clock signal CK1, and the second control subunit 43 is used to respond to the first clock signal CK1 and the potential of the first node N1, and transmit the first potential signal VGH to the second node N2.

[0081] refer to Figure 6 and Figure 7, in the first stage P1, the second clock signal CK2 controls the first control subunit 42 to be turned on, so as to transmit the first potential signal VGH to the first node N1, so that the potential of the first node N1 is high. The first clock signal CK1 controls the second control subunit 43 to be turned off, so that the first potential signal VGH cannot be transmitted to the second node N2. In the second stage P2, the second clock signal CK2 controls the first control subunit 42 to be turned off, so that the first potential signal VGH cannot be transmitted to the first node N1. The second control module 5 is turned on in response to the first clock signal CK1 and the potential of the third node N3 to transmit the second potential signal VGL to the first node N1, so that the potential of the first node N1 is low. The low level of the first node N1 controls the second control subunit 43 to be turned off, so that the first potential signal VGH cannot be transmitted to the second node N2. In the third stage P3, the second clock signal CK2 controls the first control subunit 42 to be turned on, so as to transmit the first potential signal VGH to the first node N1, so that the potential of the first node N1 is high. The first clock signal CK1 controls the second control subunit 43 to turn off so that the first potential signal VGH cannot be transmitted to the second node N2. In the fourth stage P4, the second clock signal CK2 controls the first control subunit 42 to turn off so that the first potential signal VGH cannot be transmitted to the first node N1. The potential of the third node N3 controls the second control module 5 to turn off so that the second potential signal VGL cannot be transmitted to the first node N1, and the first node N1 maintains the high level of the previous stage. The potential of the first node N1 and the first clock signal CK1 control the second control subunit 43 to turn on so as to transmit the first potential signal VGH to the second node N2. In the fifth stage P5, the second clock signal CK2 controls the first control subunit 42 to turn on so as to transmit the first potential signal VGH to the first node N1 so that the potential of the first node N1 is a high level. The first clock signal CK1 controls the second control subunit 43 to turn off so that the first potential signal VGH cannot be transmitted to the second node N2. In the sixth stage P6, the second clock signal CK2 controls the first control subunit 42 to turn off, so that the first potential signal VGH cannot be transmitted to the first node N1. The potential of the third node N3 controls the second control module 5 to turn off, so that the second potential signal VGL cannot be transmitted to the first node N1, and the first node N1 maintains the high level of the previous stage. The potential of the first node N1 and the first clock signal CK1 control the second control subunit 43 to turn on, so as to transmit the first potential signal VGH to the second node N2. In the seventh stage P7, the second clock signal CK2 controls the first control subunit 42 to turn on, so as to transmit the first potential signal VGH to the first node N1, so that the potential of the first node N1 is a high level. The first clock signal CK1 controls the second control subunit 43 to turn off, so that the first potential signal VGH cannot be transmitted to the second node N2.In the eighth stage P8, the second clock signal CK2 controls the first control subunit 42 to be turned off, so that the first potential signal VGH cannot be transmitted to the first node N1. The potential of the third node N3 and the first clock signal CK1 control the second control module 5 to be turned on, so that the second potential signal VGL is transmitted to the first node N1, so that the first node N1 is at a low level. The low level of the first node N1 controls the second control subunit 43 to be turned off, so that the first potential signal VGH cannot be transmitted to the second node N2.

[0082] Continue to refer Figure 7 Optionally, the first end of the second control module 5 is connected to the second potential signal VGL, the second end of the second control module 5 is connected to the first node N1, the first control end of the second control module 5 is connected to the first clock signal CK1, and the second control end of the second control module 5 is connected to the third node N3.

[0083] When the potential of the first clock signal CK1 and the third node N3 are both on potentials, the second control module 5 is controlled to be turned on. After the second control module 5 is turned on, the first end and the second end thereof are connected so that the potential of the first node N1 is equal to the second potential signal VGL. When at least one of the potentials of the first clock signal CK1 and the third node N3 is off potential, the second control module 5 is controlled to be turned off, that is, the connection between the first node N1 and the second potential signal VGL is disconnected.

[0084] Continue to refer Figure 7 Optionally, the first end of the write module 6 is connected to the start signal SIN, the second end of the write module 6 is connected to the third node N3, and the control end of the write module 6 is connected to the second clock signal CK2.

[0085] When the second clock signal CK2 is at the on potential, the writing module 6 is controlled to be turned on to connect the first end and the second end of the writing module 6, thereby connecting the start signal SIN to the third node N3. When the second clock signal CK2 is at the off potential, the writing module 6 is controlled to be turned off to disconnect the connection between the start signal SIN and the third node N3.

[0086] Continue to refer Figure 7 Optionally, the first end of the clamping module 3 is connected to the second potential signal VGL, the second end of the clamping module 3 is connected to the second node N2, and the control end of the clamping module 3 is connected to the third node N3.

[0087] When the potential of the third node N3 is the first potential signal VGH, i.e., the on-potential, the clamping module 3 is controlled to be turned on to connect the first end and the second end of the clamping module 3, so that the potential of the second node N2 is equal to the second potential signal VGL. When the potential of the third node N3 is the second potential signal VGL, i.e., the off-potential, the clamping module 3 is controlled to be turned off to disconnect the connection between the first end and the second end of the clamping module 3.

[0088] Continue to refer Figure 7 Optionally, the first end of the first output module 1 is connected to the second potential signal VGL, the second end of the first output module 1 is connected to the output end OUT of the light emitting control circuit, and the control end of the first output module 1 is connected to the second node N2;

[0089] A first end of the second output module 2 is connected to the first potential signal VGH, a second end of the second output module 2 is connected to the output end OUT of the light emitting control circuit, and a control end of the second output module 2 is connected to the third node N3.

[0090] When the second node N2 is at the on potential, the first output module 1 is controlled to be on, so as to connect the first end and the second end of the first output module 1, so that the potential of the output end OUT of the light emitting control circuit is the second potential signal VGL. When the second node N2 is at the off potential, the first output module 1 is controlled to be off, so as to disconnect the first end and the second end of the first output module 1. When the third node N3 is at the on potential, the second output module 2 is controlled to be on, so as to connect the first end and the second end of the second output module 2, so that the potential of the output end OUT of the light emitting control circuit is the first potential signal VGH. When the third node N3 is at the off potential, the second output module 2 is controlled to be off, so as to disconnect the first end and the second end of the second output module 2.

[0091] Continue to refer Figure 7 Optionally, the light emitting control circuit further includes: a boost module 7, the boost module 7 is connected to the third node N3, and the boost module is used to write the jump voltage difference into the third node N3 when the first clock signal CK1 connected to itself jumps from the second potential signal VGL to the first potential signal VGH, wherein the jump voltage difference is the difference between the first potential signal VGH and the second potential signal VGL.

[0092] The boost module has a boosting function. When the potential of the first clock signal CK1 changes from the second potential signal VGL to the first potential signal VGH, that is, when it changes from a low level to a high level, the voltage value of the third node N3 can be raised so that the voltage of the control end of the second output module 2 can reach a higher potential, thereby enabling the output end OUT of the light-emitting control circuit to normally output the first potential signal VGH, thereby avoiding the influence of the threshold voltage of the transistor included in the second output module 2.

[0093] against Figure 7 The circuit shown in the embodiment of the present invention provides a specific circuit structure. Figure 8 A schematic diagram of another light emitting control circuit provided by an embodiment of the present invention, referring to Figure 7 and Figure 8 , Optionally, the storage unit 41 includes a first capacitor C1, the first control subunit 42 includes a first transistor T1, and the second control subunit 43 includes a second transistor T2 and a third transistor T3;

[0094] A first end of the first capacitor C1 is connected to the first potential signal VGH, and a second end of the first capacitor C1 is connected to the first node N1;

[0095] A first electrode of the first transistor T1 is connected to the first potential signal VGH, a second electrode of the first transistor T1 is connected to the first node N1, and a gate of the first transistor T1 is connected to the second clock signal CK2;

[0096] The first electrode of the second transistor T2 is connected to the first electrode of the first transistor T1, the second electrode of the second transistor T2 is connected to the first electrode of the third transistor T3, the gate of the second transistor T2 is connected to the first node N1, the second electrode of the third transistor T3 is connected to the second node N2, and the gate of the third transistor T3 is connected to the first clock signal CK1.

[0097] The first transistor T1 may be an N-type transistor or a P-type transistor. The second transistor T2 may be an N-type transistor or a P-type transistor. The third transistor T3 may be an N-type transistor or a P-type transistor. When the transistor is an N-type transistor, the gate is at a low level to control the transistor to be turned off, and when the gate is at a high level, the transistor is controlled to be turned on. When the transistor is a P-type transistor, the gate is at a high level to control the transistor to be turned off, and when the gate is at a low level, the transistor is controlled to be turned on.

[0098] Continue to refer Figure 7 and Figure 8Optionally, the second control module 5 includes a fourth transistor T4 and a fifth transistor T5, the first electrode of the fourth transistor T4 is connected to the second potential signal VGL, the second electrode of the fourth transistor T4 is connected to the first electrode of the fifth transistor T5, the gate of the fourth transistor T4 is connected to the first clock signal CK1, the second electrode of the fifth transistor T5 is connected to the first node N1, and the gate of the fifth transistor T5 is connected to the third node N3. The writing module 6 includes a sixth transistor T6, the first electrode of the sixth transistor T6 is connected to the start signal SIN, the second electrode of the sixth transistor T6 is connected to the third node N3, and the gate of the sixth transistor T6 is connected to the second clock signal CK2. The writing module 6 includes only one transistor, the structure is simple, and it is easy to implement. Optionally, the clamping module 3 includes a seventh transistor T7, the first electrode of the seventh transistor T7 is connected to the second potential signal VGL, the second electrode of the seventh transistor T7 is connected to the second node N2, and the gate of the seventh transistor T7 is connected to the third node N3. The clamping module 3 includes only one transistor, the structure is simple, and it is easy to implement. Optionally, the first output module 1 includes a second capacitor C2 and an eighth transistor T8, the first electrode of the eighth transistor T8 is connected to the second potential signal VGL, the second electrode of the eighth transistor T8 is connected to the output end OUT of the light emitting control circuit, the gate of the eighth transistor T8 is connected to the second node N2, the first end of the second capacitor C2 is connected to the first electrode of the eighth transistor T8, and the second end of the second capacitor C2 is connected to the gate of the eighth transistor T8; the second output module 2 includes a third capacitor C3 and a ninth transistor T9, the first electrode of the ninth transistor T9 is connected to the first potential signal VGH, the second electrode of the ninth transistor T9 is connected to the output end OUT of the light emitting control circuit, the gate of the ninth transistor T9 is connected to the third node N3, the first end of the third capacitor C3 is connected to the second electrode of the ninth transistor T9, and the second end of the third capacitor C3 is connected to the gate of the ninth transistor T9. The second capacitor C2 is used to maintain the potential of the gate of the eighth transistor T8, and the third capacitor C3 is used to maintain the potential of the gate of the ninth transistor T9. The boost module 7 includes a tenth transistor T10 and a fourth capacitor C4, the first electrode of the tenth transistor T10 is connected to the first clock signal CK1, the second electrode of the tenth transistor T10 is connected to the first end of the fourth capacitor C4, the gate of the tenth transistor T10 is connected to the second end of the fourth capacitor C4, and the second end of the fourth capacitor C4 is connected to the third node N3.

[0099] The tenth transistor T10 and the fourth capacitor C4 form a bootstrap circuit. When the potential of the first clock signal CK1 jumps from a low level to a high level, the potential of the third node N3, i.e., the control terminal of the ninth transistor T9, can be raised due to the coupling effect of the fourth capacitor C4. If the potential of the gate of the ninth transistor T9 is not raised, when the sixth transistor T6 is turned on and the high level of the start signal SIN is transmitted to the control terminal of the ninth transistor T9, the ninth transistor T9 is turned on in response to the high level of its own gate to transmit the first potential signal VGH, i.e., the high level, to its own second electrode. When the difference between the gate voltage of the ninth transistor T9 and the voltage of the second electrode is equal to the threshold voltage, the ninth transistor T9 is turned off. Because the high level of the gate voltage is equal to the first potential signal VGH, when the voltage at the second electrode is charged to the difference between the first potential signal VGH and the threshold voltage of the ninth transistor T9, the ninth transistor T9 is turned off and cannot charge the second electrode to the first potential signal VGH. Therefore, the gate voltage of the ninth transistor T9 is raised through the tenth transistor T10 and the fourth capacitor C4, so that the ninth transistor T9 can normally output the first potential signal and avoid the influence of the threshold voltage.

[0100] Figure 6 The timing shown also applies to Figure 8 The light control circuit shown in the reference Figure 6 and Figure 8 In one frame, the working process of the light emitting control circuit includes the first stage P1 to the eighth stage P8.

[0101] Figures 9 to 16 The schematic diagrams are respectively the working process of the light emitting control circuit in each stage of the present embodiment, and the arrows in the figure indicate the direction of current flow, the circle represents the transistor being turned on, and the cross represents the transistor being turned off. Figure 6 and Fig. 9, in the first stage P1, the start signal SIN is at a high level, the first clock signal CK1 is at a low level, and the second clock signal CK2 is at a high level. The second clock signal CK2 controls the sixth transistor T6 to turn on, and the turned-on sixth transistor T6 transmits the start signal SIN to the third node N3, so that the potential of the third node N3 is at a high level. The high level of the third node N3 controls the seventh transistor T7 to turn on, and the turned-on seventh transistor T7 transmits the second potential signal VGL to the second node N2. The second clock signal CK2 controls the first transistor T1 to turn on, and the turned-on first transistor T1 transmits the first potential signal VGH to the first node N1. The first clock signal CK1 controls the fourth transistor T4 to turn off. Although the potential of the third node N3 controls the fifth transistor T5 to turn on, because the fourth transistor T4 is turned off, the second potential signal VGL cannot be transmitted to the first node N1 through the fourth transistor T4 and the fifth transistor T5, thereby avoiding the influence of the second potential signal on the high level of the first node N1. The first node N1 is at a high level, controlling the second transistor T2 to turn on, and the first clock signal CK1 controls the third transistor T3 to turn off. The first potential signal VGH cannot be transmitted to the second node N2 through the turned-off third transistor T3, thereby preventing the first potential signal VGH from affecting the second potential signal VGL written into the second node N2. The second node N2 is at a low level, controlling the eighth transistor T8 to turn off. The third node N3 is at a high level, controlling the ninth transistor T9 to turn on, and the turned-on ninth transistor T9 transmits the first potential signal VGH to the output terminal OUT of the light emitting control circuit.

[0102] refer to Figure 6 and Fig.10, in the second stage P2, the start signal SIN is at a high level, the first clock signal CK1 is at a high level, and the second clock signal CK2 is at a low level. The second clock signal CK2 controls the sixth transistor T6 to turn off, so that the start signal SIN cannot be transmitted to the third node N3, and the potential of the third node N3 maintains the high level of the previous stage, i.e., the first stage P1. The high level of the third node N3 controls the seventh transistor T7 to turn on, and the turned-on seventh transistor T7 transmits the second potential signal VGL to the second node N2. The high level of the third node N3 controls the fifth transistor T5 to turn on, and the first clock signal CK1 controls the fourth transistor T4 to turn on, and the turned-on fourth transistor T4 and the fifth transistor T5 transmit the second potential signal VGL to the first node N1. The second clock signal CK2 controls the first transistor T1 to turn off, so as to prevent the first potential signal VGH from being transmitted to the first node N1 through the first transistor T1, and affecting the low level of the first node N1. The low level of the first node N1 controls the second transistor T2 to turn off. Although the first clock signal CK1 controls the third transistor T3 to turn on, the first potential signal VGH cannot be transmitted to the second node N2 because the second transistor T2 is turned off, avoiding the influence of the low level written to the second node N2. The low level of the second node N2 controls the eighth transistor T8 to turn off, and the high level of the third node N3 controls the ninth transistor T9 to turn on. The turned-on ninth transistor T9 transmits the first potential signal VGH to the output terminal OUT of the light emitting control circuit. The high level of the third node N3 controls the tenth transistor T10 to turn on. At the start of the second stage P2, the first clock signal CK1 jumps from a low level to a high level. Due to the coupling effect of the fourth capacitor C4, the potential of the third node N3 is raised to VH+Vup, Vup=VH-VL, where VH is a high level, that is, the voltage of the first potential signal VGH, and VL is a low level, that is, the voltage of the second potential signal VGL. The potential of the third node N3 is raised, which can ensure that the ninth transistor T9 normally outputs a high level without being affected by the threshold voltage of the ninth transistor T9.

[0103] refer to Figure 6 and Fig.11, in the third stage P3, the start signal SIN is at a low level, the first clock signal CK1 is at a low level, and the second clock signal CK2 is at a high level. The second clock signal CK2 controls the sixth transistor T6 to turn on, so that the start signal SIN is transmitted to the third node N3, so that the potential of the third node N3 is at a low level. The low level of the third node N3 controls the tenth transistor T10 to turn off. The second clock signal CK2 controls the first transistor T1 to turn on, and the turned-on first transistor T1 transmits the first potential signal VGH to the first node N1, so that the first node N1 is at a high level. The potential of the third node N3 controls the fifth transistor T5 to turn off, the first clock signal CK1 controls the fourth transistor T4 to turn off, and the second potential signal VGL cannot be transmitted to the first node N1 through the turned-off fourth transistor T4 and the fifth transistor T5, avoiding the influence of the high level written to the first node N1. The high level of the first node N1 controls the second transistor T2 to turn on, and the first clock signal CK1 controls the third transistor T3 to turn off, and the first potential signal VGH cannot be transmitted to the second node N2 through the second transistor T2 and the third transistor T3. The low level of the third node N3 controls the seventh transistor T7 to turn off, and the second potential signal VGL cannot be transmitted to the second node N2, and the second node N2 maintains the low level of the previous stage, i.e., the second stage P2. The potential of the second node N2 controls the eighth transistor T8 to turn off, and the potential of the third node N3 controls the ninth transistor T9 to turn off, and the output terminal OUT of the light emitting control circuit maintains the high level of the previous stage.

[0104] refer to Figure 6 and Fig.12, in the fourth stage P4, the start signal SIN is at a low level, the first clock signal CK1 is at a high level, and the second clock signal CK2 is at a low level. The second clock signal CK2 controls the sixth transistor T6 to turn off, so that the start signal SIN cannot be transmitted to the third node N3, and the third node N3 maintains the low level of the previous stage, i.e., the third stage P3. The low level of the third node N3 controls the tenth transistor T10 and the fifth transistor T5 to turn off. Although the first clock signal CK1 controls the fourth transistor T4 to turn on, because the fifth transistor T5 is turned off, the second potential signal VGL cannot be transmitted to the first node N1 through the fourth transistor T4 and the fifth transistor T5. The second clock signal CK2 controls the first transistor T1 to turn off, so that the first potential signal VGH cannot be transmitted to the first node N1 through the first transistor T1, and the first node N1 maintains the high level of the previous stage. The high level of the first node N1 controls the second transistor T2 to turn on, the first clock signal CK1 controls the third transistor T3 to turn on, and the turned-on second transistor T2 and third transistor T3 transmit the first potential signal VGH to the second node N2, so that the second node N2 is at a high level. The low level of the third node N3 controls the seventh transistor T7 to turn off, preventing the second potential signal VGL from being transmitted to the second node N2 and affecting the high level of the second node N2. The low level of the third node N3 controls the ninth transistor T9 to turn off, and the high level of the second node N2 controls the eighth transistor T8 to turn on, and the turned-on eighth transistor T8 transmits the second potential signal VGL to the output terminal OUT of the light emitting control circuit.

[0105] refer to Figure 6 and Fig.13, in the fifth stage P5, the start signal SIN is at a low level, the first clock signal CK1 is at a low level, and the second clock signal CK2 is at a high level. The second clock signal CK2 controls the sixth transistor T6 to turn on, and the turned-on sixth transistor T6 transmits the start signal SIN to the third node N3, so that the third node N3 is at a low level. The low level of the third node N3 controls the tenth transistor T10 and the fifth transistor T5 to turn off, the first clock signal CK1 controls the fourth transistor T4 to turn off, and the second potential signal VGL cannot be transmitted to the first node N1 through the fourth transistor T4 and the fifth transistor T5. The second clock signal CK2 controls the first transistor T1 to turn on, and the turned-on first transistor T1 transmits the first potential signal VGH to the first node N1, so that the potential of the first node N1 is at a high level. The potential of the first node N1 controls the second transistor T2 to turn on, and the first clock signal CK1 controls the third transistor T3 to turn off, and the first potential signal VGH cannot be transmitted to the second node N2 through the second transistor T2 and the third transistor T3. The low level of the third node N3 controls the seventh transistor T7 to turn off, and the second potential signal VGL cannot be transmitted to the second node N2 through the seventh transistor T7, and the second node N2 maintains the high level of the previous stage, i.e., the fourth stage P4. The low level of the third node N3 controls the ninth transistor T9 to turn off, and the high level of the second node N2 controls the eighth transistor T8 to turn on, and the turned-on eighth transistor T8 transmits the second potential signal VGL to the output terminal OUT of the light emitting control circuit.

[0106] refer to Figure 6 and Fig.14, in the sixth stage P6, the start signal SIN is at a high level, the first clock signal CK1 is at a high level, and the second clock signal CK2 is at a low level. The second clock signal CK2 controls the sixth transistor T6 to turn off, so that the start signal SIN cannot be transmitted to the third node N3, and the third node N3 maintains the low level of the previous stage, that is, the fifth stage P5. The low level of the third node N3 controls the tenth transistor T10 and the fifth transistor T5 to turn off, the first clock signal CK1 controls the fourth transistor T4 to turn on, and the second potential signal VGL cannot be transmitted to the first node N1 through the fourth transistor T4 and the fifth transistor T5. The second clock signal CK2 controls the first transistor T1 to turn off, and the first potential signal VGH cannot be transmitted to the first node N1 through the first transistor T1, and the first potential signal VGH maintains the high level of the previous stage. The high level of the first node N1 controls the second transistor T2 to turn on, the first clock signal CK1 controls the third transistor T3 to turn on, and the turned-on second transistor T2 and the third transistor T3 transmit the first potential signal VGH to the second node N2, so that the potential of the second node N2 is high. The low level of the third node N3 controls the seventh transistor T7 to turn off, and the second potential signal VGL cannot be transmitted to the second node N2 through the seventh transistor T7, thereby avoiding the influence of the low level of the second potential signal VGL on the potential of the second node N2. The potential of the third node N3 controls the ninth transistor T9 to turn off, and the high level of the second node N2 controls the eighth transistor T8 to turn on, and the turned-on eighth transistor T8 transmits the second potential signal VGL to the output terminal OUT of the light emitting control circuit.

[0107] refer to Figure 6 and Fig.15, in the seventh stage P7, the start signal SIN is at a high level, the first clock signal CK1 is at a low level, and the second clock signal CK2 is at a high level. The second clock signal CK2 controls the sixth transistor T6 to turn on, so that the start signal SIN is transmitted to the third node N3, so that the third node N3 is at a high level. The second clock signal CK2 controls the first transistor T1 to turn on, so that the first potential signal VGH is transmitted to the first node N1 through the first transistor T1, thereby making the potential of the first node N1 high. The high level of the third node N3 controls the fifth transistor T5 to turn on, the first clock signal CK1 controls the fourth transistor T4 and the third transistor T3 to turn off, and the second potential signal VGL cannot be transmitted to the first node N1 through the fourth transistor T4 and the fifth transistor T5, avoiding the influence on the high level of the first node N1. The high level of the third node N3 controls the seventh transistor T7 to turn on, so that the second potential signal VGL is transmitted to the second node N2, thereby making the potential of the second node N2 low. The potential of the first node N1 controls the second transistor T2 to turn on, and the first potential signal VGH cannot be transmitted to the second node N2 through the second transistor T2 and the third transistor T3, thereby avoiding the influence on the low level of the second node N2. The potential of the second node N2 controls the eighth transistor T8 to turn off, and the high level of the third node N3 controls the ninth transistor T9 to turn on. The turned-on ninth transistor T9 transmits the first potential signal VGH to the output terminal OUT of the light emitting control circuit.

[0108] refer to Figure 6 and Fig.16, in the eighth stage P8, the start signal SIN is at a high level, the first clock signal CK1 is at a high level, and the second clock signal CK2 is at a low level. The second clock signal CK2 controls the sixth transistor T6 to turn off, so that the start signal SIN cannot be transmitted to the third node N3, and the third node N3 maintains the high level of the previous stage. The potential of the third node N3 controls the fifth transistor T5 to turn on, and the first clock signal CK1 controls the fourth transistor T4 to turn on. The turned-on fourth transistor T4 and the fifth transistor T5 transmit the second potential signal VGL to the first node N1, so that the potential of the first node N1 is a low level. The second clock signal CK2 controls the first transistor T1 to turn off, so as to prevent the first potential signal VGH from being transmitted to the first node N1 through the first transistor T1, affecting the low level written to the first node N1. The high level of the third node N3 controls the seventh transistor T7 to turn on, so as to transmit the second potential signal VGL to the second node N2, so that the potential of the second node N2 is a low level. The low level of the first node N1 controls the second transistor T2 to turn off, the first clock signal CK1 controls the third transistor T3 to turn on, and the first potential signal VGH cannot be transmitted to the second node N2 through the second transistor T2 and the third transistor T3, so as to avoid affecting the low level of the second node N2. The low level of the second node N2 controls the eighth transistor T8 to turn off, and the high level of the third node N3 controls the ninth transistor T9 to turn on. The turned-on ninth transistor T9 transmits the first potential signal VGH to the output terminal OUT of the light emitting control circuit.

[0109] After the eighth stage P8 ends, the seventh stage P7 and the eighth stage P8 are continuously repeated until the current frame ends. An embodiment of the present invention further provides a display panel, which includes the above-mentioned light emitting control circuit.

[0110] The beneficial effects of the display panel are the same as those of the light emitting control circuit, and will not be described in detail in this embodiment.

[0111] Fig.17 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention, the display panel includes at least two cascaded light-emitting control circuits 01, the light-emitting control circuits include a start signal input terminal IN, a first clock signal input terminal L1, a second clock signal input terminal L2, a first power supply terminal H1 and a second power supply terminal H2, each level of the light-emitting control circuit 01 drives two rows of pixels 02, and the light-emitting control circuit 01 adopts a two-end drive. In two adjacent light-emitting control circuits 01, the signal output by the output terminal OUT of the previous level of light-emitting control circuit 01 is used as the start signal connected to the start signal input terminal IN of the next level of light-emitting control circuit 01;

[0112] The display panel includes a first power line V1, a second power line V2, a first clock line K1 and a second clock line K2, the first power line V1 is used to provide a first potential signal, the second power line V2 is used to provide a second potential signal, the first clock line K1 is used to provide a first clock signal, and the second clock line K2 is used to provide a second clock signal;

[0113] The first clock signal input terminal L1 of the i-th level light emitting control circuit is connected to the first clock line K1, and the second clock signal input terminal L2 is connected to the second clock line K2;

[0114] The first clock signal input terminal L1 of the i+1th level light emitting control circuit is connected to the second clock line K2, and the second clock signal input terminal L2 is connected to the first clock line K1; wherein, i is greater than or equal to 1.

[0115] The light emitting control circuit 01 adopts a double-end drive. For a large-size display panel, the difference in light emitting start time in different pixels in the same row caused by the long signal line transmitting the light emitting control signal is reduced, which is beneficial to improving the uniformity of display.

[0116] Fig.18 A simulation result diagram of a display panel provided by an embodiment of the present invention, comprising Fig.17 The display panel shown is simulated, and the specific structure of the light emitting control circuit in the display panel can be seen in Figure 8 In this embodiment, the display panel includes four cascaded light control circuits. The light control signal output by the first light control circuit is a first light control signal EM1. The light control signal output by the second light control circuit is a second light control signal EM2. The light control signal output by the third light control circuit is a third light control signal EM3. The light control signal output by the fourth light control circuit is a fourth light control signal EM4. Fig.18 It can be seen that the light-emitting control circuit provided by the embodiment of the present invention can normally output the waveform of the light-emitting control signal and realize the shift output of light-emitting control signals of different levels.

[0117] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0118] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A light emitting control circuit, characterized in that: include: A first output module, a second output module, a clamping module, a first control module, a second control module and a writing module; The first control module is used to respond to the first clock signal, the second clock signal and the potential of the first node, and transmit the first potential signal to the second node; wherein the first node is connected to the second control module, and the second node is connected to the control end of the first output module; The second control module is used to respond to the first clock signal and the potential of the third node, transmit the second potential signal to the first node, and the third node is connected to the control end of the second output module; The writing module is used for transmitting a start signal to the third node in response to the second clock signal; The clamping module is used for controlling the signal of the second node to be the second potential signal in response to the first potential signal of the third node; The first output module is used to control the second potential signal to be transmitted to the output end of the light emitting control circuit according to the potential of the second node; The second output module is used to control the first potential signal to be transmitted to the output end of the light emitting control circuit according to the potential of the third node.

2. The light emitting control circuit according to claim 1, characterized in that: The first control module includes a storage unit, a first control subunit and a second control subunit, the first end of the storage unit is connected to the first potential signal, the second end of the storage unit is connected to the first node, and the storage unit is used to store the potential of the first node; The first terminal of the first control subunit is connected to the first potential signal, the second terminal of the first control subunit is connected to the first node, the control terminal of the first control subunit is connected to the second clock signal, and the first control subunit is used to respond to the second clock signal and transmit the first potential signal to the first node; The first end of the second control subunit is connected to the first end of the first control subunit, the second end of the second control subunit is connected to the second node, the first control end of the second control subunit is connected to the first node, the second control end of the second control subunit is connected to the first clock signal, and the second control subunit is used to respond to the first clock signal and the potential of the first node, and transmit the first potential signal to the second node.

3. The light emitting control circuit according to claim 2, characterized in that: The storage unit includes a first capacitor, the first control subunit includes a first transistor, and the second control subunit includes a second transistor and a third transistor; The first end of the first capacitor is connected to the first potential signal, and the second end of the first capacitor is connected to the first node; A first electrode of the first transistor is connected to the first potential signal, a second electrode of the first transistor is connected to the first node, and a gate of the first transistor is connected to the second clock signal; The first electrode of the second transistor is connected to the first electrode of the first transistor, the second electrode of the second transistor is connected to the first electrode of the third transistor, the gate of the second transistor is connected to the first node, the second electrode of the third transistor is connected to the second node, and the gate of the third transistor is connected to the first clock signal.

4. The light emitting control circuit according to claim 1, characterized in that: The first end of the second control module is connected to the second potential signal, the second end of the second control module is connected to the first node, the first control end of the second control module is connected to the first clock signal, and the second control end of the second control module is connected to the third node.

5. The light emitting control circuit according to claim 4, characterized in that: The second control module includes a fourth transistor and a fifth transistor, the first electrode of the fourth transistor is connected to the second potential signal, the second electrode of the fourth transistor is connected to the first electrode of the fifth transistor, the gate of the fourth transistor is connected to the first clock signal, the second electrode of the fifth transistor is connected to the first node, and the gate of the fifth transistor is connected to the third node.

6. The light emitting control circuit according to claim 1, characterized in that: The first end of the writing module is connected to the start signal, the second end of the writing module is connected to the third node, and the control end of the writing module is connected to the second clock signal.

7. The light emitting control circuit according to claim 6, characterized in that: The writing module includes a sixth transistor, a first electrode of the sixth transistor is connected to the start signal, a second electrode of the sixth transistor is connected to the third node, and a gate of the sixth transistor is connected to the second clock signal.

8. The light emitting control circuit according to claim 1, characterized in that: The first end of the clamping module is connected to the second potential signal, the second end of the clamping module is connected to the second node, and the control end of the clamping module is connected to the third node.

9. The light emitting control circuit according to claim 8, characterized in that: The clamping module includes a seventh transistor, a first electrode of the seventh transistor is connected to the second potential signal, a second electrode of the seventh transistor is connected to the second node, and a gate of the seventh transistor is connected to the third node.

10. The light emitting control circuit according to claim 1, characterized in that: The first end of the first output module is connected to the second potential signal, the second end of the first output module is connected to the output end of the light emitting control circuit, and the control end of the first output module is connected to the second node; The first terminal of the second output module is connected to the first potential signal, the second terminal of the second output module is connected to the output terminal of the light emitting control circuit, and the control terminal of the second output module is connected to the third node.

11. The light emitting control circuit according to claim 10, characterized in that: The first output module includes a second capacitor and an eighth transistor, the first electrode of the eighth transistor is connected to the second potential signal, the second electrode of the eighth transistor is connected to the output end of the light-emitting control circuit, the gate of the eighth transistor is connected to the second node, the first end of the second capacitor is connected to the first electrode of the eighth transistor, and the second end of the second capacitor is connected to the gate of the eighth transistor.

12. The light emitting control circuit according to claim 10, characterized in that: The second output module includes a third capacitor and a ninth transistor, the first electrode of the ninth transistor is connected to the first potential signal, the second electrode of the ninth transistor is connected to the output end of the light-emitting control circuit, the gate of the ninth transistor is connected to the third node, the first end of the third capacitor is connected to the second electrode of the ninth transistor, and the second end of the third capacitor is connected to the gate of the ninth transistor.

13. The light emitting control circuit according to claim 1, characterized in that: The light-emitting control circuit also includes: a boost module, which is connected to the third node, and is used to write a transition voltage difference into the third node when the first clock signal connected to the boost module jumps from the second potential signal to the first potential signal, wherein the transition voltage difference is the difference between the first potential signal and the second potential signal.

14. The light emitting control circuit according to claim 13, characterized in that: The first end of the boost module is connected to the first clock signal, and the second end of the boost module is connected to the third node.

15. The light emitting control circuit according to claim 14, characterized in that: The boost module includes a tenth transistor and a fourth capacitor, the first electrode of the tenth transistor is connected to the first clock signal, the second electrode of the tenth transistor is connected to the first end of the fourth capacitor, the gate of the tenth transistor is connected to the second end of the fourth capacitor, and the second end of the fourth capacitor is connected to the third node.

16. A display panel, characterized in that: It comprises the light emitting control circuit as described in any one of claims 1-15.

Images