A silicon-based detector and a method for manufacturing the same

Abstract

The present application relates to a silicon-based detector, which designs and processes the p+ injection area of the device without changing the thickness of the substrate, and performs carbon injection, increases the area of generating electron-hole pairs and avalanche effect, thereby increasing the breakdown voltage of the device and improving the anti-radiation performance of the device. In addition, the present application introduces a deep trench ring isolation structure. Compared with the traditional silicon-based detector, the protection ring does not need to be obtained by ion implantation, the influence of the edge electric field on the performance of the device is reduced, and the dead area can be smaller when the array is formed, the integration density is improved, and the detection efficiency is improved. The present application also relates to a preparation method of the silicon-based detector.

Description

Technical Field

[0001] This invention relates to the field of semiconductor detector fabrication technology, and specifically to a silicon-based detector and its fabrication method. Background Technology

[0002] Silicon-based detectors are considered promising candidates for time detectors. Their primary applications are particle detectors and time detectors. Typical silicon-based detectors include silicon photomultiplier tubes (SiPMs), avalanche detectors (APDs), and low-gain avalanche detectors (LGADs). SiPMs offer excellent time resolution, but their gain is sensitive to temperature and reverse bias, resulting in significant crosstalk, high noise, and low radiation resistance, making them unsuitable for high-radiation environments. Avalanche detectors (APDs) offer good radiation resistance and time resolution, but their high gain leads to relatively high noise and dark current. LGADs combine the advantages of both, offering moderate gain, eliminating the need for quenching circuitry, providing better radiation resistance compared to standard pins, and boasting the lowest time resolution (~40 ps) among the three, making them an excellent choice for time detectors. However, existing LGADs suffer from low breakdown voltage and poor radiation resistance.

[0003] Therefore, this invention is proposed. Summary of the Invention

[0004] The purpose of this invention is to overcome the problems existing in the prior art and provide a silicon-based detector that designs and processes the p+ injection region of the device without changing the substrate thickness and performs carbon injection to increase the area for generating electron-hole pairs and avalanche effects, thereby increasing the breakdown voltage of the device and improving its radiation resistance.

[0005] Another object of the present invention is to provide a method for fabricating the silicon-based detector.

[0006] To achieve the above objectives, the present invention provides the following technical solution.

[0007] A silicon-based detector, comprising:

[0008] Substrate;

[0009] The first doped region, which is a carbon-containing P-type heavily doped region, is disposed inside the substrate, and the lower surface of the first doped region is recessed inward;

[0010] The second doped region, which is an N-type heavily doped region, is disposed on the upper surface of the first doped region, and the upper surface of the second doped region is flush with the upper surface of the substrate.

[0011] Upper electrode layer, the upper electrode layer covering the upper surface of the second doped region;

[0012] A passivation protective layer, the passivation protective layer covering a portion of the surface of the upper electrode layer; and

[0013] A lower electrode layer is disposed on the lower surface of the substrate.

[0014] The present invention also provides a method for fabricating the silicon-based detector, comprising the following steps:

[0015] Provide substrate;

[0016] A first doped region is formed inside the substrate, such that the lower surface of the first doped region is recessed inward, and the first doped region is a carbon-containing P-type heavily doped region.

[0017] A second doped region is formed on the upper surface of the first doped region, such that the upper surface of the second doped region is flush with the upper surface of the substrate, and the second doped region is an N-type heavily doped region;

[0018] An upper electrode layer is formed on the upper surface of the second doped region;

[0019] A passivation protective layer is formed on the upper electrode layer, covering a portion of the surface of the upper electrode layer; and

[0020] A lower electrode layer is formed on the lower surface of the substrate.

[0021] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0022] This invention provides a silicon-based detector that, without changing the substrate thickness, designs and processes the p+ injection region of the device, moderately increasing the area for generating electron-hole pairs and avalanche effects, and introduces a carbon-containing layer through carbon implantation to generate interstitial atoms, reducing the acceptor displacement effect under irradiation conditions. This results in a device that is superior to conventional silicon-based detectors (see...). Figure 1 This invention reduces dark current, increases breakdown voltage, extends device lifespan, and enhances device reliability. Furthermore, compared to conventional devices, this invention exhibits a smaller surface electric field, reducing surface capacitive coupling and improving detection efficiency.

[0023] Furthermore, this invention introduces a deep trench annular isolation structure. Compared to traditional silicon-based detectors, it eliminates the need for a protective ring obtained through ion implantation, reducing the impact of edge electric fields on device performance. It also allows for a smaller dead zone area during array formation, increasing integration density and thus improving detection efficiency. Attached Figure Description

[0024] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0025] Figure 1 This is a schematic diagram of the structure of a traditional silicon-based detector.

[0026] Figure 2-15 The diagram shows the structure obtained in each step of the silicon-based detector fabrication method provided in the embodiments of the present invention.

[0027] Explanation of reference numerals in the attached figures:

[0028] 100 is the substrate, 101 is the annular trench, 200 is the third doped region, 300a is the initial isolation layer, 300 is the annular isolation layer, 400 is the gate oxide layer, 500a is the carbon-containing layer, 500 is the first doped region, 600 is the second doped region, 700 is the upper electrode layer, 800 is the lower electrode layer, and 900 is the passivation protection layer. Detailed Implementation

[0029] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0030] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0031] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0032] Silicon-based detectors are considered to have good prospects as time detectors. Typical silicon-based detectors include silicon photomultiplier tubes (SiPM), avalanche detectors (APD), and low-gain avalanche detectors (LGAD). Low-gain avalanche detectors (LGAD) combine the advantages of the former two, but they are limited by: (1) the protection ring structure of low-gain avalanche detectors is complex and interferes with device performance; (2) the gain control is unstable or the gain is too low, and the time resolution is difficult to break through to 10-20 ps; (3) when low-gain avalanche detectors are formed into an array, the effective area of ​​the detector is low and the dead zone is large due to the isolation design between each unit, which affects the detection efficiency; (4) it is difficult to withstand the effects of high-irradiation environments.

[0033] To address the above problems, the inventors, through in-depth research, designed a silicon-based detector, comprising: a substrate; a first doped region, which is a carbon-containing P-type heavily doped region disposed inside the substrate, with its lower surface recessed inward; a second doped region, which is an N-type heavily doped region disposed on the upper surface of the first doped region, with its upper surface flush with the upper surface of the substrate; an upper electrode layer covering the upper surface of the second doped region; a passivation protection layer covering a portion of the surface of the upper electrode layer; and a lower electrode layer disposed on the lower surface of the substrate.

[0034] The first doped region of this invention is formed by two carbon implantations followed by two P-type ion implantations. The ion implantation sites at the edges of the first doped region are deeper, forming a carbon-containing gain layer. This increases the area of ​​the gain region during detector operation, improves the probability of electron-hole pair collisions and avalanche effects, increases the device's depletion voltage and breakdown voltage, improves detection efficiency, reduces device area, and achieves suitable gain and high time resolution. Simultaneously, carbon implantation helps improve the sensor's radiation resistance.

[0035] The substrate can be a homogeneous epitaxial layer, such as a homogeneous high-resistivity epitaxial layer. The substrate can be a p-type heavily doped substrate. The doping concentration can be 1×10⁻⁶. 18 ~1×10 21 cm -3 Within the range, preferably within 1×10 19 ~1×10 20 cm -3 Within the range. P-type implanted ions can be boron (B), aluminum (Al), gallium (Ga), or indium (In), etc.

[0036] In some embodiments of the present invention, the lower surface of the first doped region is recessed from the outer periphery to the center to form a stepped surface. The stepped shape of the lower surface of the first doped region is beneficial to increasing the area of ​​the region where electron-hole pairs are generated without occupying too much substrate area. At the same time, it can optimize the edge electric field and improve the edge breakdown voltage.

[0037] The carbon doping concentration in the first doped region can be 3 × 10⁻⁶. 12 ~3×10 16 cm -3 Within the range, preferably within 5×10 13 ~5×10 14 cm -3 Within the range. The P-type ion doping concentration of the first doped region can be 1×10⁻⁶. 16 ~1×10 20 cm -3 Within the range, preferably within 1×10 17 ~1×10 19 cm -3 Within the range. P-type implanted ions can be boron (B), aluminum (Al), gallium (Ga), or indium (In), etc.

[0038] The doping concentration of the second doped region can be 1×10 16 ~1×10 20 cm -3 Within the range, preferably within 1×10 17 ~1×10 19 cm -3 Within the specified range. Dopant ions can be phosphorus (P), arsenic (As), antimony (Sb), or bismuth (Bi), etc. The upper surface of the second doped region is flush with the upper surface of the substrate, and its lower surface is in contact with the upper surface of the first doped region.

[0039] In some embodiments of the present invention, the substrate includes a central portion and an edge portion, and the upper surface height of the edge portion is lower than the upper surface height of the central portion. The silicon-based detector further includes an annular isolation layer disposed on the upper surface of the edge portion and surrounding the first doped region and the second doped region. The inner sidewall of the annular isolation layer is in contact with the sidewalls of both the first doped region and the second doped region.

[0040] This invention solves the problem of low array detection efficiency by introducing a deep trench isolation edge structure. It also solves the problems of unstable gain control, inability to withstand high-intensity irradiation environment, need to form a protective ring, and large dead area when forming an array in existing avalanche detectors.

[0041] Preferably, the height of the upper surface of the annular isolation layer is higher than the height of the upper surface of the second doped region, thereby forming a step and achieving a better isolation effect.

[0042] The material of the annular isolation layer may include silicon oxide or silicon nitride.

[0043] The thickness of the annular isolation layer can be 5-10 μm, for example, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm or 10 μm.

[0044] In some embodiments of the present invention, the silicon-based detector further includes a third doped region. The third doped region is a lightly doped P-type region. The third doped region is disposed on the upper surface of the edge portion of the substrate, and the upper surface of the third doped region is in contact with the lower surface of the annular isolation layer.

[0045] After etching to form deep trenches, P-type implantation is performed at the bottom to form a third doped region, which can prevent charge defects, produce better isolation, and prevent the substrate from being affected when the oxide is deposited in the trench.

[0046] The doping concentration of the third doped region can be 1×10⁻⁶. 10 ~1×10 14 cm -3 Within the range, preferably within 1×10 12 ~1×10 13 cm -3 Within a certain range. Doping ions can be boron (B), gallium (Ga), or indium (In), etc.

[0047] In some embodiments of the present invention, the silicon-based detector further includes a gate oxide layer. The gate oxide layer is disposed between the second doped region and the upper electrode layer, and covers the edge portion of the upper surface of the second doped region.

[0048] Preferably, the height of the upper surface of the gate oxide layer is lower than the height of the upper surface of the annular isolation layer, thereby forming a step. The higher height of the upper surface of the annular isolation layer is to provide better pixel isolation, which is beneficial for isolation during array formation. In one specific embodiment, the height of the upper surface of the annular isolation layer is higher than the height of the upper surface of the gate oxide layer, and the height of the upper surface of the gate oxide layer is higher than the height of the upper surface of the second doped region, thereby forming a two-stage step.

[0049] The thickness of the gate oxide layer can be 200 to 500 angstroms, for example, 200 angstroms, 300 angstroms, 400 angstroms or 500 angstroms.

[0050] In some embodiments of the present invention, the upper electrode layer covers the upper surface of the second doped region, the upper surface of the gate oxide layer, and a portion of the upper surface of the annular isolation layer. The width of the upper electrode layer is smaller than the width of the substrate.

[0051] In some embodiments of the present invention, the passivation protective layer is Γ-shaped. The passivation protective layer covers part of the upper surface and all of the side surfaces of the upper electrode layer, and also covers part of the upper surface of the annular isolation layer. This design provides both protection and exposes the electrode, ensuring its normal operation.

[0052] Both the upper electrode layer and the lower electrode layer can be made of aluminum.

[0053] The present invention also provides a method for fabricating the silicon-based detector, specifically including the following steps:

[0054] Provide substrate;

[0055] A first doped region is formed inside the substrate, such that the lower surface of the first doped region is recessed inward, and the first doped region is a carbon-containing P-type heavily doped region.

[0056] A second doped region is formed on the upper surface of the first doped region, such that the upper surface of the second doped region is flush with the upper surface of the substrate, and the second doped region is an N-type heavily doped region;

[0057] An upper electrode layer is formed on the upper surface of the second doped region;

[0058] A passivation protective layer is formed on the upper electrode layer, covering a portion of the surface of the upper electrode layer; and

[0059] A lower electrode layer is formed on the lower surface of the substrate.

[0060] In some embodiments of the present invention, the method for forming the first doped region includes: firstly implanting carbon into the substrate to form a carbon-containing layer, such that the lower surface of the carbon-containing layer is recessed from the outer periphery to the center to form a stepped surface; then implanting ions into the carbon-containing layer to form a P-type heavy doping layer (i.e., a gain layer), thereby obtaining the first doped region. Preferably, before forming the P-type heavy doping layer, the resulting structure is annealed to advance the implanted carbon to a predetermined position. The annealing temperature can be 1000–1100°C, and the annealing time can be 20–30 s.

[0061] By controlling the ion implantation conditions (including ion implantation energy), the gain layer and the carbon-containing layer can be made to overlap. The gain layer is a highly doped layer, which can be implanted with high-energy P-type ions. Similarly, high-energy carbon ions can be implanted. For example, to make the gain layer overlap with the carbon-containing layer, the implantation energy of P-type impurities (such as boron) can be about 4 to 5 times higher than that of carbon, so that the implantation depth of different types of ions is roughly the same.

[0062] In some embodiments of the present invention, before forming the first doped region, the method further includes: etching the edge of the substrate to form an annular trench, making the substrate convex; filling the annular trench with an isolation layer; forming a gate oxide layer on the upper surface of the substrate; and after forming the second doped region and before forming the upper electrode layer, the method further includes: etching the gate oxide layer to expose the central portion of the upper surface of the second doped region.

[0063] Preferably, the method for etching the substrate includes wet anisotropic etching. The sidewalls of the annular trench are perpendicular to the horizontal plane.

[0064] Preferably, filling the isolation layer includes: forming an initial isolation layer using chemical vapor deposition (CVD), the initial isolation layer covering the upper surface of the substrate; smoothing the upper surface of the initial isolation layer using chemical mechanical polishing (CMP); and performing isotropic wet etching or plasma etching on the initial isolation layer to expose the upper surface of the central portion of the substrate.

[0065] Before forming the first doped region, a gate oxide layer is formed on the upper surface of the substrate to prevent carbon atom leakage. Furthermore, the gate oxide layer acts as a barrier to prevent damage to the substrate during ion implantation. For example, the gate oxide layer can be formed by thermal oxidation.

[0066] The aspect ratio of the annular trench is preferably 30:1 or higher, for example, 50:1-60:1. A higher aspect ratio is beneficial for better pixel isolation and saves the area occupied by the pixel isolation region.

[0067] In some embodiments of the present invention, before filling the isolation layer, the method further includes: implanting ions into the bottom of the annular trench to form a lightly doped P-type region, thereby obtaining a third doped region.

[0068] In some embodiments of the present invention, the method for forming the passivation protective layer includes: firstly forming a passivation protective layer on the upper electrode layer by chemical vapor deposition, and then etching the passivation protective layer to form an opening, thereby exposing a portion of the upper surface of the upper electrode layer.

[0069] Preferably, the etching includes wet etching or plasma etching.

[0070] In some embodiments of the present invention, the upper electrode layer and the lower electrode layer can be formed by sputtering.

[0071] A specific embodiment of the preparation method of the present invention will now be described in detail with reference to the accompanying drawings.

[0072] First, prepare substrate 100, such as Figure 2 As shown.

[0073] Then, the substrate 100 is etched to form an annular trench 101, and the longitudinal section of the resulting structure is as follows. Figure 3 As shown.

[0074] Subsequently, P-type ions were implanted into the bottom of the annular trench 101 to form the third doped region 200. The longitudinal section of the resulting structure is shown below. Figure 4 As shown.

[0075] Next, the annular trench 101 is filled with an isolation medium to form an initial isolation layer 300a. The longitudinal section of the resulting structure is shown below. Figure 5 As shown.

[0076] Then, the initial isolation layer 300a is etched to expose the upper surface of the central portion of the substrate 100, resulting in an annular isolation layer 300. The longitudinal section of the resulting structure is shown below. Figure 6 As shown.

[0077] Subsequently, a gate oxide layer 400 is formed on the substrate 100 by thermal oxidation, and the longitudinal section of the resulting structure is shown below. Figure 7 As shown.

[0078] Next, carbon ions are implanted into the substrate 100, and the longitudinal section of the resulting structure is shown below. Figure 8 As shown.

[0079] Then, carbon ions were implanted and annealed to ensure that the ion implantation depth at the edge of the resulting 500a carbon layer was greater than that at the center. The longitudinal section of the resulting structure is shown below. Figure 9 As shown, the lower surface of the carbon layer 500a is concave inward.

[0080] Subsequently, p-type ions were implanted into the carbon-containing layer 500a, and the longitudinal section of the resulting structure is shown below. Figure 10 As shown.

[0081] Then, P-type ions are implanted into the carbon-containing layer 500a to obtain a gain layer. The gain layer and the carbon-containing layer 500a overlap to form a first doped region 500. The lower surface of the first doped region 500 is concave inward, and the ion implantation depth at the edge of the first doped region 500 is greater than the ion implantation depth at its center. The longitudinal section of the resulting structure is shown below. Figure 11 As shown.

[0082] Next, N-type ions are implanted into the surface layer of the substrate 100 to form a second doped region 600. The upper surface of the second doped region 600 is flush with the upper surface of the substrate 100, and its lower surface is in contact with the first doped region 500. The longitudinal section of the resulting structure is shown below. Figure 12 As shown.

[0083] Then, the gate oxide layer 400 is etched to expose the upper surface of the central portion of the second doped region 600, and the resulting structure has a longitudinal section as shown in Figure 1. Figure 13 As shown.

[0084] Subsequently, an upper electrode layer 700 is formed by sputtering, covering the upper surface of the second doped region 600, the upper surface of the gate oxide layer 400, and part of the upper surface of the annular isolation layer 300. A lower electrode layer 800 is then formed on the lower surface of the substrate 100 by sputtering. The longitudinal section of the resulting structure is shown below. Figure 14 As shown.

[0085] Finally, a passivation protective layer is formed by chemical vapor deposition. After etching, an open passivation protective layer 900 is obtained. The passivation protective layer 900 covers the upper surface of the upper electrode layer 700 and the annular isolation layer 300. The longitudinal section of the resulting structure is shown in Figure 1. Figure 15 As shown.

[0086] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A silicon-based detector, characterized in that, include: A substrate; the substrate includes a central portion and an edge portion, wherein the upper surface height of the edge portion is lower than the upper surface height of the central portion; The first doped region, which is a carbon-containing P-type heavily doped region, is disposed inside the substrate, and the lower surface of the first doped region is recessed inward; The second doped region, which is an N-type heavily doped region, is disposed on the upper surface of the first doped region, and the upper surface of the second doped region is flush with the upper surface of the substrate. Upper electrode layer, the upper electrode layer covering the upper surface of the second doped region; A passivation protective layer, the passivation protective layer covering a portion of the surface of the upper electrode layer; as well as A lower electrode layer is disposed on the lower surface of the substrate; An annular isolation layer is disposed on the upper surface of the edge portion and surrounds the first doped region and the second doped region; the inner sidewall of the annular isolation layer is in contact with the sidewall of both the first doped region and the sidewall of the second doped region. The P-type ion doping concentration in the heavily doped P-type region is 1×10⁻⁶. 16 ~1×10 20 cm -3 ; The N-type ion doping concentration in the heavily doped N-type region is 1×10⁻⁶. 16 ~1×10 20 cm -3 .

2. The silicon-based detector according to claim 1, characterized in that, The lower surface of the first doped region is recessed from the outer periphery to the center to form a stepped surface.

3. The silicon-based detector according to claim 1 or 2, characterized in that, The substrate includes a central portion and an edge portion, and the upper surface height of the edge portion is lower than the upper surface height of the central portion; Furthermore, the silicon-based detector also includes an annular isolation layer disposed on the upper surface of the edge portion, and surrounding the first doped region and the second doped region.

4. The silicon-based detector according to claim 3, characterized in that, Also includes: The third doped region, which is a lightly doped P-type region, is disposed on the upper surface of the edge portion, and the upper surface of the third doped region is in contact with the lower surface of the annular isolation layer.

5. The silicon-based detector according to claim 4, characterized in that, Also includes: A gate oxide layer is disposed between the second doped region and the upper electrode layer, and covers the edge portion of the upper surface of the second doped region.

6. A method for fabricating a silicon-based detector, characterized in that, Includes the following steps: A substrate is provided; the substrate includes a central portion and an edge portion, and the upper surface height of the edge portion is lower than the upper surface height of the central portion; A first doped region is formed inside the substrate, such that the lower surface of the first doped region is recessed inward, and the first doped region is a carbon-containing P-type heavily doped region. A second doped region is formed on the upper surface of the first doped region, such that the upper surface of the second doped region is flush with the upper surface of the substrate, and the second doped region is an N-type heavily doped region; An upper electrode layer is formed on the upper surface of the second doped region; A passivation protective layer is formed on the upper electrode layer to cover a portion of the surface of the upper electrode layer. as well as A lower electrode layer is formed on the lower surface of the substrate; It also includes forming an annular isolation layer on the upper surface of the edge portion, and the annular isolation layer surrounds the first doped region and the second doped region; the inner sidewall of the annular isolation layer is in contact with the sidewall of the first doped region and the sidewall of the second doped region. The P-type ion doping concentration in the heavily doped P-type region is 1×10⁻⁶. 16 ~1×10 20 cm -3 ; The N-type ion doping concentration in the heavily doped N-type region is 1×10⁻⁶. 16 ~1×10 20 cm -3 .

7. The preparation method according to claim 6, characterized in that, The method for forming the first doped region includes: firstly implanting carbon into the substrate to form a carbon-containing layer, such that the lower surface of the carbon-containing layer is recessed from the outer periphery to the center to form a stepped surface; then implanting ions into the carbon-containing layer to form P-type heavy doping, thereby obtaining the first doped region.

8. The preparation method according to claim 6 or 7, characterized in that, Before forming the first doped region, the method further includes: etching the edge of the substrate to form an annular trench, making the substrate convex; filling the annular trench with an isolation layer; forming a gate oxide layer on the upper surface of the substrate; and After the second doped region is formed and before the upper electrode layer is formed, the method further includes etching the gate oxide layer to expose the central portion of the upper surface of the second doped region.

9. The preparation method according to claim 8, characterized in that, Before filling the isolation layer, the method further includes: implanting ions into the bottom of the annular trench to form a lightly doped P-type region, thereby obtaining a third doped region.

10. The preparation method according to claim 6 or 7, characterized in that, The method for forming the passivation protective layer includes: firstly, forming a passivation protective layer on the upper electrode layer by chemical vapor deposition, and then etching the passivation protective layer to form an opening, thereby exposing a portion of the upper surface of the upper electrode layer.

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