A Merging Optimization Method Based on Extended Factor Instructions

Abstract

The present invention discloses a merging optimization method based on extended factor instructions. For simple accesses to array elements, jumps of pointer addresses, or other similar operations, the two-step operations of multiplication and addition / subtraction can be optimized to be executed as one instruction. In particular, for software programs with mixed operations of arrays and pointers, the present invention realizes iterative merging in the merging optimization pass at the back end of the compiler, optimizing a series of related operations to be executed as one instruction, which can effectively reduce the time overhead and improve the program performance. The present invention takes advantage of the feature that the compiler front end generates intermediate expressions with shift marks according to the data type when calculating array addresses, and pays attention to the correlation between the source and destination registers in the instruction template of the shift operation; combined with the characteristics of the merging optimization pass at the back end of the compiler, for the processor platform, an instruction template with an extended factor is provided and iterative merging is realized, making the instruction generation in related scenarios reach the optimal.

Description

Technical Field

[0001] The present invention relates to a merging optimization method based on extended factor instructions, belonging to the technical field of compiler optimization. Background Art

[0002] Common optimization means of compilers include loop optimization, global optimization, local optimization, and storage optimization, etc. Among them, peephole optimization is a local optimization method. In this optimization process, the compiler only performs instruction conversion in one basic block or multiple basic blocks for the generated code, combining the characteristics of processor instructions, through some conversion rules that are considered likely to bring performance improvement, or overall analysis, so as to improve the performance of the code. Although peephole optimization replaces local code, it may bring great performance improvement. Peephole optimization is usually divided into the following four types: redundant instruction deletion, control flow optimization, strength reduction, and utilization of special instructions. The present invention belongs to the optimization by using special instructions.

[0003] Address calculation is very common in programs, such as accessing array elements and jumping of pointer addresses. The compiler front-end usually decomposes address calculation into two steps for address calculation: one is to use an integer multiple of the variable type length as an offset, that is, to generate an intermediate expression with a shift mark; the other is to subtract or add the offset from the current address to obtain the target address to achieve forward and backward jumps of the address, that is, to generate an intermediate expression with a subtraction or addition mark, and then generate corresponding multiplication operation and addition / subtraction operation instructions through the middle end and the back end.

[0004] Currently, for common address calculations in programs, such as accessing array elements and jumping of pointer addresses, the compiler front-end generates an intermediate expression with a shift mark for multiplication according to the data type, and generates an intermediate expression with an addition / subtraction mark for addition / subtraction. Then, after a series of optimization passes through the middle end and the back end, finally two instructions of left shift and addition / subtraction are generated. This implementation method fails to combine the characteristics of the compiler back-end merging optimization pass and use more efficient instructions of the processor platform for processing. Summary of the Invention

[0005] The purpose of the present invention is to overcome the deficiencies in the prior art and provide a merging optimization method based on extended factor instructions. Combining the characteristics of the compiler back-end merging optimization pass, for the processor platform, an instruction template with an extended factor is provided and iterative merging is implemented, so that the instruction generation in related scenarios reaches the optimal.

[0006] To achieve the above purpose, the present invention is implemented by adopting the following technical solution:

[0007] In the first aspect, the present invention provides a merging optimization method based on extended factor instructions, applicable to a compiler. The method includes:

[0008] Step 1: Identify multi - operation scenarios in the program according to lexical and syntactic analysis, generate intermediate expressions with shift marks, and then execute Step 2;

[0009] Step 2: Check the relevance of the operands of each intermediate expression through the compiler backend's merge and optimization pass. If there are addition / subtraction operations related to the intermediate expressions with shift marks, then execute Step 3. If not, then execute Step 5;

[0010] Step 3: After merging the intermediate expressions with shift marks and addition / subtraction marks generated after the addition / subtraction operations, match the preset instruction templates with expansion factors;

[0011] If an instruction template with an expansion factor is matched, call the instruction merge cost check function to determine whether the time overhead decreases after instruction merging. If it decreases, replace the marks of the intermediate expressions with those with expansion factors, and then execute Step 4. If it increases, split the merged intermediate expressions, and then execute Step 5;

[0012] If an instruction template with an expansion factor is not matched, split the merged intermediate expressions to restore them to the original intermediate expressions, and then execute Step 5;

[0013] Step 4: Through the compiler backend's merge and optimization pass, merge the intermediate expressions whose marks are replaced with those with expansion factors again until there are no more intermediate expressions to merge, and then execute Step 5;

[0014] Step 5: After determining that there are no more intermediate expressions to merge, continue to execute the subsequent optimization passes, and finally output an addition / subtraction instruction with an expansion factor.

[0015] Furthermore, the identifying multi - operation scenarios in the program according to lexical and syntactic analysis includes:

[0016] Identifying array address calculations in the program,

[0017] Or, identifying pointer address jump operations in the program.

[0018] Furthermore, after identifying array address calculations in the program, if accessing from low address to high address, generate intermediate expressions with left - shift and addition marks. If accessing from high address to low address, generate intermediate expressions with left - shift and subtraction marks.

[0019] In a second aspect, the present invention provides a merge and optimization device based on expansion - factor instructions, applicable to a compiler. The device includes:

[0020] An identification module, which is used to identify multi-operation scenarios in a program according to lexical and syntactic analysis, generate an intermediate expression with a shift mark, and send it to the inspection module;

[0021] An inspection module, which checks the relevance of the operands of each intermediate expression through the compiler backend's merging and optimization pass. If there is an addition / subtraction operation related to the intermediate expression with a shift mark, it transfers to the template matching module; if not, it transfers to the subsequent optimization input module;

[0022] A template matching module, which is used to merge the intermediate expressions with shift marks and addition / subtraction marks generated after the addition / subtraction operation, and then match a preset instruction template with an extended factor;

[0023] The matching module includes a replacement unit and a splitting unit, where:

[0024] The replacement unit is used to call an instruction merging cost check function to determine whether the time overhead decreases after instruction merging after matching an instruction template with an extended factor. If it decreases, it replaces the mark of the intermediate expression with the extended factor and transfers to the merging module; if it increases, it splits the merged intermediate expression and restores it to the initial intermediate expression, and then transfers to the subsequent optimization input module;

[0025] The splitting unit is used to split the merged intermediate expression and restore it to the initial intermediate expression after not matching an instruction template with an extended factor, and then transfer to the subsequent optimization input module;

[0026] A merging module, which is used to merge the intermediate expressions with marks replaced by the extended factor again through the compiler backend's merging and optimization pass until there are no more mergeable intermediate expressions, and then transfer to the subsequent optimization input module;

[0027] The subsequent optimization input module, after determining that there are no more mergeable intermediate expressions, continues to execute the subsequent optimization pass and finally outputs an addition / subtraction instruction with an extended factor.

[0028] Further, the identification module includes a first identification unit or a second identification unit, where:

[0029] The first identification unit is used to identify array address calculations in the program;

[0030] The second identification unit is used to identify known address pointer calculations in the program.

[0031] Further, the first identification unit includes a first generation subunit and a second generation subunit, where:

[0032] The first generation subunit is used to identify and generate an intermediate expression with left shift and addition marks when accessing from low address to high address;

[0033] The second generation subunit is configured to, when accessing from a high address to a low address, identify and generate an intermediate expression with left shift and subtraction marks after identification.

[0034] In a third aspect, the present invention provides an electronic device, including a processor and a storage medium;

[0035] The storage medium is used to store instructions;

[0036] The processor is configured to operate according to the instructions to execute the steps of the method according to any one of the foregoing.

[0037] In a fourth aspect, the present invention provides a computer-readable storage medium, on which a computer program is stored, and when the program is executed by a processor, the steps of the method according to any one of the foregoing are implemented.

[0038] Compared with the prior art, the beneficial effects achieved by the present invention:

[0039] The present invention provides a merging and optimization method based on extended factor instructions. For access to simple array elements, pointer address jumps, or other similar operations, the two-step operations of multiplication and addition / subtraction can be optimized to be executed by one instruction. In particular, for software programs with mixed operations of arrays and pointers, the present invention realizes iterative merging in the merging and optimization pass at the back end of the compiler, and optimizes a series of related operations to be executed by one instruction, which can effectively reduce the time overhead and improve the program performance. Description of the Drawings

[0040] Figure 1 is a flowchart of a merging and optimization method based on extended factor instructions provided by an embodiment of the present invention;

[0041] Figure 2 is a schematic diagram of the conversion of an assembly instruction sequence for address access from a low address to a high address provided by an embodiment of the present invention;

[0042] Figure 3 is a schematic diagram of the conversion of an assembly instruction sequence for address access from a high address to a low address provided by an embodiment of the present invention;

[0043] Figure 4 is a schematic diagram of the iteration of the conversion of an assembly instruction sequence provided by an embodiment of the present invention. Detailed Embodiments

[0044] The present invention will be further described below with reference to the drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention, and cannot be used to limit the protection scope of the present invention.

[0045] Embodiment 1

[0046] This embodiment introduces a merging optimization method based on extended factor instructions, which is applicable to compilers. The method includes:

[0047] Step 1: Identify multi-operation scenarios in the program according to lexical and syntactic analysis, generate intermediate expressions with shift marks, and then execute Step 2;

[0048] Step 2: Check the relevance of the operands of each intermediate expression through the merging optimization pass of the compiler backend. If there are addition / subtraction operations related to the intermediate expression with a shift mark, then execute Step 3. If not, then execute Step 5;

[0049] Step 3: After merging the intermediate expressions with shift marks and addition / subtraction marks generated after the addition / subtraction operations, match the preset instruction template with an extended factor;

[0050] If the instruction template with an extended factor is matched, call the instruction merging cost check function to determine whether the time overhead decreases after the instruction merging. If it decreases, replace the mark of the intermediate expression with the extended factor, and then execute Step 4. If it increases, split the merged intermediate expression, and then execute Step 5;

[0051] If the instruction template with an extended factor is not matched, split the merged intermediate expression and restore it to the original intermediate expression, and then execute Step 5;

[0052] Step 4: Through the merging optimization pass of the compiler backend, merge the intermediate expressions with the mark replaced by the extended factor again until there are no mergeable intermediate expressions, and then execute Step 5;

[0053] Step 5: After determining that there are no mergeable intermediate expressions, continue to execute the subsequent optimization passes, and finally output an addition / subtraction instruction with an extended factor.

[0054] As Figure 1 shown, the merging optimization method based on extended factor instructions provided in this embodiment specifically involves the following steps in its application process:

[0055] The compiler front-end identifies multi-operation scenarios in the program according to lexical and syntactic analysis, such as array address calculation, pointer address jump, etc., and generates intermediate expressions with shift marks, including the following two cases:

[0056] Address access is from low address to high address, such as Figure 2 the shown assembly instruction sequence;

[0057] Address access is from high address to low address, such as Figure 3 the shown assembly instruction sequence;

[0058] The compiler generates a corresponding intermediate expression sequence according to the address access method, and then executes step 2;

[0059] When the compiler goes through the back-end merging and optimization pass, it checks the correlation of each intermediate expression operand. If there are addition / subtraction operations related to the intermediate expression with a shift flag, it then executes step 3. If not, it executes step 5;

[0060] After merging the generated intermediate expressions with shift flags and addition / subtraction flags, and matching the instruction templates with expansion factors in the back-end, there are the following two cases:

[0061] If there is an instruction template with an expansion factor, after calling the relevant function to check the change in instruction cost, replace the flag of the intermediate expression with the one with the expansion factor, and then execute step 4;

[0062] If there is no instruction template with an expansion factor, split the merged intermediate expression and restore it to the original intermediate expression, and then execute step 5.

[0063] The compiler back-end merging and optimization pass performs a new round of correlation analysis. For the following assembly instruction sequence, it will be merged again until there are no mergeable intermediate expressions. As Figure 4 shown, then execute step 5;

[0064] After the compiler determines that there are no mergeable intermediate expressions, it continues to execute the subsequent optimization passes and finally outputs an addition / subtraction instruction with an expansion factor.

[0065] In the above technical solution, the instruction template in step 3 is related to the compilation target platform.

[0066] In the above technical solution, the assembly instructions exemplified in steps 1 and 4 are related to the target platform.

[0067] The key points of the present invention are the following two points:

[0068] Taking advantage of the feature that the compiler front-end generates intermediate expressions with shift flags according to the data type when calculating array addresses, etc., in the instruction template of the shift operation, the correlation between the source and destination registers is noted;

[0069] Combining the characteristics of the compiler back-end merging and optimization pass, for the processor platform, an instruction template with an expansion factor is provided and iterative merging is implemented, making the instruction generation in related scenarios optimal.

[0070] Based on the present invention, for access to simple array elements, pointer address jumps, or other similar operations, the two-step operations of multiplication and addition / subtraction can be optimized to be executed as one instruction. In particular, for software programs with mixed array and pointer operations, the present invention realizes iterative merging in the compiler backend merging optimization pass, optimizing a series of related operations to be executed as one instruction, which can effectively reduce the time overhead and improve the program performance.

[0071] Embodiment 2

[0072] This embodiment provides a merging optimization device based on an extended factor instruction, which is applicable to a compiler. The device includes:

[0073] An identification module, configured to identify multi-operation scenarios in a program according to lexical and syntactic analysis, generate an intermediate expression with a shift mark, and send it to the check module;

[0074] A check module, which checks the relevance of the operands of each intermediate expression through the compiler backend merging optimization pass. If there is an addition / subtraction operation related to the intermediate expression with a shift mark, it transfers to the template matching module; if not, it transfers to the subsequent optimization input module;

[0075] A template matching module, configured to merge the intermediate expression with a shift mark and an addition / subtraction mark generated after the addition / subtraction operation, and then match a preset instruction template with an extended factor;

[0076] The matching module includes a replacement unit and a splitting unit, where:

[0077] The replacement unit is configured to, after matching the instruction template with an extended factor, call an instruction merging cost check function to determine whether the time overhead decreases after the instruction merging. If it decreases, replace the mark of the intermediate expression with an extended factor and transfer to the merging module; if it increases, split the merged intermediate expression and restore it to the initial intermediate expression, and transfer to the subsequent optimization input module; where the instruction merging cost check function is the combine_validate_cost function;

[0078] The splitting unit is configured to, after not matching the instruction template with an extended factor, split the merged intermediate expression and restore it to the initial intermediate expression, and transfer to the subsequent optimization input module;

[0079] A merging module, configured to perform re-merging on the intermediate expression with the mark replaced by an extended factor through the compiler backend merging optimization pass until there are no mergeable intermediate expressions, and then transfer to the subsequent optimization input module;

[0080] Subsequently, optimize the input module. After determining that there are no intermediate expressions that can be merged, continue to execute the subsequent optimization passes, and finally output an addition / subtraction instruction with an expansion factor.

[0081] Specifically, the recognition module includes a first recognition unit or a second recognition unit, where:

[0082] The first recognition unit is used to recognize array address calculations in the program;

[0083] The second recognition unit is used to recognize known address pointer calculations in the program.

[0084] Specifically, the first recognition unit includes a first generation subunit and a second generation subunit, where:

[0085] The first generation subunit is used to recognize and generate an intermediate expression with left shift and addition marks when accessing from low address to high address;

[0086] The second generation subunit is used to recognize and generate an intermediate expression with left shift and subtraction marks when accessing from high address to low address.

[0087] Embodiment 3

[0088] This embodiment provides an electronic device, including a processor and a storage medium;

[0089] The storage medium is used to store instructions;

[0090] The processor is used to operate according to the instructions to execute the steps of the method according to any one of Embodiment 1.

[0091] Embodiment 4

[0092] This embodiment provides a computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, it implements the steps of the method according to any one of Embodiment 1.

[0093] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the technical principle of the present invention, several improvements and deformations can be made, and these improvements and deformations should also be regarded as the protection scope of the present invention.

Claims

1. A merging optimization method based on an extended factor instruction, characterized in that, Applicable to a compiler, the method includes: Step 1: Identify multi-operation scenarios in the program according to lexical and syntactic analysis, generate an intermediate expression with a shift mark, and then execute Step 2; Step 2: Check the relevance of each intermediate expression operand through the compiler backend merge optimization pass. If there are addition / subtraction operations related to the intermediate expression with a shift mark, then execute Step 3. If not, then execute Step 5; Step 3: After merging the intermediate expressions with shift marks and addition / subtraction marks generated after the addition / subtraction operations, match the preset instruction template with an extension factor; If the instruction template with an extension factor is matched, call the instruction merge cost check function to determine whether the time overhead decreases after instruction merging. If it decreases, replace the mark of the intermediate expression with the extension factor, and then execute Step 4. If it increases, split the merged intermediate expression, and then execute Step 5; If the instruction template with an extension factor is not matched, split the merged intermediate expression and restore it to the original intermediate expression, and then execute Step 5; Step 4: Through the compiler backend merge optimization pass, merge the intermediate expressions with the mark replaced by the extension factor again until there are no more mergeable intermediate expressions, and then execute Step 5; Step 5: After determining that there are no more mergeable intermediate expressions, continue to execute the subsequent optimization pass, and finally output an addition / subtraction instruction with an extension factor.

2. The merging optimization method based on the extended factor instruction according to claim 1, characterized in that, The identifying multi-operation scenarios in the program according to lexical and syntactic analysis includes: Identifying array address calculations in the program, Or, identifying pointer address jump operations in the program.

3. The merging optimization method based on the extended factor instruction according to claim 2, characterized in that, After identifying array address calculations in the program, if accessing from a low address to a high address, generate an intermediate expression with left shift and addition marks. If accessing from a high address to a low address, generate an intermediate expression with left shift and subtraction marks.

4. A merging and optimizing device based on an extended factor instruction, characterized in that, Applicable to a compiler, the device includes: An identification module for identifying multi-operation scenarios in the program according to lexical and syntactic analysis, generating an intermediate expression with a shift mark, and sending it to the check module; A check module for checking the relevance of each intermediate expression operand through the compiler backend merge optimization pass. If there are addition / subtraction operations related to the intermediate expression with a shift mark, transfer to the template matching module. If not, transfer to the subsequent optimization input module; A template matching module for merging the intermediate expressions with shift marks and addition / subtraction marks generated after the addition / subtraction operations and then matching the preset instruction template with an extension factor; The matching module includes a replacement unit and a splitting unit, where: The replacement unit is used to call the instruction merge cost check function to determine whether the time overhead decreases after instruction merging when the instruction template with an extension factor is matched. If it decreases, replace the mark of the intermediate expression with the extension factor and transfer to the merge module. If it increases, split the merged intermediate expression and restore it to the original intermediate expression, and then transfer to the subsequent optimization input module; The splitting unit is used to split the merged intermediate expression into the initial intermediate expression after failing to match the instruction template with an expansion factor, and transfer it to the subsequent optimization input module; The merging module is used to merge the intermediate expressions with the expansion factor after the marker replacement again through the compiler backend merging optimization pass until there are no more mergeable intermediate expressions, and then transfer it to the subsequent optimization input module; The subsequent optimization input module, after determining that there are no more mergeable intermediate expressions, continues to execute the subsequent optimization pass, and finally outputs an addition / subtraction instruction with an expansion factor.

5. The merging optimization device based on the extended factor instruction according to claim 4, characterized in that The recognition module includes a first recognition unit or a second recognition unit, where: The first recognition unit is used to recognize the array address calculation in the program; The second recognition unit is used to recognize the known address pointer calculation in the program.

6. The merging optimization device based on the extended factor instruction according to claim 5, characterized in that The first recognition unit includes a first generation subunit and a second generation subunit, where: The first generation subunit is used to generate an intermediate expression with left shift and addition markers after recognition when accessing from low address to high address; The second generation subunit is used to generate an intermediate expression with left shift and subtraction markers after recognition when accessing from high address to low address.

7. An electronic device, characterized in that: It includes a processor and a storage medium; The storage medium is used to store instructions; The processor is used to operate according to the instructions to execute the steps of the method according to any one of claims 1 to 3.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by the processor, the steps of the method according to any one of claims 1 to 3 are implemented.

Images