In-memory computing circuit, compensation method thereof, memory device and chip

Abstract

The application discloses an in-memory computing circuit and a compensation method thereof, a storage device and a chip. The in-memory computing circuit comprises: an in-memory computing array comprising a plurality of input ends, a plurality of output ends and a plurality of programmable semiconductor devices arranged in an array; the signal of the input end is an input vector, the signal of the output end is an output vector, and the in-memory computing array is used for performing matrix operation on the input vector to obtain the output vector; and an error compensation module connected with the in-memory computing array and used for performing scaling compensation and / or offset compensation on the output vector. Compared with the prior art, the embodiment of the application realizes compensation on the calculation result of the in-memory computing circuit, and improves the calculation precision.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor integrated circuits, and in particular to an in-memory computing circuit, a compensation method thereof, a storage device and a chip. BACKGROUND

[0002] The in-memory computing circuit is usually integrated in an in-memory computing chip and is widely used in the fields of data mining such as image processing, recommendation systems and data dimension reduction. The in-memory computing circuit is used to implement vector-matrix multiplication operation, which can improve the performance of the chip and reduce the power consumption of the chip. However, in actual application, due to internal or external non-ideal factors such as environment, temperature and noise, the calculation result of the in-memory computing circuit has errors. SUMMARY

[0003] The present application provides an in-memory computing circuit, a compensation method thereof, a storage device and a chip to compensate the calculation result and improve the calculation accuracy of the in-memory computing circuit.

[0004] According to an aspect of the present application, an in-memory computing circuit is provided, comprising:

[0005] an in-memory computing array comprising a plurality of input terminals, a plurality of output terminals and a plurality of programmable semiconductor devices arranged in an array; the signal of the input terminal is an input vector, the signal of the output terminal is an output vector, and the in-memory computing array is used to perform matrix operation on the input vector to obtain the output vector;

[0006] an error compensation module connected with the in-memory computing array and used to perform scaling compensation and / or offset compensation on the output vector.

[0007] Optionally, the error compensation module is connected to the output terminal of the in-memory computing array to implement scaling compensation; and the error compensation module comprises at least one of an analog compensation unit and a digital compensation unit.

[0008] The in-memory computing circuit further comprises an analog-digital conversion module, the analog compensation unit is connected between the output terminal of the in-memory computing array and the input terminal of the analog-digital conversion module, and the digital compensation unit is connected to the output terminal of the analog-digital conversion module.

[0009] Optionally, the analog compensation unit comprises an operational amplifier and a variable element.

[0010] The operational amplifier comprises a first terminal, a second terminal and an output terminal, the first terminal of the operational amplifier serves as the input terminal of the analog compensation unit, the second terminal of the operational amplifier is connected to a bias voltage, the output terminal of the operational amplifier serves as the output terminal of the analog compensation unit, and the variable element is connected between the first terminal and the output terminal of the operational amplifier.

[0011] The resistance of the variable element is adjusted according to a scaling factor.

[0012] Optionally, the variable element includes a transistor or a resistor.

[0013] Optionally, the number of the analog compensation unit is one, and the programmable semiconductor devices in each column share the analog compensation unit;

[0014] Alternatively, there may be multiple analog compensation units, with each column of programmable semiconductor devices connected to one of the analog compensation units.

[0015] Optionally, it further includes a multiplexing circuit; the analog compensation unit is connected between the output of the in-memory computing array and the input of the multiplexing circuit; or, the analog compensation unit is connected between the output of the multiplexing circuit and the input of the analog-to-digital conversion module.

[0016] Optionally, the digital compensation unit includes at least one of a shifter, a multiplier, or an adder.

[0017] Optionally, the error compensation module includes a compensation array for offset compensation; the compensation array is disposed in the in-memory computing array as part of the compensation array.

[0018] Optionally, the in-memory computing array is a gate-coupled in-memory computing array or a source-coupled in-memory computing array.

[0019] According to another aspect of the present invention, a compensation method for an in-memory computing circuit is provided, applied to an in-memory computing circuit as described in any embodiment of the present invention, the compensation method comprising:

[0020] The input vector is applied to the plurality of programmable semiconductor devices;

[0021] Based on the noise-compensation relationship model, find the error amount under the corresponding environmental noise;

[0022] The error compensation module is activated based on the error amount to perform scaling compensation and / or offset compensation on the output vector, thereby obtaining the compensated output vector.

[0023] According to another aspect of the present invention, a storage device is provided, comprising: an in-memory computing circuit as described in any embodiment of the present invention.

[0024] According to another aspect of the present invention, a chip is provided, comprising: an in-memory computing circuit as described in any embodiment of the present invention.

[0025] The error compensation module is arranged, the output vector can be scaled and compensated according to actual needs, the output vector is enlarged or reduced as a whole, and the multiple of the output vector is compensated; and / or the output vector can be offset compensated according to actual needs, and the deviation of the output vector is compensated. In conclusion, the calculation result of the in-memory calculation circuit is compensated, and the calculation precision is improved.

[0026] It should be understood that the matters described in this section are not intended to identify key or important features of the embodiments of the application, and are not used to limit the scope of the application. Other features of the application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the application, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort.

[0028] Figure 1 A schematic diagram of an in-memory calculation circuit provided by an embodiment of the application is shown in the figure.

[0029] Figure 2 A schematic diagram of another in-memory calculation circuit provided by an embodiment of the application is shown in the figure.

[0030] Figure 3 A schematic diagram of another in-memory calculation circuit provided by an embodiment of the application is shown in the figure.

[0031] Figure 4 A schematic diagram of another in-memory calculation circuit provided by an embodiment of the application is shown in the figure.

[0032] Figure 5 A schematic diagram of another in-memory calculation circuit provided by an embodiment of the application is shown in the figure.

[0033] Figure 6 A schematic diagram of another in-memory calculation circuit provided by an embodiment of the application is shown in the figure.

[0034] Figure 7 A schematic diagram of another in-memory calculation circuit provided by an embodiment of the application is shown in the figure.

[0035] Figure 8 A schematic diagram of another in-memory calculation circuit provided by an embodiment of the application is shown in the figure.

[0036] Figure 9 A schematic diagram of another in-memory calculation circuit provided by an embodiment of the application is shown in the figure.

[0037] Figure 10A flowchart of a compensation method of an in-memory computing circuit provided by an embodiment of the present application is shown. DETAILED DESCRIPTION

[0038] In order to make the personnel in the technical field better understand the present application scheme, the technical scheme in the embodiment of the present application will be described clearly and completely below by combining the drawings in the embodiment of the present application. Obviously, the described embodiment is only a part of the embodiment of the present application, not all. Based on the embodiment in the present application, all other embodiments obtained by the person skilled in the art without creative labor should belong to the protection scope of the present application.

[0039] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0040] The embodiment of the present application provides an in-memory computing circuit. Figure 1 A schematic diagram of an in-memory computing circuit provided by an embodiment of the present application is shown. Referring to Figure 1 The in-memory computing circuit comprises an in-memory computing array 1 and an error compensation module 2.

[0041] The in-memory computing array 1 comprises a plurality of input terminals, a plurality of output terminals and a plurality of programmable semiconductor devices arranged in an array; the signal of the input terminal is an input vector, which can be represented by the letter A; the signal of the output terminal is an output vector, which can be represented by the letter Y; the in-memory computing array 1 is used for matrix operation on the input vector A to obtain the output vector Y. Exemplarily, the calculation formula is Y = AW, which realizes the matrix multiplication and addition operation.

[0042] The error compensation module 2 is connected with the in-memory computing array 1 and is used for scaling compensation and / or offset compensation on the output vector. Exemplarily, the error compensation module 2 connected to the output terminal of the in-memory computing array 1 is used to realize the scaling compensation, and the error compensation module 2 connected in the in-memory computing array 1 is used to realize the offset compensation. Specifically, the scaling factor is represented by the letter s, which can perform scaling compensation; the offset is represented by the letter b, which can perform offset compensation; the compensated output vector Y = sAW + b.

[0043] Therefore, the embodiment of the present application can scale and compensate the output vector according to actual needs, so that the output vector becomes larger or smaller as a whole, and the multiple of the output vector is compensated; and / or, the output vector can be offset compensated according to actual needs, and the deviation of the output vector is compensated. In summary, the embodiment of the present application compensates the calculation result of the in-memory calculation circuit, and improves the calculation accuracy.

[0044] Figure 2 Another schematic diagram of an in-memory calculation circuit provided by the embodiment of the present application is shown in FIG. 6. Figure 2 On the basis of the above-mentioned embodiments, optionally, the error compensation module 2 is connected to the output end of the in-memory calculation array 1, so as to realize scaling compensation. The in-memory calculation circuit further comprises an analog-to-digital conversion module 3, abbreviated as ADC, which is connected to the output end of the in-memory calculation array 1, and is used to convert the output vector in analog form into digital form, so as to match the subsequent digital calculation requirements. Based on this, the error compensation module 2 comprises at least one of an analog compensation unit and a digital compensation unit. Figure 2 The error compensation module 2 shown in FIG. 5 is an analog compensation unit 21, and the digital compensation unit is not shown in FIG. 6. Figure 2 The analog compensation unit is connected between the output end of the in-memory calculation array 1 and the input end of the analog-to-digital conversion module 3; and the digital compensation unit is connected to the output end of the analog-to-digital conversion module 3.

[0045] Therefore, the embodiment of the present application can realize analog compensation, and can also realize digital compensation, which can be set according to needs in actual application. The specific implementation modes of the analog compensation unit and the digital compensation unit will be described below, but not as a limitation on the present application.

[0046] Figure 3 Another schematic diagram of an in-memory calculation circuit provided by the embodiment of the present application is shown in FIG. 6. Figure 3 In one embodiment of the present application, optionally, the analog compensation unit 21 comprises an operational amplifier and a variable element. The operational amplifier comprises a first end, a second end and an output end, the first end of the operational amplifier serves as the input end of the analog compensation unit 21, the second end of the operational amplifier is connected to a first bias voltage Vs, and the output end of the operational amplifier serves as the output end of the analog compensation unit 21, and the variable element is connected between the first end and the output end of the operational amplifier. The resistance of the variable element is adjusted according to the scaling factor. Specifically, the first end of the operational amplifier can be a non-inverting input end or an inverting input end, and correspondingly, the second end thereof can be an inverting input end or a non-inverting input end.

[0047] Continuing to refer to FIG. 6, Figure 3In an embodiment of the present application, the variable element comprises a resistor. The resistor is a variable resistor, which can be adjusted according to actual needs, so as to adjust the scaling factor and compensate the output vector.

[0048] Figure 4 Another schematic diagram of the in-memory computing circuit is provided in an embodiment of the present application. Referring to Figure 4 In an embodiment of the present application, the variable element comprises a transistor. The voltage (bias) of each electrode of the transistor is different, and the equivalent resistance is also different. Specifically, the bias of the transistor can be adjusted by adjusting the gate voltage Vg. Therefore, the transistor can be equivalent to a variable resistor, so as to realize the scaling compensation of the output vector.

[0049] Continuing to refer to Figure 3 and Figure 4 In an embodiment of the present application, the number of the analog compensation units 21 is one, and the analog compensation unit 21 is shared by the programmable semiconductor devices in each column. In this way, the output vector can be scaled down or up as a whole, which is suitable for adjusting the system error.

[0050] Continuing to refer to Figure 3 and Figure 4 In an embodiment of the present application, the in-memory computing circuit further comprises a multiplexing circuit 7, and the analog compensation unit 21 is connected between the output end of the multiplexing circuit 7 and the input end of the analog-to-digital conversion module 3. The multiplexing circuit 7 has multiple input ends and one output end, and can output multiple signals at the input ends in time division. In this way, one analog compensation unit 21 can be used to realize the scaling compensation of the entire in-memory computing array 1. In addition, the number of the analog-to-digital conversion modules 3 can be reduced to one, so that the output vectors in each column share the analog-to-digital conversion module 3, thereby reducing the manufacturing cost of the chip.

[0051] Figure 5 Another schematic diagram of the in-memory computing circuit is provided in an embodiment of the present application. Referring to Figure 5 Unlike the above-mentioned embodiments, the number of the analog compensation units 21 is multiple, and each column of programmable semiconductor devices is connected to one analog compensation unit 21. The scaling factors of the analog compensation units 21 can be the same, and the improvement effect is equivalent to the above-mentioned embodiments. In addition, the scaling factors of the analog compensation units 21 can also be different. In this way, the error caused by the manufacturing process of a column can be compensated, so as to further improve the error compensation accuracy of the in-memory computing circuit. In this embodiment, the specific setting mode of the analog compensation unit 21 can refer to the above-mentioned embodiments, which will not be described here.

[0052] Figure 6 Another schematic diagram of the in-memory computing circuit provided by the embodiments of the present application is shown. Referring to Figure 6 Unlike the embodiments shown in Figure 5 , the embodiment further comprises a multiplexing circuit 7; the analog compensation unit 21 is connected between the output of the in-memory computing array 1 and the input of the multiplexing circuit 7. The input of the multiplexing circuit 7 is multiple, the output is one, and the multiplexing circuit 7 can output multiple signals at the input at different times. In this way, the multiple analog-to-digital conversion modules 3 can be reduced to one analog-to-digital conversion module 3, so that the output vectors of each column share the analog-to-digital conversion module 3, thereby reducing the manufacturing cost of the chip.

[0053] Continuing to refer to Figures 1-6 , on the basis of the above embodiments, optionally, the in-memory computing array 1 is a gate-coupled in-memory computing array, and the principle of implementing matrix operation is as follows. The in-memory computing array 1 comprises: M input terminals, M rows by N columns of programmable semiconductor devices, N output terminals (output currents I1-I N ) and N bias voltage terminals.

[0054] The gates of all programmable semiconductor devices in each row are connected to the same input terminal, and the M rows of programmable semiconductor devices are connected to the M input terminals correspondingly. The drains of all programmable semiconductor devices in each column are connected to the same bias voltage terminal, and the N columns of programmable semiconductor devices are connected to the N bias voltage terminals correspondingly. The bias voltage is V b . The sources of all programmable semiconductor devices in each column are connected to the same output terminal, and the N columns of programmable semiconductor devices are connected to the N output terminals correspondingly. The threshold voltage of each programmable semiconductor device is adjustable. N is a positive integer greater than or equal to zero, M is a positive integer greater than or equal to zero, and M and N can be equal or not equal.

[0055] Through the above circuit connection mode, a gate-coupled and source-summed topology structure is formed.

[0056] Among them, by dynamically adjusting the threshold voltage V TH of each programmable semiconductor device in advance according to certain rules, each programmable semiconductor device can be regarded as a variable equivalent analog weight (denoted as W k,j , where 0k

[0057]

[0058] During operation of the circuit, a column of analog voltage signals V1-V MAn analog voltage signal V is applied to the gates of all programmable semiconductor devices in row M, where the gate of each programmable semiconductor device in row K receives an analog voltage signal V. k A bias voltage V is applied to the drain input. b The source outputs current signal I respectively. k,1 ~I k,N According to the characteristics of programmable semiconductor devices, I = V × W. The source output current of each programmable semiconductor device is equal to the gate voltage multiplied by the weight of that programmable semiconductor device, i.e., I0. k,1 =V k W k,1 I k,N =V k W k,N Because the sources of all programmable semiconductor devices in each column are connected to the same output terminal, according to Kirchhoff's laws, the current I at that output terminal is... j The sum of the source currents of all programmable semiconductor devices in this column is... Multiple output terminals output multiple currents and Implement matrix multiplication and addition operations.

[0059] Because an analog compensation unit 21 is provided at the output end of the in-memory computing array 1, this embodiment of the invention can perform scaling compensation on the output signal. Figure 3 and Figure 4 In the middle, the scaling factor is set to The formula for calculating the j-th column in the output vector Y is: Accordingly, multiple output terminals output multiple currents and sums. This achieves overall scaling of the calculation results. Figure 5 and Figure 6 In the text, the scaling factor for each column is set to... Multiple output terminals output multiple currents and sum to This allows for separate scaling of the calculation results for each column.

[0060] See also Figures 1-6 Based on the above embodiments, optionally, the programmable semiconductor device can be implemented using a floating gate transistor. The floating gate transistor includes a substrate, an insulating layer, a gate G, a source S, a drain D, and a floating gate F. The floating gate is disposed between the gate and the insulating layer, and the insulating layer is disposed between the floating gate and the substrate to protect the electrons in the floating gate from leakage. Electrons can be stored in the floating gate. By adjusting the number of electrons in the floating gate, the threshold voltage of the floating gate transistor can be dynamically adjusted. Due to this structural characteristic of the floating gate transistor, it can be regarded as a variable equivalent analog weight to store analog data.

[0061] The floating-gate transistor can be a SONOS type floating-gate transistor, a split-gate floating-gate transistor or a charge-trapping floating-gate transistor, but is not limited thereto, and all the transistors capable of adjusting the threshold voltage of the transistor itself by adjusting the number of electrons in the floating gate fall within the protection scope of the embodiments of the present application.

[0062] With reference to the above embodiments, Figures 2-6 On the basis of the above embodiments, the in-memory computing circuit can further comprise a digital-to-analog conversion module 4, referred to as DAC, connected to the input end of the in-memory computing array 1, for converting the input vector in digital form into analog form to perform matrix operation.

[0063] Optionally, the in-memory computing circuit can further comprise:

[0064] The programming circuit is connected to the source, gate and / or substrate of each programmable semiconductor device in the array of programmable semiconductor devices, and is used to adjust the threshold voltage of the programmable semiconductor device.

[0065] Preferably, the programming circuit comprises a voltage generation circuit and a voltage control circuit, the voltage generation circuit is used to generate a programming voltage or an erasing voltage, and the voltage control circuit is used to load the programming voltage to the source of the selected programmable semiconductor device, or load the erasing voltage to the gate or substrate of the selected programmable semiconductor device, so as to adjust the threshold voltage of the programmable semiconductor device.

[0066] Specifically, the programming circuit uses the hot electron injection effect, applies a high voltage to the source of the programmable semiconductor device according to the threshold voltage requirement data of the programmable semiconductor device, accelerates the channel electrons to a high speed, so as to increase the threshold voltage of the programmable semiconductor device.

[0067] In addition, the programming circuit uses the tunneling effect, applies a high voltage to the gate or substrate of the programmable semiconductor device according to the threshold voltage requirement data of the programmable semiconductor device, so as to reduce the threshold voltage of the programmable semiconductor device.

[0068] With reference to the above embodiments, Figures 2-6 On the basis of the above embodiments, the in-memory computing circuit can further comprise:

[0069] The controller 6 is connected to the programming circuit, adjusts the number of programmable semiconductor devices put into work and the threshold voltage of each programmable semiconductor device by controlling the work of the programming circuit, so as to adapt to the matrix multiplication operation requirement.

[0070] Preferably, the controller 6 comprises a row-column decoder for strobing the programmable semiconductor devices to be programmed.

[0071] Figure 7 A schematic diagram of another in-memory computing circuit is provided in an embodiment of the present application. Referring to Figure 7 On the basis of the above embodiments, the in-memory computing circuit optionally further comprises a conversion device 5 connected to the input end of the in-memory computing array, for converting the plurality of analog current input signals into analog voltage input signals respectively and inputting to the corresponding input end. In the embodiment of the present application, the application of the conversion device 5 is suitable for the scene of converting into current output by the digital-to-analog conversion module.

[0072] Optionally, the conversion device 5 comprises a plurality of programmable semiconductor devices. The gate and the drain of each programmable semiconductor device are connected, and are connected to the input end of the corresponding in-memory computing array. The source of each programmable semiconductor device is connected to a bias voltage. It can be understood that the bias voltage can be a ground voltage, that is, the source is grounded.

[0073] In this embodiment, the gate and the drain of each programmable semiconductor device are connected to receive the analog current input signal.

[0074] Optionally, the programmable semiconductor device in the conversion device 5 can adopt a floating gate transistor.

[0075] It should be noted that in the above embodiments, the topological structure of gate coupling and source summation is taken as an example for description, and is not a limitation of the present application. In other embodiments, the source and the drain of each programmable semiconductor device can be interchanged, or the in-memory computing array 1 can be set as a source-coupled in-memory computing array 1, and the principle of implementing matrix operation is similar, which will not be described in detail.

[0076] Figure 8 A schematic diagram of another in-memory computing circuit is provided in an embodiment of the present application. Referring to Figure 8 On the basis of the above embodiments, the in-memory computing circuit optionally further comprises a conversion device 5 connected to the input end of the in-memory computing array, for converting the plurality of analog current input signals into analog voltage input signals respectively and inputting to the corresponding input end. In the embodiment of the present application, the application of the conversion device 5 is suitable for the scene of converting into current output by the digital-to-analog conversion module.

[0077] Figure 9 A schematic diagram of another in-memory computing circuit is provided in an embodiment of the present application. Referring to Figure 9On the basis of the above-mentioned embodiments, optionally, the error compensation module 2 comprises a compensation array 23 for realizing offset compensation; the compensation array 23 is arranged in the in-memory computing array 1 as a part of the compensation array 23. Wherein, the number of columns of the compensation array 23 is equal to the number of columns of the in-memory computing array 1, and the number of rows of the compensation array 23 is not limited, which can be one row, two rows or multiple rows; the compensation array 23 can be located between any two rows of the in-memory computing array. Optionally, the structure of the programmable semiconductor device in the compensation array 23 is the same as that of the programmable semiconductor device in the in-memory computing array 1, for example, both are the structure of a floating gate transistor.

[0078] Optionally, the controller 6 is further configured to adjust the number of programmable semiconductor devices in the compensation array 23 and the threshold voltage of each programmable semiconductor device to adapt to the matrix multiplication operation requirement.

[0079] Optionally, the gate voltage and drain voltage of the programmable semiconductor device in the compensation array 23 need to be adjusted according to the size of the offset amount to be compensated.

[0080] The principle of realizing offset compensation by the compensation array 23 is that the offset amount of each column is set as (b1, b2, b3, … b N ), and multiple output ends output multiple current sums Thus, the offset compensation of the calculation results of each column is realized.

[0081] It should be noted that the above-mentioned analog compensation unit 21, digital compensation unit and compensation array 23 provided by the embodiments of the present application can be simultaneously arranged in one in-memory computing circuit, or one or two of them can be selected and arranged as needed, which is not limited by the present application. In actual application, each error compensation module 2 can be activated or not activated. Therefore, the embodiments of the present application can compensate the output vector according to actual needs, so that the output vector becomes larger or smaller as a whole, and the multiple of the output vector is compensated; and / or, the output vector can be offset compensated according to actual needs, and the deviation of the output vector is compensated. In summary, the embodiments of the present application realize the compensation of the calculation results of the in-memory computing circuit, and improve the calculation accuracy.

[0082] The embodiments of the present application also provide a compensation method of an in-memory computing circuit, which is applied to the in-memory computing circuit provided by any of the embodiments of the present application. Figure 10 A flowchart of a compensation method of an in-memory computing circuit provided by the embodiments of the present application is provided. Referring to FIG. 6, the compensation method comprises the following steps: Figure 10

[0083] S110, applying an input vector to a plurality of programmable semiconductor devices. ​

[0084] S120, according to the noise-compensation quantity relationship model, searching for the error quantity under the corresponding environmental noise.

[0085] Specifically, the use environment is indoor, suburban or on the road, and the compensation value needs to be different. The noise-compensation quantity relationship model reflects the specific compensation value, and the relationship model can be pre-stored in the controller, which can be in the form of a curve or a table. The relationship model can be obtained through the statistical characteristics of the programmable semiconductor device at real-time temperature or the test data in the early stage.

[0086] S130, according to the error quantity, activating the error compensation module, performing scaling compensation and / or offset compensation on the output vector, and obtaining a compensated output vector.

[0087] The embodiment of the present application can scale the output vector according to actual needs, so that the output vector as a whole becomes larger or smaller, and the multiple of the output vector is compensated. And / or, the output vector can be offset compensated according to actual needs, and the deviation of the output vector is compensated. In summary, the embodiment of the present application realizes compensation of the calculation result of the in-memory calculation circuit, and improves the calculation accuracy.

[0088] The embodiment of the present application also provides a storage device, which can be a flash memory, an electrically erasable programmable read-only memory or a memristor. Preferably, the flash memory is a NOR type flash memory. The storage device includes the in-memory calculation circuit provided by any embodiment of the present application, which has similar technical principles and effects, and will not be repeated here.

[0089] The embodiment of the present application also provides a chip, which can be an AI chip, and the chip includes the in-memory calculation circuit provided by any embodiment of the present application, which has similar technical principles and effects, and will not be repeated here.

[0090] It should be understood that various forms of flow shown above can be used to reorder, add or delete steps. For example, the steps described in the present application can be executed in parallel, sequentially or in different order, as long as the desired results of the technical solutions of the present application can be achieved, which is not limited herein.

[0091] The above specific embodiments do not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent replacement and improvement within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. An in-memory computing circuit, comprising: The in-memory computing circuit comprises: an in-memory computing array comprising a plurality of input terminals, a plurality of output terminals, and a plurality of programmable semiconductor devices arranged in an array; a signal of the input terminal is an input vector, a signal of the output terminal is an output vector, and the in-memory computing array is configured to perform a matrix operation on the input vector to obtain the output vector; an error compensation module connected to the in-memory computing array and configured to perform scaling compensation and offset compensation on the output vector, wherein the error compensation module comprises an analog compensation unit and a digital compensation unit, the analog compensation unit is configured to perform scaling compensation on the output vector, and the digital compensation unit is configured to perform offset compensation on the output vector.

2. The in-memory computing circuit of claim 1, wherein, The in-memory computing circuit further comprises an analog-to-digital conversion module, the analog compensation unit is connected between an output terminal of the in-memory computing array and an input terminal of the analog-to-digital conversion module, and the digital compensation unit is connected to an output terminal of the analog-to-digital conversion module.

3. The in-memory computing circuit of claim 2, wherein, The analog compensation unit comprises an operational amplifier and a variable element. The operational amplifier comprises a first terminal, a second terminal, and an output terminal, the first terminal of the operational amplifier serves as an input terminal of the analog compensation unit, the second terminal of the operational amplifier is connected to a bias voltage, the output terminal of the operational amplifier serves as an output terminal of the analog compensation unit, and the variable element is connected between the first terminal and the output terminal of the operational amplifier. The resistance of the variable element is adjusted according to a scaling factor.

4. The in-memory computing circuit of claim 3, wherein, The variable element comprises a transistor or a resistor.

5. The in-memory computing circuit of claim 2, wherein, One analog compensation unit is shared by a plurality of columns of the programmable semiconductor devices. Alternatively, one analog compensation unit is connected to each column of the programmable semiconductor devices.

6. The in-memory computing circuit of claim 2, wherein, The in-memory computing circuit further comprises a multiplexing circuit, the analog compensation unit is connected between an output terminal of the in-memory computing array and an input terminal of the multiplexing circuit, or the analog compensation unit is connected between an output terminal of the multiplexing circuit and an input terminal of the analog-to-digital conversion module.

7. The computing-in-memory circuit of claim 2, wherein, The digital compensation unit comprises an adder.

8. The in-memory computing circuit of any one of claims 1-7, wherein, The in-memory computing array is a gate-coupled in-memory computing array or a source-coupled in-memory computing array.

9. A compensation method of an in-memory computing circuit, characterized by, The compensation method is applied to the in-memory computing circuit according to any one of claims 1-8, and the compensation method comprises: applying the input vector to the plurality of programmable semiconductor devices; looking up an error amount under the corresponding environmental noise according to a noise-compensation amount relationship model; activating the error compensation module according to the error amount to perform scaling compensation and / or offset compensation on the output vector, to obtain a compensated output vector.

10. A memory device, comprising: The in-memory computing circuit comprises: The in-memory computing circuit according to any one of claims 1-8.

11. A chip, characterized by The in-memory computing circuit comprises: The in-memory computing circuit according to any one of claims 1-8.

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