Overwrite at memory system

Abstract

This application relates to overwriting in a memory system. The memory system can be configured to overwrite portions of a memory array with new data, which can be associated with omitting an erase operation. For example, a write operation can be performed according to a first boundary configuration to store information in a portion of the memory array. A portion of the memory system can then be determined to overwrite that portion of the memory array with different or updated information, which may include performing a write operation according to a second boundary configuration. The second boundary configuration can be associated with different cell characteristics for one or more logical states, such as different distributions of stored charge or other cell properties, different boundary characteristics, different write operations, and other differences, which can support performing an overwrite operation without first performing an erase operation.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 462,228, filed August 31, 2021, entitled “Overwriting at a memory system”, by Parry et al., which is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to overwriting in memory systems. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to one of two supported states, typically corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device into corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR (Non-OR), and NAND (NAND) memory devices. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) can lose their programmed state over time unless periodically updated by an external power supply. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for extended periods even in the absence of an external power supply. Summary of the Invention

[0006] Describe an apparatus. The apparatus may include a memory device having a memory array and a controller coupled to the memory device. The controller may be configured to cause the apparatus to: perform a write operation based on a first voltage boundary between logical states to store first information at a portion of the memory array; determine to overwrite the portion of the memory array with second information; and, based on the determination to overwrite the portion of the memory array, perform a write operation based on a second voltage boundary between the logical states to store the second information at the portion of the memory array.

[0007] Describe a device. The device may include a memory array and a controller coupled to the memory array. The controller may be configured to cause the device to: receive signaling to write first information to a portion of the memory array; determine a first voltage boundary for writing the second information to the portion of the memory array based on the portion of the memory array being written with the second information according to the second voltage boundary for writing a number of logic states; and write the first information to the portion of the memory array according to the determined first voltage boundary for writing the number of logic states.

[0008] Describe an apparatus. The apparatus may include a memory device comprising a memory array and a controller coupled to the memory device. The controller may be configured to cause the apparatus to: receive from a host device a read command to read a portion of the memory array that has been written with a number of logical states; determine whether the portion of the memory array has been written with the number of logical states according to a first voltage boundary between logical states or according to a second voltage boundary between logical states; and transmit signaling for reading the portion of the memory array to the memory device, wherein the signaling includes an indication of the portion of the memory array and an indication of whether the portion of the memory array has been written with the number of logical states according to the first voltage boundary between logical states or according to the second voltage boundary between logical states.

[0009] Describe a device. The device may include a memory array and a controller coupled to the memory array. The controller may be configured to cause the device to: receive from a controller of a memory system a signaling to read information from a portion of the memory array that has been written with a number of logical states; select between a first read voltage boundary and a second read voltage boundary based on whether the portion of the memory array has been written with the number of logical states according to a first voltage boundary or a second voltage boundary between the logical states; and perform a read operation on the portion of the memory array based at least in part on the selected first read voltage boundary or the selected second read voltage boundary. Attached Figure Description

[0010] Figure 1 This document describes an example of a system that supports overwriting at the memory system, based on the examples disclosed herein.

[0011] Figure 2 This document describes an example of a memory device that supports overwriting at a memory system, based on the examples disclosed herein.

[0012] Figure 3 This document describes an example of a memory circuit that supports overwriting at the memory system, based on the examples disclosed herein.

[0013] Figure 4 and 5 This document describes an example of an overwrite scheme that supports overwriting at the memory system, based on the examples disclosed herein.

[0014] Figure 6A and 6B This document describes an instance of a process flow that supports overwriting at a memory system, based on the examples disclosed herein.

[0015] Figure 7 This describes an instance of an overwrite map that supports overwriting at the memory system, based on the examples disclosed herein.

[0016] Figure 8 A block diagram illustrating a memory system that supports overwriting at the memory system based on the examples disclosed herein.

[0017] Figure 9 A block diagram of a memory device supporting overwriting at a memory system according to an example disclosed herein is shown.

[0018] Figures 10 to 13 A flowchart illustrating one or more methods for overwriting at a supporting memory system according to the examples disclosed herein is shown. Detailed Implementation

[0019] A memory system may include one or more memory devices operating according to various memory architectures. A memory device may include an array of memory cells and circuitry operable to perform access operations on the memory cells. In some memory architectures, memory cells of a memory device can be written to store a specific logic state and can be erased before being written to store a different logic state or otherwise storing different information. For example, in a NAND memory architecture, NAND memory cells can be written by storing charge on the floating gate of a transistor. This can affect the threshold voltage used to activate the memory cell, or it can affect the amount of current flowing through the transistor when it is activated. The amount of current can be sensed to detect the logic state stored in the memory cell. In some cases, some portions of data written into the memory array may be temporary (e.g., may become invalid after a certain period of time). In some instances, in order to write a portion of a NAND memory array with different information, the portion of the NAND memory array may first be erased by removing or otherwise changing the amount of charge stored on the floating gate of the transistor in that portion of the NAND memory array. However, in these and other instances, erasing a memory cell or otherwise altering the state of a memory cell (e.g., flipping bits of a logically altered state) can be associated with power consumption, latency, or memory cell degradation or wear and tear, as well as other defects.

[0020] According to the examples disclosed herein, one or more components of a memory system may be configured to overwrite portions of a memory array with new data, which may be associated with omitting erase operations (e.g., according to a "reuse without erasure" configuration). For example, components of the memory system may perform a write operation to store information in a portion of the memory array according to a first boundary (e.g., a first boundary configuration, a first set of write signals associated with a corresponding logical state, and a first set of one or more reference signals for distinguishing the logical states to be written). Following such a write operation, components of the memory system may determine to overwrite said portion of the memory array with different or updated information, which may include performing a write operation according to a second boundary (e.g., a second boundary configuration, a second set of write signals associated with a corresponding logical state, and a second set of one or more reference signals for distinguishing the logical states to be written). In some instances, the second boundary may be associated with different cell characteristics for a given logical state, such as different distributions of stored charge or other cell properties, different boundary characteristics (e.g., different reference voltages), different write operations (e.g., different write voltages, different write currents), and other differences.

[0021] In some implementations, components of the memory system can compare a new state to be stored in a memory cell (e.g., the desired logical state after overwriting) with the current state of the target memory cell to be written (e.g., the logical state associated with previously written information). If the state of the target memory cell does not correspond to the new logical state, the components of the memory system can determine to overwrite the target memory cell with the new state according to an overwrite demarcation configuration. If the state of the target memory cell does correspond to the new logical state, the components of the memory system can determine to prevent the overwrite operation from being performed, which may further reduce power consumption or memory cell fatigue compared to a scenario where an overwrite operation is performed. In some instances, overwrite demarcation configurations associated with an increase in the number of demarcations (e.g., an increase in the number of reference voltages) or an increase in the number of cell characteristic distributions for a corresponding number of logical states can support such techniques.

[0022] In some implementations, the memory system can overwrite the same portion of the memory array multiple times. At each overwrite pass, depending on the new information being written, different portions of valid and invalid data can be overwritten or retained. Components of the memory system can store information related to the overwrite conditions of one or more portions of the memory array, which can be used to identify appropriate read boundaries for the corresponding portions of the memory array, or to assess whether the corresponding portions of the memory array are available for subsequent overwrites (e.g., configured to support overwrite, in conditions supporting another overwrite operation), and for other purposes. Overwrite schemes as disclosed herein can be implemented during garbage collection operations for updating system tables (e.g., logical-to-physical (L2P) tables), for reusing write booster memory blocks, or for several other applications, including those where information storage is relatively transient, or for portions of the memory array (e.g., subarrays, planes, blocks) configured to store or allocate storage for relatively transient information (e.g., information that is likely to change). Based on these and other examples, by overwriting memory cells with write operations that selectively omit one or more aspects of erasing associated memory cells, memory systems can operate with reduced memory degradation, reduced power consumption, or increased array availability (supporting longer operating lifetimes, such as a larger number of total bytes written (TBW), larger program / erase endurance ratings, or other lifetime metrics), or reduced over-provisioning (such as a reduced number of memory cells that can be allocated for memory management, such as garbage collection, or for memory cell retirement), and other benefits.

[0023] As per reference Figures 1 to 3 Features of this disclosure are described in the context of the systems, apparatus, and circuits described herein. (Refer to...) Figure 4-7The features of this disclosure are described in the context of overwrite schemes, process flows, and overwrite mappings. These and other features of this disclosure are further illustrated and described in the context of the device diagrams and flowcharts relating to overwrite at memory systems, as referenced in 8-13.

[0024] Figure 1 This document describes an example of a system 100 that supports overwriting at a memory system, based on the examples disclosed herein. System 100 includes a host system 105 coupled to a memory system 110.

[0025] The memory system 110 may be or include any device or collection of devices, wherein the device or collection of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash memory (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital card (SD card), a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small form factor DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), and other possibilities.

[0026] System 100 may be contained in a computing device such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capability, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or any other computing device containing memory and processing means.

[0027] System 100 may include a host system 105 that can be coupled to a memory system 110. In some instances, this coupling may include an interface to a host system controller 106, which may be an instance of a controller or control component configured to cause the host system 105 to perform various operations as described herein. The host system 105 may include one or more devices, and in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory native to the host system 105 or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 may use the memory system 110, for example, to write data to and read data from the memory system 110. Although Figure 1 The diagram shows a memory system 110, but the host system 105 can be coupled to any number of memory systems 110.

[0028] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., to exchange or otherwise convey control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Dual Data Rate (DDR) interfaces, DIMM interfaces (e.g., DDR-enabled DIMM sockets), Open NAND Flash Interface (ONFI), and Low Power Dual Data Rate (LPDDR) interfaces. In some instances, one or more such interfaces may be contained in or otherwise supported between host system controller 106 of host system 105 and memory system controller 115 of memory system 110. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 included in memory system 110 or via a corresponding physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0029] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, if the memory system 110 contains more than one memory device 130, then the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0030] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a controller, control component, or firmware configured to cause the memory system 110 to perform various operations as described herein. The memory system controller 115 may also be coupled to and communicate with the memory device 130 to perform operations generally referred to as access operations at the memory device 130, such as reading data, writing data, erasing data, or refreshing data, and other such operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute these commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to implement the desired access to the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 may translate responses associated with the memory device 130 (e.g., data packets or other signals) into corresponding signals for the host system 105.

[0031] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection or error correction operations, retirement operations, encryption operations, caching operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0032] The memory system controller 115 may include hardware such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include circuitry with dedicated (e.g., hard-decoded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuitry system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0033] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory capable of storing operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions belonging to the memory system controller 115 herein. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory available for internal storage or computation by the memory system controller 115, for example, internal storage or computation related to the functions belonging to the memory system controller 115 herein. Additionally or alternatively, local memory 120 may be used as a cache for the memory system controller 115. For example, if data is read from or written to memory device 130, then data may be stored in local memory 120, and the data may be available within local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 (e.g., with reduced latency relative to memory device 130) according to a caching strategy.

[0034] Although Figure 1 The memory system 110 described herein has been illustrated as including a memory system controller 115, but in some cases, the memory system 110 may not include a memory system controller 115. For example, the memory system 110 may additionally or alternatively rely on an external controller or firmware (e.g., implemented by the host system 105) or one or more local controllers 135 within the memory device 130 to respectively perform the functions belonging to the memory system controller 115 herein. Generally, one or more functions belonging to the memory system controller 115 herein may, in some cases, be alternatively performed by the host system 105, the local controller 135, or any combination thereof. In some cases, the memory device 130, at least partially managed by the memory system controller 115, may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0035] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Alternatively or additionally, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0036] In some instances, memory device 130 may (e.g., on the same die or within the same package) include a local controller 135, which can perform operations on one or more memory cells of the respective memory device 130. The local controller 135 may operate in conjunction with memory system controller 115, or may perform one or more functions attributed herein to memory system controller 115. For example, such as Figure 1 As described, memory device 130-a may include local controller 135-a, and memory device 130-b may include local controller 135-b.

[0037] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package containing one or more dies 160. In some instances, die 160 may be a block of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, wherein each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0038] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information; if configured to store two bits of information, it may be referred to as a multi-level cell (MLC); if configured to store three bits of information, it may be referred to as a three-level cell (TLC); if configured to store four bits of information, it may be referred to as a four-level cell (QLC), or more generally, a multi-level memory cell. Multi-level memory cells can provide greater storage density compared to SLC memory cells, but in some cases, this may involve narrower read or write tolerances or greater complexity for supporting circuitry.

[0039] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, concurrent operations can be performed within different planes 165. For example, memory cells within different blocks 170 can be operated on in parallel, as long as the different blocks 170 are located in different planes 165. In some cases, individual blocks 170 may be referred to as physical blocks, and virtual blocks 180 may refer to a group of blocks 170 within which parallel operations can occur. For example, blocks 170-a, 170-b, 170-c, and 170-d within planes 165-a, 165-b, 165-c, and 165-d can be operated on in parallel, and blocks 170-a, 170-b, 170-c, and 170-d can be collectively referred to as virtual blocks 180. In some cases, a virtual block may contain blocks 170 from different memory devices 130 (e.g., blocks in one or more planes including memory devices 130-a and 130-b). In some cases, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be “block 0” of plane 165-a, block 170-b may be “block 0” of plane 165-b, etc.). In some cases, parallel operations in different planes 165 may be subject to one or more restrictions, such as parallel operations on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0040] In some cases, block 170 may contain memory cells organized in rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may alternatively be referred to as a bit line) (e.g., coupled thereto).

[0041] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level), but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 may be the smallest unit of memory (e.g., a collection of memory cells) that can be independently programmed or read (e.g., simultaneously programmed or read as part of a single programming or reading operation), and block 170 may be the smallest unit of memory (e.g., a collection of memory cells) that can be independently erased (e.g., simultaneously erased as part of a single erase operation). Furthermore, in some cases, NAND memory cells may be erased before they can be rewritten with new data. Therefore, for example, in some cases, the used page 175 may not be updated until the entire block 170 containing page 175 has been erased.

[0042] In some cases, to update some data within block 170 while retaining other data within block 170, memory device 130 may copy the data to be retained to a new block 170 and write the updated data to one or more remaining pages of the new block 170. Memory device 130 (e.g., local controller 135) or memory system controller 115 may mark or otherwise designate data held in the old block 170 as invalid or obsolete, and update the logical-to-physical (L2P) mapping table so that the logical address (e.g., LBA) of the data is associated with the new valid block 170 rather than the old invalid block 170. In some cases, such copying and remapping may be performed instead of erasing and rewriting the entire old block 170, for example, due to latency or wear and tear considerations. In some cases, one or more copies of the L2P mapping table may be stored within memory cells of memory device 130 (e.g., within one or more blocks 170 or plane 165) for use by local controller 135 or memory system controller 115 (e.g., for reference and updating).

[0043] In some cases, an L2P mapping table can be maintained, and data can be marked as valid or invalid at the page level. Page 175 may contain valid data, invalid data, or no data. Invalid data may be outdated data due to a newer or more recent version of the data being stored in a different page 175 of memory device 130. Invalid data may have previously been programmed into an invalid page 175 but may no longer be associated with a valid logical address (e.g., a logical address referenced by host system 105). Valid data may be the latest version of such data stored on memory device 130. Page 175 that does not contain data may be a page 175 that has never been written to or has been erased.

[0044] In some cases, the memory system controller 115 or the local controller 135 may perform operations on the memory device 130 (e.g., as part of one or more media management algorithms), such as wear leveling, background refresh, garbage collection, erasure, block scan, health monitoring, cell or subarray retirement (e.g., retirement of block 170) or others, or any combination thereof. For example, within the memory device 130, block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. To avoid waiting for all pages 175 of block 170 to have invalid data in order to erase and reuse block 170, an algorithm called "garbage collection" may be invoked to allow block 170 to be erased and freed up as a free block for subsequent write operations. Garbage collection can refer to a set of media management operations, including, for example, selecting a block 170 containing valid and invalid data, selecting a page 175 containing valid data within the block, copying the valid data from the selected page 175 to a new location (e.g., a free page 175 in another block 170), marking the data in the previously selected page 175 as invalid, and erasing the selected block 170. Therefore, the number of erased blocks 170 can be increased, allowing more blocks 170 to be used to store subsequent data (e.g., data subsequently received from the host system 105).

[0045] System 100 may include any number of non-transitory computer-readable media that support overwriting at the memory system. For example, host system 105, memory system controller 115, or memory device 130 (e.g., local controller 135) may include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware) to perform the functions attributed herein to host system 105, memory system controller 115, or memory device 130. For example, such instructions, when executed by host system 105 (e.g., by host system controller 106), memory system controller 115, or memory device 130 (e.g., by local controller 135), may cause host system 105, memory system controller 115, or memory device 130 to perform one or more associated functions as described herein.

[0046] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and associated circuitry combined with a local (e.g., on-die or in-package) controller (e.g., local controller 135). An example of a managed memory system is a managed NAND (MNAND) system.

[0047] According to the examples disclosed herein, one or more components of memory system 110 may be configured to support overwriting portions of a memory array (e.g., memory die 160) with new data, which may be associated with omitting erase operations. For example, components of memory system 110 may perform write operations according to a first boundary configuration to store information at a portion of the memory array. Following such a write operation, components of memory system 110 may determine to overwrite said portion of the memory array with different or updated information, which may include performing write operations according to a second boundary configuration. In some instances, the second boundary configuration may be associated with different cell characteristics for a given logical state, such as different distributions of stored charge or other cell properties, different boundary characteristics, or different write operation configurations, and other differences. By overwriting memory cells with write operations that selectively omit one or more aspects of erasing associated memory cells, memory system 110 or some of its components may operate with reduced memory degradation, reduced power consumption, or increased array availability, and other benefits.

[0048] Figure 2 This describes an example of a memory device 200 that supports overwriting at a memory system, based on the examples disclosed herein. In some cases, the memory device 200 may be a reference. Figure 1 An example of the described memory device 130. Figure 2 This is an illustrative representation of the various components and features of the memory device 200. Therefore, it should be understood that the components and features of the memory device 200 are shown to illustrate functional interrelationships and are not necessarily their actual physical locations within the memory device 200. Furthermore, although... Figure 2 Some of the elements included are labeled with numerical indicators, while other corresponding elements are not labeled, but they are the same or will be understood as similar, in order to increase the visibility and clarity of the depicted features.

[0049] The memory device 200 may include one or more memory cells, such as memory cell 205-a and memory cell 205-b. For example, in an enlarged view of memory cell 205-a, memory cell 205 may be, for example, a flash or other type of NAND memory cell.

[0050] Each memory cell 205 is programmable to store a logic value representing one or more information bits. In some cases, a single memory cell 205 (e.g., SLC memory cell 205) is programmable to one of two supporting states and therefore can store one information bit (e.g., logic 0 or logic 1) at a time. In other cases, a single memory cell 205 (e.g., MLC, TLC, QLC, or other types of multi-level memory cell 205) is programmable to more than one of two supporting states and therefore can store more than one information bit at a time. In some instances, a single MLC memory cell 205 is programmable to one of four supporting states and therefore can store two information bits corresponding to one of four logic values ​​(e.g., logic 00, logic 01, logic 10, or logic 11) at a time. In some instances, a single TLC memory cell 205 is programmable to one of eight supporting states and therefore can store three information bits corresponding to one of eight logic values ​​(e.g., 000, 001, 010, 011, 100, 101, 110, or 111) at a time. In some instances, a single QLC memory cell 205 can be programmed to one of sixteen supported states and thus can store four information bits corresponding to one of sixteen logic values ​​(e.g., 0000, 0001, ..., 1111) at a time.

[0051] In some cases, multilevel memory cells 205 (e.g., MLC memory cells, TLC memory cells, or QLC memory cells) may be physically different from SLC cells. For example, multilevel memory cells 205 may use different cell geometries or may be manufactured using different materials. In some cases, multilevel memory cells 205 may be physically identical or similar to SLC cells, and other circuitry within the memory block (e.g., controllers, sense amplifiers, drivers) may be configured to operate (e.g., read and program) the memory cells as SLC cells, or MLC cells, or TLC cells, etc.

[0052] Different types of memory cells 205 can store information in different ways. In a DRAM memory array, for example, each memory cell 205 may include a capacitor containing a dielectric material (e.g., an insulator) that stores charge representing a programmable state and therefore the information stored. In a FeRAM memory array, as another example, each memory cell 205 may include a capacitor containing a charge or polarized ferroelectric material that stores charge representing a programmable state and therefore the information stored.

[0053] In some NAND memory arrays (e.g., flash arrays), each memory cell 205 may include a transistor with a charge trapping structure (e.g., a floating gate, a replacement gate, or a dielectric material) for storing the amount of charge representing a logic value. For example, Figure 2 The enlarged illustration includes a NAND memory cell 205-a containing a transistor 210 (e.g., a metal-oxide-semiconductor (MOS) transistor) for storing logic values. The transistor 210 has a control gate 215 and may also include a charge trapping structure 220 (e.g., a floating gate or a replacement gate) sandwiched between two portions of a dielectric material 225. The transistor 210 includes a first node 230 (e.g., a source or drain) and a second node 235 (e.g., a drain or source). Logic values ​​can be stored in the transistor 210 by placing (e.g., writing, storing) a certain number of electrons (e.g., a certain amount of charge) onto the charge trapping structure 220. The amount of charge to be stored on the charge trapping structure 220 may depend on the logic value to be stored. The charge stored on the charge trapping structure 220 can affect the threshold voltage of the transistor 210, and consequently affect the amount of current flowing through the transistor 210 when the transistor 210 is activated (e.g., when a voltage is applied to the control gate 215). In some instances, the charge trapping structure 220 may be an example of a floating gate, which may be part of a 3D NAND structure. For example, a 3D NAND may have multiple floating gates arranged around a single channel (e.g., a horizontal or vertical channel). Other structures may also be used in 3D NAND, including the use of replacement gate technology instead of floating gates.

[0054] The logic value stored in the transistor 210 (e.g., as part of a read operation) can be sensed by applying a voltage to the control gate 215 (e.g., applied to the control node 240 via word line 265) to activate the transistor 210 and measuring (e.g., detecting, sensing) the amount of current flowing through the first node 230 or the second node 235 (e.g., via digital line 255). For example, the sensing component 270 can determine whether the SLC memory cell 205 stores logic 0 or logic 1 in a binary manner (e.g., based on the presence or absence of current through the memory cell 205 when the read voltage is applied to the control gate 215, or based on whether the current is above or below a current threshold, such as a threshold current). For the multilevel memory cell 205, the sensing component 270 can determine the logic value stored in the memory cell 205 based on various intermediate threshold levels (e.g., threshold current levels) when a read voltage is applied to the control gate 215, or based on evaluating the presence or absence of current through the memory cell at various intermediate threshold levels (e.g., multiple different values ​​of the read or reference voltage applied to the control gate 215, which may be applied sequentially). In one example of a multilevel architecture, the sensing component 270 can determine the logic value of the TLC memory cell 205 based on seven different thresholds or ranges (e.g., seven different current levels, or current ranges) of cell characteristics, separating eight potential logic values ​​that can be stored by the TLC memory cell 205.

[0055] The SLC memory cell 205 can be written by applying one of two voltages (e.g., a voltage above a threshold or boundary, and a voltage below a threshold or boundary) to the memory cell 205 to store or not store charge on the charge trapping structure 220, thereby causing the memory cell 205 to store one of two possible logic values. For example, when a first voltage is applied to the control node 240 relative to the bulk node 245 of transistor 210 (e.g., via word line 265) (e.g., when the control node 240 is at a higher voltage than the bulk node), electrons can tunnel into the charge trapping structure 220. In some cases, the bulk node 245 may be alternatively referred to as the body node. Injecting electrons into the charge trapping structure 220 may be referred to as the programmable memory cell 205 and may be performed as part of a programming operation. The programmable memory cell may be considered as storing logic 0 in some cases. When a second voltage is applied to the control node 240 relative to the body node 245 of transistor 210 (e.g., via word line 265) (e.g., when the control node 240 is at a lower voltage compared to the body node 245), electrons can leave the charge trapping structure 220. Removing electrons from the charge trapping structure 220 can be referred to as erasing memory cell 205 and can occur as part of an erase operation. An erased memory cell can be considered as storing logic 1 in some cases. In some cases, memory cell 205 can be attributed to memory cells 205 of page 175 sharing a common word line 265 and being programmed at the page 175 granularity, and memory cell 205 can be attributed to memory cells 205 of a block sharing a common biased body node 245 and being erased at the block 170 granularity.

[0056] Writing to a multilevel (e.g., MLC, TLC, or QLC) memory cell 205, compared to writing to an SLC memory cell 205, may involve applying different voltages to the memory cell 205 (e.g., to its control node 240 or body node 245) at a finer granular level to more precisely control the amount of charge stored on the charge trapping structure 220, thereby enabling the representation of larger sets of logic values. Therefore, multilevel memory cells 205 can provide greater storage density than SLC memory cells 205, but in some cases, may involve narrower read or write tolerances or greater complexity for supporting circuitry systems.

[0057] The charge-trapping NAND memory cell 205 may operate in a similar manner to the floating-gate NAND memory cell 205, but instead of storing charge on the charge-trapping structure 220, the charge-trapping NAND memory cell 205 may store charges representing logic states in the dielectric material below the control gate 215. Therefore, the charge-trapping NAND memory cell 205 may or may not include the charge-trapping structure 220.

[0058] In some instances, each row of memory cells 205 may be connected to a corresponding word line 265, and each column of memory cells 205 may be connected to a corresponding digital line 255. Therefore, a memory cell 205 may be located at the intersection of word line 265 and digital line 255. This intersection may be referred to as the address of memory cell 205. Digital lines 255 may be alternatively referred to as bit lines. In some cases, word lines 265 and digital lines 255 may be substantially perpendicular to each other and may create a memory cell array 205. In some cases, word lines 265 and digital lines 255 may generally be referred to as access lines or select lines.

[0059] In some cases, memory device 200 may include a three-dimensional (3D) memory array, wherein multiple two-dimensional (2D) memory arrays may be formed one on top of the other. This can increase the number of memory cells 205 that can be placed or fabricated on a single die or substrate compared to a 2D array, thereby reducing manufacturing costs, or improving the performance of the memory array, or both. Figure 2 In some instances, memory device 200 includes multiple levels (e.g., stacks) of memory cells 205. In some instances, the levels may be separated by an electrically insulating material. Each level may be aligned or positioned such that the memory cells 205 can be aligned with each other across each level (e.g., precisely aligned, overlapping, or substantially aligned), thereby forming a memory cell stack 275. In some cases, the memory cell stack 275 may be referred to as a memory cell string 205 (e.g., reference '...'). Figure 3 (As described).

[0060] Access to memory cell 205 can be controlled via row decoder 260 and column decoder 250. For example, row decoder 260 may receive a row address from memory controller 285 (e.g., an instance of local controller 135) and activate the appropriate word line 265 based on the received row address. Similarly, column decoder 250 may receive a column address from memory controller 285 and activate the appropriate digital line 255. Thus, a memory cell 205 can be accessed by activating one word line 265 and one digital line 255.

[0061] Following access, memory cell 205 can be read or sensed via sensing component 270. For example, sensing component 270 can be configured to determine the stored logic value of memory cell 205 based on signals generated by accessing memory cell 205. The signals may include current, voltage, or both, and the current and voltage on the digital line 255 of memory cell 205 may depend on the stored logic value of memory cell 205. Sensing component 270 may include individual transistors or amplifiers configured to detect and amplify signals (e.g., current or voltage) on digital line 255. The logic value of memory cell 205 detected by sensing component 270 can be output via input / output component 280. In some cases, sensing component 270 may be part of column decoder 250 or row decoder 260, or sensing component 270 may otherwise be connected to or electronically communicate with column decoder 250 or row decoder 260.

[0062] Memory cell 205 can be programmed or written by activating the associated word line 265 and the digital line 255 to enable logical values ​​(e.g., information representing one or more bits) to be stored in memory cell 205. Column decoder 250 or row decoder 260 can accept data, for example, from input / output component 280 to write to memory cell 205. As previously discussed, in the case of NAND memory (e.g., flash memory used in some NAND and 3D NAND memory devices), memory cell 205 can be written by storing electrons in a charge trapping structure or an insulating layer.

[0063] The memory controller 285 can control the operation (e.g., read, write, rewrite, refresh) of the memory cell 205 through various components, such as row decoder 260, column decoder 250, and sensing component 270. In some cases, one or more of the row decoder 260, column decoder 250, and sensing component 270 may be located in the same position as the memory controller 285. The memory controller 285 can generate row address signals and column address signals to activate the desired word line 265 and digital line 255. In some instances, the memory controller 285 can generate and control various voltages or currents used during the operation of the memory device 200.

[0064] According to the examples disclosed herein, one or more components of memory device 200 may be configured to support overwriting memory cell 205 with new data, which can be performed without performing an erase operation on memory cell 205. For example, memory cell 205 may be programmed and read according to a first boundary configuration and other cell operation characteristics associated with the first boundary configuration, which may be associated with a first set of write voltages associated with a corresponding logic state, or a first set of one or more reference voltages used to distinguish the corresponding logic state. Following such operations, memory cell 205 may be overwritten according to a second boundary configuration and other cell operation characteristics associated with the second boundary configuration, which may be associated with a second set of write voltages associated with a corresponding logic state, or a second set of one or more reference voltages used to distinguish the corresponding logic state. In some instances, the second boundary configuration may be associated with different cell characteristics for a given logic state, such as different distributions of stored charge or other cell properties, different boundary characteristics (e.g., different reference voltages), different write operations (e.g., different write voltages, different write currents), and other differences relative to the first boundary configuration. By overwriting memory cells 205 with write operations that selectively omit erasing one or more aspects of the associated memory cells 205, memory device 200 can operate with reduced degradation, reduced power consumption, or increased array availability, as well as other benefits.

[0065] Figure 3 This describes an example of a memory circuit 300 that supports overwriting at a memory system, based on the examples disclosed herein. The memory circuit 300 may be an example of a part of a memory device, such as memory device 130 or memory device 200. Although Figure 3 Some of the elements included are marked with reference numerals, while other corresponding elements are not marked, but they are the same or will be understood to be similar, in order to increase the visibility and clarity of the depicted features.

[0066] Memory circuitry 300 includes a plurality of memory cells 305 connected in a NAND configuration (e.g., reference 305). Figure 2 The described flash memory cell 305). In a NAND memory configuration, multiple flash memory cells 305 may be connected in series to form a string 310 of memory cells 305, wherein the drain of each flash memory cell 305 in the string 310 may be coupled to the source of another flash memory cell 305 in the string.

[0067] String 310 may be a set of memory cells 305, each associated (e.g., coupled) with a corresponding digital line 315. Each memory cell 305 in string 310 may be associated with a separate word line 330 (e.g., one of word lines 330-a, 330-i, 330-n), such that the number of word lines 330 may be equal to the number of memory cells 305 in string 310. For example, as Figure 3 The string 310 shown can be used as a reference. Figure 2 An example of an aspect of the described memory cell stack 275.

[0068] Page 355 may be a set of memory cells 305 each associated (e.g., coupled) with a corresponding word line 330. Therefore, string 310 may contain memory cells 305 from multiple different pages 355, and page 355 may contain memory cells 305 from multiple different strings 310. For example, such as Figure 3 Page 355 shown here may be used as a reference. Figure 1 Examples of aspects described on page 175.

[0069] Block 360 can be a set of multiple pages 355 and therefore can also contain multiple strings 310. For example, such as Figure 3 Block 360 shown can be used as a reference. Figure 1 An instance of an aspect of the described block 170.

[0070] In some cases, NAND memory cell 305 may be programmed (e.g., set to logic 0) and read at the page 355 granularity level, but may not be erasable at the page granularity level (e.g., reset to logic 1). For example, NAND memory may actually be erasable at a higher granularity level, such as at the block 360 granularity level. In some cases, NAND memory cell 305 may need to be erased before it becomes reprogrammable. Different memory devices may have different read, write, or erase characteristics.

[0071] In some cases, each string 310 of memory cells 305 in memory circuit 300 may be coupled at one end of string 310 to a corresponding string select transistor (SST) 320 and at the other end of string 310 to a corresponding ground select transistor (GST) 325. The gate of each SST 320 may be coupled to a string select line 345, which may be common to all SSTs 320 of block 360. The gate of each GST 325 may be coupled to a ground select line 340, which may be common to all GSTs 325 of block 360. The source of each GST 325 of block 360 may be coupled to a common source line 350. And the drain of each SST 320 may be coupled to a corresponding digital line 315, which is specific to the individual string 310.

[0072] SST 320 can be used to selectively couple the corresponding string 310 of memory cell 305 to digital line 315, and thus to the gate of SST 320, based on applying a voltage to string select line 345. Similarly, GST 325 can be used to selectively couple the corresponding string 310 of memory cell 305 to source line 350, and thus to the gate of GST 325, based on applying a voltage to ground select line 340.

[0073] To operate memory circuitry 300 (e.g., to perform programming, reading, or erasing operations on one or more memory cells 305 of block 360), various voltages can be applied to serial select line 345 (e.g., applied to the gate of SST 320), to one or more digital lines 315 (e.g., applied to the drain of one or more SST 320), to one or more word lines 330, to ground select line 340 (e.g., applied to the gate of GST 325), to source line 350 (e.g., applied to the source of GST 325), or to the body of memory cell 305 (not shown) of block 360. In some cases, each memory cell 305 of block 360 may have a common body whose voltage can be controlled independently of the bodies of other blocks 360.

[0074] In some cases, as part of a read operation for memory cell 305, a positive voltage can be applied to the corresponding digital line 315 when the source line 350 can be grounded or otherwise biased at a voltage lower than that applied to the digital line 315. In parallel, voltages higher than the threshold voltages of SST 320 and GST 325 for memory cell 305 can be applied to string select line 345 and ground select line 340, thereby “turning on” SST 320 and GST 325, so that the channel associated with the string 310 containing memory cell 305 can be electrically connected to the corresponding digital line 315 and source line 350. The channel can be an electrical path that can conduct current under certain operating conditions through the memory cell 305 in the string 310 (e.g., through the source and drain of the transistors in the memory cell 305 of the string 310).

[0075] In parallel, multiple word lines 330 of block 360 (e.g., in some cases, all word lines 330) (except for selected word lines 330 coupled to the memory cell 305 to be read) can be set to a voltage (e.g., VREAD) higher than the threshold voltage (VT) of the memory cell 305. VREAD can cause all memory cells 305 in the unselected page 355 (e.g., row) to be "on," such that each unselected memory cell 305 in the string 310 can maintain high conductivity within the channel. In some instances, the word line 330 associated with the memory cell 305 to be read can be set to a boundary voltage VTarget. In the case that the memory cell 305 operates as an SLC memory cell, VTarget can be the voltage between the VT of the memory cell 305 in (i) an erased state and the VT of the memory cell 305 in a programmed state.

[0076] When the memory cell 305 to be read exhibits an erased VT (e.g., VTarget > VT of memory cell 305), memory cell 305 can be "turned on" in response to VTarget applied to the selected word line 330, which allows current to flow in the channel of string 310, and thus from digital line 315 to source line 350. When the memory cell 305 to be read exhibits a programmed VT (e.g., VTarget < VT of selected memory cell), memory cell 305 can remain "turned off" even if VTarget is applied to the selected word line 330, thus preventing current from flowing in the channel of string 310, and thus preventing current from flowing from digital line 315 to source line 350.

[0077] Sensible (e.g., via reference) Figure 2 The described sensing component 270) provides a signal (e.g., a current amount below or above a threshold or other boundary) on the digital line 315 of the memory cell 305, and this signal indicates whether the memory cell 305 becomes conductive or remains non-conductive in response to VTarget applied to the selected word line 330. The sensed signal can therefore indicate whether the memory cell 305 is in an erased state (e.g., storing logic 1) or a programmed state (e.g., storing logic 0). In some cases, a single read operation can read the selected page 355 based on the corresponding signal associated with the corresponding digital line 315 of the memory cell 305 of a page 355, because the memory cells 305 of the page 355 may all share a common word line 330.

[0078] Although the above example read operation has been explained in the context of SLC memory cell 305 for clarity, those skilled in the art will understand how the technique can be extended or modified and applied to the context of multi-level memory cell 305 (e.g., by using multiple delimiters, such as multiple values ​​of VTarget, corresponding to different amounts of charge that can be stored in a multi-level memory cell 305).

[0079] In some cases, as part of the programming operation of memory cell 305, charge can be added to a portion of memory cell 305 such that when memory cell 305 is read later, the current flowing through memory cell 305 and therefore through the corresponding string 310 can be prevented. For example, charge can be injected into such... Figure 2 The charge trapping structure 220 shown in memory cell 205-a. In some cases, a corresponding voltage can be applied to the word line 330 and the body of the memory cell 305 to be programmed, such that the control gate 215 of the memory cell 305 is at a higher voltage than the body of the memory cell 305 (e.g., a positive voltage can be applied to the word line 330). In parallel, a voltage higher than the threshold voltages of the SST 320 and GST 325 of the memory cell 305 can be applied to the serial select line 345 and the ground select line 340, thereby “turning on” the SST 320 and GST 325, and the digital line 315 of the memory cell 305 to be programmed can be set to a relatively high voltage. This can generate an electric field that draws electrons from the source of the memory cell 305 toward the drain. Through a process that can be referred to in some cases as tunneling injection, the electric field can also cause some of these electrons to be drawn through the dielectric material 225 and injected into the charge trapping structure 220 of the memory cell 205. In some cases, programming memory cell 305 may correspond to writing logic 0 into memory cell 305.

[0080] In some cases, a single programming operation can program some or all of the memory cells 305 in page 355 because the memory cells 305 of page 355 can all share a common word line 330 and a common body. For memory cells 305 of page 355 that are not intended to be written to (e.g., memory cells 305 are not intended to be programmed), the corresponding digital line 315 can be set to a relatively low voltage (e.g., ground), which can prevent electron injection into the charge trap structure 220.

[0081] Although the programming operations of the example above have been explained in the context of SLC memory cell 305 for clarity, those skilled in the art will understand how the technique can be extended and applied to the context of multilevel memory cell 305 (e.g., by using multiple programming voltages applied to word line 330, or multiple passes or pulses of programming voltage applied to word line 330, corresponding to different amounts of charge that can be stored in a multilevel memory cell 305).

[0082] In some cases, as part of the erase operation of memory cell 305, charge may be removed from a portion of memory cell 305 such that when memory cell 305 is read later, the current flowing through memory cell 305 and therefore through the corresponding string 310 may not be prevented (e.g., at least to a greater extent allowed). For example, it may be from such Figure 2 The charge trapping structure 220 shown in memory cell 205-a removes charge. In some cases, a corresponding voltage can be applied to the word line 330 and the body of the memory cell 305 to be erased, such that the control gate 215 of the memory cell 305 is at a lower voltage than the body of the memory cell 305 (e.g., a positive voltage can be applied to the body). This can generate an electric field that draws electrons out of the charge trapping structure 220 and into the body of the memory cell 305. In some cases, a single programming operation can erase all memory cells 305 in block 360 because the memory cells 305 in block 360 can all share a common body.

[0083] In some cases, the electron injection and removal processes associated with programming and erasing operations can induce stress on memory cell 305 (e.g., on dielectric material 225). Over time, in some cases, such stress can cause one or more aspects of memory cell 305 (e.g., dielectric material 225) to degrade. For example, charge trapping structure 220 may become unable to retain stored charge. Such degradation can be an example of a wear mechanism of memory cell 305, and for this or other reasons, some memory cells 305 may support a limited number of programming and erasing cycles. In some instances, memory device 130 may include an over-allocation of memory cells (e.g., a number of memory cells exceeding the stated capacity of the memory device), which can support the retirement of memory cells 305 that have experienced wear conditions or are performing inadequately or unreliably, thereby extending the operational lifetime of memory device 130 by avoiding operation of retired memory cells 305.

[0084] According to the examples disclosed herein, one or more components of memory circuitry 300 may be configured to support overwriting memory cell 305 with new data, which can be performed without performing an erase operation on memory cell 305. For example, memory cell 305 may be programmed and read according to a first boundary configuration and aspects thereof, the first boundary configuration being associated with a first set of cell characteristics related to a corresponding logic state, or a first set of one or more reference voltages used to distinguish the corresponding logic states. Following such operations, memory cell 305 may be overwritten according to a second boundary configuration and aspects thereof different from the first boundary configuration, the second boundary configuration being associated with a second set of cell characteristics related to a corresponding logic state, or a second set of one or more boundaries used to distinguish the corresponding logic states.

[0085] By overwriting memory cells 205 with write operations that selectively omit one or more aspects of erasing associated memory cells 205, memory device 200 can operate with reduced degradation, reduced power consumption, increased array availability, and other benefits. For example, a given memory cell 205 can support being programmed multiple times before an erase operation is performed on the memory cell 205, which reduces the number of erase operations performed for the total amount of information written over the lifetime of the memory cell 205. Furthermore, in some instances, each successive overwrite configuration can be associated with progressively higher write signaling (e.g., progressively higher write voltage, progressively higher write current), such that some write operations in the overwrite configuration can store information using write signaling that imposes less programming stress on the memory cell 205 compared to the initial write configuration associated with the highest configuration write signaling (e.g., a write configuration that does not support overwrite configuration). Thus, by accumulating less stress from programming and erasing operations, memory cell 205 can support writing a larger amount of information, or support a longer operational lifetime by reducing the degree of degradation or fatigue of the memory cell.

[0086] Figure 4 This document describes an example of an overwrite scheme 400 supporting overwrite at a memory system, based on the examples disclosed herein. Overwrite scheme 400 may include boundary configurations 401-a (e.g., an initial write configuration), boundary configurations 401-b (e.g., a first overwrite configuration), and boundary configurations 401-c (e.g., a second overwrite configuration), each of which may include a logical state distribution set 415 and a boundary 410 relative to cell characteristics 420. Overwrite scheme 400 may be derived from references... Figure 1 , 2The memory system 110 described in section 3 may be implemented using one or more components. For example, one or more components of the memory system 110 may operate at least a portion of the memory die 160 (e.g., one or more memory cells 205 or 305) according to a demarcation configuration 401-a for initial programming and read operations, determine to overwrite a portion of the memory die 160 (e.g., without performing an erase operation), and subsequently operate a portion of the memory die 160 according to a demarcation configuration 401-b or demarcation configuration 401-c.

[0087] Each of the boundary configurations 401 may be described relative to cell characteristic 420, which may be associated with the physical characteristics of the memory cell itself, or with physical characteristics associated with operation (e.g., reading, writing) of the memory cell. In some instances, cell characteristic 420 may represent voltage or charge, such as voltage or charge written to or stored by the memory cell, activation threshold voltage (e.g., VT) of the memory cell, or voltage or charge generated by reading the memory cell. In some instances, cell characteristic 420 may represent resistance or current, such as detected resistance or current associated with reading the memory cell.

[0088] Each of the boundary configurations 401 may be associated with a set of logic state distributions 415, each of which may correspond to a distribution of values ​​of cell characteristics 420 associated with the corresponding logic state. For example, in boundary configuration 401-a, logic state distribution 415-a-1 may correspond to a range of values ​​of cell characteristics 420 associated with logic 1, and logic state distribution 415-a-2 may correspond to a range of values ​​of cell characteristics 420 associated with logic 0 (and vice versa). In some instances, logic state distributions 415 may represent different logic states associated with a group of memory cells of memory die 160. For example, a given logic state distribution 415 may describe the distribution of voltage or current associated with a group of memory cells when programmed with logic states corresponding to the given logic state distribution. In an example of overwrite scheme 400, each of the boundary configurations 401 includes two logic state distributions 415, which may correspond to operations based on two logic states. However, other instances of the demarcation configuration 401 may be associated with different numbers of logical state distributions 415 (e.g., to support overwrite implementations in more than two logical states, for example, in a multi-level cell overwrite configuration).

[0089] Each of the logic state distributions 415 can be associated with a corresponding write operation configuration (e.g., a corresponding write voltage or write current) for programming a memory cell in the corresponding logic state. For example, in the boundary configuration 401-a, a memory cell can be programmed (e.g., to write logic 1) by applying a first write voltage or write current according to logic state distribution 415-a-1, and a memory cell can be programmed (e.g., to write logic 0) by applying a second write voltage or write current having a value different from the first write voltage or write current (e.g., a higher value, a lower value) according to logic state distribution 415-a-1. In various instances, such techniques can be supported by a single corresponding write signal or multiple corresponding write signals (e.g., with different configurations, such as different magnitudes or timings) associated with each of the logic state distributions 415.

[0090] Each of the boundary configurations 401 may also be associated with a boundary 410, which may specify a value that supports the differentiation of cell characteristics 420 for logic state distributions 415 (e.g., a boundary between logic states, supporting evaluation or differentiation between one logic state and another). For example, boundary 410 may specify a read boundary, such as a reference voltage (e.g., a reference voltage applied to control gate 215 to evaluate the presence or absence of current through the memory cell, such as VTarget, a reference voltage compared to a sensed voltage when reading the memory cell), a reference current, or a reference resistor used to evaluate whether the memory cell is programmed with cell characteristics 420 associated with logic 1 or logic 0 or is storing cell characteristics 420 associated with logic 1 or logic 0. In an example of overwrite scheme 400, each of the boundary configurations 401 includes a single boundary 410 for differentiating two corresponding logic state distributions 415 associated with two logic states. However, other instances of the boundary configuration 401 may be associated with different numbers of boundaries 410 to support additional evaluations between two or more logical states, or between two or more logical state distributions 415.

[0091] An example of overwrite scheme 400 illustrates the process of a demarcation configuration 401 that can be implemented by a memory system 110 supporting overwrite techniques according to the examples disclosed herein. For example, demarcation configuration 401-a can illustrate an initial demarcation configuration associated with the initial programming of memory cells that have been erased or have not previously been programmed. According to demarcation configuration 401-a, at least a portion of the memory cells of the memory array can be programmed by applying a first write signal (e.g., write voltage, write current) associated with a first logic state (e.g., logic 1) of the memory cells included in logic state distribution 415-a-1, or by applying a second write signal associated with a second logic state (e.g., logic 0) of the memory cells included in logic state distribution 415-a-2. Following this type of programming, in order to evaluate whether a given memory cell has been programmed to have a first logic state or a second logic state, the memory system 110 may support performing a read operation based on a boundary 410-a (e.g., evaluating whether the value of the cell characteristic 420 associated with the memory cell being read is below the boundary 410-a, which indicates logic 1, or above the boundary 410-a, which indicates logic 0).

[0092] In various embodiments, a portion of the memory system 110 (e.g., the controller of the memory system) may determine which memory cells are being or have been operated according to a boundary configuration 401-a, which may include switching to operate such memory cells according to a boundary configuration 401-b (e.g., a first overwrite boundary configuration). According to the boundary configuration 401-b, the memory cells may be programmed by applying a first write signal (e.g., write voltage, write current) associated with a first logic state (e.g., logic 1) of the memory cells included in the logic state distribution 415-b-1, or by applying a second write signal associated with a second logic state (e.g., logic 0) of the memory cells included in the logic state distribution 415-b-2. Following this type of programming, in order to evaluate whether a given memory cell has been programmed with a first logic state or a second logic state, the memory system 110 may support performing a read operation according to boundary 410-b (e.g., evaluating whether the value of cell characteristic 420 associated with the memory cell being read is below boundary 410-b, which may indicate logic 1, or above boundary 410-b, which may indicate logic 0). Therefore, a memory cell being operated on according to boundary configuration 401-b may be configured as an SLC memory cell (e.g., programmed or configured according to a single boundary 410, programmed according to one of two possible logic states), and its logic state may be read via a single-level read operation (e.g., a read operation associated with a single reference voltage or a single reference current). However, in an example of boundary configuration 401-b, the range of values ​​of cell characteristic 420 associated with the corresponding logic state distribution 415-b and the value of cell characteristic 420 at boundary 410-b may be shifted along the axis of cell characteristic 420 (e.g., to a higher magnitude).

[0093] In some implementations, memory cell overwriting according to boundary configuration 401-b can support writing (e.g., overwriting) information to previously written portions of the memory array without the need for an intermediate erase operation. For example, because logical state distribution 415-b-2 is associated with a range of values ​​of cell characteristics that do not overlap with logical state distributions 415-a-1 or 415-a-2, logical state distribution 415-b-2 can be distinguishable from those values ​​of cell characteristic 420 associated with logical state distributions 415-a-1 and 415-a-2 (e.g., according to boundary 410-b). In NAND memory architecture, for example, such techniques can be supported when overwriting a boundary configuration 401 (e.g., each of two or more logic state distributions 415 of boundary configurations 401-b and 401-c) has a cell characteristic 420 that is greater than or equal to the corresponding range of the logic state distribution 415 or the previous boundary configuration (e.g., those ranges not lower than the previous boundary configuration 401 (e.g., boundary configuration 401-a)).

[0094] In some implementations, a write signal with a magnitude greater than that associated with logic state distribution 415-b-2 (e.g., higher voltage, higher current) can support such a transition. In various instances, logic state distribution 415-b-1 may have a range value of cell characteristic 420 that is the same as, partially overlaps with, or is at least partially greater than or equal to (e.g., not less than) the range value of logic state distribution 415-a-2. For example, a write signal associated with logic state distribution 415-b-1 may have a magnitude equal to or greater than that of the write signal associated with logic state distribution 415-a-2. Therefore, in some instances, there may not be a memory cell being written according to the range value of cell characteristic 420 previously associated with logic state distribution 415-a-1 of boundary configuration 401-a associated with boundary configuration 401-b.

[0095] In some instances, operation according to certain boundary configurations 401 (e.g., boundary configuration 401-a) may involve relatively lower programming stress compared to other boundary configurations (e.g., boundary configurations 401-b or 401-c), which may be related to the relatively low magnitude of write signaling associated with such boundary configurations 401. Therefore, examples of overwrite scheme 400 can illustrate instances of operating a portion of the memory array in an SLC overwrite mode with reduced tolerances (e.g., compared to the tolerances associated with logic state distributions 415-a-1 corresponding to one logic state and logic state distributions 415-b-2 corresponding to another logic state), which can reduce memory cell fatigue. By supporting data written at lower programming stress in some boundary configurations before reaching the highest configuration programming stress level (e.g., associated with boundary configuration 401-c), the memory cell can support a relatively high amount of new information written before reaching the highest configuration programming stress and the subsequent erase operation (e.g., according to the sequence of boundary configurations 401-a, 401-b, and 401-c), which can support a higher TBW rating for the associated memory device.

[0096] The assignment of logic states to logic state distributions 415-b-1 and 415-b-2 can be configured according to various techniques, including assignments that may relate to the assignments of logic states in boundary configuration 401-a. For example, in a configuration that maintains positioning relative to boundary 410, logic state distributions 415 smaller than boundary 410 may be associated with one logic state (e.g., logic state distributions 415-a-1 and 415-b-1 are each associated with logic 1), and logic state distributions 415 larger than boundary 410 may be associated with another logic state (e.g., logic state distributions 415-a-2 and 415-b-2 are associated with logic 0). In another instance, in a configuration that maintains the range of logical states for cell characteristic 420 (e.g., where logical state distributions 415-a-2 and 415-b-1 generally extend together, or extend together within a threshold), logical state distributions 415-a-2 and 415-b-1 may each be associated with logic 0, and logical state distributions 415-a-1 and 415-b-1 may each be associated with logic 1. In some instances, the memory system may support dynamic selection of such assignments, such as selection from one boundary configuration 401 to another boundary configuration 401, minimizing the number of memory cells written under relatively high write signaling, or minimizing the number of memory cells written under normal circumstances, and other criteria, which may be evaluated at the page level, block level, or plane level, and other granularities.

[0097] In some instances, by maintaining a single boundary 410 for each boundary configuration 401, the overwrite scheme 400 can support overwriting with relatively faster or less complex sensing schemes or circuit systems. For example, the overwrite scheme 400 can support the same or similar read bandwidth as other SLC configurations, including SLC configurations or other techniques for single-level read operations that may not be configured to support overwrite techniques.

[0098] Memory system 110 may support any number of one or more overwrite demarcation configurations 401 according to an instance of overwrite scheme 400. For example, in a configuration supporting a second overwrite demarcation configuration, a portion of memory system 110 may determine which memory cells are being overwritten or have been operated according to demarcation configuration 401-b, which may include operating such memory cells according to demarcation configuration 401-c. According to demarcation configuration 401-c, memory cells may be programmed by applying a first write signal associated with a first logic state (e.g., logic 1) of a memory cell included in logic state distribution 415-c-1, or by applying a second write signal associated with a second logic state (e.g., logic 0) of a memory cell included in logic state distribution 415-c-2. Following this type of programming, in order to assess whether a given memory cell has been programmed in a first or second logical state, the memory system 110 may support performing a read operation based on a boundary 410-c (e.g., assessing whether the value of the cell characteristic 420 of the memory cell being read is below the boundary 410-c, which indicates logic 1, or above the boundary 410-c, which indicates logic 0). In some cases, the memory system 110 may utilize a check for failed byte traces for each consecutive write (e.g., to ensure the accuracy of access operations after consecutive overwrites).

[0099] In some instances, the duration of consecutive overwrites to memory cells (e.g., programming operations according to boundary configurations 401-b and 401-c) can be increased. For example, increasing the write semaphore value could involve a longer duration for reaching a higher voltage, or a higher stored charge, or a longer duration for a physical change in the memory cell being invoked, and other phenomena. Therefore, the configuration duration for performing programming operations can be increased for different boundary configurations 401, or otherwise changed.

[0100] In some instances, the difference in cell characteristics 420 between boundaries 410 of one boundary configuration 401 and another, or the difference in the highest logic state distribution 415 from one boundary configuration 401 to another, can be considered a step (e.g., a voltage step). In some cases, such steps can be configured to be relatively small, which may be associated with avoiding exceeding thresholds (e.g., voltage thresholds) related to writing data to memory cells. Furthermore, by implementing small steps between consecutive boundary configurations 401, the memory system 110 can support a larger number of boundary configurations 401 (e.g., a larger number of overwrites) without exceeding such thresholds.

[0101] In some instances, portions of the memory that support overwrite scheme 400, etc., may be configured to operate according to the overwrite scheme and another multi-level cell configuration. For example, a portion of the memory array that supports operation according to four logic state distributions 415 and such logic state distributions 415 may be associated (e.g., statically, dynamically) with an MLC configuration in which each of the four logic state distributions 415 can store one of four logic states (e.g., logic 00, logic 01, logic 10, or logic 11) at a given time, or in which for each boundary configuration 401, two logic state distributions 415 may be used to support operation in an SLC overwrite configuration that supports logic 0 and logic 1. For example, in the context of the logic state distribution 415 of the overwrite scheme 400, MLC configuration may be supported when logic state distribution 415-a corresponds to logic 00, logic state distributions 415-a-2 and 415-b-1 correspond to logic 01, logic state distributions 415-b-2 and 415-c-1 correspond to logic 10, and logic state distribution 415-c-2 corresponds to logic 11, and other associations. In some such instances, boundaries 410-a, 410-b, and 410-c may be associated with multi-level read operations or circuitry that support MLC operation, and in some instances, such operations or circuitry may operate with reduced power consumption or increased read bandwidth when operating in an overwrite scheme (e.g., an SLC overwrite scheme, associated with the use of a single boundary 410 at a time).

[0102] In some instances, the memory system 110 may consider such conditions when determining how to configure or operate such portions of the memory device 130. For example, the memory system 110 may determine to operate in MLC mode for relatively high capacity, for information less likely to be replaced, for information or operating conditions where read bandwidth is relatively less important, or for conditions where stress associated with programming and erasing operations is relatively less important. In some instances, the memory system 110 may determine to operate in SLC overwrite mode or other overwrite modes for information more likely to be replaced (e.g., L2P tables, write booster buffers, parity data), for information or operating conditions where read bandwidth is relatively more important, or for conditions where stress associated with programming and erasing operations is relatively more important. In some instances, the memory system 110 may make such determinations dynamically (e.g., based on current operating conditions), or the memory system 110 may configure certain portions of the memory device 130 to operate in MLC mode, while certain other portions of the memory device 130 or another memory device 130 operates in overwrite mode. Although described in the context of four logical state distributions 415 and with trade-offs between MLC mode and SLC demarcation configuration 401, such techniques can be applied to various implementations of any number of logical state distributions 415 and multi-level write configurations (e.g., TLC write configuration, QLC write configuration) and overwrite configurations (e.g., SLC overwrite configuration, multi-level overwrite configuration).

[0103] In some cases, access operation signaling (e.g., read operation signaling or write operation signaling, command signaling between memory system controller 115 and memory device 130) may indicate a boundary configuration 401, or a boundary 410 (e.g., an indication of a reference voltage). For example, command signaling may instruct memory device 130 to write logical state to a memory cell, or to read logical state from a memory cell, according to a specific boundary configuration 401 or boundary 410. In some instances, boundary configuration 401 may be managed by memory device 130 (e.g., by local controller 135), in which case access operation signaling may ignore the boundary indication. For example, memory device 130 (e.g., local controller 135) may determine to overwrite a portion of memory with new information, which may be associated with a transition from one boundary configuration 401 to another boundary configuration 401 (e.g., determined at the memory device).

[0104] In some cases, components of memory system 110 (e.g., memory system controller 115, local controller 135) may track the number of overwrites, or a boundary configuration 401 or its boundary 410, to determine which boundary configuration 401 to use in future overwrites. For example, multiple patterns (e.g., A / B / C patterns) for read offsets may be stored in each portion (e.g., per block, per page) of the memory array in components of memory system 110. In some cases, firmware at memory system 110 may track read offsets stored in the system. Overwrite scheme 400 may enable memory device 130 to save a number of erase cycles (e.g., memory device 130 may not erase or perform garbage collection to write new data to the cells), or may reduce single-level cell program-erase cycle requirements, and other benefits.

[0105] Figure 5 This document describes an example of an overwrite scheme 500 that supports overwriting at a memory system, based on the examples disclosed herein. Overwrite scheme 500 may include an erased state 505, wherein in some cases, an erased memory cell may be considered as storing logic 1 (e.g., associated with cell characteristic 420-a within logic state distribution 415-d). Overwrite scheme 500 may also include demarcation configurations 401-d (e.g., initial write configuration), 401-e (e.g., first overwrite configuration), and 401-f (e.g., second overwrite configuration). Overwrite scheme 500 may be derived from references... Figure 1 , 2 The memory system 110 described in 3 is implemented using one or more components.

[0106] In an example of overwrite scheme 500, each of the boundary configurations 401 may be described in relation to cell feature 420-a, which may be a reference Figure 4 Examples of the described cell characteristic 420. Each of the boundary configurations 401 may also be associated with a corresponding logical state distribution set 415, each of which may correspond to a distribution of values ​​of cell characteristic 420-a associated with a corresponding logical state, and each of the corresponding logical state distribution sets 415 may be associated with a corresponding write operation configuration for programming a memory cell in the corresponding logical state. Each of the boundary configurations 401 may also be associated with one or more boundaries 410, which may indicate the support of cell characteristic 420-a to distinguish the values ​​of logical state distributions 415.

[0107] The example of overwrite scheme 500 illustrates another process of the demarcation configuration 401 that can be implemented by memory system 110 to support the overwrite technique according to the examples disclosed herein. For example, when performing an overwrite operation, the transition between one demarcation configuration 401 and another demarcation configuration 401 may involve one or more save operations 510 on memory cells of a portion of the memory array (e.g., saving the value of cell characteristic 420-a, saving the logical state), one or more flip operations 515 on memory cells of a portion of the memory array (e.g., changing the value of cell characteristic 420-a, flipping the logical state), or various combinations thereof. In some instances, such transitions may involve evaluating the stored state of a given memory cell (e.g., logical state, value of cell characteristic 420-a) to determine whether to perform a save operation 510 or a flip operation 515. For example, for each memory cell in the portion of the memory being overwritten, the memory system 110 (e.g., memory device 130, local controller 135) can evaluate whether to preserve the logical state or cell characteristic 420-a stored at the memory cell, or to change the logical state of the cell characteristic 420-a stored at the memory cell. In various instances, such operations can be performed on portions of the memory array marked as storing invalid data, and such operations can subsequently mark said portions of the memory array as storing valid data regardless of whether a write signal is applied.

[0108] In some instances, for the portion of the memory array associated with erased state 505, all memory cells may initially be associated with logic state distribution 415-d, which may be associated with logic 1 (e.g., a first logic state). To program memory cells according to boundary configuration 401-d, memory device 130 may perform a save operation 510-a to establish a memory cell as storing logic 1 (e.g., a first logic state), or perform a toggle operation 515-a to establish a memory cell as storing logic 0 (e.g., a second logic state). In some instances, save operation 510-a may be associated with applying a first write signal (e.g., a write voltage or write current associated with save operation 510-a or logic state distribution 415-e-1, a refresh signal), and toggle operation 515-a may be associated with applying a second write signal (e.g., a write voltage or write current associated with toggle operation 515-a or logic state distribution 415-e-2). In some instances, the save operation 510-a may be associated with applying an empty or zero bias voltage to the memory cell, or with preventing the application of a write signal to the memory cell, thereby maintaining the cell characteristic 420-a or the logic state already programmed into the memory cell.

[0109] In some instances, the transition from erased state 505 to demarcation configuration 401-d can be performed without evaluating the memory cell for the stored logical state or cell characteristics 420-a (e.g., before performing save operation 510-a or flip operation 515-a), for example, when an indication that a portion of the memory array has been erased is associated with a memory cell being in a known state. In other words, the determination of whether to perform save operation 510-a or flip operation 515-a on a target memory cell can be based on the logical state to which data will be written and can be independent of the current state of the target memory cell. After performing save operation 510-a or flip operation 515-a on a corresponding memory cell of a portion of the memory array, said portion of the memory array can store data according to demarcation configuration 401-d. To evaluate whether a given memory cell has been programmed with logic 1 or logic 0, memory system 110 may support read operations based on boundary 410-d (e.g., evaluating whether the value of cell characteristic 420-a is below boundary 410-d, which indicates logic 1, or above boundary 410-d, which indicates logic 0).

[0110] In various embodiments, a portion of the memory system 110 may determine the portion of the memory array that has been operated according to boundary configuration 401-d, which may include operating such memory cells according to boundary configuration 401-e (e.g., a first overwrite boundary configuration). In some instances, the evaluation of the memory cells may support the overwrite transition from boundary configuration 401-d to boundary configuration 401-e to determine whether to perform a save operation 510 or a flip operation 515.

[0111] For example, to establish a memory cell as storing logic 1, the memory cell can first be evaluated during a read or other sensing operation to determine the current logic state or value of the cell characteristic 420-a. If the memory cell is associated with a logic state or value of cell characteristic 420-a corresponding to logic state distribution 415-e-1, then a save operation 510-b can be performed so that the value of cell characteristic 420-a associated with the written memory cell is within logic state distribution 415-f-1. The save operation 510-b can be associated with applying a first write signal or with preventing the application of a write signal to the memory cell. If the memory cell is associated with a logic state or value of cell characteristic 420-a corresponding to logic state distribution 415-e-2, then a toggle operation 515-c can be performed so that the value of cell characteristic 420-a associated with the written memory cell is within logic state distribution 415-f-3, indicating that a second logic state distribution 415 (e.g., multiple logic state distributions 415) corresponds to logic 1. The toggle operation 515-c may be associated with the application of a third write signal (e.g., a write voltage or write current associated with the toggle operation 515-c or logic state distribution 415-f-3), which may have a higher magnitude than both the first and second write signals.

[0112] In some instances, to establish a memory cell as stored logic 0, the memory cell may first be evaluated during a read or other sensing operation to determine the current logic state or value of cell characteristic 420-a. If the memory cell is associated with a logic state or value of cell characteristic 420-a corresponding to logic state distribution 415-e-1, then a toggle operation 515-b may be performed so that the value of cell characteristic 420-a associated with the written memory cell is within logic state distribution 415-f-2. In some embodiments, the toggle operation 515-b may be associated with applying a second write signal, for example, when logic state distributions 415-e-2 and 415-f-2 extend substantially together or extend within a threshold. If the memory cell is associated with a logic state or value of cell characteristic 420-a corresponding to logic state distribution 415-e-2, then a save operation 510-c may be performed so that the value of cell characteristic 420-a associated with the written memory cell is within logic state distribution 415-f-2. The toggle operation 515-c can also be associated with applying a second write signal, or with preventing the application of a write signal to a memory cell. In some instances, because the logic state distribution 415-f-2 can be associated with the second write signal and is independent of the previous state of the memory cell, the operation of programming logic 0 in the overwrite transition to the demarcation configuration 401-e can be performed without evaluating the memory cell to be written.

[0113] After performing a save operation 510-b or 510-c or a toggle operation 515-b or 515-c, a portion of the memory array may store data according to boundary configuration 401-e. To evaluate whether a given memory cell has been programmed with logic 1 or logic 0, the memory system 110 may support read operations according to boundaries 410-e-1 and 410-e-2, which represent instances of increasing the number of boundaries 410 (e.g., two boundaries 410) for a given number of logic states (e.g., two logic states). In some instances, each boundary 410-e may be associated with a corresponding read operation (e.g., multiple single-level reads, e.g., when boundary 410-e indicates a reference voltage applied to control gate 215). If the memory system 110 determines (e.g., in a read evaluation) that the value of cell characteristic 420-a of a memory cell is below boundary 410-e-1, then the memory system 110 may determine that the memory cell is within logic state distribution 415-f-1 (e.g., associated with logic state 1). If memory system 110 determines that the value of cell characteristic 420-a of a memory cell is higher than boundary 410-e-1, then a read evaluation based on boundary 410-e-2 can support a logic state evaluation. If memory system 110 determines that the value of cell characteristic 420-a of a memory cell is lower than boundary 410-e-2, then memory system 110 can determine that the memory cell is within logic state distribution 415-f-2 (e.g., associated with logic state 0), and if memory system 110 determines that the value of cell characteristic 420-a of a memory cell is higher than boundary 410-e-2, then memory system 110 can determine that the memory cell is within logic state distribution 415-f-3 (e.g., associated with logic state 1). Although described in the context of different operations, in some instances, boundaries 410-e-1 and 410-e-2 may be associated with a hierarchy of multi-level read operations or sensing circuitry systems.

[0114] Memory system 110 can support any number of one or more overwrite boundary configurations 401 according to an instance of overwrite scheme 500. For example, in a configuration supporting a second overwrite boundary configuration, a portion of memory system 110 can determine to overwrite portions of the memory array that have been operated according to boundary configuration 401-e, which may include operations on portions of the memory array according to boundary configuration 401-f. As illustrated, various save operations 510 and flip operations 515 can support transitions from boundary configuration 401-e to boundary configuration 401-f, which can be supported by evaluation of memory cells prior to such operations according to the instances disclosed herein. After performing such operations, portions of the memory array can store data according to boundary configuration 401-f. To evaluate whether a given memory cell has been programmed with logic 1 or logic 0, memory system 110 can support read operations according to boundaries 410-f-1, 410-f-2, and 410-f-3, which can be performed using various single-level or multi-level techniques.

[0115] Another instance of writing (e.g., overwriting) information to a previously written portion of memory according to the memory cell overwrite instructions of overwrite scheme 500 without the need for an intermediate erase operation. For example, to support a transition from one boundary configuration 401 to another boundary configuration 401 in overwrite scheme 500, memory device 130 may determine whether to overwrite the memory cell by flipping operation 515 or to save the previously written state by save operation 510. In some instances, such operations according to overwrite scheme 500 can reduce the number of write signals applied to the memory cell, or reduce the magnitude of the write signals written to the memory cell, which can reduce the power consumption or degradation of the memory cell, and other advantages. While such techniques may be associated with relatively slower read bandwidth compared to overwrite schemes (e.g., those related to multi-level read implementations in boundary configurations 401-e and 401-f), the reduction in the incidence and magnitude of write operations can be associated with improvements in memory device cycle fatigue, cell degradation, and overall operational lifetime (e.g., larger TBW, higher programming / erasing endurance).

[0116] While the example of overwrite scheme 500 illustrates a technique in which logical states are maintained within a corresponding range of cell characteristic 420-a, in some instances, logical states corresponding to a corresponding range of cell characteristic 420-a can be flipped through successive overwrites. In some instances, such logical state assignments can be determined based on a comparison of the proportion of cells that can be maintained in a given state, such as save operation 510 and flip operation 515, which would result in one logical state assignment compared to another logical state assignment. Furthermore, similar to the example of overwrite scheme 400, each of the logical state distributions 415 of overwrite scheme 500 may be associated with or otherwise configured with another multilevel cell mode (e.g., MLC, TLC, or QLC mode), and the memory system 110 or memory device 130 may be configured to operate according to one or more aspects of overwrite scheme 500 depending on various factors or operating conditions.

[0117] In some implementations, memory system 110 may be configured to support aspects of both overwrite scheme 400 and overwrite scheme 500, and memory system 110 may be configured to operate based on performance trade-offs between memory device 130 or portions thereof (e.g., one portion of the memory array versus another). In some instances, aspects of overwrite scheme 400 may be selected for relatively low latency associated with a single or consistent number of boundaries 410 for each boundary configuration 401. In some instances, aspects of overwrite scheme 500 may be selected for relatively low power consumption or relatively low fatigue or degradation associated with the possibility of omitting write operations, or for performing relatively low-value write operations, regardless of relatively more complex read operations. In some instances, each portion of the memory array may be configured by enabling or disabling overwrite techniques, or by a specific overwrite scheme or configuration thereof, which may correspond to the type of implementation of a given memory device 130, or the priority or other characteristics of the information stored at memory device 130, such characteristics being adaptable to various granularities of such configurations. In some instances, such techniques can be determined or configured for specific types of information, or for the physical allocation associated with specific types of information (e.g., L2P tables, parity information, or other relatively transient data). In some instances, such techniques can be associated with "in-situ" garbage collection, which avoids the erase operations associated with this type of garbage collection. In some instances, such determination can be based on associated firmware complexity, the relative tendency of read interference, the associated raw bit error rate (RBER), read bandwidth or latency or booster buffer availability, and other considerations.

[0118] Figure 6A This describes an example of a process flow 600 that supports overwriting at the memory system, based on the examples disclosed herein. Process flow 600 can be found in references... Figure 1-3 The described memory system 110 is implemented by one or more components. For example, aspects of process flow 600 may be executed by or between the memory system controller 115-a and the memory device 130-c.

[0119] At 625, the memory system (e.g., memory device 130-c) can perform a write operation to store first information at a portion of the memory array (e.g., memory device 130-c). The write operation can be performed according to a first boundary (e.g., a first voltage boundary, a first boundary configuration 401). In some instances, the write operation at 625 can be performed according to an initial boundary configuration 401 or a subsequent overwrite boundary configuration 401. The writing of the first information can be associated with a first write signaling or set of values ​​(e.g., voltage, current, resistance) of the cell characteristic 420 associated with the logic state of the write. The write at 625 can be associated with the number of logic states (e.g., two logic states in SLC operating mode), and in some instances, the number of logic states may be less than the total number of operable logic states for a portion of the memory array (e.g., which may be operable in MLC mode, TLC mode, or QLC mode, etc.). The write operation of 625 may be in response to a write command received from host system 105, or may be associated with memory management operations (such as wear leveling or garbage collection, and other instances). In various instances, the execution of the write operation of 625 may be associated with an indication of the number of overwrites performed at a portion of the memory array stored in memory system controller 115-a or memory device 130-c, or with an indication of writing a portion of the memory array according to a specific demarcation configuration 401 or its demarcation 410. In some instances (e.g., when the write operation of 625 is performed in response to signaling from memory system controller 115-a), the write operation of 625 may be an instance of memory system controller 115-a performing a write operation or at least a portion thereof according to overwrite demarcation configuration 401. In some instances, such write operations may be performed on a portion of memory allocated by an overwrite scheme (e.g., overwrite scheme 400 or 500), or the memory system controller 115-a or memory device 130-c may determine at 625 to perform a write operation in a manner that supports a subsequent overwrite, which may be based on the type of information, or the conditions under which the operation or execution is to be performed (e.g., write bandwidth, read bandwidth, degraded configuration), and other considerations.

[0120] At 630, in some instances, the memory system (e.g., memory system controller 115-a) may determine to overwrite a portion of the memory array. In some instances, this overwrite determination may be based on a validity indication associated with a portion of the memory array (e.g., an indication that data stored in a portion of the memory array is invalid or no longer needed). In some instances, the determination to overwrite a portion of the memory array may be associated with the type of information stored in or to be written to a portion of the memory array, or with a configuration associated with a portion of the array itself (e.g., an indication that overwriting is enabled for a portion of the memory array). For example, if a portion of the memory array is associated with relatively transient data (e.g., write boost information, parity information, L2P address information), then the memory system controller 115-a may determine to overwrite information already stored in a portion of the memory array but not yet erased (e.g., rather than a portion that is not erased and is written to the memory array with relatively non-transient data). In some instances, the memory system controller 115-a may determine that a portion of the memory array is available for overwriting (e.g., has an available demarcation configuration 401). In some instances, such as when a determination is made at memory device 130-c (e.g., in response to receiving a write operation signaling) whether to overwrite a portion of the memory array, the operation at 630 may be omitted.

[0121] At 635, the memory system controller 115-a may transmit a write operation signal (e.g., a signal to write second information to a portion of the memory array of memory device 130-c) to memory device 130-c. The write operation signal at 635 may be associated with overwriting with the second information according to the second demarcation configuration 401. Therefore, writing the second information may be associated with a second write signal or set of values ​​(e.g., voltage, current, resistance) of the cell characteristic 420 associated with the logical state of the write. In some instances, the write operation signal at 635 may include the second information and an indication of a write to a portion of the memory (e.g., logical address, physical address). In some cases (e.g., when memory system controller 115-a manages the overwrite status of addresses for memory device 130-a), the write operation signaling of 635 may indicate the amount of overwrite associated with (e.g., performed on) delimited configuration 401, or its delimited configuration 410, or a portion of the memory array. This amount may be prefixed (e.g., as a prefix, algorithm-qualifying prefix, of the write operation signaling associated with the write configuration for writing second information). The write operation signaling of 635 may respond to a write command received from host system 105, or may be associated with memory management operations (e.g., wear leveling or garbage collection) manageable by memory system controller 115-a, and other instances. In some instances, the issuance of the write operation signaling of 635 may be an instance of memory system controller 115-a performing a write operation or at least a portion thereof according to overwrite delimited configuration 401.

[0122] In some instances, at 640, memory device 130-c may determine a boundary for writing the second information (e.g., a voltage boundary, boundary 410, boundary configuration 401, second boundary). In some instances, the determined boundary may be associated with the same number of logic states as the logic states for writing the first information (e.g., maintaining SLC operation or some other multi-level cell operation), but may be associated with different write semaphore values, different number of boundaries 410, and other differences. In some cases, memory device 130-c may determine the boundary for writing the second information based on the indication of the write operation signaling at 635. In some instances, memory device 130-c may determine the boundary for writing the second information based on an indication such as an overwrite state stored at memory device 130-c or an indication of the number of overwrites performed on a portion of the memory array.

[0123] At 645, memory device 130-c can perform a write operation to store second information (e.g., based on write operation signaling at 635), which can be performed according to a boundary determined by memory device 130-c at 640. The write operation performed at 645 can be associated with a boundary configuration 401 different from the write operation performed at 625. For example, the boundary configuration 401 associated with the write operation at 645 can have different write signaling, such as different voltages or currents for writing a given logic state, or can correspond to different numbers of write signals for a given logic state. In some instances, the write operation at 645 can be associated with a boundary 410 having different values ​​of cell characteristic 420 (e.g., different reference voltages) to distinguish one logic state from another, or a different number of logic state distributions 415 or boundaries 410. However, in some instances, the write operation at 645 and the write operation at 625 can be associated with a write based on the same number of logic states (e.g., the same number of two or more possible logic states). In some instances, the write operation at 645 can be performed without performing an erase operation after the write operation at 625. In some cases, after performing the second write operation, the memory device 130-c may store an indication of the portion of the memory that has been written according to the second demarcation.

[0124] In some instances, the write operation of 645 may be associated with (e.g., according to one or more aspects of overwrite scheme 500) a state assessment stored at the corresponding memory cell. For example, the write operation of 645 may include determining a logical state to be stored at the memory cell and determining whether the state stored at the memory cell corresponds to the logical state to be stored at the memory cell. In some instances, such techniques may include performing a read or other sensing operation on the memory cell at one or more reference voltages or other thresholds that are the same as or different from those used in a typical read operation, and determining whether the logical state associated with performing the read operation corresponds to the logical state to be stored at the memory cell. In some instances, such determination may be used to select a save operation 510 or a flip operation 515, and other options. In various instances, such techniques may include updating validity indications (e.g., identifying portions of the memory array as having valid data) regardless of whether a write signal is applied to individual memory cells, and may be associated with a boundary 410 or logical state distribution 415 that is different from the number of boundary configurations 401 associated with writing the first information at 625.

[0125] Figure 6B This describes an example of a process flow 650 that supports reading a portion of memory at a memory system, based on the examples disclosed herein. Process flow 650 can be found in references... Figure 1-3The described memory system 110 is implemented by one or more components. For example, aspects of process flow 650 may be executed by or between the memory system controller 115-b and the memory device 130-d. In some cases, process flow 650 may be implemented to read previously overwritten portions of the memory, including references... Figure 4 , 5 And the examples described in 6A.

[0126] At 655, in some instances, the memory system controller 115-b may receive a read command (e.g., from host system 105, from host system controller 106). In some cases, the memory system controller 115-b may determine the read location based on the indication in the read command. The read command may be associated with a command to read a portion of the memory array of memory device 130-d that may have been written according to the number of logical states (e.g., two logical states, such as logical 0 or logical 1, or more than two logical states, such as in an MLC configuration). In some instances, the memory system controller 115-b may not receive a read command but may determine another condition for a read from memory device 130-d, such as performing memory management operations (e.g., garbage collection, wear leveling, block retirement), or another operation associated with reading information from memory device 130-d.

[0127] At 660, the memory system controller 115-b may transmit a read operation signaling to the memory device 130-d, which may be received at the memory device 130-d (e.g., at the local controller 135). The read operation signaling at 660 may contain an indication to read a portion of the memory array of the memory device 130-d (e.g., associated with a read command, as identified for a memory management operation). In some instances, the memory system controller 115-b may track overwrite conditions associated with a portion of the memory array to be read (e.g., the number of write operations since the previous erase operation, how much programming has occurred), or boundary configuration 401 or its boundary 410, and the read operation signaling of 660 may include indications of overwrite conditions or boundary configuration 401 associated with a portion of the memory array (e.g., indications of whether a portion of the memory array has been written a certain number of logic states according to one boundary configuration 401 or another boundary configuration 401, prefixes indicating which boundary configuration or read level will be used for read operation signaling of programmed data, algorithm qualifying prefixes). In some other instances, the memory system controller 115-b may not track such conditions (e.g., when such conditions are tracked at memory device 130-d), such that indications of conditions can be omitted from the read operation signaling of 660.

[0128] At 665, memory device 130-d can select boundaries (e.g., voltage boundaries, reference voltage, the value of boundary 410, the number of boundaries 410, the number of levels in the multi-level read circuitry system). In some instances, memory device 130-d can perform selection within a set of boundaries based on indications of read operation signaling at 660 (e.g., indications of whether a portion of the memory array has been written a certain number of logic states according to one boundary configuration 401 or another boundary configuration 401). In some other instances, memory device 130-d can track overwrite conditions associated with the portion of the memory array to be read (e.g., the number of write operations since the previous erase operation), or boundary configuration 401 or its boundaries 410, and can select boundaries based on indications stored at memory device 130-d. In some instances, such selection can be based on the number of write operations performed on a portion of the memory array since the previous erase operation on that portion, or a determination of whether a portion of the memory array has been erased before the target information is written. In some instances, such selection may include determining whether to use one reference voltage or another to distinguish logic states, or determining the number of boundaries 410 for a given number of logic states, which may include a number of boundaries equal to or greater than the number of logic states. In some cases, the memory system controller 115-b may determine the boundaries based on the read location. For example, in some cases, the memory system controller 115-b may determine whether to perform a read based on a first boundary or a second boundary based on the write operation history at a portion of the memory (e.g., how many write or overwrite commands have been sent at a portion of the memory since the last erase operation).

[0129] At 670, memory device 130-d may perform a read operation according to a boundary selected at 665. In some cases, depending on the number of overwrites at a portion of the memory array (e.g., the number of overwrites performed according to overwrite scheme 400 or overwrite scheme 500), memory device 130-d may perform a read operation according to an initial boundary configuration 401 or an overwrite boundary configuration that may be associated with a single boundary 410 or with multiple boundaries 410 (e.g., according to N-1 read levels, where N is the number of overwrites). In some cases, such operations may involve one or more single-level read operations or sensing circuitry, or may involve multi-level read operations or circuitry systems.

[0130] Figure 7 This document describes an example of an overwrite map 700 supporting overwriting at a memory system, based on the examples disclosed herein. The overwrite map 700 may include a first address block 705-a, a second address block 705-b, and a combined address block 705-c, which may refer to a logical or physical address group of the memory device 130. In some instances, each of the address blocks 705 may be a reference... Figure 3 An instance of the described block 360.

[0131] In an example of overwrite mapping 700, each address block 705 may refer to a portion of a memory array (e.g., memory cell set 305) where data has been written, the writing may include writes according to an overwrite scheme (e.g., according to one or more aspects of overwrite scheme 400 or 500). For example, a first address block 705-a may contain valid data 720-a and invalid data 725-a, and a second address block 705-b may contain valid data 720-b and invalid data 725-b. In some instances, invalid data 725 may be outdated data (e.g., due to a newer or updated version of the data being stored in a different location, or the data no longer being needed). In some instances, valid data 720 may be the latest version of the data stored at memory device 130. In some cases, the data written to address block 705 may include an indication of whether it is valid data 720 (e.g., a write timestamp). In some cases, different sub-parts of the data at address 705 in the first address block may become invalid at different times, which may result in a mix of valid data 720 and invalid data 725.

[0132] In some cases, to enable the reuse of portions of memory, memory system 110 or memory device 130 may perform garbage collection to consolidate valid data 720 at one address block 705, freeing up another address block 705 for erasing and writing new data. For example, to make first address block 705-a available for new information, valid data 720-a may be read and written to another location, making the entire first address block 705-a erasable (e.g., depending on the erasure granularity). In some instances, memory system 110 may append valid data 720 from one address block 705 to the end of a usable location that has not yet been written since the self-erasure operation of another address block 705. However, in some instances, such information movement and subsequent erasure may be associated with information transfer delays, power consumption, biasing, or other operations of the associated memory cells that could degrade the memory cells or cause performance degradation. In some instances, implementing one or more aspects of an overwrite scheme for this type of memory management technology can improve memory utilization or efficiency, reduce power consumption, or reduce degradation of the memory device 130.

[0133] For example, to integrate valid data 720-a and valid data 720-b, one or more components of memory system 110 may implement aspects of overwrite scheme 400 or overwrite scheme 500 to directly overwrite invalid data 725. In various instances, such techniques may include moving valid data 720-a to a second address block 705-b (e.g., to an address associated with invalid data 725-b), or moving valid data 720-b to a first address block 705-a (e.g., to an address associated with invalid data 725-a). In some cases, to support evaluation between these and other alternatives, memory system 110 may compare the ratio of valid data 720 to invalid data 725 in one or more address blocks 705, or the valid address count (VAC), which may be associated with relocating a target address block 705 for reading valid data 720 (e.g., to open address block 705 for erasure), or relocating a target address block 705 for writing valid data 720, or both. In some instances, such evaluations may include overwrite conditions for address block 705 (e.g., whether a portion of address block 705 has been overwritten, or whether a portion of address block 705 is available for further overwriting) or wear leveling conditions for address block 705 (e.g., other indications of total accesses or degradation or available lifetime), as well as the determination of other considerations. In some cases, memory system 110 may perform such comparisons as an iterative process to perform several overwrites at the address block containing the most valid data.

[0134] In the illustrated example, the first address block 705-a may be associated with a larger quantity or proportion of valid data 720 (e.g., the quantity of valid data 720-a is greater than the quantity of valid data 720-b, and the ratio of valid data 720-a to invalid data 725-a is greater than the ratio of valid data 720-b to invalid data 725-b). Therefore, assuming such overwriting is available or supported, valid data 720-b can be read more efficiently (e.g., with fewer access operations and fewer system resources) from the second address block 705-b (e.g., according to process flow 650, according to one or more aspects of overwriting scheme 400 or 500), and valid data 720-b can be written to the address associated with invalid data 725-a (e.g., according to process flow 600, according to one or more aspects of overwriting scheme 400 or 500). In this example, the combined address block 705-c can be associated with the same physical address in the memory array as the first address block 705-a, and after such a transfer, the physical address associated with the second address block 705-b can be erased, or overwritten entirely according to one or more aspects of overwrite scheme 400 or 500. For example, after relocating valid data 720-b, the physical address associated with the second address block 705-b can be erased according to an erase operation, which can be associated with resetting the corresponding validity indication and overwrite condition indication. By implementing such techniques, garbage collection can be simplified or subject to less memory degradation (e.g., by eliminating the steps of erasing invalid data 725-a or erasing the first address block 705-a entirely), or memory utilization can be improved (e.g., by overwriting rather than appending data), and other benefits. In some instances, information moved from the second address block 705-b can be associated with different identifiers (e.g., prefixes, overwrite identifiers), such as assigning a logical block address (LBA) “B” identifier to valid data 720-b in the composite address block 705-c (e.g., according to overwrite delimiter configuration 401), while assigning an LBA “A” to valid data 720-a in the composite address block 705-c (e.g., according to initial delimiter configuration 401, which can be associated with an address or mapping of such data that has not been updated and remains in place).

[0135] While some aspects of overwrite map 700 are described in the context of garbage collection operations, overwrite map 700 illustrates the benefits of the described overwrite technique that can be implemented in other memory management operations (or more generally, any write operation). For example, because the address associated with invalid data 725 is still available for overwriting, it may not be necessary to use empty block 170 or portions thereof to write new information. Therefore, the available space in memory device 130 is not limited to cells that have been erased or never programmed, which improves the availability of memory device 130 for storing new information. In some instances, this increase in availability can be an example of reducing the amount of over-allocation implemented at memory device 130 (e.g., to support a given flexibility in relocating information or erasing block 170), and can increase the availability of such transient information as L2P tables, write booster buffers, parity information, etc. Furthermore, by reducing the number of erase operations, or by performing write operations at reduced write semaphore values, or both, memory cells can incur less stress, fatigue, or other degradation, and correspondingly support larger TBW ratings, or larger program / erase endurance ratings, and other benefits. In some instances, the relatively longer operating lifetime of memory cells can reduce the extent of block retirement, which is another instance of reducing the amount of overfeeding implemented at memory device 130 (e.g., to support a given design lifetime).

[0136] Figure 8 A block diagram 800 illustrates a memory system 820 that supports overwriting at a memory system according to an example disclosed herein. The memory system 820 may be referenced. Figures 1 to 7 Examples of aspects of the described memory system. Memory system 820 or its various components may be examples of means for performing various aspects of overwriting at a memory system as described herein. For example, memory system 820 may include write operation component 825, overwrite evaluation component 830, overwrite operation component 835, read operation component 840, memory system signaling component 845, instruction storage component 850, erase operation component 855, or any combination thereof. Each of these components may communicate directly or indirectly with each other (e.g., via one or more buses).

[0137] Write operation component 825 may be configured or otherwise supported to perform a write operation based on a first voltage boundary between logic states to store first information at a portion of the memory array. Overwrite evaluation component 830 may be configured or otherwise supported to determine how to overwrite the portion of the memory array with second information. Overwrite operation component 835 may be configured or otherwise supported to perform a write operation based on a second voltage boundary between the logic states, at least in part, based on the determination to overwrite the portion of the memory array, to store the second information at the portion of the memory array.

[0138] In some instances, the write operation based on the second voltage boundary between the logical states can be performed without performing an erase operation on the portion of the memory array after the write operation based on the first voltage boundary between the logical states.

[0139] In some instances, the first voltage boundary between logic states may be associated with a first reference voltage used to distinguish between the first and second logic states. In some instances, the second voltage boundary between logic states may be associated with a second reference voltage higher than the first reference voltage used to distinguish between the first and second logic states.

[0140] In some instances, the first voltage boundary between logic states may be associated with a first voltage used to write the logic state. In some instances, the second voltage boundary between logic states may be associated with a second voltage used to write the logic state, the second voltage being higher than the first voltage used to write the logic state.

[0141] In some instances, the write operation based on the first voltage boundary between logical states and the write operation based on the second voltage boundary between logical states may each be associated with writing the same number of logical states.

[0142] In some instances, the portion of the memory array may contain NAND memory cells.

[0143] In some instances, to support the write operation performed based on the second voltage boundary between logical states, the memory system signaling component 845 may be configured or otherwise supported to transmit means for transmitting signaling containing the second information and an indication of the second voltage boundary between logical states to the memory device.

[0144] In some instances, the storage component 850 is configured, or otherwise supports, means for storing indications of portions of the memory array that have been written to according to the second voltage boundary between logical states.

[0145] In some instances, determining to overwrite the portion of the memory array may be based at least in part on the first information, the second information, or both, in association with write boost information, parity information, or logical-to-physical address information.

[0146] In some instances, determining whether to overwrite the portion of the memory array may be based at least in part on a validity indication associated with the first information or the portion of the memory array.

[0147] In some instances, the overwrite evaluation component 830 may be configured or otherwise supported as means for determining parameters associated with enabling the portion of the memory array for overwrite operations, and the determination of overwriting the portion of the memory array may be based at least in part on the determined parameters.

[0148] In some instances, the overwrite evaluation component 830 may be configured or otherwise supported as means for determining the portion of the memory array based at least in part on the proportion of the portion of the memory array associated with valid data.

[0149] In some instances, the overwrite evaluation component 830 may be configured or otherwise supported to include means for determining the second portion of the memory array based at least in part on a proportion of the second portion of the memory array associated with valid data. In some instances, the read operation component 840 may be configured or otherwise supported to include means for reading the second information from the determined second portion of the memory array. In some instances, the erase operation component 855 may be configured or otherwise supported to include means for performing an erase operation on the second portion of the memory array after the second information has been written to that portion of the memory array.

[0150] The read operation component 840 may be configured or otherwise supported to support means for receiving from a host device a read command for reading a portion of the memory array of the memory device that has been written with a number of logical states. In some instances, the overwrite evaluation component 830 may be configured or otherwise supported to support means for determining whether the portion of the memory array has been written with the number of logical states according to a first voltage boundary between logical states or according to a second voltage boundary between the logical states. The memory system signaling component 845 may be configured or otherwise supported to support means for transmitting signaling for reading the portion of the memory array to the memory device, wherein the signaling may include an indication of the portion of the memory array and an indication of whether the portion of the memory array has been written with the number of logical states according to the first voltage boundary between the logical states or according to the second voltage boundary between the logical states.

[0151] In some instances, to support determining whether the portion of the memory array has been written with the number of logic states based on a first voltage boundary between logic states or a second voltage boundary between logic states, the overwrite evaluation component 830 may be configured or otherwise support means for determining the number of write operations performed on the portion of the memory array since a previous erase operation on the portion of the memory array.

[0152] Figure 9 A block diagram 900 illustrates a memory device 920 for overwriting a memory system according to an example disclosed herein. The memory device 920 may be referenced. Figures 1 to 7 Examples of aspects of the described memory device. Memory device 920 or its various components may be examples of means for performing various aspects of overwriting at a memory system as described herein. For example, memory device 920 may include write evaluation component 925, voltage threshold evaluation component 930, write operation component 935, read operation component 940, or any combination thereof. Each of these components may communicate directly or indirectly with each other (e.g., via one or more buses).

[0153] Write evaluation component 925 may be configured or otherwise supported to support means for receiving signaling to write first information to a portion of the memory array. Voltage boundary evaluation component 930 may be configured or otherwise supported to support means for determining a first voltage boundary for writing the second information to the portion of the memory array, at least in part based on the portion of the memory array having the second information written to it according to a second voltage boundary for writing a number of logic states. Write operation component 935 may be configured or otherwise supported to support means for writing the first information to the portion of the memory array according to the determined first voltage boundary for writing the number of logic states.

[0154] In some instances, the first information can be written to the portion of the memory array without performing an erase operation on the portion of the memory array after the portion of the memory array has been written with the second information.

[0155] In some instances, the write evaluation component 925 may be configured or otherwise supported to determine, at least in part, that portion of the memory array has been written with the second information according to the second voltage threshold, based on an indication associated with the command, and the determination of the first voltage threshold for writing the number of logic states may be at least in part based on the indication associated with the command.

[0156] In some instances, the write evaluation component 925 may be configured or otherwise support means for determining, at least in part, that portion of the memory array has the second information written to it according to the second voltage threshold, based on an indication stored at the memory device and associated with the portion of the memory array, and determining that the first voltage threshold for writing the number of logic states may be at least in part based on the indication stored at the memory device.

[0157] In some instances, to support the determination of the first voltage threshold for writing the logic state, the voltage threshold evaluation component 930 may be configured or otherwise support means for determining a first voltage for writing the logic state to the portion of the memory array, wherein the first voltage is different from a second voltage for writing the logic state associated with the second voltage threshold for writing the logic state.

[0158] The read operation component 940 may be configured or otherwise support means for receiving signaling from the controller of the memory system for partial read information of a number of logical states written to the memory array. In some instances, the voltage threshold evaluation component 930 may be configured or otherwise support means for selecting between a first read voltage threshold and a second read voltage threshold, at least in part based on whether the portion of the memory array has the number of logical states written to it according to a first voltage threshold or a second voltage threshold between the logical states. In some instances, the read operation component 940 may be configured or otherwise support means for performing a read operation on the portion of the memory array, at least in part based on the selected first read voltage threshold or the selected second read voltage threshold.

[0159] In some instances, to support determining whether a read operation is performed based on a first voltage boundary between the logic states or a second voltage boundary between the logic states, the write evaluation component 925 may be configured or otherwise support means for determining the number of write operations performed on the portion of the memory array since a previous erase operation on the portion of the memory array.

[0160] In some instances, determining whether to perform the read operation based on the first voltage boundary between the logical states or the second voltage boundary between the logical states is at least in part based on the indication of the received signaling.

[0161] In some instances, determining whether to perform the read operation based on a first voltage boundary between the logic states or a second voltage boundary between the logic states is at least in part based on an indication stored in the memory device and associated with the portion of the memory array.

[0162] In some instances, to support determining whether a read operation is performed based on a first voltage boundary between the logic states or a second voltage boundary between the logic states, the voltage boundary evaluation component 930 may be configured or otherwise support means for determining whether to use a first reference voltage to distinguish between the first and second logic states or a second reference voltage to distinguish between the first and second logic states.

[0163] Figure 10 A flowchart illustrating a method 1000 for overwriting at a supporting memory system according to an example disclosed herein is shown. Operation of method 1000 may be implemented by the memory system or its components described herein. For example, operation of method 1000 may be implemented by reference to... Figures 1 to 8The described memory system performs the functions. In some instances, the memory system may execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively, the memory system may use dedicated hardware to perform aspects of the described functions.

[0164] At point 1005, the method may include performing a write operation based on a first voltage boundary between logic states to store first information at a portion of the memory array. The operation at point 1005 may be performed according to the examples disclosed herein. In some instances, it may be performed by reference... Figure 8 The described write operation component 825 performs the operation of 1005.

[0165] At 1010, the method may include determining to overwrite the portion of the memory array with second information. The operation at 1010 may be performed according to examples disclosed herein. In some instances, it may be performed by reference... Figure 8 The described aspects of the overwrite evaluation component 830 performing the operation of 1010.

[0166] At 1015, the method may include performing a write operation based at least in part on determining that a portion of the memory array will be overwritten, according to a second voltage boundary between the logic states, to store the second information at that portion of the memory array. The operation at 1015 may be performed according to the examples disclosed herein. In some instances, it may be performed by reference to... Figure 8 The described aspect of the overwrite operation component 835 performing the operation 1015.

[0167] In some instances, the device as described herein may perform one or more methods, such as method 1000. The device may include features, circuitry, logic, means, or instructions (e.g., processor-executable instructions stored in a non-transitory computer-readable medium) for: performing a write operation based on a first voltage boundary between logic states to store first information at a portion of the memory array; determining to overwrite the portion of the memory array with second information; and performing a write operation based on a second voltage boundary between the logic states, at least in part based on the determination to overwrite the portion of the memory array, to store the second information at the portion of the memory array.

[0168] In some instances of the method 1000 and device described herein, the write operation based on the second voltage boundary between the logical states can be performed without performing an erase operation on the portion of the memory array after performing the write operation based on the first voltage boundary between the logical states.

[0169] In some instances of the method 1000 and apparatus described herein, the first voltage boundary between logic states may be associated with a first reference voltage for distinguishing between the first logic state and the second logic state, and the second voltage boundary between logic states may be associated with a second reference voltage higher than the first reference voltage for distinguishing between the first logic state and the second logic state.

[0170] In some instances of the method 1000 and device described herein, the first voltage boundary between logic states may be associated with a first voltage for writing the logic state, and the second voltage boundary between logic states may be associated with a second voltage for writing the logic state, the second voltage being higher than the first voltage for writing the logic state.

[0171] In some instances of the method 1000 and device described herein, the write operation based on the first voltage boundary between logical states and the write operation based on the second voltage boundary between logical states may each be associated with writing the same number of logical states.

[0172] In some instances of the method 1000 and apparatus described herein, the portion of the memory array comprises NAND memory cells.

[0173] In some instances of the method 1000 and device described herein, performing the write operation based on the second voltage boundary between logical states may include operations, features, circuitry, logic, means, or instructions for transmitting signaling containing the second information and an indication of the second voltage boundary between logical states to the memory device.

[0174] Some examples of the methods 1000 and devices described herein may additionally include operations, features, circuit systems, logic, means, or instructions for storing indications that may have been written to said portion of the memory array according to the second voltage boundary between logic states.

[0175] Some examples of the methods 1000 and devices described herein may additionally include operations, features, circuit systems, logic, means, or instructions for determining that overwriting a portion of the memory array may be at least partially based on the first information, the second information, or both, and associated with write boost information, parity information, or logic-to-physical address information.

[0176] Some examples of the methods 1000 and devices described herein may additionally include operations, features, circuit systems, logic, means, or instructions for determining that overwriting the portion of the memory array may be based at least in part on a validity indication associated with the first information or the portion of the memory array.

[0177] Some examples of the methods 1000 and devices described herein may additionally include operations, features, circuit systems, logic, means, or instructions for determining parameters associated with enabling said portion of the memory array for overwrite operations, wherein determining to overwrite said portion of the memory array may be based at least in part on said determined parameters.

[0178] Some examples of the methods 1000 and devices described herein may additionally include operations, features, circuit systems, logic, means, or instructions for determining the portion of the memory array based at least in part on the proportion of the portion of the memory array that can be associated with valid data.

[0179] Some examples of the methods 1000 and devices described herein may additionally include operations, features, circuit systems, logic, means, or instructions for: determining a second portion of the memory array based at least in part on a proportion of a second portion of the memory array that can be associated with valid data; reading the second information from the determined second portion of the memory array; and performing an erase operation on the second portion of the memory array after the second information has been written to the portion of the memory array.

[0180] Figure 11 A flowchart illustrating a method 1100 for overwriting a memory system according to an example disclosed herein is shown. Operation of method 1100 may be implemented by a memory device or its components as described herein. For example, operation of method 1100 may be performed by reference to... Figure 1 and 7 The memory device described in section 9 performs the functions described. In some instances, the memory device may execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0181] At 1105, the method may include receiving signaling at the memory device to write first information to a portion of the memory array. The operation at 1105 may be performed according to the examples disclosed herein. In some instances, it may be performed by reference... Figure 9 The described aspect of the write evaluation component 925 performing the operation of 1105.

[0182] At 1110, the method may include determining a first voltage boundary for writing the number of logic states to the portion of the memory array, based at least in part on the fact that the portion of the memory array has been written with second information according to a second voltage boundary for writing a number of logic states. The operation of 1110 may be performed according to the examples disclosed herein. In some instances, it may be performed by reference to... Figure 9 The voltage boundary assessment component 930 described performs the operation of 1110.

[0183] At 1115, the method may include writing the first information to the portion of the memory array according to the determined first voltage threshold for writing the number of logic states. The operation at 1115 may be performed according to the examples disclosed herein. In some instances, it may be performed by reference to... Figure 9 The described write operation component 935 performs the operation of 1115.

[0184] In some instances, the device as described herein may perform one or more methods, such as method 1100. The device may include features, circuitry, logic, means, or instructions (e.g., processor-executable instructions stored in a non-transitory computer-readable medium) for: receiving at a memory device signaling to write first information to a portion of a memory array; determining a first voltage boundary for writing the second information to the portion of the memory array, at least in part based on the portion of the memory array being written with the second information according to a second voltage boundary for writing a number of logic states; and writing the first information to the portion of the memory array according to the determined first voltage boundary for writing the number of logic states.

[0185] Some examples of the method 1100 and apparatus described herein may additionally include operations, features, circuit systems, logic, means, or instructions for writing the first information to the portion of the memory array without performing an erase operation on the portion of the memory array after the portion of the memory array has been written with the second information.

[0186] Some examples of the method 1100 and apparatus described herein may additionally include operations, features, circuit systems, logic, means, or instructions for determining, at least in part, based on an indication associated with the command, that a portion of the memory array is written with the second information according to a second voltage threshold, wherein the first voltage threshold for determining the number of logic states to be written may be at least in part based on the indication associated with the command.

[0187] Some examples of the method 1100 and apparatus described herein may additionally include operations, features, circuit systems, logic, means, or instructions for determining, at least in part, that portion of the memory array is written with the second information according to a second voltage threshold, based on an indication stored in the memory device and associated with the portion of the memory array, wherein determining the first voltage threshold for writing the number of logic states may be at least in part based on the indication stored in the memory device.

[0188] In some instances of the method 1100 and apparatus described herein, determining a first voltage boundary for writing a logic state may include operations, features, circuitry, logic, means, or instructions for determining a first voltage for writing a logic state to the portion of the memory array, wherein the first voltage may be different from a second voltage for writing the logic state that may be associated with the second voltage boundary for writing the logic state.

[0189] Figure 12 A flowchart illustrating method 1200 for overwriting at a supporting memory system according to an example disclosed herein is shown. Operation of method 1200 may be implemented by a memory system or its components as described herein. For example, operation of method 1200 may be performed by reference to... Figures 1 to 8 The memory system described herein performs the functions described. In some instances, the memory system may execute a set of instructions to control the functional elements of the device to perform the functions described below. Alternatively, the memory system may use dedicated hardware to perform aspects of the functions described below.

[0190] At 1205, the method may include receiving a read command from a host device at the memory system to read a portion of the memory array of the memory device that has been written with a number of logical states. The operation at 1205 may be performed according to the examples disclosed herein. In some instances, it may be performed by reference to... Figure 8 The described read operation component 840 performs the operation of 1205.

[0191] At 1210, the method may include determining whether the portion of the memory array has the number of logic states written to it according to a first voltage boundary between logic states or a second voltage boundary between the logic states. The operation of 1210 may be performed according to the examples disclosed herein. In some instances, it may be provided by reference... Figure 8 The described aspects of the overwrite evaluation component 830 performing the operation of 1210.

[0192] At 1215, the method may include transmitting signaling to the memory device for reading the portion of the memory array, wherein the signaling includes an indication of the portion of the memory array and an indication of whether the portion of the memory array has been written with the number of logic states according to a first voltage boundary between the logic states or according to a second voltage boundary between the logic states. The operation of 1215 may be performed according to the examples disclosed herein. In some examples, it may be provided by reference... Figure 8 The described memory system signaling component 845 performs the operation of 1215.

[0193] In some instances, the device as described herein may perform one or more methods, such as method 1200. The device may include features, circuitry, logic, means, or instructions (e.g., processor-executable instructions stored in a non-transitory computer-readable medium) for: receiving from a host device at a memory system a read command to read a portion of a memory array of the memory device that has been written with a number of logical states; determining whether the portion of the memory array has been written with the number of logical states according to a first voltage boundary between logical states or according to a second voltage boundary between the logical states; and transmitting signaling to the memory device to read the portion of the memory array, wherein the signaling includes an indication of the portion of the memory array and an indication of whether the portion of the memory array has been written with the number of logical states according to the first voltage boundary between the logical states or according to the second voltage boundary between the logical states.

[0194] In some instances of the method 1200 and apparatus described herein, determining whether a portion of the memory array has been written to according to a first voltage boundary between logic states or a second voltage boundary between the logic states may include operations, features, circuitry, logic, means, or instructions for determining the number of write operations performed on the portion of the memory array since a previous erase operation on the portion of the memory array.

[0195] Figure 13 A flowchart illustrating method 1300 for overwriting at a supporting memory system according to an example disclosed herein is shown. Operation of method 1300 may be implemented by the memory device or its components described herein. For example, operation of method 1300 may be performed by reference to... Figures 1 to 7 The memory device described in section 9 performs the functions described therein. In some instances, the memory device may execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0196] At 1305, the method may include receiving, at a memory device of the memory system, signaling from a controller of the memory system to read information partially written to the memory array of the memory device, including a number of logical states. The operation of 1305 may be performed according to the examples disclosed herein. In some instances, it may be performed by reference to... Figure 9 The described read operation component 940 performs the operation of 1305.

[0197] At 1310, the method may include selecting between a first read voltage boundary and a second read voltage boundary, at least in part based on whether the portion of the memory array is written with the number of logic states according to a first voltage boundary between logic states or according to a second voltage boundary between logic states. The operation of 1310 may be performed according to the examples disclosed herein. In some examples, it may be provided by reference... Figure 9 The voltage boundary assessment component 930 described performs the operation of 1310.

[0198] At 1315, the method may include performing a read operation on the portion of the memory array based at least in part on the selected first read voltage boundary or the selected second read voltage boundary. The operation at 1315 may be performed according to the examples disclosed herein. In some instances, it may be provided by reference... Figure 9 The described read operation component 940 performs the operation of 1315.

[0199] In some instances, the device as described herein may perform one or more methods, such as method 1300. The device may include features, circuitry, logic, means, or instructions (e.g., processor-executable instructions stored in a non-transitory computer-readable medium) for: receiving, at a memory device of a memory system, signaling from a controller of the memory system to read information from a portion of the memory array of the memory device that has been written with a number of logical states; selecting between a first read voltage boundary and a second read voltage boundary, at least in part based on whether the portion of the memory array has been written with the number of logical states according to a first voltage boundary or a second voltage boundary between the logical states; and performing a read operation on the portion of the memory array, at least in part based on the selected first read voltage boundary or the selected second read voltage boundary.

[0200] In some instances of the method 1300 and apparatus described herein, determining whether to perform a read operation based on a first voltage boundary between the logic states or a second voltage boundary between the logic states may include operations, features, circuitry, logic, means, or instructions for determining the number of write operations performed on the portion of the memory array since a previous erase operation on the portion of the memory array.

[0201] Some examples of the methods 1300 and devices described herein may additionally include operations, features, circuit systems, logic, means, or instructions for determining whether to perform a read operation based on a first voltage boundary between said logic states or a second voltage boundary between said logic states, which may be based at least in part on an indication of received signaling.

[0202] Some examples of the methods 1300 and devices described herein may additionally include operations, features, circuit systems, logic, means, or instructions for determining whether to perform a read operation based on a first voltage boundary between the logic states or a second voltage boundary between the logic states, based at least in part on an indication stored at the memory device and associated with the portion of the memory array.

[0203] In some instances of the method 1300 and apparatus described herein, determining whether to perform a read operation based on a first voltage boundary between the logic states or a second voltage boundary between the logic states may include operations, features, circuitry, logic, means, or instructions for determining whether to use a first reference voltage for distinguishing between the first and second logic states or a second reference voltage for distinguishing between the first and second logic states.

[0204] It should be noted that the methods described above describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described may be combined.

[0205] Describe an apparatus. The apparatus may include a memory device having a memory array and a controller coupled to the memory device. The controller may be configured to cause the apparatus to: perform a write operation based on a first voltage boundary between logical states to store first information at a portion of the memory array; determine to overwrite the portion of the memory array with second information; and, at least in part based on the determination to overwrite the portion of the memory array, perform a write operation based on a second voltage boundary between the logical states to store the second information at the portion of the memory array.

[0206] In some instances of the device, the write operation based on the second voltage boundary between the logical states can be performed without performing an erase operation on the portion of the memory array after the write operation based on the first voltage boundary between the logical states.

[0207] In some instances of the device, the first voltage boundary between logic states may be associated with a first reference voltage for distinguishing between the first logic state and the second logic state, and the second voltage boundary between logic states may be associated with a second reference voltage higher than the first reference voltage for distinguishing between the first logic state and the second logic state.

[0208] In some instances of the device, the first voltage boundary between logic states may be associated with a first voltage for writing the logic state, and the second voltage boundary between logic states may be associated with a second voltage for writing the logic state, the second voltage being higher than the first voltage for writing the logic state.

[0209] In some instances of the device, the write operation based on the first voltage boundary between logical states and the write operation based on the second voltage boundary between logical states may each be associated with writing the same number of logical states.

[0210] In some instances of the device, a portion of the memory array includes NAND memory cells.

[0211] In some instances of the device, in order to perform the write operation based on the second voltage boundary between logical states, the controller may be configured to cause the device to transmit signaling including the second information and an indication of the second voltage boundary between logical states to the memory device.

[0212] In some instances of the device, the controller may be further configured to cause the device to store an indication of a portion of the memory array that has been written to the memory array according to the second voltage boundary between logical states.

[0213] In some instances of the device, the controller may be further configured to cause the device to determine, at least in part, to overwrite the portion of the memory array based on the first information, the second information, or both in association with write boost information, parity information, or logical-to-physical address information.

[0214] In some instances of the device, the controller may be configured to cause the device to determine to overwrite the portion of the memory array based at least in part on a validity indication associated with the first information or the portion of the memory array.

[0215] In some instances of the device, the controller may be further configured to cause the device to determine parameters associated with enabling the portion of the memory array for overwrite operations, wherein the determination to overwrite the portion of the memory array is based at least in part on the determined parameters.

[0216] In some instances of the device, the controller may be further configured to cause the device to determine the portion of the memory array based at least in part on the proportion of the portion of the memory array associated with valid data.

[0217] In some instances of the device, the controller may be further configured to cause the device to determine, at least in part, the second portion of the memory array based on a proportion of the second portion of the memory array associated with valid data; read the second information from the determined second portion of the memory array; and, after writing the second information to the portion of the memory array, perform an erase operation on the second portion of the memory array.

[0218] Describe a device. The device may include a memory array and a controller coupled to the memory array. The controller may be configured to cause the device to: receive signaling to write first information to a portion of the memory array; determine a first voltage boundary for writing the second information to the portion of the memory array, at least in part based on the portion of the memory array being written with the second information according to a second voltage boundary for writing a number of logic states; and write the first information to the portion of the memory array according to the determined first voltage boundary for writing the number of logic states.

[0219] In some instances of the device, the controller may be configured to write the first information to the portion of the memory array without performing an erase operation on the portion of the memory array after the portion of the memory array has been written with the second information.

[0220] In some instances of the device, the controller may be further configured to cause the device to determine, at least in part, based on an indication associated with the command, that the portion of the memory array has been written with the second information according to the second voltage threshold, and to determine, at least in part, the first voltage threshold for writing the number of logic states may be based on the indication associated with the signaling.

[0221] In some instances of the device, the controller may be further configured to cause the device to determine, at least in part, that the portion of the memory array has the second information written according to the second voltage threshold, based on an indication stored at the device and associated with the portion of the memory array, and to determine that the first voltage threshold for writing the number of logic states may be at least in part based on the indication stored at the device.

[0222] In some instances of the device, in order to determine the first voltage threshold for writing the logic state, the controller may be configured to cause the device to: determine a first voltage for writing the logic state to the portion of the memory array, wherein the first voltage may be different from a second voltage for writing the logic state associated with the second voltage threshold for writing the logic state.

[0223] Describe an apparatus. The apparatus may include a memory device comprising a memory array and a controller coupled to the memory device. The controller may be configured to cause the apparatus to: receive from a host device a read command to read a portion of the memory array that has been written with a number of logical states; determine whether the portion of the memory array has been written with the number of logical states according to a first voltage boundary between logical states or according to a second voltage boundary between logical states; and transmit signaling for reading the portion of the memory array to the memory device. In some instances, the signaling may include an indication of the portion of the memory array and an indication of whether the portion of the memory array has been written with the number of logical states according to the first voltage boundary between logical states or according to the second voltage boundary between logical states.

[0224] In some instances, in order to determine whether the portion of the memory array has been written with the number of logic states according to a first voltage boundary between logic states or a second voltage boundary between logic states, the controller may be configured to cause the device to: determine the number of write operations performed on the portion of the memory array since a previous erase operation on the portion of the memory array.

[0225] Describe a device. The device may include a memory array and a controller coupled to the memory array. The controller may be configured to cause the device to: receive signaling from a controller of a memory system to read information from a portion of the memory array that has been written with a number of logical states; select between a first read voltage boundary and a second read voltage boundary, at least in part based on whether the portion of the memory array has been written with the number of logical states according to a first voltage boundary or a second voltage boundary between the logical states; and perform a read operation on the portion of the memory array, at least in part based on the selected first read voltage boundary or the selected second read voltage boundary.

[0226] In some instances of the device, in order to determine whether to perform a read operation based on a first voltage boundary between the logical states or a second voltage boundary between the logical states, the controller may be configured to cause the device to: determine the number of write operations performed on the portion of the memory array since a previous erase operation on the portion of the memory array.

[0227] In some instances of the device, the controller may be configured to cause the device to determine, at least in part, whether to perform the read operation based on a first voltage boundary between the logical states or a second voltage boundary between the logical states, based on an indication of the received signaling.

[0228] In some instances of the device, the controller may be configured to cause the device to determine, at least in part, whether to perform the read operation based on a first voltage boundary between the logical states or a second voltage boundary between the logical states, based on an indication stored in the device and associated with the portion of the memory array.

[0229] In some instances of the device, in order to determine whether to perform a read operation based on a first voltage boundary between the logic states or a second voltage boundary between the logic states, the controller may be configured to cause the device to: determine whether to use a first reference voltage for distinguishing between the first logic state and the second logic state or to use a second reference voltage for distinguishing between the first logic state and the second logic state.

[0230] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate signaling as a single signal; however, signals may represent buses of signals, which may have various bit widths.

[0231] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of electrons between them. Components are considered to be in electronic communication with each other (or in conductive contact, connected, or coupled) if any conductive path exists between them that can support the flow of signals at any given time. At any given time, the conductive path between components that are electronically connected (or in conductive contact, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the signal flow between connected components for a period of time.

[0232] The term "coupling" refers to the condition that moves from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path, while in a closed-circuit relationship, signals can travel between components via a conductive path. If a component, such as a controller, couples other components together, then the component initiates a change that allows signals to flow between other components via conductive paths that were previously not permitted.

[0233] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between them are isolated from each other when the switch is open. If a controller isolates two components, it prevents signals from flowing between the components using previously permitted conductive paths.

[0234] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, the terms “if,” “when,” “based on,” or “at least partially based on” are used to describe a connection between conditional actions, conditional processes, or parts of a process.

[0235] The term "in response to" can refer to a condition or action that occurs at least partially (if not completely) as a result of a preceding condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least partially as a result of the preceding condition or action (whether directly after the first condition or action or after one or more other intermediate conditions or actions following the first condition or action).

[0236] Additionally, the terms "directly in response to" or "directly responding to" can refer to a condition or action occurring as a direct result of a previous condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as "based on," "at least in part based on," or "in response to" a certain other step, action, event, or condition may additionally or alternatively (e.g., in alternative instances) "directly in response to" or "directly responding to" such other condition or action.

[0237] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0238] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, a drain, and a gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped, for example, degenerate, semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or a channel. If the channel is n-type (i.e., the majority of charge carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority of charge carriers are holes), then the FET may be called a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "off" or "deactivated."

[0239] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior" to other instances. The detailed description includes specific details that provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0240] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a hyphen following the reference numeral and a second numeral used to differentiate between similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0241] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented as software executed by a processor, the functions may be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions may also be physically located in various locations, including distributed configurations such that portions of the functions are implemented in different physical locations.

[0242] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or executed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components, or any combination thereof. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0243] As used herein, the word "or," as used in the claims, such as in a list of items (e.g., a list followed by phrases such as "at least one of..." or "one or more of..."), indicates a list containing endpoints such that a list of at least one of, for example, A, B, or C, means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0244] Computer-readable media includes both non-transitory computer-readable storage media and communication media, with communication media encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), compressed optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then such coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital video discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0245] The description provided herein enables those skilled in the art to make or use this disclosure. Those skilled in the art will appreciate the various modifications that can be made to this disclosure, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: A memory device, comprising a memory array; and A controller, coupled to the memory device and configured to cause the device to: A write operation is performed based on a first voltage boundary between logical states to store first information at a portion of the memory array; Determine to overwrite the portion of the memory array with the second information; and The write operation is performed, at least in part, based on determining that a portion of the memory array will be overwritten, according to a second voltage boundary between the logical states that is different from the first voltage boundary between the logical states. The second information is stored in the portion of the memory array.

2. The device of claim 1, wherein the write operation is performed according to the second voltage boundary between the logical states without performing an erase operation on the portion of the memory array after performing the write operation according to the first voltage boundary between the logical states.

3. The device according to claim 1, wherein: The first voltage boundary between logic states is associated with a first reference voltage used to distinguish between the first logic state and the second logic state. and The second voltage boundary between logic states is associated with a second reference voltage that is higher than the first reference voltage and is used to distinguish between the first logic state and the second logic state.

4. The device according to claim 1, wherein: The first voltage boundary between logic states is associated with a first voltage used to write the logic state; and The second voltage boundary between logic states is associated with a second voltage used to write the logic state, the second voltage being higher than the first voltage used to write the logic state.

5. The device of claim 1, wherein the write operation based on the first voltage boundary between logic states and the write operation based on the second voltage boundary between logic states are each associated with writing the same number of logic states.

6. The device of claim 1, wherein the portion of the memory array comprises NAND memory cells.

7. The device of claim 1, wherein, in order to perform the write operation based on the second voltage boundary between logic states, the controller is configured to cause the device to: The indication of the second voltage boundary between the signaling and logic state, including the second information, is transmitted to the memory device.

8. The device of claim 1, wherein the controller is further configured to cause the device to: The storage indicates that the portion of the memory array has been written according to the second voltage boundary between logical states.

9. The device of claim 1, wherein the controller is configured to cause the device to: The determination to overwrite the portion of the memory array is based at least in part on the first information, the second information, or both, in association with write boost information, parity information, or logical-to-physical address information.

10. The device of claim 1, wherein the controller is configured to cause the device to: The determination to overwrite the portion of the memory array is based at least in part on a validity indication associated with the first information or the portion of the memory array.

11. The device of claim 1, wherein the controller is further configured to cause the device to: Determine parameters associated with enabling the portion of the memory array for overwrite operations, wherein the determination to overwrite the portion of the memory array is based at least in part on the determined parameters.

12. The device of claim 1, wherein the controller is further configured to cause the device to: The portion of the memory array is determined at least in part based on the proportion of the portion of the memory array associated with valid data.

13. The device of claim 12, wherein the controller is further configured to cause the device to: The second portion of the memory array is determined at least in part based on the proportion of the second portion of the memory array associated with valid data; Read the second information from the determined second portion of the memory array; and After the second information is written to the portion of the memory array, an erase operation is performed on the second portion of the memory array.

14. An apparatus comprising: Memory array; and A controller, coupled to the memory array and configured to cause the device to: Receive signaling to write first information into a portion of the memory array; At least in part, based on the fact that the portion of the memory array is written with second information according to a second voltage boundary for writing a number of logic states, a first voltage boundary for writing the number of logic states to the portion of the memory array is determined, the second voltage boundary being different from the first voltage boundary for writing the number of logic states. and The first information is written to the portion of the memory array according to the determined first voltage boundary for writing the number of logic states.

15. The device of claim 14, wherein the controller is configured to cause the device to: Without performing an erase operation on the portion of the memory array after the second information has been written to that portion, the first information is written to that portion of the memory array.

16. The device of claim 14, wherein the controller is further configured to cause the device to: The portion of the memory array is determined to be written with the second information according to the second voltage threshold, based at least in part on an indication associated with the signaling that writes the first information to the portion of the memory array, wherein the first voltage threshold for writing the number of logic states is determined at least in part on the indication associated with the signaling.

17. The device of claim 14, wherein the controller is further configured to cause the device to: Based at least in part on an indication stored at the device and associated with the portion of the memory array, it is determined that the portion of the memory array is written with the second information according to the second voltage boundary, wherein the first voltage boundary for determining the number of logic states to be written is based at least in part on the indication stored at the device.

18. The device of claim 14, wherein, in order to determine the first voltage threshold for writing the logic state, the controller is configured to cause the device to: A first voltage is determined for writing a logic state to the portion of the memory array, wherein the first voltage is different from a second voltage for writing the logic state associated with a second voltage boundary for writing the logic state.

19. An apparatus comprising: A memory device, comprising a memory array; and A controller, coupled to the memory device and configured to cause the device to: Receive a read command from the host device to read a portion of the memory array that has been written with a number of logical states; Determine whether the portion of the memory array is written with the number of logic states based on a first voltage boundary between logic states or a second voltage boundary between the logic states; and Signaling to read the portion of the memory array is transmitted to the memory device, wherein the signaling includes an indication of the portion of the memory array and an indication of whether the portion of the memory array is written with the number of logic states according to a first voltage boundary between the logic states or according to a second voltage boundary between the logic states that is different from the first voltage boundary between the logic states.

20. The device of claim 19, wherein, in order to determine whether the portion of the memory array is written with the number of logic states according to a first voltage boundary between logic states or a second voltage boundary between the logic states, the controller can be configured to cause the device to: Determine the number of write operations performed on the portion of the memory array since the previous erase operation on that portion.

21. An apparatus comprising: Memory array; and A controller, coupled to the memory array and configured to cause the device to: Receive signaling from the controller of the memory system to read information from a portion of the memory array that has been written with a number of logical states; The selection is made between a first read voltage boundary and a second read voltage boundary, based at least in part on whether the portion of the memory array is written with the number of logical states according to a first voltage boundary between logical states or according to a second voltage boundary between logical states that is different from the first voltage boundary between logical states. and A read operation is performed on a portion of the memory array, at least in part, based on either the selected first read voltage threshold or the selected second read voltage threshold.

22. The device of claim 21, wherein, in order to determine whether to perform a read operation based on a first voltage boundary between the logic states or a second voltage boundary between the logic states, the controller is configured to cause the device to: Determine the number of write operations performed on the portion of the memory array since the previous erase operation on that portion.

23. The device of claim 21, wherein the controller is configured to cause the device to: The read operation is determined, at least in part, based on the indication of the received signaling, whether to perform the read operation according to the first voltage boundary between the logical states or according to the second voltage boundary between the logical states.

24. The device of claim 21, wherein the controller is configured to cause the device to: The read operation is determined, at least in part, based on an indication stored at the device and associated with the portion of the memory array, whether it is performed according to the first voltage boundary between the logical states or according to the second voltage boundary between the logical states.

25. The device of claim 21, wherein, in order to determine whether to perform a read operation based on a first voltage boundary between the logic states or a second voltage boundary between the logic states, the controller is configured to cause the device to: Determine whether to use a first reference voltage to distinguish between the first logic state and the second logic state, or a second reference voltage to distinguish between the first logic state and the second logic state.

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