Fast programming using early cache register release in memory subsystems

Abstract

The present application relates to fast programming in a memory subsystem using early cache register release. Control logic in a memory device initiates a fast programming operation to program a group of memory cells to a target programming level from a set of programming levels. A set of data associated with the fast programming operation is stored in a cache register. At a first time during execution of the fast programming operation, a prediction operation is performed to determine a predicted result corresponding to a programming state of the group of memory cells. The predicted result is compared to a threshold level to determine whether a condition is satisfied. In response to satisfying the condition, the set of data is caused to be released from the cache register.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to fast programming in memory subsystems using early cache register deallocation. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally speaking, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] According to aspects of the present disclosure, a memory device is provided. The memory device includes: a memory array including a group of memory cells configured as a multi-level cell (MLC) memory; and control logic operably coupled to the memory array, the control logic configured to perform operations including: initiating a fast programming operation to program the group of memory cells to a target programming level among a group of programming levels; storing a group of data associated with the fast programming operation in a cache register; at a first time during execution of the fast programming operation, performing a prediction operation to determine a predicted result corresponding to a programming state of the group of memory cells; comparing the predicted result to a threshold level to determine whether a condition is satisfied; and causing the group of data associated with the fast programming operation to be released from the cache register in response to the condition being satisfied.

[0004] According to another aspect of the present disclosure, a method is provided. The method includes: initiating a first fast programming operation to program a group of memory cells of a memory array of a memory device to a target programming level among a group of programming levels; storing a first set of data associated with the first fast programming operation in a cache register; performing a prediction operation by a processing device at one or more checkpoints during execution of the first fast programming operation to determine a predicted result corresponding to a programming state of the group of memory cells; comparing the predicted result to a threshold level to determine whether a condition is satisfied; causing the first set of data associated with the first fast programming operation to be released from the cache register in response to the condition being satisfied; and loading a second set of data associated with a second fast programming operation to be applied to the memory array into the cache register.

[0005] According to another aspect of the present disclosure, a memory device is provided. The memory device includes: a memory array including a group of memory cells; and control logic operably coupled to the memory array, the control logic configured to perform operations including: initiating a first fast programming operation to program the group of memory cells to a target programming level among a group of programming levels; storing a first set of data associated with the first fast programming operation in a cache register; performing a prediction operation at one or more checkpoints during execution of the first fast programming operation to determine a predicted result corresponding to a programming state of the group of memory cells; comparing the predicted result to a threshold level to determine whether a condition is satisfied; causing the first set of data associated with the first fast programming operation to be released from the cache register in response to the condition being satisfied; and loading a second set of data associated with a second fast programming operation to be applied to the memory array into the cache register. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1A An example computing system including a memory subsystem in accordance with some embodiments is described.

[0008] Figure 1B is a block diagram of a memory device in communication with a memory subsystem controller of a memory subsystem according to one or more embodiments of the present disclosure.

[0009] Figures 2A to 2C According to one or more embodiments of the present disclosure, Figure 1B A schematic diagram depicting a portion of a memory cell array of a type of memory.

[0010] Figure 3 According to one or more embodiments of the present disclosure, Figure 1B A block schematic diagram of a portion of a memory cell array of the type described.

[0011] Figure 4 A comparison is illustrated of a first example timeline corresponding to ready / busy signals representing a state of a cache register associated with execution of a typical programming operation for programming a group of memory cells of a memory device and a second example timeline corresponding to ready / busy signals representing a state of a cache register associated with execution of a fast programming operation in accordance with one or more embodiments of the present disclosure.

[0012] Figure 5Example fast programming operations and multiple timelines associated with early cache register release operations according to one or more embodiments of the present disclosure are described.

[0013] Figure 6 is a flow chart of an example fast programming operation using early cache register release according to one or more embodiments of the present disclosure.

[0014] Figure 7 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0015] Aspects of the present disclosure relate to rapidly programming memory cells of a memory array of a memory device in a memory subsystem using an early cache register release operation with reduced programming time. The memory subsystem may be a memory device, a memory module, or a mixture of a memory device and a memory module. Figure 1A Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more components, such as memory devices, that store data. The host system may provide data to be stored at the memory subsystem and may request data to be retrieved from the memory subsystem.

[0016] The memory subsystem may include a high-density non-volatile memory device where it is desirable to retain data when no power is supplied to the memory device. An example of a non-volatile memory device is a NAND memory device. Figure 1A Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die can be composed of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane is composed of a set of physical blocks. Each block is composed of a set of pages. Each page is composed of a set of memory cells ("cells"). A cell is an electronic circuit that stores information. Depending on the cell type, a cell can store one or more binary bits of information and have various logical states related to the number of bits stored. The logical states can be represented by binary values ​​such as "0" and "1," or combinations of such values.

[0017] Memory cells are etched into an array of columns (also referred to below as "bit lines") and rows (also referred to below as "word lines") on a silicon wafer. A word line may refer to one or more rows of memory cells of a memory device that are used with one or more bit lines to generate an address for each of the memory cells. The intersection of a bit line and a word line constitutes the address of the memory cell.

[0018] A block, hereinafter, refers to a unit of a memory device for storing data and may include a group of memory cells, a wordline group, a wordline, or an individual memory cell. Each block may include several sub-blocks, each defined by associated pillars (e.g., vertical conductive traces) extending from a shared bitline. A memory page (also referred to herein as a "page") stores one or more binary data bits corresponding to data received from a host system. To achieve high density, a string of memory cells in a nonvolatile memory device may be constructed to include several memory cells with pillars at least partially surrounding a polysilicon channel material (i.e., a channel region). The memory cells may be coupled to access lines (i.e., wordlines) that are typically fabricated together with the memory cells to form an array of strings in a memory block (e.g., a memory array). The compact nature of certain nonvolatile memory devices, such as 3D flash NAND memory, means that wordlines are common to many memory cells within a memory block. Some memory devices use certain types of memory cells that store three bits of data in each memory cell, such as triple-level cell (TLC) memory cells, which makes it affordable to move more applications from legacy hard drives to newer memory subsystems, such as NAND solid-state drives (SSDs).

[0019] Memory access operations (e.g., programming operations, erase operations, etc.) can be performed on memory cells by applying a word line bias voltage to the word lines to which the memory cells of a selected page are connected. For example, during a programming operation, one or more selected memory cells can be programmed by applying a programming voltage to the selected word line. In one approach, an incremental step pulse programming (ISPP) process or scheme can be used to maintain a tight cell threshold voltage distribution to achieve higher data reliability. In ISPP, a series of high amplitude pulses with voltage levels of increasing magnitude (e.g., consecutive pulses that increase by a predefined pulse step height) are applied to the word lines to which one or more memory cells are connected to gradually raise the voltage levels of the memory cells to above the word line voltage level (e.g., target programming level) corresponding to the memory access operation. The application of uniformly increasing pulses by the word line driver of the memory device enables the selected word line to be ramped up or increased to the word line voltage level (V wl ). Similarly, during execution of an erase operation, a series of voltage pulses having uniformly increasing voltage levels may be applied to the word lines to ramp the word lines to corresponding word line voltage levels.

[0020] A series of increasing voltage programming pulses is applied to a selected word line to increase the charge level of certain memory cells connected to that word line, thereby increasing the threshold voltage of those memory cells. After each programming pulse, or after several programming pulses, a program verify operation is performed to determine whether the threshold voltage of one or more memory cells has increased to the desired programming level. For example, the value of the programming pulses may be incrementally increased (e.g., by a step voltage value, such as 0.33V) to increase the charge stored on the charge storage structure corresponding to each pulse. The memory device can reach a target programming level voltage for a particular programming level by incrementally storing or increasing the amount of charge corresponding to the programming step voltage.

[0021] According to this method, a series of programming pulses and program verification operations are applied to sequentially program each programming level (e.g., programming levels L1 to L7 for TLC memory cells). For example, this method sequentially programs the levels of memory cells (e.g., L1 to L7) by applying a first set of pulses to program level L1 cells to a first target voltage level, then applying a second set of pulses to program level L2 cells to a second target voltage level, and so on until cells at all levels are programmed.

[0022] In this approach, each level may require multiple programming pulses and program-verify operations to reach the target programming voltage associated with the corresponding programming level. Consequently, this results in a long programming time (e.g., the time from the initial programming pulse to reaching the program-verify threshold voltage, also referred to as "Tprog") associated with one or more memory cells. For example, programming each level of TLC memory cells (e.g., programming levels L1 to L7) one at a time requires a large number of total programming pulses (e.g., approximately 24 pulses) and a large number of associated program-verify operations (e.g., approximately 42 program-verify operations). In this example, if the time associated with each pulse is 37.5 μs, the total time for a set of pulses (i.e., 24 pulses) may be approximately 900 μs. Additionally, the time associated with performing the program-verify operation may add an additional 900 μs, resulting in a total programming time (Tprog) of, for example, 1800 μs.

[0023] During execution of the programming algorithm, the system controller detects completion of the programming cycle by monitoring the ready / busy (RB) pin of the status register to detect a ready / busy signal (also referred to as an "RB signal") indicating the ready / busy status of a cache register in a page buffer of the memory device. The ready / busy signal may have a first value (e.g., "0") indicating a busy status indicating that the cache register is busy and cannot accept new data due to an ongoing or current memory access operation. When the cache register has the busy status, new data associated with the next memory access operation (e.g., the next programming operation) must wait and cannot be loaded into the cache register. After the programming algorithm is completed, the cache register is released so that the data stored in the cache register is released (i.e., removed or deleted) and the ready / busy signal is updated to a second value (e.g., "1") indicating a ready status indicating that the cache register is ready to accept new data (e.g., data associated with the next memory access operation).

[0024] Typically, the cache register is released after both the programming phase (i.e., application of all programming loops) including the final programming pulse (also referred to as "programming pulse N," where N is the total number of programming pulses in the programming operation) and the voltage release phase, in which the internal voltage is released, are completed. Therefore, the ready / busy signal remains in a busy state until the entire programming algorithm is completed, thereby preventing new data associated with the next memory access operation from being loaded into the cache register.

[0025] Some systems use cache programming operations to improve bus efficiency. Cache programming operations use cache registers with a set page size to program data pages within a block. Cache programming operations allow data associated with a programming operation (i.e., data to be programmed into a page of the memory device) to be inserted into the cache registers while the data registers are copied into the memory array. Cache programming operations include multiple data input breakpoints at which data can be input into the memory page. Using cache programming operations, initially, data is copied into the cache registers. At a checkpoint, the data is transferred to the data registers. Next, when the RB output returns to the ready (high) state, the page data is programmed from the data registers into the memory array. When the RB output returns to the ready state, another command can be issued to write the new data to the cache registers. However, in doing so, the new data is committed to the memory array before the programming state (e.g., the verify state) of the previous data set is known or established. Therefore, when a failure occurs with respect to programming of a subsequent memory page, data corresponding to a previous page has already been committed and the previous data has been overwritten in the cache register, resulting in data recovery problems and performance degradation.

[0026] According to a typical programming algorithm, sometime before the programming operation is complete (e.g., 50 μs to 100 μs), the memory cell has substantially reached its final position within the target programming distribution, and the status of the programming operation is established (e.g., it is known or established whether the memory cell has passed programming or failed programming, as determined by a program verify operation). After this, a program comprising a final programming pulse (PP N ), and a voltage release phase is performed to release all internal voltages in preparation for the next memory access operation. However, even if the programmed state is substantially known or established before the programming cycle is complete, the cache register is not released until after all programming cycles, including the final programming pulse (also referred to as "program pulse N," where N is the total number of programming pulses in the programming cycle) and the voltage release phase, are complete. Thus, the longer programming time associated with the results of the current programming operation and the release of the cache register after the entire current programming operation is completed prevent new data associated with the next programming operation from being stored in the cache register.

[0027] Aspects of the present disclosure relate to programming operations, including an early or premature release of a cache register (also referred to as a "fast programming operation") in response to satisfying a condition associated with a prediction operation associated with a current or ongoing programming operation (also referred to as a "prediction condition"). In one embodiment, a prediction operation (e.g., a predictive count fail bytes (CFBYTE) operation) is performed to generate a prediction result indicating a predicted state of the current programming operation (e.g., a pass or fail state associated with corresponding memory cells being programmed). In one embodiment, the prediction condition is satisfied if the prediction level associated with the current programming operation reaches or exceeds a threshold level. In one embodiment, the prediction level or prediction result represents a predicted level or amount of memory cells that will pass or fail program verify in a current programming cycle (e.g., a programming pulse and one or more program verify operations). In one embodiment, the early cache register release is performed after the prediction condition is satisfied (i.e., the predicted state of the amount of memory cells programmed by the current programming operation is above the threshold level). In an embodiment, early cache register release includes the release or removal of a set of data associated with the current programming operation from the cache register and the updating of the ready / busy signal from a busy signal value (i.e., busy state) to a ready signal value (i.e., ready state), and the associated cache register is released so that new data associated with the next memory access command can be stored in the cache register.

[0028] Advantageously, the fast programming operation of the present disclosure includes the use of a predictive condition to cause the cache register to be released before the current or ongoing programming operation is completed. The early release of the cache register (i.e., before the completion of one or more final programming pulses and the voltage release phase) enables a reduction in programming time compared to typical programming algorithms. In addition, after the early release of the cache register, new data corresponding to the next programming operation can be stored in the cache register, allowing the next programming operation to be initiated and executed upon completion of the previous programming operation. The next programming operation can be initiated and executed in parallel with the ongoing programming operation after the early release of the cache register. Thus, bus efficiency is improved because a new command associated with the next programming operation can be issued, and the new data can be stored in the cache register in parallel with the completion of the remaining programming and voltage release phases of the previous programming operation.

[0029] Figure 1A An example computing system 100 is illustrated that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such things.

[0030] The memory subsystem 110 can be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital drives (SDs), and hard disk drives (HDDs). Examples of memory modules include dual inline memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual inline memory modules (NVDIMMs).

[0031] Computing system 100 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (such as an airplane, drone, car, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0032] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1AAn example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0033] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0034] The host system 120 can be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM slot interface supporting Double Data Rate (DDR)), and the like. The physical host interface can be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 via a physical host interface (e.g., a PCIe bus), the host system 120 can further utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface can provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1A Memory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0035] Memory devices 130 and 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices, such as memory device 140, may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0036] Some examples of nonvolatile memory devices (e.g., memory device 130) include NAND-type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of nonvolatile memory cells. Cross-point arrays of nonvolatile memory can perform bit storage based on bulk resistance changes in conjunction with a stackable crossbar-style data access array. Thus, in contrast to many flash-based memories, cross-point nonvolatile memory can perform write-in-place operations, where nonvolatile memory cells can be programmed without previously erasing the nonvolatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0037] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion and an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells. The memory cells of the memory devices 130 may be grouped into pages, which may refer to a logical unit of a memory device for storing data. For some types of memory (such as NAND), pages may be grouped to form blocks. In one embodiment, the term "MLC memory" may be used to refer to any type of memory cell that stores more than one bit per cell (e.g., 2 bits, 3 bits, 4 bits, or 5 bits per cell).

[0038] Although nonvolatile memory components such as a 3D cross-point array of nonvolatile memory cells and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), "NOR" (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0039] The memory subsystem controller 115 (or, for simplicity, the controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 can include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic for performing the operations described herein. The memory subsystem controller 115 can be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0040] The memory subsystem controller 115 may be a processing device including one or more processors (e.g., processor 117) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0041] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1A The example memory subsystem 110 in FIG. 1 is illustrated as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0042] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120 and convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical block addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access the memory device 130, and also convert responses associated with the memory device 130 into information for the host system 120.

[0043] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0044] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) can externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device that includes a raw memory device 130 with on-die control logic (e.g., local media controller 135) and a controller for media management (e.g., memory subsystem controller 115) within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0045] In one embodiment, the memory subsystem 110 includes a memory interface component 113. The memory interface component 113 is responsible for handling the interaction between the memory subsystem controller 115 and the memory devices of the memory subsystem 110, such as the memory device 130. For example, the memory interface component 113 may send memory access commands corresponding to requests received from the host system 120, such as program commands, read commands, or other commands, to the memory device 130. In addition, the memory interface component 113 may receive data from the memory device 130, such as data retrieved in response to a read command or confirmation that a program command was successfully executed. For example, the memory subsystem controller 115 may include a processor 117 (processing device) configured to execute instructions stored in the local memory 119 to perform the operations described herein.

[0046] In one embodiment, memory device 130 includes a program manager 134 configured to perform corresponding memory access operations in response to receiving memory access commands from memory interface 113. In some embodiments, local media controller 135 includes at least a portion of program manager 134 and is configured to perform the functionality described herein. In some embodiments, program manager 134 is implemented on memory device 130 using firmware, hardware components, or a combination thereof. In one embodiment, program manager 134 receives a request from a requester (e.g., memory interface 113) to program data into a memory array of memory device 130. The memory array may include an array of memory cells formed at the intersection of word lines and bit lines. In one embodiment, for example, memory cells are grouped into blocks, which are further divided into sub-blocks, where a given word line is shared across several sub-blocks. In one embodiment, each sub-block corresponds to a separate plane in the memory array. A group of memory cells associated with a word line within a sub-block is referred to as a physical page. In one embodiment, there may be multiple portions of a memory array, such as a first portion in which sub-blocks are configured as SLC memory and a second portion in which sub-blocks are configured as multi-level cell (MLC) memory (i.e., including memory cells that can store two or more bits of information per cell). For example, the second portion of the memory array may be configured as TLC memory. The voltage levels of the memory cells in the TLC memory form a set of eight programming distributions representing eight different combinations of three bits stored in each memory cell. Depending on how they are configured, each physical page in one of the sub-blocks may include multiple page types. For example, a physical page formed of single-level cells (SLC) has a single page type called a lower logical page (LP). Multi-level cell (MLC) physical page types may include an LP and an upper logical page (UP), TLC physical page types are LP, UP, and an extra logical page (XP), and QLC physical page types are LP, UP, XP, and a top logical page (TP). For example, a physical page formed of memory cells of the QLC memory type may have a total of four logical pages, where each logical page may store data that is different from data stored in other logical pages associated with that physical page.

[0047] In one embodiment, program manager 134 may receive data to be programmed into memory device 130 (eg, a TLC memory device) and store the data in a cache register (eg, Figure 1B). Thus, program manager 134 can perform a fast programming operation to program a group of memory cells in memory cell array 150 of memory devices 130, 140, wherein the cache register is released in response to a condition associated with the prediction operation being satisfied (i.e., the cache register is cleared and can receive and store new data associated with the next programming operation and the ready / busy signal is updated to the ready signal value). At one or more checkpoints during an ongoing or current programming operation, a prediction operation is performed to generate a prediction result representing the level (e.g., the number, quantity, percentage, etc.) of a group of memory cells predicted to pass or fail program verification in the next or current programming cycle based on information associated with a previous programming cycle. Program manager 134 checks to determine whether the condition is satisfied by comparing the prediction result to a threshold level. In one embodiment, the condition is satisfied when the prediction result (e.g., the level of the memory cells predicted to pass or fail verification in the next programming cycle) is greater than or equal to the threshold level. In one embodiment, the threshold level can be established to achieve a program prediction that meets a target or desired bit error rate (BER) or other reliability metric. In one embodiment, program manager 134 may tune or adjust the threshold level to have a first level (e.g., threshold level X) corresponding to a first BER level. In this embodiment, program manager 134 may determine that the prediction condition using the first level has been met approximately after the last or final program verify operation is completed but before the final program pulse and voltage release phase (e.g., approximately 50 μs before the completion of the programming operation). Advantageously, using a fast programming operation that includes an early or premature release of the cache register in response to the prediction condition using the first threshold level may result in a reduction in programming time of approximately 50 μs.

[0048] In one embodiment, program manager 134 may tune the threshold level to have a different threshold level (e.g., threshold level Y) corresponding to the second BER level. In this embodiment, program manager 134 may determine that the prediction condition using the second level is satisfied approximately sometime after program loop N-1 of a program operation having a total of N program loops is completed. In this embodiment, early release of the cache register (e.g., after the prediction condition is satisfied based on threshold level Y) results in an approximately reduced programming time corresponding to the final program loop (e.g., a program pulse and program verify operation), the final program pulse, and the voltage release time (e.g., a reduction of approximately 100 μs in programming time).

[0049] Advantageously, updating the signal to the ready signal value before the ongoing programming operation is completed enables loading new data for the next programming operation. Thus, overlapping programming operations can be performed after early release of the cache register. Further details on the operation of program manager 134 are described below.

[0050] Figure 1B is in accordance with an embodiment and presents a memory subsystem (eg Figure 1A 1 is a simplified block diagram of a first device in the form of a memory device 130 communicating with a second device in the form of a memory subsystem controller 115 of a memory subsystem 110. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, game consoles, home appliances, vehicles, wireless devices, mobile phones, and the like. Memory subsystem controller 115 (e.g., a controller external to memory device 130) may be a memory controller or other external host device.

[0051] Memory device 130 includes a memory cell array 150 that is logically arranged in rows and columns. Memory cells in a logical row are typically connected to the same access line (e.g., a word line), while memory cells in a logical column are typically selectively connected to the same data line (e.g., a bit line). A single access line can be associated with more than one logical row of memory cells, and a single data line can be associated with more than one logical column. Memory cells ( Figure 1B ) can be programmed to one of at least two target data states.

[0052] Row decoding circuitry 108 and column decoding circuitry 110 are provided to decode address signals. Address signals are received and decoded to access memory cell array 150. Memory device 130 also includes input / output (I / O) control circuitry 112 to manage the input of commands, addresses, and data to memory device 130, as well as the output of data and status information from memory device 130. Address registers 114 communicate with I / O control circuitry 112 and row decoding circuitry 108 and column decoding circuitry 110 to latch address signals prior to decoding. Command registers 124 communicate with I / O control circuitry 112 and local media controller 135 to latch incoming commands.

[0053] A controller, such as a local media controller 135 within the memory device 130, controls access to the memory cell array 150 in response to commands and generates status information for the external memory subsystem controller 115. That is, the local media controller 135 is configured to perform access operations (such as read operations, program operations, and / or erase operations) on the memory cell array 150. The local media controller 135 communicates with the row decoding circuitry 108 and the column decoding circuitry 110 to control the row decoding circuitry 108 and the column decoding circuitry 110 in response to addresses. In one embodiment, the local media controller 135 includes a program manager 134 that can implement full-level programming of the memory device 130, as described herein.

[0054] The local media controller 135 also communicates with the cache registers 118. The cache registers 118 latch incoming or outgoing data to temporarily store the data while the memory cell array 150 is busy writing or reading other data, respectively, according to the direction of the local media controller 135. During a programming operation (e.g., a write operation), data can be transferred from the cache registers 118 to the data registers 120 for transmission to the memory cell array 150; then, the new data can be latched in the cache registers 118 from the I / O control circuitry 112. During a read operation, data can be transferred from the cache registers 118 to the I / O control circuitry 112 for output to the memory subsystem controller 115; then, the new data can be transferred from the data registers 120 to the cache registers 118. The cache registers 118 and / or the data registers 120 can form (e.g., can form part of) a page buffer for the memory device 130. The page buffer may further include a sensing device ( ) for sensing the data state of a memory cell in the memory cell array 150, for example, by sensing the state of a data line connected to the memory cell. Figure 1B 1 . Status register 122 may communicate with I / O control circuitry 112 and local media controller 135 to latch status information for output to memory subsystem controller 115.

[0055] Memory device 130 receives control signals from memory subsystem controller 115 via control link 132 from a local media controller 135. For example, the control signals may include chip enable signal CE#, command latch enable signal CLE, address latch enable signal ALE, write enable signal WE#, read enable signal RE#, and write protect signal WP#. Additional or alternative control signals (not shown) may be received via control link 132 depending on the nature of memory device 130. In one embodiment, memory device 130 receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from memory subsystem controller 115 via a multiplexed input / output (I / O) bus 136 and outputs the data to memory subsystem controller 115 via I / O bus 136.

[0056] For example, a command may be received at I / O control circuitry 112 via input / output (I / O) pins [7:0] of I / O bus 136 and then written to command register 124. An address may be received at I / O control circuitry 112 via input / output (I / O) pins [7:0] of I / O bus 136 and then written to address register 114. Data may be received at I / O control circuitry 112 via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices and then written to cache register 118. The data may then be written to data register 120 to program memory cell array 150.

[0057] In an embodiment, cache register 118 may be omitted and data may be written directly to data register 120. Data may also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. Although reference may be made to I / O pins, these may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that provide electrical connection to memory device 130 by an external device (e.g., memory subsystem controller 115).

[0058] It will be appreciated by those skilled in the art that additional circuitry and signals may be provided and that the Figure 1B It will be appreciated that the reference Figure 1B The functionality of the various block components described may not necessarily be separated into distinct components or component portions of an integrated circuit device. For example, a single component or component portion of an integrated circuit device may be adapted to perform Figure 1B Alternatively, one or more components or component parts of an integrated circuit device may be combined to perform Figure 1B Additionally, while specific I / O pins are described according to popular conventions for receiving and outputting various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0059] Program manager 134 communicates with cache registers 118. Cache registers 118 latch incoming or outgoing data to temporarily store data while memory cell array 150 is busy writing or reading other data, respectively, according to the direction of program manager 134. During a programming operation, data is transferred from cache registers 118 to data registers 120 for transmission to memory cell array 150; the new data is then latched into cache registers 118 from I / O control circuitry 112. Status registers 122 communicate with I / O control circuitry 112 and program manager 134 to latch status information for output to memory subsystem controller 115.

[0060] Status register 122 includes a ready / busy (R / B) register. For example, a 1-bit register may be used to indicate whether memory device 100 is busy (e.g., memory device 130 is currently performing a memory access operation) or ready (e.g., memory device 130 has completed performing a memory access operation or is not currently performing a memory access operation). Status register 122 may further include a cache ready / busy register. For example, a 1-bit register may be used to indicate whether cache register 118 is ready to accept new data (e.g., data has been transferred to data register 120 for writing to memory cell array 150 or I / O control circuitry 112). Thus, reading status register 122, for example, by a controller (e.g., local media controller 135), may be used to determine whether memory device 100 is involved in an access operation, e.g., whether the memory device is ready to initiate an access operation or whether cache register 118 is ready to accept data input. The controller may be an external controller (e.g., memory subsystem controller 115) or an internal controller (e.g., local media controller 135 including program manager 134).

[0061] In one embodiment, the programming manager 134 of the local media controller 135 can provide an R / B signal to provide an external controller and / or host system with an indication of whether the memory device 100 is involved in an access operation or otherwise busy. For example, memory devices typically provide a pin (e.g., a pin of the control link 132) that is asserted to a logic low when the device is involved in an access operation and pulled up to a logic high when the device is available again (e.g., not involved in an access operation). The indication of the ready / busy signal can depend on the access operation being performed by the memory device 130.

[0062] Figures 2A to 2C is according to the embodiment as can be used for reference Figure 1BSchematic diagram of a portion of a memory cell array 200A (e.g., a NAND memory array) in a memory of the type described (e.g., as part of memory cell array 150). Memory array 200A includes access lines (e.g., word lines 2020 through 2021). N ) and data lines (eg, bit lines 2040 to 204 M ). The word lines 202 may be connected to the Figure 2A For some embodiments, memory array 200A may be formed on a semiconductor, which may be conductively doped to have a certain conductivity type (e.g., p-type conductivity, such as for forming a p-well, or n-type conductivity, such as for forming an n-well).

[0063] The memory array 200A can be arranged into rows (each corresponding to a word line 202) and columns (each corresponding to a bit line 204). Each column can include a string of memory cells (eg, nonvolatile memory cells) connected in series, such as NAND strings 2060-206 M Each NAND string 206 can be connected (eg, selectively connected) to a common source (SRC) 216 and can include memory cells 2080-208 N The memory cells 208 may represent non-volatile memory cells for data storage. The memory cells 208 of each NAND string 206 may be connected in series to a select gate 210 (eg, a field effect transistor) (eg, select gates 2100 to 2101). M One of the transistors (eg, which may be a source select transistor, often referred to as a select gate source) and a select gate 212 (eg, a field effect transistor) (eg, select gates 2120 to 212 M One of the select gates 2100 to 210 is connected to the select gate 2100. M The gates 2120 to 2121 may be connected in common to a select line 214 (eg, a source select line (SGS)). M 2 and 3. The select gates 210 and 212 may be commonly connected to a select line 215 (e.g., a drain select line (SGD)). Although depicted as conventional field effect transistors, the select gates 210 and 212 may utilize a similar (e.g., identical) structure as the memory cell 208. The select gates 210 and 212 may represent a plurality of select gates connected in series, wherein each select gate in the series is configured to receive the same or an independent control signal.

[0064] The source of each select gate 210 can be connected to a common source 216. The drain of each select gate 210 can be connected to a memory cell 2080 of a corresponding NAND string 206. For example, the drain of select gate 2100 can be connected to a memory cell 2080 of a corresponding NAND string 2060. Thus, each select gate 210 can be configured to selectively connect a corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 can be connected to a select line 214.

[0065] The drain of each select gate 212 can be connected to the bit line 204 of the corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to the bit line 2040 of the corresponding NAND string 2060. The source of each select gate 212 can be connected to the memory cell 208 of the corresponding NAND string 206. N For example, the source of the select gate 2120 may be connected to the memory cell 208 of the corresponding NAND string 2060. N Thus, each select gate 212 can be configured to selectively connect a corresponding NAND string 206 to a corresponding bit line 204 . The control gate of each select gate 212 can be connected to a select line 215 .

[0066] Figure 2A The memory array 200A in can be a quasi-two-dimensional memory array and can have a generally planar structure, for example, where the common source 216, NAND strings 206, and bit lines 204 extend in substantially parallel planes. Alternatively, Figure 2A The memory array 200A in FIG. 2 can be a three-dimensional memory array, for example, where the NAND strings 206 can extend substantially perpendicular to a plane containing the common source 216 and can extend substantially parallel to a plane containing the bit lines 204 .

[0067] The typical structure of the memory cell 208 includes a data storage structure 234 (e.g., a floating gate, a charge trap, and the like) that can determine the data state of the memory cell (e.g., by a change in threshold voltage), and a control gate 236, such as Figure 2A . The data storage structure 234 may include both conductive and dielectric structures, while the control gate 236 is typically formed of one or more conductive materials. In some cases, the memory cell 208 may further have a defined source / drain (e.g., source) 230 and a defined source / drain (e.g., drain) 232. The memory cell 208 has its control gate 236 connected to (and in some cases forming) the word line 202.

[0068] A column of memory cells 208 may be a NAND string 206 or several NAND strings 206 that are selectively connected to a given bit line 204. A row of memory cells 208 may be the memory cells 208 that are commonly connected to a given word line 202. A row of memory cells 208 may, but need not, include all of the memory cells 208 that are commonly connected to a given word line 202. Rows of memory cells 208 may generally be divided into physical pages of one or more groups of memory cells 208, and a physical page of memory cells 208 generally includes every other memory cell 208 that is commonly connected to a given word line 202. For example, a physical page of memory cells 208 may be commonly connected to a word line 202. N The memory cells 208 selectively connected to the even bit lines 204 (eg, bit lines 2040, 2042, 2044, etc.) may be memory cells 208 (eg, even memory cells) of one physical page, and are commonly connected to the word line 202. N The memory cells 208 selectively connected to the odd bit lines 204 (eg, bit lines 2041 , 2043 , 2045 , etc.) may be memory cells 208 of another physical page (eg, odd memory cells).

[0069] Despite Figure 2A The bit lines 2043 to 2045 are not explicitly depicted in the figure, but it is obvious from the figure that the bit line 204 of the memory cell array 200A can be from the bit line 2040 to the bit line 204. M 202. The memory cells 208 of other groups commonly connected to a given word line 202 may also define a physical page of memory cells 208. For a particular memory device, all memory cells commonly connected to a given word line may be considered a physical page of memory cells. The portion of a physical page of memory cells (which may still be an entire row in some embodiments) that is read during a single read operation or programmed during a single program operation (e.g., an upper page or lower page of memory cells) may be considered a logical page of memory cells. A block of memory cells may include those memory cells that are configured to be erased together, such as those connected to word lines 2020 through 202. N Unless explicitly distinguished, references herein to a page of memory cells refer to the memory cells of a logical page of memory cells. Figure 2A The examples are discussed in conjunction with NAND flash, but the embodiments and concepts described herein are not limited to a particular array architecture or structure and may include other structures (e.g., SONOS, phase change, ferroelectric, etc.) and other architectures (e.g., AND arrays, NOR arrays, etc.).

[0070] Figure 2B Is available for reference Figure 1BAnother schematic diagram of a portion of a memory cell array 200B (eg, as part of memory cell array 150) in a memory of the type described. Figure 2B Like numbered elements in FIG. 1 correspond to those in FIG. 1 and FIG. 2 . Figure 2A Description provided. Figure 2B Additional details are provided for one example of a three-dimensional NAND memory array structure. The three-dimensional NAND memory array 200B can incorporate a vertical structure that can include semiconductor pillars, where a portion of the pillars can serve as a channel region for the memory cells of the NAND string 206. Each of the NAND strings 206 can be selectively connected to bit lines 2040 through 2044 through a select transistor 212 (e.g., which can be a drain select transistor, often referred to as a select gate drain). M The plurality of NAND strings 206 can be selectively connected to the same bit line 204. A subset of the NAND strings 206 can be selectively connected to the common source 216 by biasing the select lines 2150 to 2155. K Each particular select transistor 212 between the NAND string 206 and the bit line 204 is selectively activated to connect to its corresponding bit line 204. The select transistors 210 can be activated by biasing the select line 214. Each word line 202 can be connected to multiple rows of memory cells in the memory array 200B. The rows of memory cells commonly connected to each other by a particular word line 202 can be collectively referred to as a level.

[0071] Figure 2C Is available for reference Figure 1B Another schematic diagram of a portion of a memory cell array 200C (eg, as part of memory cell array 150) in a memory of the type described. Figure 2C Like numbered elements in FIG. 1 correspond to those in FIG. 1 and FIG. 2 . Figure 2A The memory cell array 200C may include a memory cell string (e.g., a NAND string) 206, an access (e.g., word) line 202, a data (e.g., bit) line 204, a select line 214 (e.g., a source select line), a select line 215 (e.g., a drain select line), and a source 216 connected in series. Figure 2A For example, a portion of the memory cell array 200A may be a portion of the memory cell array 200C.

[0072] Figure 2C Depicts the grouping of NAND strings 206 into memory cell blocks 250, such as memory cell blocks 2500 to 250 LMemory cell blocks 250 may be groupings of memory cells 208 that may be erased together in a single erase operation, sometimes referred to as erase blocks. Each block of memory cells 250 may represent those NAND strings 206 that are typically associated with a single select line 215 (e.g., select line 2150). The sources 216 for a memory cell block 2500 may be the same as the source lines for the memory cell block 250. L For example, each memory cell block 2500 to 250 L Typically, the access line 202 and the select lines 214 and 215 of a memory cell block 250 may not be directly connected to the memory cell blocks 250 to 250, respectively. L The access line 202 and the select lines 214 and 215 of any other memory cell block are connected.

[0073] Bit lines 2040 to 204 M The memory device 130 may be connected (eg, selectively connected) to a buffer portion 240, which may be part of a page buffer 152 of the memory device 130. The buffer portion 240 may correspond to a memory plane (eg, a group of memory cell blocks 2500 to 250 L ). Buffer portion 240 may include sensing circuitry (which may include a sense amplifier) ​​to sense the data value indicated on the corresponding bit line 204.

[0074] Figure 3 Is available for reference Figure 1B Schematic diagram of a portion of a memory cell array 300 in a memory of the type described. The memory cell array 300 is depicted as having four memory planes 350 (e.g., memory planes 3500-3503), each of which communicates with a respective buffer portion 240 that may collectively form a page buffer 352. Although four memory planes 350 are depicted, other numbers of memory planes 350 may collectively communicate with the page buffer 352. Each memory plane 350 is depicted as including L+1 memory cell blocks 250 (e.g., memory cell blocks 2500-2503). L ).

[0075] Figure 4 A comparison of a first example timeline 410 corresponding to ready / busy signals representing the state of a cache register associated with execution of a typical programming operation for programming a group of memory cells of a memory device and a second example timeline 420 corresponding to ready / busy signals representing the state of a cache register associated with execution of a fast programming operation is illustrated in accordance with one or more embodiments of the present disclosure. Figure 4As shown in the timeline 410 associated with a typical programming operation, the cache register release 412 is performed at the last programming pulse (PP N ) complete and the voltage release phase complete (e.g., at Tdischarge_complete). As shown in timeline 410, the programming time (Tprog_A) extends from the start of the programming operation to the time of cache register release 412 corresponding to the completion of the programming operation (e.g., completion of the programming phase and the release phase).

[0076] In an embodiment, as compared, as shown in timeline 420 associated with the fast programming operation of the present disclosure, the early cache register release 422 is performed at least at the last programming pulse (PP) N ) complete and the voltage release phase completes (e.g., at Tdischarge_complete). In another embodiment, the early cache register release 422 occurs sometime before the last programming cycle (i.e., the programming pulse and program verify operation) completes, the last programming pulse (i.e., the PP pulse following the last programming cycle) completes, and the voltage release phase completes (e.g., at Tdischarge_complete). N ) is completed and the voltage release phase is completed. As shown in timeline 420, the advance cache register release 422 of the fast programming operation achieves a reduction in programming time (Tprog_Express) compared to Tprog_A of timeline 410. In one embodiment, the programming time reduction of Tprog_B is approximately equal to the duration from the advance cache register release 422 (i.e., Tadvanced_release) to Tdischarge_complete. In one embodiment, Tprog_Express (i.e., the programming time using the fast programming operation) can be represented by the following expression: Tprog_Express = Tprog_A - Tprog_B;

[0077] Wherein Tprog_A is a first duration from the start of the fast programming operation to when the voltage discharge is completed (ie, Tdischarge_complete), and wherein Tprog_B is a second duration from the advance cache register release 422 to Tdischarge_complete.

[0078] In an embodiment, the early cache register release 422 is triggered (at Tadvanced_release) in response to determining that a prediction condition is met, such as Figure 5 Described in more detail in .

[0079] Figure 5 An example fast programming operation and multiple timelines associated with an early cache register release operation are described. Figure 5As shown in FIG, a fast programming operation 505 is started. As illustrated, the fast programming operation 505 includes a series of programming loops (eg, programming loop 1 to programming loop N). Figure 5 As shown in FIG, each programming loop may include a program verify operation (PV) that includes a ladder or series of multiple verify voltages (eg, PV1 of programming loop 1, PV2 of programming loop 2, and PV3 of programming loop 3). 1A and PV 1B ). In an embodiment, after the fast programming operation 505 is initiated, the ready bit is updated from a first bit value (e.g., "1") indicating that the cache register is ready to store new data associated with the programming operation to a second bit value (e.g., "0") indicating that the data is already stored in the cache register and that the cache register is busy at the current time and cannot store new data. In an embodiment, a series of programming cycles are performed as part of the fast programming operation to program a group of memory cells to a target programming level from a group of programming levels.

[0080] In one embodiment, a prediction operation is performed at one or more checkpoints during a fast programming operation. In one embodiment, the prediction operation includes determining a prediction result representing a predicted level for a memory cell whose program verify state (e.g., passed or failed verification) is known (i.e., established). In one embodiment, the predicted level for the memory cell with the known verify state is compared to a threshold level to determine whether a condition is satisfied. In one embodiment, the condition is satisfied if the prediction result corresponding to the predicted program state of the memory cell is greater than or equal to the threshold level. In one embodiment, if the prediction result satisfies the condition, the fast programming operation determines that a sufficient level of reliability has been achieved with respect to the known or established program state of the memory cell.

[0081] In an embodiment, in response to determining that the condition is met, an early release of the cache register is performed (ie, the cache register is released early or before all programming pulses and voltage release phase 540 of the fast programming operation are completed). Figure 5 , a first example timeline 520 is shown in which a prediction operation applies a first threshold level to determine whether a prediction condition satisfies a prediction operation checkpoint.

[0082] Figure 5A second example timeline 530 is illustrated in which the prediction operation applies a second threshold level. For example, the second threshold level may be a metric representing the number of cells left to be programmed. It should be noted that the threshold level may be established in view of a desired or target BER level (or other reliability metric) and may have any desired value. In one embodiment, if a higher reliability level is desired with respect to the prediction operation, the first threshold level may be used to determine whether condition 1 is satisfied. In another example, if a relatively lower reliability level is desired with respect to the prediction operation (i.e., compared to a prediction operation using condition 1), the second threshold level may be used to determine whether condition 2 is satisfied.

[0083] In an embodiment, the prediction operation may be performed at any number of checkpoints corresponding to the fast programming operation. For example, the first checkpoint for the prediction operation may be established after programming loop N-5 (where N is equal to the predicted or average number of programming loops for completing the programming operation), the second checkpoint for the prediction operation may be established after programming loop N-4, and so on. In an embodiment, at each of the one or more checkpoints, a prediction operation is performed and a determination is made as to whether the prediction result satisfies a condition (i.e., whether the prediction result exceeds an applicable threshold level).

[0084] In an embodiment, the prediction result represents the number, amount, percentage, amount, etc. of memory cells that will pass or fail program verification in the current programming cycle based on the prediction. In response to determining that the prediction result satisfies a condition (e.g., condition 1 associated with threshold level 1 of timeline 520 or condition 2 associated with threshold level 2 of timeline 530), the cache register is released and new data can be loaded into the cache register (e.g., advance cache register release 522 of example timeline 520 or advance cache register release 532 of example timeline 530).

[0085] In an embodiment, the prediction operation may include a predictive count fail bytes (CFBYTE) operation. In an embodiment, the predictive CFBYTE operation determines the number of memory cells that will pass or fail verification in a current programming loop. In this embodiment, the prediction operation may determine the number of memory cells based at least in part on information from a previous programming loop. The previous programming loop was performed before the current programming loop. In an embodiment, the predictive CFBYTE operation determines a count (e.g., a predicted result) of the expected number of memory cells that exceed a threshold voltage value and compares that predicted result to an applicable threshold level (e.g., a threshold voltage). Figure 5 The threshold level 1 in the first example shown in Figure 5 ). According to an embodiment, other prediction operations may be performed to generate a prediction result to determine whether a condition is met such that an early release of a cache register may be initiated.

[0086] Figure 5 Two examples (e.g., the first example in timeline 520 and the second example in timeline 530) of applying different threshold levels during a prediction operation to determine whether corresponding conditions are met are illustrated. In the embodiment shown in timeline 520, the threshold level for the prediction operation is tuned to a threshold level of 1, corresponding to a first target or desired reliability level (e.g., a reliability level corresponding to a first desired or target BER). In the embodiment shown in timeline 530, the threshold level for the prediction operation is tuned to a threshold level of 2, corresponding to a second target or desired reliability level (e.g., a reliability level corresponding to a second desired or target BER different from the first target BER). In an embodiment, a fast programming operation may include tuning or adjusting the threshold level of the prediction operation (e.g., from threshold level 1 to threshold level 2 or vice versa) based on BER measurements associated with one or more previously performed fast programming operations. For example, if a first fast programming operation using threshold level 2 results in a first BER level that is deemed too high (e.g., based on the target or threshold BER level), processing logic may dynamically adjust or change to threshold level 1 during subsequent fast programming operations.

[0087] Advantageously, as Figure 5 As shown in the example shown in timeline 520, in response to condition 1 being satisfied due to a prediction operation, an early cache register release 522 is performed at the final programming pulse (e.g., PP Final ) and voltage release phase 540. Triggering the early cache register release 522 before all programming pulses and the voltage release phase 540 are completed results in a reduction in programming time compared to a typical programming operation that releases the cache register only after all programming pulses and the release phase.

[0088] In addition, if Figure 5 As shown in the example shown in timeline 530, in response to condition 2 being satisfied due to the prediction operation, the early cache register release 532 is performed at the end of the final programming loop (e.g., programming loop N), the end of the final programming pulse (e.g., PP Final ) and is triggered sometime before the completion of both the voltage release phase 540 and the voltage release phase 540. In an embodiment, the release of the cache register and the storage of new data associated with the next fast programming operation overlap with at least a portion of the current or ongoing fast programming operation. Thus, triggering the early cache register release 532 results in a reduction in programming time compared to a typical programming operation and enables new data (e.g., data associated with the next fast programming operation) to be stored in the cache register at Tadvanced_release2 upon completion of the ongoing fast programming operation 505.

[0089] Figure 6 is a flow chart of an example method 600 of a fast programming operation for programming a group of memory cells of a memory device in a memory subsystem according to some embodiments of the present disclosure. The method 600 may be performed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, the method 600 is performed by Figure 1A and Figure 1B The processes are executed by the programming manager 134. Although shown in a particular order or sequence, the order of the processes is modifiable unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, in various embodiments, one or more processes may be omitted. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0090] At operation 610, an operation is initiated. For example, processing logic (e.g., program manager 134) may initiate a fast programming operation to program a group of memory cells of a memory device to a target programming level in a group of programming levels. In one embodiment, the fast programming operation includes a set of programming loops (e.g., iterations of incrementally increasing programming pulses and program verification operations, e.g., 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 79, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 90, 91, 92, 93, 94, Figure 5 Programming loop 1 to programming loop N), the final or last programming pulse (e.g. Figure 5 PP Final ) and voltage release phase (e.g. Figure 5 In one embodiment, the fast programming operation is directed to one or more specific memory cell addresses. In one embodiment, the processing logic may identify a group of memory cells (e.g., Figure 1B In one embodiment, a fast programming operation is performed by programming a subset of memory cells of memory array 150, such as those memory cells associated with a particular word line or multiple word lines of memory array 150. In one embodiment, a group of memory cells is configured as MLC memory (e.g., any type of memory cell that stores more than one bit per cell, including 2 bits, 3 bits, 4 bits, or more bits per cell). In one embodiment, a command for initiating a fast programming operation is associated with a set of physical or logical addresses corresponding to the group of memory cells to be programmed. In one embodiment, processing logic identifies the group of memory cells based on the set of addresses provided as part of the command.

[0091] At operation 620, data is stored. For example, processing logic may store a set of data associated with the programming operation in a cache register. In an embodiment, the cache register stores the data and a ready bit (e.g., RB pin) of the cache register indicating that the state of the cache register is set to a "busy" bit value (e.g., the bit is set to "0" as shown in FIG. 6). Figure 4 Timeline 420 and Figure 5 5. In an embodiment, when the cache register is set to the busy bit value, the cache register is being used to store data associated with an ongoing program operation (ie, the fast program operation initiated in operation 610).

[0092] At operation 630, a result is determined. For example, processing logic may perform a prediction operation at a first time during execution of a fast programming operation to determine a predicted result corresponding to a program state of a group of memory cells. In one embodiment, the prediction result represents a level (e.g., an amount, percentage, ratio, etc.) of the group of memory cells whose program state (e.g., a pass verify state or a fail verify state) will be known or established during the current programming loop. In one embodiment, the prediction operation may be performed at one or more checkpoints during the fast programming operation (e.g., after programming loop X-1, after programming loop X, after programming loop X+1, etc., where X is any non-zero integer). For example, the prediction operation may be performed after programming loop X-1, such that the prediction result provides a predicted level of the group of memory cells that will have a known or established program state (e.g., a pass or fail state) upon completion of programming loop X. In this example, the prediction result representing the level of the known program state for the current programming loop (e.g., programming loop X) is based at least in part on the program state identified for one or more previous programming loops (e.g., programming loop X-1). In one embodiment, the prediction operation may be a predictive CFBYTE operation. In an embodiment, for example, the prediction operation may be implemented by measuring a precharge current associated with a program verify operation, such that if the precharge current decreases during the program verify operation, a prediction may be made that programming is about to complete.

[0093] At operation 640, a comparison is performed. For example, processing logic may compare the prediction result to a threshold level to determine whether a condition is satisfied. In one embodiment, the threshold level may represent an acceptable level of the predicted state, such that the condition is satisfied when the prediction result is greater than or equal to the threshold level. For example, the threshold level may be a percentage of a group of memory cells for which the predicted programming state is known. For example, the prediction result (e.g., a first percentage of a group of memory cells having the predicted programming state for a target programming level known based on the prediction operation) is compared to a second percentage (e.g., a Y percentage) of the threshold level, where the condition is satisfied if the first percentage is greater than or equal to the second percentage. In one embodiment, the prediction result may be based on a determination of the number of memory cells having an unprogrammed state and information identifying an average number of memory cells passed through for each programming pulse. In one embodiment, the number of cells to be programmed (e.g., the number of unprogrammed cells) is measured and compared to a threshold number to determine whether the condition is satisfied. In one embodiment, the condition is satisfied when the number of unprogrammed cells is less than a maximum acceptable value.

[0094] In embodiments, the threshold level may be established based at least in part on a desired or target BER level or other reliability metric. In embodiments, the threshold level may be established or dynamically tuned in view of a reliability metric (e.g., BER) associated with the memory subsystem. For example, a BER level may be determined based on the execution of a first fast programming operation, and that BER level may be used to adjust or tune a threshold level associated with a predicted operation of a next or second fast programming operation.

[0095] At operation 650, the cache register is released. For example, processing logic may cause the cache register to be released in response to a condition being met. In an embodiment, when the condition is met, processing logic may release the cache register (i.e., advance the cache register release) to enable new data associated with a new or next fast programming operation to be stored. In an embodiment, in response to the condition being met, the ready bit value may be set to a "ready" state level (e.g., "1," as in Figure 5 530 in conjunction with timelines 520 and 530, respectively). In embodiments, a ready bit value of "1" signals to an external controller and / or host system that new data may be loaded into the cache register in conjunction with the execution of a new or next fast programming operation. Advantageously, the early cache register release of operation 650 may be performed at a time prior to the completion of a current or ongoing fast programming operation. In embodiments, the early cache register release of operation 650 may be performed at the end of a final programming pulse (e.g., Figure 5 PP Final) and voltage release phase 540. In an embodiment, the early cache register release of operation 650 may occur before the final programming cycle (e.g. Figure 5 Programming cycle N), the final programming pulse (eg Figure 5 PP Final ) and voltage release phase (e.g. Figure 5 In an embodiment, the early cache register release in response to the satisfaction of a condition associated with the prediction operation may occur at a time of approximately 50 μs to 100 μs before the current fast programming operation is completed.

[0096] Figure 7 An example machine illustrating a computer system 700 is shown within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein is executed. In some embodiments, the computer system 700 may correspond to a host system (e.g., Figure 1A ) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1A memory subsystem 110) or can be used to perform operations of the controller (for example, execute an operating system to execute corresponding Figure 1A In some embodiments, the machine may be connected (e.g., using a network) to other machines. The machine may operate in the capacity of a server or a client user machine in server-client user network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client user machine in a cloud computing infrastructure or environment.

[0097] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Furthermore, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute one (or more) sets of instructions to perform any one or more of the methodologies discussed herein.

[0098] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), a static memory 706 (e.g., flash memory, static random access memory (SRAM)), etc.), and a data storage system 718, which communicate with each other via a bus 730.

[0099] The processing device 702 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing another instruction set or multiple processors implementing a combination of instruction sets. The processing device 702 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. The computer system 700 may further include a network interface device 708 for communicating over a network 720.

[0100] The data storage system 718 may include a machine-readable storage medium 724 (also referred to as a computer-readable medium, e.g., a non-transitory computer-readable medium) on which is stored one or more sets of instructions 726 or software embodying any one or more of the methodologies or functionality described herein. The instructions 726 may also reside, completely or at least partially, within the main memory 704 and / or within the processing device 702 during execution thereof by the computer system 700, the main memory 704 and the processing device 702 also constituting machine-readable storage media. The machine-readable storage medium 724, the data storage system 718, and / or the main memory 704 may correspond to Figure 1A Memory subsystem 110.

[0101] In one embodiment, instructions 726 include implementing instructions corresponding to Figure 1A The functional instructions of the programming manager 134 are provided. Although the machine-readable storage medium 724 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be understood to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that can store or encode a set of instructions for execution by a machine and cause the machine to perform any one or more of the methods of the present disclosure. The term "machine-readable storage medium" should accordingly be understood to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0102] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is herein and generally conceived to be a self-consistent sequence of operations leading to a desired result. Operations are those requiring physical manipulation of physical quantities. Typically, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient, sometimes for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0103] It should be remembered, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may involve actions and processes of computer systems or similar electronic computing devices that manipulate or transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0104] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0105] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems may be used in conjunction with programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. The structures of a variety of these systems will appear as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure described herein.

[0106] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform processes according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form that can be read by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, or the like.

[0107] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A memory device comprising: a memory array comprising a group of memory cells configured as a multi-level cell (MLC) memory; and Control logic operatively coupled to the memory array, the control logic configured to perform operations including: initiating a fast programming operation to program the set of memory cells to a target programming level from a set of programming levels; storing a set of data associated with the fast programming operation in a cache register; performing, at a first time during execution of the fast programming operation, a prediction operation to determine a prediction result corresponding to a programming state of the group of memory cells; comparing the prediction result with a threshold level to determine whether a condition is satisfied; as well as The set of data associated with the fast programming operation is caused to be released from the cache register in response to the condition being satisfied.

2. The memory device of claim 1, wherein the prediction result represents a predicted number of the set of memory cells associated with an established programming state.

3. The memory device of claim 2, wherein the condition is satisfied if the predicted number of the prediction results is greater than or equal to the threshold level.

4. The memory device of claim 1, the operations further comprising updating a signal associated with the cache register from a busy state to a ready state in response to the condition being satisfied.

5. The memory device of claim 4, the operations further comprising loading a next set of data associated with a next fast programming operation applied to the memory array into the cache register in view of the ready state.

6. The memory device of claim 1, wherein the set of data is released from the cache register sometime before the fast programming operation is completed.

7. The memory device of claim 1, wherein the set of data is released from the cache register at a time prior to one or more programming pulses and voltage release phases associated with the fast programming operation applied to the memory array.

8. The memory device of claim 1, wherein the set of data is released from the cache register at a time prior to one or more programming loops, a final programming pulse, and a voltage release phase associated with the fast programming operation.

9. The memory device of claim 5, the operations further comprising initiating execution of the next fast program operation based on the next set of data stored in the cache register before the fast program operation is completed.

10. A method comprising: initiating a first fast programming operation to program a group of memory cells of a memory array of a memory device to a target programming level among a group of programming levels; storing a first set of data associated with the first fast programming operation in a cache register; performing, by a processing device, a prediction operation at one or more checkpoints during execution of the first fast programming operation to determine a prediction result corresponding to a programming state of the group of memory cells; comparing the prediction result with a threshold level to determine whether a condition is satisfied; causing the first set of data associated with the first fast programming operation to be released from the cache register in response to the condition being satisfied; as well as A second set of data associated with a second fast programming operation to be applied to the memory array is loaded into the cache register.

11. The method of claim 10, further comprising updating a signal associated with the cache register from a busy state to a ready state in response to the condition being satisfied. 12 . The method of claim 10 , wherein the second set of data is loaded into the cache register before the first fast program operation is completed.

13. The method of claim 10, wherein the first set of data is released from the cache register before the first fast program operation is completed.

14. The method of claim 10, wherein the one or more checkpoints associated with the performance of the prediction operation are established after one or more programming loops of the first fast programming operation, wherein each of the one or more programming loops includes application of a programming pulse and performance of a program verify operation.

15. The method of claim 10, wherein the prediction operation is performed after a programming loop, and wherein the prediction result comprises a predicted number of the set of memory cells whose program states are known after a next programming loop.

16. A memory device comprising: a memory array comprising a set of memory cells; and Control logic operatively coupled to the memory array, the control logic configured to perform operations including: initiating a first fast programming operation to program the group of memory cells to a target programming level from a group of programming levels; storing a first set of data associated with the first fast programming operation in a cache register; performing a prediction operation to determine a prediction result corresponding to a programming state of the group of memory cells at one or more checkpoints during execution of the first fast programming operation; comparing the prediction result with a threshold level to determine whether a condition is satisfied; causing the first set of data associated with the first fast programming operation to be released from the cache register in response to the condition being satisfied; as well as A second set of data associated with a second fast programming operation to be applied to the memory array is loaded into the cache register.

17. The memory device of claim 16, wherein the second set of data is loaded into the cache register before the first fast programming operation is completed.

18. The memory device of claim 16, wherein the releasing of the cache register is caused before the first fast programming operation is completed.

19. The memory device of claim 16, wherein the one or more checkpoints associated with the execution of the prediction operation are established after one or more programming loops of the first fast programming operation, wherein each of the one or more programming loops includes application of a programming pulse and execution of a program verify operation.

20. The memory device of claim 16, wherein the prediction operation is performed after a programming loop, and Wherein the prediction result comprises a predicted number of the set of memory cells whose program states are known after a next programming loop.

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