Systems and methods for prefetch scanning of memory devices

Abstract

This application relates to a system and method for pre-fetch scanning of a memory device. The method and system include a memory device having a memory array comprising a plurality of memory cells. The memory device includes control circuitry operatively coupled to the memory array and configured to receive a read request for data and to apply a plurality of read voltages to the memory array based on the read request. The control circuitry is further configured to perform data analysis on a first dataset of the applied reads based on the plurality of read voltages, and to derive a boundary bias voltage VDM based on the data analysis. The control circuitry is also configured to apply the VDM to the memory array to read a second dataset.

Description

Technical Field

[0001] This application relates to memory devices, and more particularly to systems and methods for prefetch scanning of memory devices. Background Technology

[0002] This section aims to introduce the reader to various aspects of the technology that may be related to the aspects of the invention described below and / or claimed. This discussion is intended to help provide the reader with background information to better understand the various aspects of this disclosure. Therefore, it should be understood that these statements should be read in this context and not as an endorsement of prior art.

[0003] Generally, a computing system includes a processing circuitry, such as one or more processors or other suitable components; and a memory device, such as a chip or integrated circuit. One or more memory devices may be used on memory modules, such as dual in-line memory modules (DIMMs), to store data accessible to the processing circuitry. For example, based on user input to the computing system, the processing circuitry may request a memory module to retrieve data corresponding to the user input from its memory device. In some examples, the retrieved data may contain firmware, or instructions executable by the processing circuitry to perform an operation, and / or may contain data to be used as input to said operation. Additionally, in some cases, data output from said operation may be stored in memory, for example, to enable subsequent retrieval of said data from said memory.

[0004] Some memory devices include memory cells that can be accessed by turning on a transistor, which couples the memory cell (e.g., a capacitor) to a word line or bit line. In contrast, threshold memory devices include memory devices that are accessed by providing a voltage across the memory cell, wherein data values ​​are stored based on a threshold voltage of the memory cell. For example, the data value may be based on whether it exceeds the threshold voltage of the memory cell, and the memory cell conducts current in response to the voltage provided across the memory cell. The stored data value may be changed, for example, by applying a voltage sufficient to change the threshold voltage of the memory cell. An example of a threshold memory cell may be a crosspoint memory cell.

[0005] For threshold-type memories, word lines and bit lines are used to transmit selection signals to the corresponding memory cells. The selection signals may include signals characterized by voltage levels used to store data in or retrieve data from the memory cells. Word lines and bit lines may be coupled to the selection signal source via drivers. Memory cells may be organized into one or more layers, such as layers defined between overlapping word lines and bit lines. These layers may be referred to as stacks (e.g., memory stacks). Various combinations of word lines, bit lines, and / or decoders may be referenced for specific memory operations using addresses (e.g., memory addresses). The address may indicate which memory cell will be selected using a combination of signals from the word lines, bit lines, and / or decoders, and a specific value of the address may be based on a range of addresses for the memory device. A voltage may then be applied to the selected word line and / or bit line to turn on the memory cell, for example, to read data from the memory cell. Improving read techniques for threshold-type memories can be advantageous. Summary of the Invention

[0006] In one aspect, this application relates to a memory device comprising: a memory array including a plurality of memory cells; and control circuitry operatively coupled to the memory array, the control circuitry being configured to: receive a read request for data; apply a plurality of read voltages to the memory array based on the read request; perform data analysis on a first dataset read based on the application of the plurality of read voltages; derive a boundary bias voltage (VDM) based on the data analysis; and apply the VDM to the memory array to read a second dataset.

[0007] In another aspect, this application relates to a method comprising: receiving a read request for data at a control circuit included in a memory device; transmitting a pre-scan read to the memory array based on the read request; performing data analysis on a first dataset of the transmitted read based on the pre-scan read; deriving a boundary bias voltage (VDM) based on the data analysis; and applying the VDM to the memory array to read a second dataset.

[0008] In another aspect, this application relates to a memory device comprising: a memory array including a plurality of memory cells; and control circuitry operatively coupled to the memory array, the control circuitry being configured to: receive a read request for data; transmit a plurality of read voltages in parallel to the memory array to read a first dataset; perform data analysis on the first dataset; derive a boundary bias voltage (VDM) based on the data analysis; and apply the VDM to the memory array to read a second dataset. Attached Figure Description

[0009] A better understanding of the various aspects of this disclosure can be achieved by reading the following detailed description and referring to the figures, in which:

[0010] Figure 1 This is a simplified block diagram illustrating certain features of a memory device comprising a memory array of memory cells according to embodiments of the present disclosure.

[0011] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 A side view of a portion of the memory array diagram;

[0012] Figure 3 According to embodiments of this disclosure, the memory array has been partitioned into multiple partitions. Figure 1 A block diagram of an embodiment of a memory device;

[0013] Figure 4 This is a block diagram of a user data pattern encoding technique according to embodiments of the present disclosure;

[0014] Figure 5 This illustrates the applicability of embodiments of this disclosure to [the public / the world]. Figure 1 Timing diagram of the ramp voltage (e.g., read voltage) used to read data from the memory array;

[0015] Figure 6 The embodiments shown in this disclosure include Figure 1 Certain partitions in the memory array and timings available in one or more of said partitions; and

[0016] Figure 7 It is suitable for storage according to embodiments of this disclosure. Figure 1 The flowchart shows the process of pre-scanning and reading data from a memory array. Detailed Implementation

[0017] One or more specific embodiments will be described below. To provide a concise description of these embodiments, not all features of the actual implementation are described in the specification. It should be understood that, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developer's specific goals, such as complying with system-related and business-related constraints that may vary from one implementation to another. Furthermore, it should be understood that this development work may be complex and time-consuming, but will still be a common practice for those skilled in the art to engage in design, fabrication, and manufacturing, as will be the case with this disclosure.

[0018] Memory typically comprises an array of memory cells, each of which is coupled between at least two access lines. For example, a memory cell may be coupled to access lines, such as bit lines and word lines. Each access line may be coupled to a plurality of memory cells. To select a memory cell, one or more drivers may provide selection signals (e.g., voltage and / or current) on the access lines to access the memory cell's storage capacity. By applying voltage and / or current to the corresponding access line, the memory cell can be accessed to write data to and / or read data from the memory cell.

[0019] In some memories, memory cells in an array can be organized into stacks of memory cells. A stack of memory cells can be a single plane of memory cells positioned between word line layers and bit line layers. An array can be a stack of stacks containing any number of memory cell stacks (e.g., 1 stack, 2 stacks, 4 stacks, any number of stacks) as different layers of the array.

[0020] In some embodiments, logic state 1 (e.g., the SET state of a memory cell, which may also be referred to as a SET cell or bit) may correspond to a set of threshold voltages (Vth) lower than the set of threshold voltages associated with logic state 0 (e.g., the RESET state of a memory cell, which may also be referred to as a RESET cell or bit). Accordingly, a lower voltage can be used to read a SET cell compared to a RESET cell. During operation, the threshold voltages of one or more memory cells may “drift.” That is, as time increases, a higher threshold may now be available for reading data compared to the original initial threshold. Accordingly, the memory array may use active media management, such as monitoring tiles (e.g., tiles in a partition), and attempt to mitigate the effects of drift by deriving a new boundary bias voltage (VDM) to be used to read memory cells.

[0021] Instead of using active media management (e.g., tile-level management), the prefetch scanning technique described herein can apply a two-step (or more-step) read approach. In one embodiment, the first step (e.g., a scan step) may include applying multiple voltages (e.g., read voltages) to the memory array. In some embodiments, the read voltages may be applied in parallel via partitions, where each voltage has a different value, as further described below. The applied read voltages can initiate a series of switching events by activating a group of memory cells storing data to be read. Switching events can be attributed to a memory cell turning on (e.g., conducting a considerable amount of current) when the applied voltage across the memory cell exceeds a threshold voltage (Vth) of the memory cell.

[0022] Memory cells that have already been activated can then be read as storing logic 1 (e.g., SET cells), and the remaining cells that have not yet been activated can be read as storing logic 0 (e.g., RESET cells). The read data can then be analyzed to determine which of the multiple applied read voltages is preferred, as further described below. The preferred voltage can then be used to derive a preferred VDM, and subsequently applied during a second read step. Accordingly, a read-ahead scan technique can provide read voltages more efficiently when accessing data in the memory array.

[0023] Now let's look at the various figures. Figure 1 This is a block diagram of a portion of a memory device 100. The memory device 100 may be any suitable form of memory, such as non-volatile memory (e.g., crosspoint memory) and / or volatile memory. The memory device 100 may include one or more memory cells 102, one or more bit lines 104 (e.g., 104-0, 104-1, 104-2, 104-3), one or more word lines 106 (e.g., 106-0, 106-1, 106-2, 106-3), one or more word line decoders 108 (e.g., word line decoding circuitry), and one or more bit line decoders 110 (e.g., bit line decoding circuitry). The memory cells 102, bit lines 104, word lines 106, word line decoders 108, and bit line decoders 110 may form a memory array 112.

[0024] Each of the memory cells 102 may include a selector and / or a storage element. When the voltage across the selector of the respective memory cell reaches a threshold, the storage element can be accessed to read data values ​​from the storage element and / or write data values ​​to the storage element. In some embodiments, each of the memory cells 102 may not include a separate selector and storage element, and may have a configuration that allows the memory cell to function as if it had a selector and a storage element (e.g., it may include materials that behave similarly to both the selector material and the storage element material). For ease of discussion, the bit line 104, word line 106, word line decoder 108, and bit line decoder 110 may be discussed. Figure 1 However, these designations are non-limiting. The scope of this disclosure should be understood to cover memory cells 102 coupled to and accessed via respective decoders, wherein the access lines are used to store data in and read data from memory cells 102. Furthermore, memory device 100 may include other circuitry, such as biasing circuitry configured to bias bit lines 104 or word lines 106 in corresponding directions. For example, bit lines 104 may be biased using a positive biasing circuitry system, while word lines 106 may be biased using a negative biasing circuitry system.

[0025] Bit line decoders 110 can be organized into multiple groups of decoders. For example, memory device 100 may include a first group of bit line decoders 114 (e.g., multiple bit line decoders 110) and / or a second group of bit line decoders 116 (e.g., multiple bit line decoders 110 in different groups). Similarly, word line decoders 108 may also be arranged as groups of word line decoders 108, such as a first group of word line decoders 118 and / or a second group of word line decoders 120. Decoders can be used in combination to drive memory cell 102 when a target memory cell 102A is selected from memory cell 102 (e.g., paired and / or matched on either side of word line 106 and / or bit line 104). For example, bit line decoder 110-3 may operate in combination with bit line decoder 110'-3 and / or in combination with word line decoders 108-0, 108'-0 to select memory cell 102A. As can be understood in this article, the decoder circuitry at either end of word line 106 and / or bit line 104 may be different.

[0026] Each of bit line 104 and / or word line 106 may be a metallic trace disposed in memory array 112 and formed of a metal such as copper, aluminum, silver, tungsten, etc. Therefore, bit line 104 and word line 106 may have uniform resistance and uniform parasitic capacitance per length, such that the resulting parasitic load increases uniformly per length. It should be noted that the components of the depicted memory device 100 may include additional circuitry not specifically depicted and / or may be disposed in any suitable arrangement. For example, a subset of word line decoder 108 and / or bit line decoder 110 may be disposed on different sides of memory array 112 and / or on different physical sides of any plane containing the circuitry.

[0027] The memory device 100 may also include control circuitry 122. For example, by causing a decoding circuitry system (e.g., a subset of word line decoders 108 and / or bit line decoders 110) to generate selection signals (e.g., selection voltage and / or selection current) to select a target memory cell, control circuitry 122 may be communicatively coupled to the respective word line decoder 108 and / or bit line decoder 110 to perform memory operations. In some embodiments, positive and negative voltages may be provided to the target memory cell 102 on one or more of the bit lines 104 and / or word lines 106, respectively. In some embodiments, the decoder circuitry may provide biased electrical pulses (e.g., voltage and / or current) to the access lines to access the memory cell. The electrical pulses may be rectangular pulses, or in other embodiments, pulses of other shapes may be used. In some embodiments, the voltage provided to the access lines may be a constant voltage.

[0028] Activating the decoder circuit enables the delivery of electrical pulses to the target memory cell 102, allowing the control circuit 122 to access the data storage device of the target memory cell for reading from or writing to the data storage device. After accessing the target memory cell 102, data stored in the storage medium of the target memory cell can be read or written. Writing to the target memory cell may involve changing the data value stored by the target memory cell. As previously discussed, the data value stored by the memory cell may be based on a threshold voltage of the memory cell. In some embodiments, the memory cell may be “set” to have a first threshold voltage or may be “reset” to have a second threshold voltage. A SET memory cell may have a lower threshold voltage than a RESET memory cell. Different data values ​​can be stored by the memory cell by setting or resetting the memory cell. Reading the target memory cell 102 may involve determining whether the target memory cell is characterized by a first threshold voltage and / or by a second threshold voltage. In this way, a threshold voltage window can be analyzed to determine the value to be stored in the target memory cell 102. A threshold voltage window can be generated by applying programming pulses with opposite polarity bias to memory cell 102 (e.g., specifically, writing to selector device (SD) material in the memory cell) and reading memory cell 102 using a signal with a given (e.g., known) fixed polarity (e.g., reading the voltage stored in the SD material of memory cell 102). In some embodiments, a selection input can be received from host device 128, such as a host processor reading data from memory device 100 to cause control circuitry 122 to access a specific memory cell 102.

[0029] The control circuit 122 may further utilize a prefetch scan technique, for example, by applying multiple read voltages to the memory cell 102 based on partitions when reading data that can be stored in the memory cell 102. In one embodiment, multiple read voltages may be applied in parallel, one voltage per partition, wherein each voltage has a different value. The read voltages may be applied via bit line 104 and word line 106. The applied read voltages may then cause an activation event (e.g., a switching event) that can be read via word line decoder 108 and bit line decoder 110. The SET cell may be activated at a first voltage threshold (Vth) lower than the second Vth of the RESET cell.

[0030] In some embodiments, the resulting read data (e.g., logic 1s and 0s) may have specific statistical assumptions. For example, the total number of logic 1s may be within a desired range of 35% to 65% of the total number of logic 0s. For example, the applied read voltage may return data that is outside the desired range because the applied voltage may be too high or too low. A better read voltage may produce data that is closer to or within the desired range. Control circuitry 122 may derive a better VDM and then adjust one or more subsequent voltages based on the derive. Accordingly, for example, pre-scan read techniques described herein may be used to account for variations attributable to drift, write endurance (e.g., later read voltages may be lower as more writes are performed) and / or distance to memory cell 102 (e.g., different read voltages may vary based on the distance of the data stored in bit line 104).

[0031] Figure 2 This is a diagram illustrating a portion of a memory array 130 according to an embodiment of the present disclosure. Within the memory array 130, memory cells are located at the intersections of certain lines (e.g., orthogonal lines). The memory array 130 may be an array of intersections comprising word lines 106 (e.g., 106-0, 106-1, ..., 106-N) and bit lines 104 (e.g., 104-0, 104-1, ..., 104-M). Memory cells 102 may be located at each of the intersections of word lines 106 and bit lines 104. Memory cells 102 may function in a two-terminal architecture (e.g., where a particular combination of word lines 106 and bit lines 104 acts as an electrode for the memory cell 102).

[0032] Each of the memory cells 102 may be a resistively variable memory cell, such as a resistive random access memory (RRAM) cell, a conductive bridged random access memory (CBRAM) cell, a phase-change memory (PCM) cell, and / or a spin-transfer torque magnetic random access memory (STT-RAM) cell, as well as other types of memory cells. Each of the memory cells 102 may include memory elements (e.g., memory material) and selector elements (e.g., selector device (SD) material) and / or material layers that functionally replace individual memory element layers and selector element layers. The selector elements (e.g., SD material) may be disposed between word line contacts (e.g., a layer interface between a corresponding word line 106 and the memory material) and bit line contacts (e.g., a layer interface between a corresponding bit line 104 and the selector element) associated with the word lines or bit lines forming the memory cell. When a read or write operation is performed on the memory cell, an electrical signal may be transmitted between the word line contacts and the bit line contacts.

[0033] The selector element can be a diode, a non-ohmic device (NOD), or a chalcogenide switching device, etc., or similar to a lower-voltage cell structure. In some instances, the selector element may include a selector material, a first electrode material, and a second electrode material. The memory element of memory cell 102 may include a memory portion of memory cell 102 (e.g., a portion programmable to different states). For example, in a variable-resistance memory cell 102, the memory element may include a resistive portion of the memory cell, which is programmable to a specific level corresponding to a specific state in response to an applied programming voltage and / or current pulse. In some embodiments, memory cell 102 may be characterized as a threshold-type memory cell selected (e.g., activated) based on a voltage and / or current across a threshold associated with the selector element and / or memory element. Embodiments are not limited to one or more specific variable-resistance materials associated with the memory element of memory cell 102. For example, the variable-resistance material may be a chalcogenide formed from various doped or undoped chalcogenide-based materials. Other examples of resistive variable materials that can be used to form memory elements include dual-state metal oxide materials, giant magnetoresistive materials, and / or various polymer-based resistive variable materials, etc.

[0034] In operation, the memory cell 102 can be programmed by applying a voltage (e.g., a write voltage) across the memory cell 102 via selected word lines 106 and bit lines 104. Sensing (e.g., read) operations can be performed to determine the state of one or more memory cells 102 by sensing current. For example, in response to a specific voltage applied to a selector of the bit lines 104 / word lines 106 forming the respective memory cell 102, current can be sensed on one or more bit lines 104 / word lines 106 corresponding to the respective memory cell 102.

[0035] As shown, the memory array 130 can be arranged in a crosspoint memory array architecture (e.g., a three-dimensional (3D) crosspoint memory array architecture) extending in any direction (e.g., x-axis, y-axis, z-axis). The multi-stack crosspoint memory array 130 may include a plurality of consecutive memory cells (e.g., 102B, 102C, 102D) disposed between alternating (e.g., staggered) stacks of word lines 106 and bit lines 104. The number of stacks can be expanded or reduced and should not be limited to the depicted volume or arrangement. Each of the memory cells 102 may be formed between the word line 106 and the bit line 104 (e.g., between two access lines) such that a corresponding one of the memory cells 102 can be directly electrically coupled (e.g., series electrical coupling) to its corresponding pair of bit lines 104 and word lines 106, and / or formed by electrodes (e.g., contacts) made of corresponding portions of the metal in the corresponding pair of bit lines 104 and word lines 106. For example, memory array 130 may comprise a three-dimensional matrix of individually addressable (e.g., randomly accessible) memory cells 102 accessible at a granularity of as small as a single memory element and / or multiple memory elements for data operations (e.g., sensing and writing). In some cases, memory array 130 may comprise more than Figure 2 Examples show more or fewer bit lines 104, word lines 106, and / or memory cells 102. Each stack may contain one or more memory cells 102 aligned in the same plane.

[0036] Figure 3 This is a block diagram of an embodiment of a memory device 200 in which the memory array 112 is divided into multiple partitions 202 (e.g., partitions 202-a, 202-b…202-n). Each partition 202 may include associated local control circuitry 204 (e.g., local control circuitry 204-a, 204-b…204-n). Furthermore, each partition may be further divided into tiles 205 (e.g., tiles 205-a, 205-b…205-n). In some embodiments, the local control circuitry 204 may be included in or interfaced with control circuitry 122. Accordingly, each partition 202 may operate independently of the other partitions 202, enabling parallel reads and writes to the memory array 112, including the use of parallel prefetch scans.

[0037] In some embodiments, memory array 112 is a 3D crosspoint (3DXP) memory array, and each partition 220 is a 1-gigabyte partition. Memory device 200 may contain 16 1-gigabyte partitions. In some instances, memory within each partition 202 can be accessed at a 16-byte granularity, thus providing 26 bits of memory address information to memory array 110. Additionally, in this example, four bits may be used to provide partition identification. It should be noted that the specific partition size, number of partitions, and bits used for command and address operations described above are provided as examples only, and different partition sizes, number of partitions, and command / address bits may be used in other embodiments.

[0038] While the pre-scan reading technique described herein can work with any type of stored data, in some embodiments, data stored in memory array 112 can be encoded, for example, by adding certain coded bits. Encoding the data bits enables faster reading, as further described below. Referring now to... Figure 4 This figure illustrates an embodiment of user data pattern 400 that can be used by the pre-scan reading techniques described herein. User data pattern 400 shows unencoded user data 402 that can be subsequently encoded into user data 404. Unencoded user data 402 may be referred to as an input vector in some cases. Encoded user data 404 may contain additional bits (e.g., b1 to b4). These additional bits may be referred to as flip bits and may indicate the state of the user data, as described below.

[0039] The described encoding technique generates encoded user data with weights within a predetermined interval (e.g., the number of bits with a logic state of 1 out of the total number of bits in the user data). In some embodiments, the interval is 50% to (50+50k)%, where k is a predetermined factor further described below. In some cases, the interval is expressed as [50%, (50+50k)%. For example, when k equals 4, the interval can be 50% to 62.5% (e.g., [50%, 62.5%]). Different weights other than 50% can be used as the lower limit of the interval. Figure 4 The illustrations in the diagram use 50% as the lower limit of the interval to achieve a more concise description of the features depicted; however, other alternatives and variations may be carefully considered and fall within the scope of this disclosure.

[0040] With the help of an example, user data 402 is shown as having 16 bits (e.g., a1 to a16). When k equals 4, the predetermined range to be satisfied by the encoded user data can be [50%, 62.5%]. Figure 4The diagram illustrates various forms of encoded user data 404 when k = 4. Encoding techniques can add k number of flipped bits (e.g., b1 to b4 when k = 4) to user data 402 (e.g., a1 to a16) to generate encoded user data 404. Alternatively, the original user data pattern can be divided into k number of parts (e.g., four parts or fragments when k = 4). For example, a first part may contain bits a1 to a4. The first part may be associated with a first flipped bit b1. A second part may contain bits a5 to a8. The second part may be associated with a second flipped bit b2. A third part may contain bits a9 to a12. The third part may be associated with a third flipped bit b3. A fourth part may contain bits a13 to a16. The fourth part may be associated with a fourth flipped bit b4. In some embodiments, the initial values ​​of b1 to b4 correspond to logic state 1 (e.g., 1111 in encoded user data pattern 406). Logic state 1 in the flipped bits can indicate that the corresponding part of the original user data is not flipped. Conversely, a logic state of 0 in the flip bit indicates that the corresponding portion of the original user data has been inverted.

[0041] As described above, the pre-scan reading technique described herein can determine the weight of encoded user data pattern 404 as a percentage (e.g., by adding a logic 1 bit and dividing the sum by the total number of unencoded bits). For example, encoded user data 560-a has a weight of 25% (e.g., 4 bits of logic state 1 out of 16 bits in the user data), which does not satisfy the predetermined interval [50%, 62.5%] when k = 4. Furthermore, the encoding technique can change the logic state of the flipped bits through all possible combinations of the logic state of the flipped bits to find a specific encoded user data with a specific weight within the predetermined interval (e.g., the interval [50%, 62.5%] when k = 4). When there are k flipped bits (e.g., k = 4), there are a total of 2^k (e.g., 2^4 = 16) combinations, such as 1111, 1110, 1101, 1100, ..., 0001 and 0000.

[0042] When the logic state of the flipped bit corresponds to logic state 0, the pre-scan read can invert the logic state of the corresponding portion of the user data and evaluate the weights. As shown, user data 406 does not contain any inversions, and therefore all flipped bits are set to 1. Data inversion can then occur. By way of example, when the flipped bit is 1110 as shown in encoded user data 408, the logic state of the fourth portion (e.g., bits a13 to a16) is inverted from 0110 to 1001. Subsequently, the encoding technique can determine that encoded user data pattern 408 has a weight of 25% (e.g., 4 bits of logic state 1 out of 16 bits in the user data), which does not satisfy the predetermined condition of weight within the range of [50%, 62.5%]. The encoding technique can restore the logic state of the fourth portion back to 0110 and change the contents of the flipped bits to the next combination (e.g., 1101 as shown in encoded user data 410). The encoding technique can invert the logic state of the third part (e.g., bits a9 to a12) from 0100 to 1011, as shown in the encoded user data 410, and determine that the encoded user data pattern 410 has a weight of 38% (e.g., 6 bits of logic state 1 out of 16 bits in the user data), which does not satisfy the predetermined condition of weight in the range of [50%, 62.5%].

[0043] The pre-scan read can continue to change the contents of the flipped bits, inverting the logical values ​​of the corresponding bits of the user data according to the flipped bits, and thereby evaluating the weight of the encoded user data until the encoded user data meets a predetermined condition (e.g., a range of [50%, 62.5%]). For example, encoded user data 412 has a weight of 38% and does not meet the predetermined condition of a weight range of [50%, 62.5%]. Encoded user data pattern 414 has a flipped bit content of 1011, and the second part of the user data (e.g., bits a5 to a8) is inverted from 0000 to 1111. Encoded user data 414 has a weight of 50% (e.g., 8 bits of logical state 1 out of 16 bits in the user data), which meets the predetermined condition of a weight between [50%, 62.5%].

[0044] The decoding technique can stop changing the contents of the flipped bits based on determining that the encoded user data pattern 414 meets predetermined conditions, and the decoded user data pattern 414 can be stored in a memory cell. The flipped bit contents (e.g., 1011) can then be used to decode the encoded user data when it is read from the memory cell. For example, the logic states of bits a5 to a8 of the encoded user data 414 (e.g., 1111) can be reversed back to their original logic states (e.g., 0000) based on the value of flipped bit b2 when the encoded user data 414 is read (e.g., logic state 0 of b2 indicates that bits a5 to a8 have been flipped). By storing the encoded bits within the desired weight range, the techniques described herein allow for faster reading of data stored in the memory device 100.

[0045] The description illustrates the advantages of a specific data reading technique using a slant-down reading method. Now refer to... Figure 5 This figure is a timing diagram or graph 450 illustrating a ramp voltage that can be applied via bit line 104 and / or word line 106 to enable data reading. In the illustrated embodiment, graph 450 includes an X-axis representing time and a Y-axis representing voltage. As time progresses in the Y direction, voltages LBL and LWL, representing the voltages of bit line 104 and word line 106 respectively, can be applied to create a bias voltage at memory cell 102. Using a ramp method, the LBL voltage can start at approximately 0 volts and then ramp up to a higher voltage at time T1, while LWL turns negative at time T2. The LBL voltage can then ramp up to a higher voltage at time T3. A SET memory cell 102 can begin to turn on at time T2, more SET cells can turn on at time T3, and so on, until all or almost all SET cells have been turned on. Sensing of memory cell 102 to read data (e.g., based on memory cell 102 switching) can then occur at time T4.

[0046] A "snapback" may occur during data reading, which can lead to undesirable changes in the voltages LBL and / or LWL. For example, a snapback discharge effect at memory cell 102 may interfere with the read voltage. For example, a snapback effect may be exhibited at time range Tr, resulting in a lower LBL voltage and a less negative LWL. For example, a snapback 452 associated with SET memory cell 102, a snapback 454 associated with RESET memory cell 102, and a snapback 456 associated with word line usage may be experienced by memory array 112. Deriving VDM values ​​via drift analysis using the ramp method shown in the figure can be more complex due to additional considerations, such as the sensing effect time attributable to the snapback effect. For example, a drift tracking system may be used, which tracks the drift of each tile 205 over time by analyzing the sensing time as a function of drift. For example, the SET and RESET threshold voltages and their corresponding drifts may be functions of different sensing times (e.g., the time taken at a given subthreshold bias voltage). However, drift tracking systems may not only consume significant amounts of memory (e.g., since they may need to track all tiles 205 in partition 202), but may also require additional complexity to account for backlash effects. Instead of tracking drift over time, for example, for each tile 205, the technique described herein can utilize a modified read procedure, in which a first pre-read scan and data analysis step is performed, followed by subsequent read steps, such as... Figure 6 As shown.

[0047] Figure 6 Multiple partitions 202 are illustrated that can be used to generate pre-read voltages that can then be used to determine a better VDM. In the depicted embodiment, each partition 202 may receive a different VDM pre-scan read voltage. In some embodiments, all partitions 202 may each receive a different VDM pre-scan read voltage. In other embodiments, a subset of partitions 202 may be used. In some embodiments, the VDM pre-scan read voltages can be delivered in parallel to each partition 202 (or a subset of partitions 202) using the parallelism provided by the partitions 202. That is, the first pre-scan read step can be performed in parallel by transmitting multiple VDM pre-scan voltages (one VDM pre-scan voltage per partition).

[0048] In the depicted embodiment, the timing graph or Figure 500 illustrates the use of the pre-scan readout step. More specifically, the graph 500 includes an X-axis representing time and a voltage (e.g., bit line voltage V). BLThe Y-axis of the data is defined. During time range T1, multiple partitions 202 can receive different VDM pre-scan voltages in parallel, and can then sense the data results stored in each partition. Based on the data sensing, the bit distribution (e.g., the percentage of bits found to have logic 1) can be derived for each partition, for example at time range T2. As previously mentioned, the bits should have approximately 50% logic 1 distribution, or be in the range of 35% to 65% of the total number of bits in which logic 1 is present. Furthermore, for example... Figure 4 The encoding described in [the document] can be used to provide a more evenly distributed distribution of logic 1 and logic 0 bits.

[0049] Some data distributions may be outside the desired range. Accordingly, the VDM pre-scan voltage that produces a data distribution outside the desired range, delivered to the partition, may not be as ideal as the VDM pre-scan voltage that produces a more uniform data distribution. In some embodiments, time range T2 can be used for further data analysis. For example, certain statistical techniques, such as Monte Carlo methods or probabilistic analysis, may be used at time T2. For example, control circuitry 122 may include Monte Carlo analysis and / or modeling that derives possible results (e.g., a better VDM) by replacing the range of values ​​(e.g., probability distributions, such as bell curves) based on the results of the pre-scan step from time range T1. In other embodiments, a better VDM can be derived by adding / subtracting based on the pre-scan read results. For example, if the read step is going to use the VDM value V, then V is now adjusted up or down based on the value of the better VDM pre-scan voltage.

[0050] As mentioned, multiple VDM pre-scan voltages can be used. If a higher voltage is found to derive an improved data distribution, the VDM value V will be adjusted upwards; similarly, if a lower voltage is found to derive an improved data distribution, the VDM value V will be adjusted downwards. The adjustment amount can be pre-calculated and / or derived for read requests of the control circuitry system 122 based on how "far" the read value is from the ideal data distribution (e.g., 50% of the distribution of logic 1).

[0051] Figure 7 This is a flowchart of an embodiment of a process 550 that can be used to apply the pre-scan read technique described herein. Process 550 may be implemented, for example, by control circuitry 122. In the depicted example, process 550 may be initiated by applying (block 552) multiple pre-scan read voltages. In some embodiments, each partition 202 of the memory device 10 may receive a different read voltage. In other embodiments, a subset of partitions 202 may be used, and each partition 202 within the selected subset may then receive a different read voltage.

[0052] For example, a read voltage (box 552) may be applied to each partition 202 via bit line 104 and word line 106. In one embodiment, the read voltages may be applied in parallel. In other embodiments, the read voltages may be applied serially, in parallel, or in a combination thereof (applying a first subset serially and / or a second subset in parallel). In some embodiments, some read voltages may be the same to achieve, for example, redundancy, while in other embodiments, each read voltage may have a different value.

[0053] Process 550 may then receive, for example, the data being read from partition 202 (box 554). Process 550 may derive (box 554) the data distribution of the read data. In one embodiment, the data distribution may be a measure such as the percentage of logical 1s found in the data of a given partition (e.g., codewords in the partition). The derived data distribution (box 554) may then be analyzed (box 556). For example, the derived data distribution may be compared to a desired range (e.g., 35% to 65%) to see which one or more of the derived data distributions fall closer to the desired range.

[0054] Process 550 can then derive (box 558) a better VDM to be applied in the second read step. For example, Monte Carlo methods, probabilistic analysis, etc., can be used. As mentioned above, Monte Carlo analysis and / or modeling can be used to derive a better VDM (box 558) by replacing the range of values ​​(e.g., probability distributions, such as bell curves) based on the results from the pre-scan step 554. In other embodiments, a better VDM can be derived (box 558) by adding or subtracting from the pre-scan read results (box 554). For example, if the read step will use the VDM value V, then V is now adjusted up or down based on the value of the pre-scan voltage of the better VDM.

[0055] Process 550 may then apply a better VDM during the second step (block 560). In one embodiment, the second step may be the final step for applying the read voltage. In other embodiments, one or more additional read voltage steps may be used. By applying a first pre-scan read and a second better VDM read, the techniques described herein enable better and more efficient reading of data stored in memory device 10.

[0056] While this disclosure allows for various modifications and alternatives, specific embodiments have been shown by way of example in the drawings and described in detail herein. However, it should be understood that this disclosure is not intended to be limited to the specific forms disclosed. In fact, this disclosure is intended to cover all modifications, equivalents, and alternatives that fall within the spirit and scope of this disclosure as defined by the appended claims.

[0057] Referring to the techniques proposed and claimed herein, and applied to tangible objects and concrete examples of practical nature, which demonstrably improve the technical field of the invention and are therefore not abstract, intangible, or purely theoretical. Furthermore, if any claim appended to this specification contains one or more elements designated as “a component for [performing]…[function]” or “a step for [performing]…[function]”, it is desired that such elements be interpreted in accordance with 35U.SC112(f). However, for any claim containing elements designated in any other manner, it is desired that such elements not be interpreted in accordance with 35U.SC112(f).

Claims

1. A memory device, comprising: a memory array comprising a plurality of memory cells; control circuitry operatively coupled to the memory array, the control circuitry configured to: receive a read request for data, wherein the data is partitioned into a plurality of portions, and wherein each of the plurality of portions corresponds to a respective number of bits; generate encoded data by inverting one or more logic values of at least some of the respective number of bits to bring the data within a desired range; apply a plurality of read voltages to the memory array based on the read request, wherein the plurality of read voltages are applied in parallel via a plurality of partitions included in the memory array, and wherein each voltage value of the plurality of read voltages is different from one another; perform a data analysis on a first set of encoded data read based on the application of the plurality of read voltages; derive a demarcation bias voltage (VDM) based on the data analysis by selecting a data distribution that falls within the desired range; and apply the VDM to the memory array to read a second set of data.

2. The memory device of claim 1, wherein the data analysis comprises deriving the data distribution of data read via each read voltage of the plurality of read voltages.

3. The memory device of claim 2, wherein the data distribution comprises a percentage of logical ones found in the data.

4. The memory device of claim 1, wherein the desired range is between 35% and 65% of logical ones found in the data.

5. The memory device of claim 1, wherein the data analysis comprises a Monte Carlo analysis, a probability distribution analysis, or a combination thereof.

6. The memory device of claim 1, wherein the control circuitry is configured to apply the VDM by using the VDM to read the second set of data from the plurality of partitions included in the memory array.

7. The memory device of claim 1, wherein the control circuitry is configured to apply the plurality of read voltages in parallel via a subset of the plurality of partitions.

8. The memory device of claim 1, wherein the control circuitry is configured to apply a second plurality of read voltages to the memory array based on the read request, wherein the second plurality of read voltages are applied serially via the plurality of partitions included in the memory array, and wherein each voltage value of the second plurality of read voltages is different from one another.

9. A method for performing memory operations, comprising: receiving, at control circuitry included in a memory device, a read request for data, wherein the data is partitioned into a plurality of portions, and wherein each of the plurality of portions corresponds to a respective number of bits; generating encoded data by inverting one or more logic values of at least some of the respective number of bits to bring the data within a desired range; ​ to transmit a pre-scan read to a memory array based on the read request, wherein the pre-scan read includes transmitting two or more read voltages in parallel to two or more partitions included in the memory array, and wherein each of the two or more read voltages is different from one another; to perform a data analysis on a first encoded data set read based on the transmission of the pre-scan read; to derive a demarcation bias voltage VDM based on the data analysis by selecting a data distribution of a plurality of data distributions that falls within the desired range; and to apply the VDM to the memory array to read a second data set.

10. The method of claim 9, wherein performing the data analysis includes deriving the plurality of data distributions of the first encoded data set, and selecting the data distribution of the plurality of data distributions that falls closest within the desired range.

11. The method of claim 10, wherein the desired range is between 35% and 65% of logical ones found in the data.

12. The method of claim 9, wherein applying the VDM to the memory array includes a final application of a read voltage for the read request.

13. The method of claim 9, wherein the VDM is adjusted up or down based on the pre-scan read.

14. The method of claim 9, wherein the data analysis includes a Monte Carlo analysis, a probability distribution analysis, or a combination thereof.

15. A memory device, comprising: a memory array including a plurality of memory cells; control circuitry operatively coupled to the memory array, the control circuitry configured to: receive a read request for data; transmit a plurality of read voltages in parallel into the memory array to read a first data set, wherein the plurality of read voltages are transmitted into a plurality of partitions included in the memory array, and wherein each value of the plurality of read voltages is different from one another; derive a plurality of data distributions of the first data set, wherein each of the plurality of data distributions corresponds to a respective partition of the plurality of partitions; perform a data analysis on the plurality of data distributions; derive a demarcation bias voltage VDM based on the data analysis by selecting a data distribution of the plurality of data distributions that falls within a desired distribution range, wherein the desired distribution range is associated with a ratio of logical ones to a total number of bits; and apply the VDM to the memory array to read a second data set.

16. The memory device of claim 15, wherein the control circuitry is configured to derive the VDM by selecting the data distribution of the plurality of data distributions that falls closest within the desired distribution range.

17. The memory device of claim 15, wherein the data analysis includes a Monte Carlo analysis, a probability distribution analysis, or a combination thereof.

18. The memory device of claim 15, wherein the control circuitry is configured to apply the VDM to the plurality of partitions included in the memory array.

19. The memory device of claim 16, wherein the plurality of data distributions comprises a percentage of the logical ones found in the data.

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