Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, wherein the forming method comprises: providing a substrate, the substrate comprising a plurality of adjacent first regions and second regions, the first regions being formed with P wells, the second regions being formed with N wells, and the first regions comprising first out-diffusion regions and the second regions comprising second out-diffusion regions; forming a first mask layer on the substrate, the first mask layer exposing the first out-diffusion regions and the second out-diffusion regions; etching the substrate of the first out-diffusion regions and the second out-diffusion regions to form a first recess in the first out-diffusion regions and a second recess in the second out-diffusion regions; forming a first epitaxial layer in the first recess, the first epitaxial layer having N-type ions therein; forming a second epitaxial layer in the second recess, the second epitaxial layer having P-type ions therein, and the first epitaxial layer and the second epitaxial layer being of the same material. The forming method provided by the embodiment of the present application is advantageous in increasing a process window, reducing process difficulty, and improving performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] In CMOS device fabrication, NMOS and PMOS devices are isolated using wells. Typically, these wells need to be connected out, either to the power supply (Vdd) or ground (GrouNd). Connecting the wells out prevents charge accumulation in unconnected wells, which could lead to substrate effects, latch-up effects, and other adverse effects on the device.

[0003] Currently, as the size of semiconductor devices continues to shrink, the distance between adjacent NMOS and PMOS devices is also decreasing. In the process of forming the well-out region, the out-of-zone region of the N-well and the source-drain region of the NMOS are usually formed simultaneously, and the out-of-zone region of the P-well and the source-drain region of the PMOS are formed simultaneously. The mask process window used to form the well-out region is small, which makes the process more difficult. Summary of the Invention

[0004] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, which reduces the process difficulty of forming the well junction region and helps to improve the performance of the formed semiconductor structure.

[0005] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a plurality of adjacent first regions and second regions, the first regions forming P-wells, the second regions forming N-wells, and the first regions including a first contact region, the second regions including a second contact region; forming a first mask layer on the substrate, the first mask layer exposing the first contact region and the second contact region; etching the substrate of the first contact region and the second contact region, forming a first groove in the first contact region, and forming a second groove in the second contact region; forming a first epitaxial layer in the first groove, the first epitaxial layer containing N-type ions; forming a second epitaxial layer in the second groove, the second epitaxial layer containing P-type ions, wherein the first epitaxial layer and the second epitaxial layer are made of the same material.

[0006] Optionally, the materials of the first epitaxial layer and the second epitaxial layer include SiGe or SiP.

[0007] Optionally, the first area further includes a first device area, and the second area further includes a second device area. The first area and the second area are arranged along a first direction, and the first output area and the first device area, as well as the second output area and the second device area, are arranged along a second direction, which is perpendicular to the first direction.

[0008] Optionally, before forming the first mask layer, the method further includes: forming a first dummy gate structure on the first contact area and the second contact area, the first dummy gate structure covering a portion of the surface of the substrate; and forming a second dummy gate structure on the first device area and the second device area, the second dummy gate structure covering a portion of the surface of the substrate.

[0009] Optionally, the method of forming a first groove in the first contact area and a second groove in the second contact area includes: using the first pseudo-gate structure as a mask, etching the substrate of the first contact area and the second contact area to form the first groove and the second groove.

[0010] Optionally, when the materials of the first epitaxial layer and the second epitaxial layer are SiGe, the first mask layer also exposes the second device region. While forming the first groove and the second groove, it also includes: etching the substrate of the second device region to form a third groove in the second device region.

[0011] Optionally, after forming the third groove in the second device region, the method further includes: forming a third epitaxial layer in the third groove, wherein the third epitaxial layer contains P-type ions.

[0012] Optionally, the material of the third epitaxial layer includes SiGe.

[0013] Optionally, after forming the third epitaxial layer in the third groove, the method further includes: removing the first mask layer; forming a second mask layer on the substrate, the second mask layer exposing the first device region; etching the substrate of the first device region to form a fourth groove in the first device region.

[0014] Optionally, after forming the fourth groove in the first device region, the method further includes: forming a fourth epitaxial layer in the fourth groove, wherein the fourth epitaxial layer contains N-type ions.

[0015] Optionally, the material of the fourth epitaxial layer includes SiP.

[0016] Optionally, after forming the first epitaxial layer, the second epitaxial layer, the third epitaxial layer, and the fourth epitaxial layer, the method further includes: forming an interlayer dielectric layer on the substrate, wherein the top surface of the interlayer dielectric layer is flush with the top surfaces of the first pseudo-gate structure and the second pseudo-gate structure.

[0017] Optionally, after forming the interlayer dielectric layer, the method further includes: removing the first dummy gate structure and the second dummy gate structure; forming a first gate opening and a second gate opening within the interlayer dielectric layer; forming a first gate structure within the first gate opening; and forming a second gate structure within the second gate opening.

[0018] Optionally, when the materials of the first epitaxial layer and the second epitaxial layer are SiP, the first mask layer also exposes the first device region, and while forming the first groove and the second groove, it also includes: etching the substrate of the first device region to form a fourth groove in the first device region.

[0019] Optionally, before forming the first pseudo-gate structure and the second pseudo-gate structure, the method further includes forming an isolation layer on the substrate of the first region and the second region.

[0020] Accordingly, embodiments of the present invention also provide a semiconductor structure, comprising: a substrate, the substrate including a plurality of adjacent first regions and second regions, the first regions and the second regions being arranged along a first direction, the first region including a first contact region and a first device region, the second region including a second contact region and a second device region, the first contact region and the first device region, and the second contact region and the second device region being arranged along a second direction, the second direction being perpendicular to the first direction; a P-well located within the substrate of the first contact region and the first device region; an N-well located within the substrate of the second contact region and the second device region; an isolation layer located on the substrate of the first region and the second region; and a first gate structure covering a portion of the first contact region and the second contact region. A substrate surface; a second gate structure covering a portion of the substrate surface of the first device region and the second device region; a first epitaxial layer located within the substrate of the first contact region on both sides of the first gate structure, the first epitaxial layer containing N-type ions; a second epitaxial layer located within the substrate of the second contact region on both sides of the first gate structure, the second epitaxial layer containing P-type ions, the first epitaxial layer and the second epitaxial layer being made of the same material; a third epitaxial layer located within the substrate of the second device region on both sides of the second gate structure, the third epitaxial layer containing P-type ions; a fourth epitaxial layer located within the substrate of the first device region on both sides of the second gate structure, the fourth epitaxial layer containing N-type ions, the fourth epitaxial layer being made of a different material than the third epitaxial layer.

[0021] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0022] The formation method provided by this technical solution forms a first epitaxial layer on a first contact area and a second epitaxial layer on a second contact area. The first epitaxial layer and the second epitaxial layer are used to contact the well. The first epitaxial layer and the second epitaxial layer are made of the same material and can be formed simultaneously. Therefore, the first mask layer can expose the first contact area and the second contact area at the same time, which expands the process window, reduces the process difficulty, and thus improves the performance of the formed semiconductor structure.

[0023] The semiconductor structure provided by this technical solution uses a first epitaxial layer and a second epitaxial layer for well contact. The first epitaxial layer and the second epitaxial layer are made of the same material. When forming the first epitaxial layer and the second epitaxial layer, the first mask layer can simultaneously expose the first contact area and the second contact area, which expands the process window, reduces the process difficulty, meets the needs of semiconductor device size reduction, and improves the performance of the semiconductor structure. Attached Figure Description

[0024] Figures 1 to 9 This is a schematic diagram of the semiconductor structure formation process in one embodiment of the present invention. Detailed Implementation

[0025] As described in the background section, due to the continuous shrinking of semiconductor device dimensions, the distance between adjacent NMOS and PMOS devices is decreasing accordingly. Currently, the N-well contact area is typically made of SiP material, and the P-well contact area is typically made of SiGe material. Therefore, when forming the N-well contact area, it is usually formed simultaneously with the source and drain of the NMOS device area, requiring a mask to expose both the N-well contact area and the NMOS device area. Similarly, when forming the P-well contact area, it is formed simultaneously with the source and drain of the PMOS device area, requiring another mask to expose both the P-well contact area and the PMOS device area. As the spacing between NMOS and PMOS devices becomes increasingly smaller, the process window exposed by the mask also decreases, making the formation of the N-well and P-well contact areas more difficult.

[0026] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure and a method for forming the same. A first mask layer is formed on a substrate, exposing a first contact region and a second contact region. The substrate of the first and second contact regions is etched, forming a first groove in the first contact region and a second groove in the second contact region. A first epitaxial layer is then formed in the first groove, and a second epitaxial layer is formed in the second groove. The first and second epitaxial layers are made of the same material and formed simultaneously. The first mask layer simultaneously exposes both the first and second contact regions, increasing the process window, reducing process difficulty, and thereby improving the performance of the formed semiconductor structure.

[0027] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0028] Figures 1 to 9 This is a schematic diagram of the semiconductor structure formation process in one embodiment of the present invention.

[0029] refer to Figure 1 and Figure 2 , Figure 1This is a simplified top view of a semiconductor structure. Figure 2 yes Figure 1 A cross-sectional view along the AA direction shows a substrate 100, which includes several adjacent first regions I and second regions II. The first regions I are formed with P-wells 101, and the second regions II are formed with N-wells 102. The first regions I include a first outlet region A1, and the second regions II include a second outlet region A2.

[0030] The substrate 100 provides a process platform for the subsequent formation of semiconductor structures.

[0031] In this embodiment, the substrate 100 includes a substrate 103.

[0032] In this embodiment, the substrate 103 is a silicon substrate. In other embodiments, the material of the substrate 103 may also include silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI), etc. Among them, the multi-element semiconductor material composed of group III-V elements includes INP, GaAs, GaP, INAs, INSb, IngaAs, or IngaAsP, etc.

[0033] For ease of explanation, this embodiment uses the formation of a well-out region in SRAM (Static Random Access Memory) as an example; in other embodiments, well-out regions can also be formed in other types of semiconductor devices.

[0034] In this embodiment, the first region I is used to form an NMOS device, and the second region II is used to form a PMOS device.

[0035] In this embodiment, the first area I and the second area II are arranged along the first direction X, and the first outlet area A1 and the second outlet area A2 are also arranged along the first direction X.

[0036] In this embodiment, the first region I further includes a first device region B1, and the second region II further includes a second device region B2. The first device region B1 and the second device region B2 are arranged along the first direction X, the first device region B1 and the first output region A1 are arranged along the second direction Y, and the second device region B2 and the second output region A2 are arranged along the second direction Y, which is perpendicular to the first direction X.

[0037] In this embodiment, the first contact area A1 and the second contact area A2 are mainly used to contact the well potential, and the first device area B1 and the second device area B2 are used to form an SRAM memory cell array.

[0038] In this embodiment, a P-well 101 is formed in the substrate 103 of the first region I, and an N-well 102 is formed in the substrate 103 of the second region II.

[0039] In this embodiment, the method for forming the P-well 101 includes: providing a first patterned layer (not shown), the first patterned layer having an opening corresponding to the position of the P-well 101 to be formed subsequently; performing P-type ion implantation into the substrate 103 exposed by the opening to form the P-well 101 in the substrate 103 of the first region I; and removing the first patterned layer.

[0040] The P-type ions include boron ions and BF ions. 2- Ions or indium ions.

[0041] The first patterning layer is a patterned photoresist layer.

[0042] In this embodiment, the method for forming the N-well 102 includes: providing a second patterned layer (not shown) having an opening in the second patterned layer corresponding to the position of the N-well to be formed subsequently; performing N-type ion implantation into the substrate 103 exposed by the opening to form an N-well in the substrate 103 of the second region II; and removing the second patterned layer.

[0043] The N-type ions include phosphorus ions or arsenic ions.

[0044] The second patterning layer is a patterned photoresist layer.

[0045] In this embodiment, the substrate 100 further includes fins located on the substrate 103.

[0046] The fin is made of the same material as the substrate 103. In this embodiment, the fin is made of silicon.

[0047] In this embodiment, the fin includes a first fin 104 located in the first outlet area A1 and a second fin 105 located in the second outlet area A2. The first fin 104 and the second fin 105 are arranged separately along the first direction X and both extend along the second direction Y.

[0048] In this embodiment, the fin also includes a third fin 106 located in the first device region B1 and a fourth fin 107 located in the second device region B2. The third fin 106 and the fourth fin 107 are arranged separately along the first direction X and both extend along the second direction Y.

[0049] In this embodiment, after the fin is formed, the method further includes forming an isolation layer 108 on the substrate 103 between adjacent fins, wherein the isolation layer 108 covers a portion of the sidewall surface of the fin.

[0050] Continue to refer to Figure 1 and Figure 2 After forming the isolation layer 108, the method further includes: forming a first pseudo-gate structure 109 on the first contact area A1 and the second contact area A2, wherein the first pseudo-gate structure 109 covers a portion of the surface of the substrate 100.

[0051] In this embodiment, the first pseudo-gate structure 109 spans the first fin 104 and the second fin 105, covering part of the top and sidewall surfaces of the first fin 104 and the second fin 105.

[0052] In this embodiment, the method further includes forming a second pseudo-gate structure 110 on the first device region B1 and the second device region B2, wherein the second pseudo-gate structure 110 covers part of the top and sidewall surfaces of the third fin 106 and the fourth fin 107.

[0053] refer to Figure 3 , Figure 3 This is a simplified top view of the semiconductor structure. A first mask layer 111 is formed on the substrate 100, and the first mask layer 111 exposes the first contact area A1 and the second contact area A2.

[0054] In this embodiment, a first groove is subsequently formed in the first contact area A1 and a second groove is formed in the second contact area A2. The first mask layer 111 exposes both the first contact area A1 and the second contact area A2, which increases the process window of the etching process and helps to reduce the process difficulty.

[0055] In this embodiment, the method further includes forming a fourth groove in the first device region B1 and forming a third groove in the second device region B2.

[0056] In this embodiment, the first mask layer 111 also exposes the second device region B2, and while forming the first groove and the second groove, a third groove is also formed in the second device region B2.

[0057] In other embodiments, the first mask layer 111 may also simultaneously expose the first contact area A1, the second contact area A2, and the first device area B1, forming a fourth groove in the first device area B1 while forming the first groove and the second groove.

[0058] refer to Figure 4 , Figure 4 and Figure 2With the view direction consistent, the substrate 100 of the first contact area A1 and the second contact area A2 is etched to form a first groove (not shown) in the first contact area A1 and a second groove (not shown) in the second contact area A2.

[0059] In this embodiment, the substrate 100 of the second device region B2 is also etched simultaneously to form a third groove (not shown) in the second device region B2.

[0060] In this embodiment, the method for forming the first groove and the second groove includes: using the first pseudo-gate structure 109 as a mask, etching the first fin portion 104 and the second fin portion 105 on both sides of the first pseudo-gate structure 109, forming a first groove in the first fin portion 104, and forming a second groove in the second fin portion 105.

[0061] In this embodiment, the method for forming the third groove includes: using the second pseudo-gate structure 110 as a mask, etching the fourth fin portion 107 on both sides of the second pseudo-gate structure 110, and forming the third groove (not shown) in the fourth fin portion 107.

[0062] In this embodiment, the first groove and the second groove provide space for the subsequent formation of the well outlet, and the third groove provides space for the subsequent formation of the source / drain doped region in the second device region B2.

[0063] Continue to refer to Figure 4 After forming the first groove, the second groove and the third groove, a first epitaxial layer 121 is formed in the first groove, a second epitaxial layer 122 is formed in the second groove, and a third epitaxial layer (not shown) is formed in the third groove.

[0064] In this embodiment, the first epitaxial layer 121, the second epitaxial layer 122 and the third epitaxial layer are formed simultaneously, which can simplify the process flow and improve process efficiency.

[0065] In this embodiment, the first epitaxial layer 121, the second epitaxial layer 122 and the third epitaxial layer are formed by an epitaxial growth process.

[0066] In this embodiment, the first region I is used to form an NMOS device, and the second region II is used to form a PMOS device. Therefore, the materials of the first epitaxial layer 121, the second epitaxial layer 122, and the third epitaxial layer include SiGe.

[0067] In this embodiment, the method further includes: in-situ doping of the first epitaxial layer 121, the second epitaxial layer 122 and the third epitaxial layer, wherein N-type ions are doped into the first epitaxial layer 121, P-type ions are doped into the second epitaxial layer 122 and P-type ions are doped into the third epitaxial layer.

[0068] The N-type ions include phosphorus ions or arsenic ions; the P-type ions include boron ions and BF ions. 2- Ions or indium ions.

[0069] refer to Figure 5 , Figure 5 This is a simplified top view of the semiconductor structure. After forming the first epitaxial layer 121, the second epitaxial layer 122 and the third epitaxial layer, the first mask layer 111 is removed, and a second mask layer 112 is formed on the substrate 100. The second mask layer 112 exposes the first device region B1.

[0070] In this embodiment, the first mask layer 111 is removed by an ashing process.

[0071] After the second mask layer 112 is formed, the substrate 100 of the first device region B1 is etched using the second mask layer 112 as a mask, and a fourth groove (not shown) is formed in the first device region B1.

[0072] In this embodiment, the method for forming the fourth groove includes: using the second pseudo-gate structure 110 as a mask, etching the third fin portion 106 on both sides of the second pseudo-gate structure 110, and forming the fourth groove (not shown) in the third fin portion 106.

[0073] In this embodiment, the fourth groove provides space for the subsequent formation of source / drain doped regions in the first device region B1.

[0074] After the fourth groove is formed, a fourth epitaxial layer (not shown) is formed within the fourth groove.

[0075] In this embodiment, the fourth epitaxial layer is formed using an epitaxial growth process, and the material of the fourth epitaxial layer includes SiP.

[0076] In this embodiment, the fourth epitaxial layer is further subjected to in-situ doping, incorporating N-type ions into the fourth epitaxial layer; the N-type ions include phosphorus ions or arsenic ions.

[0077] refer to Figure 6 In this embodiment, after forming the first epitaxial layer 121, the second epitaxial layer 122, the third epitaxial layer and the fourth epitaxial layer, the method further includes: forming an interlayer dielectric layer 113 on the substrate 100, wherein the top surface of the interlayer dielectric layer 113 is flush with the top surfaces of the first pseudo-gate structure 109 and the second pseudo-gate structure 110.

[0078] After forming the interlayer dielectric layer 113, the method further includes: removing the first dummy gate structure 109 and the second dummy gate structure 110; forming a first gate opening (not shown) and a second gate opening (not shown) within the interlayer dielectric layer 113; forming a first gate structure (not shown) within the first gate opening; and forming a second gate structure (not shown) within the second gate opening.

[0079] It also includes: etching the interlayer dielectric layer 113 of the first contact area A1 and the second contact area A2; forming a first metal layer 114 in the interlayer dielectric layer 113 of the first contact area A1, the first metal layer 114 being connected to the first epitaxial layer 121; and forming a second metal layer 115 in the interlayer dielectric layer 113 of the second contact area A2, the second metal layer 115 being connected to the second epitaxial layer 122.

[0080] In other embodiments, a fourth groove is formed in the first device region B1 while the first and second grooves are being formed.

[0081] refer to Figure 7 In this embodiment, a first mask layer 111 is formed on the substrate, the first mask layer 111 exposing the first contact area A1, the second contact area A2 and the first device area B1.

[0082] refer to Figure 8 , Figure 8 yes Figure 7 A cross-sectional structural diagram along the BB direction shows that after the first mask layer 111 is formed, the substrates of the first contact area and the second contact area are etched using the first mask layer as a mask. A first groove is formed in the first contact area A1, and a second groove is formed in the second contact area A2. At the same time, the substrate 100 of the first device area B1 is etched, and a fourth groove (not shown) is formed in the first device area B1.

[0083] The method for forming the first groove, the second groove, and the fourth groove is the same as in the above embodiment, and will not be repeated here.

[0084] Continue to refer to Figure 8 After forming the first groove, the second groove and the fourth groove, a first epitaxial layer 121 is formed in the first groove, a second epitaxial layer 122 is formed in the second groove, and a fourth epitaxial layer (not shown) is formed in the fourth groove.

[0085] In this embodiment, since the first epitaxial layer 121, the second epitaxial layer 122 and the fourth epitaxial layer are formed simultaneously, the materials of the first epitaxial layer 121, the second epitaxial layer 122 and the fourth epitaxial layer include SiP.

[0086] In this embodiment, the method further includes: in-situ doping of the first epitaxial layer 121, the second epitaxial layer 122 and the fourth epitaxial layer, wherein N-type ions are doped into the first epitaxial layer 121, P-type ions are doped into the second epitaxial layer 122 and N-type ions are doped into the fourth epitaxial layer.

[0087] The N-type ions include phosphorus ions or arsenic ions; the P-type ions include boron ions and BF ions. 2- Ions or indium ions.

[0088] refer to Figure 9 , Figure 9 This is a simplified top view of the semiconductor structure. After forming the first epitaxial layer 121, the second epitaxial layer 122 and the fourth epitaxial layer, the first mask layer 111 is removed, and a second mask layer 112 is formed on the substrate 100. The second mask layer 112 exposes the second device region B2.

[0089] After forming the second mask layer 112, and after forming the first epitaxial layer 121, the second epitaxial layer 122 and the fourth epitaxial layer, a third groove (not shown) is also formed in the second device region B2.

[0090] After the third groove is formed, a third epitaxial layer (not shown) is formed in the third groove, and the material of the third epitaxial layer includes SiGe.

[0091] In this embodiment, the method further includes in-situ doping of the third epitaxial layer by incorporating P-type ions into the third epitaxial layer; the P-type ions include boron ions and BF ions. 2- Ions or indium ions.

[0092] The semiconductor structure formation method provided in this embodiment of the invention uses the same material for the first epitaxial layer and the second epitaxial layer, and can be formed simultaneously. Therefore, the first mask layer exposes the first contact area and the second contact area at the same time, which increases the process window, reduces the process difficulty, and thus improves the performance of the formed semiconductor structure.

[0093] refer to Figure 6Accordingly, this embodiment of the invention also provides a semiconductor structure, including: a substrate 100, the substrate 100 including a plurality of adjacent first regions I and second regions II, the first regions I and the second regions II being arranged along a first direction X, the first region I including a first contact region A1 and a first device region B1, the second region II including a second contact region A2 and a second device region B2, the first contact region A1 and the first device region B1, and the second contact region A2 and the second device region B2 being arranged along a second direction Y, the second direction Y being perpendicular to the first direction X; a P-well 101, located within the substrate 100 of the first contact region A1 and the first device region B1; and an N-well 102, located within the substrate 100 of the second contact region A2 and the second device region B2. The substrate 100 is located within the first region I and the second region II; an isolation layer 108 is located on the substrate 100 of the first region I and the second region II; a first gate structure (not shown) covers a portion of the substrate surface of the first contact region A1 and the second contact region A2; a second gate structure (not shown) covers a portion of the substrate 100 surface of the first device region B1 and the second device region B2; a first epitaxial layer 121 is located within the substrate 100 of the first contact region A1 on both sides of the first gate structure, and the first epitaxial layer 121 contains N-type ions; a second epitaxial layer 122 is located within the substrate 100 of the second contact region A2 on both sides of the first gate structure, and the second epitaxial layer 122 contains P-type ions, and the first epitaxial layer 121 and the second epitaxial layer 122 are made of the same material.

[0094] In this embodiment, the substrate 100 includes a substrate 103.

[0095] In this embodiment, the semiconductor device is described using SRAM (Static Random Access Memory) as an example; in other embodiments, the semiconductor device may be of other types.

[0096] In this embodiment, the first region I is used to form an NMOS device, and the second region II is used to form a PMOS device.

[0097] In this embodiment, the first contact area A1 and the second contact area A2 are mainly used to contact the well potential, and the first device area B1 and the second device area B2 are used to form an SRAM memory cell array.

[0098] The materials of the first epitaxial layer 121 and the second epitaxial layer 122 include SiGe or SiP.

[0099] The semiconductor structure further includes: a third groove (not shown) located within the substrate of the second device region; a fourth groove located within the substrate of the first device region; a third epitaxial layer located within the third groove, the third epitaxial layer containing P-type ions; and a fourth epitaxial layer located within the fourth groove, the fourth epitaxial layer containing N-type ions.

[0100] In this embodiment, the material of the third epitaxial layer includes SiGe; the material of the fourth epitaxial layer includes SiP.

[0101] In this embodiment, the substrate 100 further includes fins located on the substrate 103.

[0102] The fin is made of the same material as the substrate 103. In this embodiment, the fin is made of silicon.

[0103] In this embodiment, the fin includes a first fin 104 located in the first outlet area A1 and a second fin 105 located in the second outlet area A2. The first fin 104 and the second fin 105 are arranged separately along the first direction X and both extend along the second direction Y.

[0104] In this embodiment, the fin also includes a third fin 106 located in the first device region B1 and a fourth fin 107 located in the second device region B2. The third fin 106 and the fourth fin 107 are arranged separately along the first direction X and both extend along the second direction Y.

[0105] In this embodiment, the isolation layer 108 covers the substrate 103 between adjacent fins and a portion of the sidewall surface of the fins.

[0106] In this embodiment, the first gate structure is located on the substrate 103 and spans the first fin 104 and the second fin 105.

[0107] In this embodiment, the second gate structure is located on the substrate 103 and spans the third fin 106 and the fourth fin 107.

[0108] In this embodiment, it further includes an interlayer dielectric layer 113, which covers the first epitaxial layer 121 and the second epitaxial layer 122, and its top surface is flush with the top surface of the first gate structure.

[0109] In this embodiment, the interlayer dielectric layer 113 also covers the third epitaxial layer and the fourth epitaxial layer.

[0110] In this embodiment, it further includes: a first metal layer 114, located within the interlayer dielectric layer 113 of the first contact area A1 and connected to the first epitaxial layer 121; and a second metal layer 115, located within the interlayer dielectric layer 113 of the second contact area A2 and connected to the second epitaxial layer 122.

[0111] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The method comprises the following steps: providing a substrate, the substrate comprising a plurality of adjacent first regions and second regions, the first regions being formed with P-wells, the second regions being formed with N-wells, and the first regions comprising first out-diffusion regions and the second regions comprising second out-diffusion regions; forming a first mask layer on the substrate, the first mask layer simultaneously exposing the first out-diffusion regions and the second out-diffusion regions; etching the substrate of the first out-diffusion regions and the second out-diffusion regions, simultaneously forming first recesses in the first out-diffusion regions and second recesses in the second out-diffusion regions; simultaneously forming a first epitaxial layer in the first recesses and a second epitaxial layer in the second recesses, the first epitaxial layer containing N-type ions and the second epitaxial layer containing P-type ions, the first epitaxial layer and the second epitaxial layer being of the same material.

2. The method of forming a semiconductor structure of claim 1, wherein, The material of the first epitaxial layer and the second epitaxial layer comprises SiGe or SiP.

3. The method of forming a semiconductor structure of claim 2, wherein, The first regions further comprise first device regions and the second regions further comprise second device regions, the first regions and the second regions being arranged along a first direction, the first out-diffusion regions and the first device regions, and the second out-diffusion regions and the second device regions being arranged along a second direction, the second direction being perpendicular to the first direction.

4. The method of forming a semiconductor structure of claim 3, wherein, Before forming the first mask layer, the method further comprises: forming first dummy gate structures on the first out-diffusion regions and the second out-diffusion regions, the first dummy gate structures covering part of the surface of the substrate; and forming second dummy gate structures on the first device regions and the second device regions, the second dummy gate structures covering part of the surface of the substrate.

5. The method of forming a semiconductor structure of claim 4, wherein, The method of forming the first recesses in the first out-diffusion regions and the second recesses in the second out-diffusion regions comprises: etching the substrate of the first out-diffusion regions and the second out-diffusion regions with the first dummy gate structures as a mask to form the first recesses and the second recesses.

6. The method of forming a semiconductor structure of claim 4, wherein, When the material of the first epitaxial layer and the second epitaxial layer is SiGe, the first mask layer further exposes the second device regions, and the method of forming the first recesses and the second recesses further comprises: etching the substrate of the second device regions to form third recesses in the second device regions.

7. The method of forming a semiconductor structure of claim 6, wherein, After forming the third recesses in the second device regions, the method further comprises: forming a third epitaxial layer in the third recesses, the third epitaxial layer containing P-type ions.

8. The method of forming a semiconductor structure of claim 7, wherein, The material of the third epitaxial layer comprises SiGe.

9. The method of forming a semiconductor structure of claim 7, wherein, After forming the third epitaxial layer in the third recesses, the method further comprises: removing the first mask layer; forming a second mask layer on the substrate, the second mask layer exposing the first device regions; and etching the substrate of the first device regions to form fourth recesses in the first device regions.

10. The method of forming a semiconductor structure of claim 9, wherein, After forming the fourth recesses in the first device regions, the method further comprises: forming a fourth epitaxial layer in the fourth recesses, the fourth epitaxial layer containing N-type ions.

11. The method of forming a semiconductor structure of claim 10, wherein, The material of the fourth epitaxial layer comprises SiP.

12. The method of forming a semiconductor structure of claim 10, wherein, After forming the first epitaxial layer, the second epitaxial layer, the third epitaxial layer, and the fourth epitaxial layer, the method further comprises: forming an interlayer dielectric layer on the substrate, a top surface of the interlayer dielectric layer being flush with top surfaces of the first dummy gate structures and the second dummy gate structures.

13. The method of forming a semiconductor structure of claim 12, wherein, After forming the interlayer dielectric layer, further comprising: removing the first dummy gate structure and the second dummy gate structure, forming a first gate opening and a second gate opening in the interlayer dielectric layer; forming a first gate structure in the first gate opening and a second gate structure in the second gate opening.

14. The method of forming a semiconductor structure of claim 4, wherein, When the material of the first epitaxial layer and the second epitaxial layer is SiP, the first mask layer further exposes the first device region, and when forming the first recess and the second recess, further comprising: etching the substrate of the first device region to form a fourth recess in the first device region.

15. The method of forming a semiconductor structure of claim 4, wherein, Before forming the first dummy gate structure and the second dummy gate structure, further comprising: forming an isolation layer on the substrate of the first region and the second region.

16. A semiconductor structure, characterized by formed by the forming method of any one of claims 1 to 15, comprising: a substrate, the substrate comprising a plurality of adjacent first regions and second regions, the first regions and the second regions being arranged along a first direction, the first regions comprising first contact-out regions and first device regions, the second regions comprising second contact-out regions and second device regions, the first contact-out regions and the first device regions and the second contact-out regions and the second device regions being arranged along a second direction, the second direction being perpendicular to the first direction; a P-well in the substrate of the first contact-out regions and the first device regions; an N-well in the substrate of the second contact-out regions and the second device regions; an isolation layer on the substrate of the first regions and the second regions; a first gate structure covering part of the substrate surface of the first contact-out regions and the second contact-out regions; a second gate structure covering part of the substrate surface of the first device regions and the second device regions; a first epitaxial layer in the substrate of the first contact-out regions on both sides of the first gate structure, the first epitaxial layer having N-type ions therein; a second epitaxial layer in the substrate of the second contact-out regions on both sides of the first gate structure, the second epitaxial layer having P-type ions therein, the material of the first epitaxial layer and the material of the second epitaxial layer being the same; a third epitaxial layer in the substrate of the second device regions on both sides of the second gate structure, the third epitaxial layer having P-type ions therein; a fourth epitaxial layer in the substrate of the first device regions on both sides of the second gate structure, the fourth epitaxial layer having N-type ions therein, the material of the fourth epitaxial layer and the material of the third epitaxial layer being different.

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