A semiconductor device and a method of fabricating the same

Abstract

The application provides a semiconductor device and a manufacturing method thereof, and relates to the technical field of semiconductors. A wide band gap substrate is provided first, then a wide band gap epitaxial layer is formed on the wide band gap substrate, and a first gate oxide layer is formed on the side of the wide band gap epitaxial layer far from the wide band gap substrate; wherein the first gate oxide layer is a silicon oxide layer doped with nitrogen and phosphorus, and finally, a second gate oxide layer is formed on the side of the first gate oxide layer far from the wide band gap substrate, and the second gate oxide layer is a silicon oxide layer doped with nitrogen or a non-doped silicon oxide layer. The semiconductor device and the manufacturing method thereof provided by the application have the advantages of reducing the interface state density and improving the channel mobility.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] Silicon carbide, as an important third-generation semiconductor material, possesses advantages such as a wide bandgap, a high critical breakdown electric field, and high thermal conductivity. Therefore, compared to traditional silicon-based power devices, silicon carbide power devices offer advantages such as higher breakdown voltage, faster switching speed, and higher operating temperature, making them highly promising for applications in new energy vehicles, photovoltaic power generation, and electric vehicle traction.

[0003] The fabrication of the gate oxide structure is the core process of SiC MOSFET devices. It is necessary to solve the problem that a large number of defects, especially carbon clusters, will appear at the SiC / SiO2 interface during the thermal oxidation of SiC to form SiO2. This results in high interface state density and low channel mobility, which greatly limits the forward current carrying capacity of SiC MOSFETs and even leads to a series of gate oxide reliability problems.

[0004] Therefore, in existing technologies, after SiC is oxidized to SiO2, annealing in a nitrogen-doped atmosphere can passivate the SiC / SiO2 interface and reduce the interface state density. However, since the oxidized SiO2 is generally quite thick, the nitrogen content at the SiC / SiO2 interface is not high after annealing in a high-temperature nitrogen-doped atmosphere, resulting in limited reduction in the interface state density.

[0005] In summary, existing technologies suffer from low nitrogen content and high interface state density at the SiC / SiO2 interface. Summary of the Invention

[0006] The purpose of this application is to provide a semiconductor device and its fabrication method to solve the problems of low nitrogen content and high interface state density at the SiC / SiO2 interface in the prior art.

[0007] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:

[0008] In a first aspect, embodiments of this application provide a semiconductor device, the semiconductor device comprising:

[0009] Wide bandgap substrate;

[0010] Wide-gap epitaxial layer disposed on the wide-gap substrate;

[0011] A first gate oxide layer is disposed on the side of the wide bandgap epitaxial layer away from the wide bandgap substrate, wherein the first gate oxide layer is a nitrogen- and phosphorus-doped silicon oxide layer;

[0012] A second gate oxide layer is disposed on the side of the first gate oxide layer away from the wide bandgap substrate; wherein the second gate oxide layer is a nitrogen-doped silicon oxide layer or an undoped silicon oxide layer.

[0013] Optionally, the thickness of the first gate oxide layer is less than the thickness of the second gate oxide layer.

[0014] Optionally, the thickness of the first gate oxide layer is And / or,

[0015] The thickness of the second gate oxide layer is

[0016] Optionally, in the first gate oxide layer, the doping concentration of P is highest at the interface between the wide bandgap epitaxial layer and the first gate oxide layer.

[0017] Optionally, the second gate oxide layer is a nitrogen-doped silicon oxide layer, and the nitrogen doping concentration of the first gate oxide layer is greater than the nitrogen doping concentration of the second gate oxide layer.

[0018] Optionally, the P doping concentration in the first gate oxide layer is 1E13 / cm. 3 -1E15 / cm 3 .

[0019] Optionally, the N doping concentration in the first gate oxide layer is 1E14 / cm³. 3 -5E16 / cm 3 .

[0020] Optionally, the wide bandgap substrate is a silicon carbide substrate; and / or

[0021] The wide-bandgap epitaxial layer is a silicon carbide epitaxial layer.

[0022] Secondly, this application also provides a method for fabricating a semiconductor device, the method comprising:

[0023] Provide a wide bandgap substrate;

[0024] A wide-gap epitaxial layer is formed on the wide-gap substrate;

[0025] A first gate oxide layer is formed on the side of the wide bandgap epitaxial layer away from the wide bandgap substrate; wherein the first gate oxide layer is a nitrogen- and phosphorus-doped silicon oxide layer;

[0026] A second gate oxide layer is formed on the side of the first gate oxide layer away from the wide bandgap substrate. The second gate oxide layer is a nitrogen-doped silicon oxide layer or an undoped silicon oxide layer.

[0027] Optionally, the step of forming a first gate oxide layer on the side of the wide-bandgap epitaxial layer away from the wide-bandgap substrate includes:

[0028] A phosphorus-doped third gate oxide layer is fabricated on the side of the wide-bandgap epitaxial layer away from the wide-bandgap substrate.

[0029] The phosphorus-doped third gate oxide layer is annealed in a nitrogen-doped atmosphere to form the first gate oxide layer.

[0030] Optionally, the fabrication of a phosphorus-doped third gate oxide layer on the side of the wide-bandgap epitaxial layer away from the wide-bandgap substrate includes:

[0031] A phosphorus-doped silicon layer is formed on the side of the wide bandgap epitaxial layer away from the wide bandgap substrate using an in-situ doping process.

[0032] The phosphorus-doped silicon layer is thermally oxidized to form a third gate oxide layer.

[0033] Optionally, the fabrication of a p-doped third gate oxide layer on the side of the wide-bandgap epitaxial layer away from the wide-bandgap substrate includes:

[0034] A polycrystalline silicon layer is fabricated on the side of the wide-bandgap epitaxial layer away from the wide-bandgap substrate;

[0035] P-doped polycrystalline silicon layers are fabricated using ion implantation or diffusion processes.

[0036] The polycrystalline silicon layer is thermally oxidized to form a P-doped third gate oxide layer.

[0037] Optionally, the step of forming a second gate oxide layer on the side of the first gate oxide layer away from the wide-bandgap substrate includes:

[0038] A SiO2 layer is deposited on the side of the first gate oxide layer away from the wide bandgap substrate to form an undoped SiO2 second gate oxide layer; or,

[0039] A polysilicon layer is deposited on the side of the first gate oxide layer away from the wide bandgap substrate;

[0040] The polycrystalline silicon layer is oxidized to form an undoped SiO2 second gate oxide layer.

[0041] Optionally, the step of forming a second gate oxide layer on the side of the first gate oxide layer away from the wide-bandgap substrate includes:

[0042] A second gate oxide layer is formed in a nitrogen-doped atmosphere; wherein the nitrogen doping concentration of the first gate oxide layer is greater than that of the second gate oxide layer.

[0043] Optionally, the thickness of the first gate oxide layer is less than the thickness of the second gate oxide layer.

[0044] Optionally, the thickness of the first gate oxide layer is And / or,

[0045] The thickness of the second gate oxide layer is

[0046] Compared with the prior art, this application has the following advantages:

[0047] This application provides a semiconductor device and its fabrication method. First, a wide-gap substrate is provided. Then, a wide-gap epitaxial layer is formed on the wide-gap substrate. Next, a first gate oxide layer is formed on the side of the wide-gap epitaxial layer away from the wide-gap substrate. The first gate oxide layer is a nitrogen- and phosphorus-doped silicon oxide layer. Finally, a second gate oxide layer is formed on the side of the first gate oxide layer away from the wide-gap substrate. The second gate oxide layer is either a nitrogen-doped silicon oxide layer or an undoped silicon oxide layer. Because the semiconductor device fabrication method provided in this application fabricates the first and second gate oxide layers based on the surface of the wide-gap epitaxial layer, and the first gate oxide layer is a nitrogen- and phosphorus-doped silicon oxide layer, the doping concentration at the interface between the first gate oxide layer and the wide-gap epitaxial layer is relatively high, thereby reducing the interface state density and improving the channel mobility.

[0048] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0049] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 A schematic diagram of a hierarchical structure for fabricating semiconductor devices using existing technology.

[0051] Figure 2 A schematic diagram of another hierarchical structure for fabricating semiconductor devices using existing technology.

[0052] Figure 3 An exemplary flowchart illustrating a semiconductor device fabrication method provided in an embodiment of this application.

[0053] Figure 4 This is a schematic diagram of a first hierarchical structure of a semiconductor device provided in an embodiment of this application.

[0054] Figure 5 Provided for the embodiments of this application Figure 3 An exemplary flowchart of the sub-step S106.

[0055] Figure 6 This is a schematic diagram of a second hierarchical structure of a semiconductor device provided in an embodiment of this application.

[0056] Figure 7 This is a schematic diagram of a third-level structure of a semiconductor device provided in an embodiment of this application. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0058] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0059] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0060] It should be noted that in this paper, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0061] The term "fabrication / deposition of B on the side of A away from the wide bandgap substrate" means that A includes two sides, a front side and a back side, with the back side facing the wide bandgap substrate and the front side facing the opposite direction of the wide bandgap substrate, and B is connected to the front side of A. The term "forming B on A" means forming B on the front side of A.

[0062] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0063] As described in the background section, the fabrication of the gate oxide structure is the core process for SiC MOSFET devices. The current fabrication process for the gate oxide structure is as follows:

[0064] like Figure 1 As shown, a wide-bandgap epitaxial layer of SiC is first grown on a SiC wide-bandgap substrate. Then, a thermal oxidation process is used to oxidize the top SiC wide-bandgap epitaxial layer to form a SiO2 gate oxide layer. The structure after oxidation is shown in the figure. Figure 2 As stated above.

[0065] However, in existing technologies, the SiC / SiO2 interface is prone to numerous defects, particularly carbon cluster defects, during the thermal oxidation process. This results in a high interface state density and low channel mobility. Optimizing the oxidation and annealing processes of the gate oxide structure can effectively reduce the interface state density. Therefore, a common industry practice is to passivate the SiC / SiO2 interface and reduce the interface state density by annealing the SiC to SiO2 in a nitrogen-doped atmosphere.

[0066] However, as Figure 2 As shown, since the thickness of the gate oxide of oxidized SiO2 is generally 40-60nm, which is relatively thick, the nitrogen content at the SiC / SiO2 interface is not actually high after annealing in a high-temperature nitrogen-doped atmosphere, and the reduction in interface state density is limited.

[0067] In view of this, in order to solve the above problems, this application provides a method for fabricating a semiconductor device, which increases the doping concentration at the interface and reduces the interface state density by setting a first gate oxide layer and a second gate oxide layer, and setting the thickness of the first gate oxide layer to be relatively thin and the doping concentration to be relatively high.

[0068] The semiconductor device fabrication method provided in this application is illustrated below:

[0069] As an optional implementation, please refer to Figure 3 The method for fabricating this semiconductor device includes:

[0070] S102 provides a wide bandgap substrate.

[0071] S104, a wide-bandgap epitaxial layer is formed on a wide-bandgap substrate.

[0072] S106, a first gate oxide layer is formed on the side of the wide bandgap epitaxial layer away from the wide bandgap substrate; wherein the first gate oxide layer is a nitrogen- and phosphorus-doped silicon oxide layer.

[0073] S108, a second gate oxide layer is formed on the side of the first gate oxide layer away from the wide bandgap substrate. The second gate oxide layer is a nitrogen-doped silicon oxide layer or an undoped silicon oxide layer.

[0074] Understandably, the first gate oxide layer and the second gate oxide layer together form the gate oxide structure. Since the first gate oxide layer is thinner than the second gate oxide layer, and the first gate oxide layer is a nitrogen and phosphorus doped silicon oxide layer with a high doping concentration, the doping concentration at the interface between the first gate oxide layer and the wide bandgap epitaxial layer is also relatively high, which can reduce the interface state density and improve the channel mobility of the device.

[0075] This application does not limit the materials of the wide-gap substrate and the wide-gap epitaxial layer. For example, the wide-gap substrate can be a SiC wide-gap substrate, a Si wide-gap substrate, a sapphire wide-gap substrate, etc., and the wide-gap epitaxial layer can be homoepitaxial or heteroepitaxial. For example, taking a SiC wide-gap substrate and a SiC wide-gap epitaxial layer as an example, the structure after growing the wide-gap epitaxial layer is as follows. Figure 1 As shown. Since epitaxial growth technology is relatively mature, it will not be described in detail here. For example, wide-bandgap epitaxial layers can be grown using vapor phase epitaxy.

[0076] After growing a wide-bandgap epitaxial layer of the target thickness, please refer to... Figure 4 Gate oxide needs to be grown on the surface of the wide-bandgap epitaxial layer. Generally, the gate oxide is a SiO2 oxide layer, meaning both the first and second gate oxide layers are SiO2 layers. For ease of explanation, the gate oxide will be referred to as a SiO2 layer in the following description. Optionally, to remove impurities from the surface of the wide-bandgap epitaxial layer, a standard RCA cleaning process needs to be performed on the wide-bandgap epitaxial layer after its growth. Furthermore, the oxide layer provided in this application is the gate oxide, which can be a SiO2 oxide layer. It should be noted that... Figure 4 The proportions of each layer in the diagram are for illustrative purposes only and do not represent the actual proportions. For example, in actual manufacturing, the thickness of the first gate oxide layer is relatively thin.

[0077] To increase the doping concentration at the interface, when fabricating the gate oxide structure, a first gate oxide layer with a high doping concentration is first fabricated on the surface of the wide bandgap epitaxial layer, and then a second gate oxide layer is fabricated, so that the thickness of the first gate oxide layer and the second gate oxide layer reaches the preset thickness.

[0078] As one implementation method, please refer to Figure 5 S106 includes:

[0079] S1061, a P-doped third gate oxide layer is fabricated on the side of the wide bandgap epitaxial layer away from the wide bandgap substrate.

[0080] S1062, the phosphorus-doped third gate oxide layer is annealed in a nitrogen-doped atmosphere to form the first gate oxide layer.

[0081] N-type doping refers to doping where the majority carrier is an electron, typically P (phosphorus) or N (nitrogen). Therefore, in the fabrication process of this application, a P-doped third gate oxide layer can be first fabricated on the surface of the wide bandgap epitaxial layer, and then annealed using an annealing process. Generally, annealing needs to be carried out in a high-temperature environment, for example, annealing at 1250°C for 30 minutes or annealing in an argon atmosphere for 90 minutes.

[0082] Through annealing, phosphorus (P) can be pushed to the interface between the gate oxide layer and the wide bandgap epitaxial layer based on the principle of high-temperature diffusion, forming the first gate oxide layer. Understandably, both the first and third gate oxide layers are actually P-doped gate oxide layers. The difference is that in the third gate oxide layer, the distribution of doped P is more uniform, while in the first gate oxide layer, due to the annealing process, the doped P is mainly distributed at the interface between the gate oxide layer and the wide bandgap epitaxial layer.

[0083] If the wide bandgap epitaxial layer is a SiC wide bandgap epitaxial layer and the first gate oxide layer is a SiO2 layer, then after annealing, the P element is actually pushed to the SiC / SiO2 interface, resulting in a higher phosphorus content at the SiC / SiO2 interface and improving the channel mobility of the device.

[0084] In one implementation, S1061 includes:

[0085] S1061-1, a phosphorus-doped silicon layer is formed on the side of the wide bandgap epitaxial layer away from the wide bandgap substrate using an in-situ doping process.

[0086] S1061-2, the silicon layer is thermally oxidized to form the third gate oxide layer.

[0087] In this implementation, the specific process for growing the P-doped polysilicon layer is not limited. For example, a silicon layer can be deposited in situ with PH3 doping at 550°C using LPCVD (Low Pressure Chemical Vapor Deposition), followed by thermal oxidation at 750°C to form the P-doped polysilicon layer. The layer structure after P doping is as follows: Figure 6 As shown in the diagram. In-situ doping refers to introducing a gas containing impurities, such as PH3 or B2H6, during the deposition of the silicon layer to achieve uniform doping. This process results in more uniform silicon doping, is simpler, and has lower costs. Of course, other processes can also be used to grow the P-doped first gate oxide layer, such as CVD or molecular beam epitaxy; this is not a limitation here.

[0088] It should be noted that, in order to ensure a higher doping concentration at the interface, N can be further doped in subsequent processes after P doping. The hierarchical structure after nitrogen doping is as follows: Figure 7As shown. To ensure a sufficiently high doping concentration in the first gate oxide layer in this application, the thickness of the first gate oxide layer needs to be set to a relatively low value to achieve better doping. Optionally, the thickness of the first gate oxide layer is...

[0089] In another implementation, S1061 includes:

[0090] S1061-3, a polycrystalline silicon layer is fabricated on the side of the wide-bandgap epitaxial layer away from the wide-bandgap substrate.

[0091] S1061-2, a P-doped polycrystalline silicon layer is fabricated by ion implantation or diffusion process.

[0092] S1061-3 involves thermally oxidizing the polycrystalline silicon layer to form a P-doped third gate oxide layer.

[0093] In this application, not only can the first gate oxide layer be fabricated using an in-situ doping process, but a P-doped gate oxide layer can also be fabricated using a process that first deposits intrinsic polysilicon and then performs doping. For example, an intrinsic polysilicon thin film can be grown using LPCVD, and then a phosphorus-doped gate oxide layer can be formed using ion implantation or furnace diffusion processes. Then, a thermal oxidation process can be used to oxidize the polysilicon to silicon dioxide to form a P-doped third gate oxide layer.

[0094] This method of fabricating the third gate oxide layer eliminates the need for the existing SiC thermal oxidation process to form SiO2, thus avoiding carbon cluster defects introduced by the thermal oxidation process, reducing the interface state density, and improving channel mobility. Furthermore, in existing technologies, overall annealing after the gate oxide structure is fabricated results in a relatively low actual doping concentration at the interface. In this application, annealing is performed after fabricating the third gate oxide layer, which is relatively thin, only [a small amount of material is needed for the final fabrication]. Therefore, it can be ensured that the doped P element is pushed to the interface between the third gate oxide layer and the wide bandgap epitaxial layer during annealing, forming the first gate oxide layer. This results in a higher doping concentration on the side closer to the wide bandgap epitaxial layer than on the side farther away from the wide bandgap epitaxial layer in the first gate oxide layer, meaning that the P element content at the interface is higher, thus improving the channel mobility.

[0095] To further increase the doping concentration at the interface, in one optional implementation, S1062 includes:

[0096] The P-doped third gate oxide layer is annealed in a nitrogen-doped atmosphere to form the first gate oxide layer.

[0097] Optionally, when annealing the third gate oxide layer, it can be annealed at 1250°C in a nitrogen-doped atmosphere for 30 min and in an argon atmosphere for 90 min to form a phosphorus-doped and nitrogen-doped first gate oxide layer. The nitrogen-doped atmosphere includes, but is not limited to, nitrogen, nitric oxide, and nitrous oxide atmospheres.

[0098] Because the thickness of the first gate oxide layer is relatively thin, only Therefore, annealing in a nitrogen-doped atmosphere can result in better nitriding and higher P and N content at the interface. In addition, since the annealing process is also completed at high temperature, N can be pushed to the interface, increasing the P and N content at the interface and further improving the channel mobility of the device.

[0099] In one alternative implementation, the P doping concentration in the first gate oxide layer is 1E13 / cm². 3 -1E15 / cm 3 The N doping concentration in the first gate oxide layer is 1E13 / cm. 3 -1E15 / cm 3 Furthermore, this application does not limit the fabrication process of the second gate oxide layer, wherein the second gate oxide layer includes a nitrogen-doped silicon oxide layer and an undoped silicon oxide layer.

[0100] When fabricating an undoped second gate oxide layer, as an optional implementation, a SiO2 layer can be deposited on the side of the first gate oxide layer away from the wide bandgap substrate, thereby forming an undoped SiO2 second gate oxide layer. For example, a SiO2 dielectric layer can be deposited using an LPCVD process, so that the thicknesses of the first and second gate oxide layers reach a predetermined gate oxide thickness setting value. For example, the thickness of the first gate oxide layer is... The thickness of the second gate oxide layer is

[0101] As an alternative implementation, a polysilicon layer can be deposited on the side of the first gate oxide layer away from the wide bandgap substrate, and then the polysilicon layer can be oxidized to form an undoped SiO2 layer.

[0102] When fabricating the doped second gate oxide layer, as an optional implementation, the second gate oxide layer can be formed in a nitrogen-doped atmosphere, resulting in an N-doped second gate oxide layer. Furthermore, the nitrogen doping concentration of the first gate oxide layer is greater than that of the second gate oxide layer. For example, the thickness of the second gate oxide layer is 15 to 80 times the thickness of the first gate oxide layer. As an optional implementation, the thickness of the first gate oxide layer is... The thickness of the second gate oxide layer is

[0103] Of course, after fabricating the gate oxide structure, it is also necessary to define the active region and electrode processes. Since these processes are conventional, they will not be described in detail in this embodiment.

[0104] In summary, the semiconductor device fabrication method provided in this application, by depositing a silicon thin film through in-situ doping with PH3 or ion implantation, can achieve more uniform silicon film doping, saving production efficiency and costs. Simultaneously, phosphorus at the SiC / SiO2 interface can improve the channel mobility of the device. Furthermore, by oxidizing the silicon thin film at a high temperature of 750℃ to form the first gate oxide layer (SiO2 dielectric), the carbon clusters generated during the SiC thermal oxidation process to form SiO2 are reduced, thus lowering the interface state density. Simultaneously, high-temperature diffusion during annealing further promotes phosphorus deposition, resulting in a higher phosphorus content at the interface between the wide-bandgap epitaxial layer and the first gate oxide layer (SiC / SiO2 interface), thereby improving the device's channel mobility. In addition, because the first gate oxide layer is relatively thin, annealing in a nitrogen-doped atmosphere facilitates nitriding of the first gate oxide layer, increasing the nitrogen content at the interface and further improving the device's channel mobility.

[0105] Based on the above implementation, this application also provides a semiconductor device, which is fabricated by the above-described method, wherein the semiconductor device includes:

[0106] The system comprises a wide bandgap substrate, a wide bandgap epitaxial layer, a first gate oxide layer, and a second gate oxide layer. The wide bandgap epitaxial layer is located on the surface of the wide bandgap substrate. The first gate oxide layer is located on the side of the wide bandgap epitaxial layer away from the wide bandgap substrate and is a nitrogen- and phosphorus-doped silicon oxide layer. The second gate oxide layer is located on the side of the first gate oxide layer away from the wide bandgap substrate. The second gate oxide layer can be either a nitrogen-doped silicon oxide layer or an undoped silicon oxide layer.

[0107] In one implementation, the thickness of the first gate oxide layer is less than the thickness of the second gate oxide layer, and the doping concentration of the first gate oxide layer is greater than the doping concentration of the second gate oxide layer.

[0108] As one implementation, to ensure better nitriding effect of the first gate oxide layer, the thickness of the first gate oxide layer is relatively small. Optionally, the thickness of the first gate oxide layer is [missing information]. Furthermore, during the fabrication of the first gate oxide layer, the annealing process can push the P and N elements to the interface between the first gate oxide layer and the wide bandgap epitaxial layer, thereby maximizing the P doping concentration at the interface between the wide bandgap epitaxial layer and the first gate oxide layer.

[0109] Optionally, the first gate oxide layer comprises a N-doped and a P-doped SiO2 layer, and the second gate oxide layer comprises a doped or undoped SiO2 layer. Furthermore, the P doping concentration in the first gate oxide layer is 1E13 / cm³. 3 -1E15 / cm 3 The N doping concentration in the first gate oxide layer is 1E14 / cm. 3 -5E16 / cm 3 .

[0110] In summary, this application provides a semiconductor device and its fabrication method. First, a wide-gap substrate is provided. Then, a wide-gap epitaxial layer is formed on the wide-gap substrate. Next, a first gate oxide layer is formed on the side of the wide-gap epitaxial layer away from the wide-gap substrate. The first gate oxide layer is a nitrogen- and phosphorus-doped silicon oxide layer. Finally, a second gate oxide layer is formed on the side of the first gate oxide layer away from the wide-gap substrate. The second gate oxide layer is either a nitrogen-doped silicon oxide layer or an undoped silicon oxide layer. Because the semiconductor device fabrication method provided in this application fabricates the first and second gate oxide layers based on the surface of the wide-gap epitaxial layer, and the first gate oxide layer is a nitrogen- and phosphorus-doped silicon oxide layer, the doping concentration at the interface between the first gate oxide layer and the wide-gap epitaxial layer is relatively high, thereby reducing the interface state density and improving the channel mobility.

[0111] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0112] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: Wide bandgap substrate; Wide-gap epitaxial layer disposed on the wide-gap substrate; A first gate oxide layer is disposed on the side of the wide bandgap epitaxial layer away from the wide bandgap substrate. The first gate oxide layer is a nitrogen- and phosphorus-doped silicon oxide layer. In the first gate oxide layer, the phosphorus doping concentration is the highest at the interface between the wide bandgap epitaxial layer and the first gate oxide layer. A second gate oxide layer is disposed on the side of the first gate oxide layer away from the wide bandgap substrate; wherein the second gate oxide layer is a nitrogen-doped silicon oxide layer or an undoped silicon oxide layer.

2. The semiconductor device as claimed in claim 1, characterized in that, The thickness of the first gate oxide layer is less than the thickness of the second gate oxide layer.

3. The semiconductor device as described in claim 2, characterized in that, The thickness of the first gate oxide layer is 10~250 Å; and / or, The thickness of the second gate oxide layer is 200 Å - 400 Å.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The second gate oxide layer is a nitrogen-doped silicon oxide layer, and the nitrogen doping concentration of the first gate oxide layer is greater than that of the second gate oxide layer.

5. The semiconductor device as described in claim 3, characterized in that, The phosphorus doping concentration in the first gate oxide layer is 1E13 / cm. 3 -1E15 / cm 3 .

6. The semiconductor device as claimed in claim 5, characterized in that, The N doping concentration in the first gate oxide layer is 1E13 / cm. 3 -1E15 / cm 3 .

7. The semiconductor device according to any one of claims 1 to 3, characterized in that, The wide-bandgap substrate is a silicon carbide substrate; and / or The wide-bandgap epitaxial layer is a silicon carbide epitaxial layer.

8. A method for fabricating a semiconductor device, characterized in that, The semiconductor device fabrication method includes: Provide a wide bandgap substrate; A wide-gap epitaxial layer is formed on the wide-gap substrate; A first gate oxide layer is formed on the side of the wide bandgap epitaxial layer away from the wide bandgap substrate; wherein the first gate oxide layer is a nitrogen and phosphorus doped silicon oxide layer; and in the first gate oxide layer, the phosphorus doping concentration is the highest at the interface between the wide bandgap epitaxial layer and the first gate oxide layer. A second gate oxide layer is formed on the side of the first gate oxide layer away from the wide bandgap substrate. The second gate oxide layer is a nitrogen-doped silicon oxide layer or an undoped silicon oxide layer.

9. The method for fabricating a semiconductor device as described in claim 8, characterized in that, The step of forming a first gate oxide layer on the side of the wide-bandgap epitaxial layer away from the wide-bandgap substrate includes: A phosphorus-doped third gate oxide layer is fabricated on the side of the wide-bandgap epitaxial layer away from the wide-bandgap substrate. The phosphorus-doped third gate oxide layer is annealed in a nitrogen-doped atmosphere to form the first gate oxide layer.

10. The method for fabricating a semiconductor device as described in claim 9, characterized in that, The fabrication of a phosphorus-doped third gate oxide layer on the side of the wide-bandgap epitaxial layer away from the wide-bandgap substrate includes: A phosphorus-doped silicon layer is formed on the side of the wide bandgap epitaxial layer away from the wide bandgap substrate using an in-situ doping process. The phosphorus-doped silicon layer is thermally oxidized to form a third gate oxide layer.

11. The method for fabricating a semiconductor device as described in claim 9, characterized in that, The fabrication of a P-doped third gate oxide layer on the side of the wide-bandgap epitaxial layer away from the wide-bandgap substrate includes: A polycrystalline silicon layer is fabricated on the side of the wide-bandgap epitaxial layer away from the wide-bandgap substrate; P-doped polycrystalline silicon layers are fabricated using ion implantation or diffusion processes. The polycrystalline silicon layer is thermally oxidized to form a P-doped third gate oxide layer.

12. The method for fabricating a semiconductor device as described in claim 9, characterized in that, The step of forming a second gate oxide layer on the side of the first gate oxide layer away from the wide bandgap substrate includes: A SiO2 layer is deposited on the side of the first gate oxide layer away from the wide bandgap substrate to form an undoped SiO2 second gate oxide layer; or, A polysilicon layer is deposited on the side of the first gate oxide layer away from the wide bandgap substrate; The polycrystalline silicon layer is oxidized to form an undoped SiO2 second gate oxide layer.

13. The method for fabricating a semiconductor device as described in claim 8, characterized in that, The step of forming a second gate oxide layer on the side of the first gate oxide layer away from the wide bandgap substrate includes: A second gate oxide layer is formed in a nitrogen-doped atmosphere; wherein the nitrogen doping concentration of the first gate oxide layer is greater than that of the second gate oxide layer.

14. The method for fabricating a semiconductor device as described in claim 8, characterized in that, The thickness of the first gate oxide layer is less than the thickness of the second gate oxide layer.

15. The method for fabricating a semiconductor device as described in claim 8, characterized in that, The thickness of the first gate oxide layer is 10~250 Å; and / or, The thickness of the second gate oxide layer is 200 Å - 400 Å.

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