Fan-out detection method
By acquiring and calculating the physical and parasitic parameters of the target circuit, and adjusting the resistance and capacitance of the components in the circuit, the problem of inaccurate fan-out results was solved, and the driving capability of the circuit was improved.
Patent Information
- Application Number
- CN202211439256.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-11-17
- Publication Date
- 2026-01-02
- Estimated Expiration
- 2042-11-17
AI Technical Summary
Existing technology cannot accurately calculate fan-out results, which makes it impossible to effectively adjust the driving capability of the drive unit and affects circuit performance.
By acquiring the physical parameters of each component in the target circuit and the parasitic parameters of the connecting wires, as well as the physical parameters of the standard circuit, the actual fan-out of the target circuit relative to the standard circuit is calculated. If the ratio does not reach the target ratio, the resistance and capacitance of the components in the target circuit are adjusted until the target effect is achieved.
It enables accurate calculation and adjustment of the actual fan-out of the target circuit, effectively improving the circuit's driving capability.
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Figure CN115733485B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of memory, in particular to a fan-out detection method. BACKGROUND
[0002] Fan-out refers to the amount of load driven by a single logic gate. At present, fan-out is mainly estimated by considering the parameters of the driving unit and the load unit itself, for example, one inverter (inv) driving one inverter of the same size is recorded as fan-out 1, and one inverter driving two inverters of the same size is recorded as fan-out 2.
[0003] However, in actual applications, the driving unit and the load unit are different, or the driving unit and the load unit are the same but have different sizes, or the parasitic parameters on the connection lines of the driving unit and the load unit, etc., all of which will affect the accuracy of the fan-out result, so that the driving capability of the driving unit cannot be effectively adjusted according to the fan-out result. SUMMARY
[0004] The present application provides a fan-out detection method, which effectively calculates the actual fan-out of a target circuit, so as to effectively adjust the driving capability of the target circuit.
[0005] In a first aspect, the present application provides a fan-out detection method, comprising:
[0006] obtaining physical parameters of components in a target circuit and parasitic parameters of connection wires, and physical parameters of components in a standard circuit, wherein the physical parameters include resistance and capacitance of the components, and the standard circuit has a corresponding standard fan-out;
[0007] calculating an actual fan-out of the target circuit relative to the standard circuit according to the physical parameters of the components in the target circuit and the parasitic parameters of the connection wires, and the physical parameters of the components in the standard circuit;
[0008] if a ratio of the actual fan-out to the standard fan-out does not reach a target ratio, adjusting resistance and / or capacitance of the components in the target circuit until the ratio of the actual fan-out to the standard fan-out reaches the target ratio, so that the actual fan-out of the target circuit reaches a target fan-out.
[0009] In some embodiments, the standard fan-out includes a first standard fan-out, the first standard fan-out corresponds to a fan-out of a P-type transistor, and the components include a P-type transistor and an N-type transistor, and the parasitic parameters include parasitic capacitance.
[0010] The calculating of the actual fan-out of the target circuit relative to the standard circuit according to the physical parameters of the components in the target circuit and the parasitic parameters of the connection wires, and the physical parameters of the components in the standard circuit specifically includes:
[0011] According to the resistance and capacitance of the P-type transistor, the capacitance of the N-type transistor, and the parasitic capacitance of the connecting wire in the target circuit, the resistance and capacitance of the P-type transistor, and the capacitance of the N-type transistor in the standard circuit, the first actual fan-out of the target circuit is calculated;
[0012] Correspondingly, if the ratio of the actual fan-out to the standard fan-out does not reach a target ratio, the resistance and / or capacitance of the transistor in the target circuit is adjusted until the ratio of the actual fan-out to the standard fan-out reaches the target ratio, specifically including:
[0013] If the ratio of the first actual fan-out to the first standard fan-out does not reach a first target ratio, the resistance and / or capacitance of the transistor in the target circuit is adjusted until the ratio of the first actual fan-out to the first standard fan-out reaches the first target ratio.
[0014] In some embodiments, the standard fan-out includes a second standard fan-out, the second standard fan-out corresponding to the fan-out of the N-type transistor, the component includes: a P-type transistor and an N-type transistor, and the parasitic parameter includes a parasitic capacitance;
[0015] According to the physical parameters of the components in the target circuit and the parasitic parameters of the connecting wire, and the physical parameters of the components in the standard circuit, the actual fan-out of the target circuit relative to the standard circuit is calculated, specifically including:
[0016] According to the resistance and capacitance of the N-type transistor, the capacitance of the P-type transistor, and the parasitic capacitance of the connecting wire in the target circuit, the resistance and capacitance of the N-type transistor, and the capacitance of the P-type transistor in the standard circuit, the second actual fan-out of the target circuit is calculated;
[0017] Correspondingly, if the ratio of the actual fan-out to the standard fan-out does not reach a target ratio, the resistance and / or capacitance of the transistor in the target circuit is adjusted until the ratio of the actual fan-out to the standard fan-out reaches the target ratio, specifically including:
[0018] If the ratio of the second actual fan-out to the second standard fan-out does not reach a second target ratio, the resistance and / or capacitance of the transistor in the target circuit is adjusted until the ratio of the second actual fan-out to the second standard fan-out reaches the second target ratio.
[0019] In some embodiments, according to the resistance and capacitance of the P-type transistor, the capacitance of the N-type transistor, and the parasitic capacitance of the connecting wire in the target circuit, the resistance and capacitance of the P-type transistor, and the capacitance of the N-type transistor in the standard circuit, and the first actual fan-out of the target circuit is calculated, specifically including:
[0020] calculating a first ratio of resistance of the P-type transistor in the target circuit to resistance of the P-type transistor in the standard circuit;
[0021] adding capacitance of the transistor in the target circuit and the parasitic capacitance to obtain a first capacitance, adding capacitance of the P-type transistor and the N-type transistor in the standard circuit to obtain a second capacitance, and calculating a second ratio of the first capacitance and the second capacitance;
[0022] multiplying the first ratio and the second ratio as the first actual fan-out of the target circuit.
[0023] In some embodiments, the calculating the first ratio of resistance of the P-type transistor in the target circuit to resistance of the P-type transistor in the standard circuit, specifically comprises:
[0024] calculating a third ratio of resistance of the N-type transistor in the target circuit to resistance of the N-type transistor in the standard circuit;
[0025] adding capacitance of the transistor in the target circuit and the parasitic capacitance to obtain a first capacitance, adding capacitance of the P-type transistor and the N-type transistor in the standard circuit to obtain a second capacitance, and calculating a second ratio of the first capacitance and the second capacitance;
[0026] multiplying the third ratio and the second ratio as the second actual fan-out of the target circuit.
[0027] In some embodiments, the calculating the first ratio of resistance of the P-type transistor in the target circuit to resistance of the P-type transistor in the standard circuit, specifically comprises:
[0028] when the P-type transistors in the target circuit are in parallel, selecting a P-type transistor with the largest resistance from the P-type transistors in the target circuit as a first target P-type transistor;
[0029] calculating a first ratio of resistance of the first target P-type transistor to resistance of the P-type transistor in the standard circuit.
[0030] In some embodiments, the calculating the third ratio of resistance of the N-type transistor in the target circuit to resistance of the N-type transistor in the standard circuit, specifically comprises:
[0031] when the N-type transistors in the target circuit are in series, adding resistances of the N-type transistors in the target circuit to obtain a first resistance;
[0032] calculating a third ratio of the first resistance to resistance of the N-type transistor in the standard circuit.
[0033] In some embodiments, the adding the capacitance of the transistor in the target circuit and the parasitic capacitance to obtain the first capacitance specifically comprises:
[0034] When the P-type transistor in the target circuit is in parallel and the N-type transistor is in series, the P-type transistor with the largest capacitance is selected from the P-type transistor in the target circuit as the second target P-type transistor.
[0035] The capacitance of the second target P-type transistor and the N-type transistor in the target circuit, and the parasitic capacitance are added to obtain the first capacitance.
[0036] In some embodiments, the target circuit comprises: a first P-type transistor, a second P-type transistor, a third P-type transistor, a first N-type transistor, a second N-type transistor and a third N-type transistor.
[0037] The gate of the first P-type transistor and the first N-type transistor receives a first control signal, the gate of the second P-type transistor and the second N-type transistor receives a second control signal, the gate of the third P-type transistor and the third N-type transistor receives a third control signal, the source of the first P-type transistor, the source of the second P-type transistor and the source of the third P-type transistor are connected to a power supply voltage, the drain of the first P-type transistor, the drain of the second P-type transistor and the drain of the third P-type transistor are connected to each other, the drain of the first N-type transistor is connected to the drain of the third P-type transistor, the source of the first N-type transistor is connected to the drain of the second N-type transistor, the source of the second N-type transistor is connected to the drain of the third N-type transistor, and the source of the third N-type transistor is grounded.
[0038] In some embodiments, the calculating the actual fan-out of the target circuit relative to the standard circuit according to the physical parameters of the components in the target circuit and the parasitic parameters of the connecting wires, and the physical parameters of the components in the standard circuit specifically comprises:
[0039] The resistance and capacitance of the first P-type transistor, the second P-type transistor and the third P-type transistor, and the resistance and capacitance of the first N-type transistor, the second N-type transistor and the third N-type transistor are obtained, and the actual fan-out of the target circuit relative to the standard circuit is calculated according to the resistance and capacitance of the first P-type transistor, the second P-type transistor and the third P-type transistor, and the resistance and capacitance of the first N-type transistor, the second N-type transistor and the third N-type transistor, and the parasitic parameters of the connecting wires, and the physical parameters of the components in the standard circuit.
[0040] In some embodiments, the actual fan-out of the target circuit relative to the standard circuit is calculated according to the resistance and capacitance of the first P-type transistor, the second P-type transistor and the third P-type transistor, the resistance and capacitance of the first N-type transistor, the second N-type transistor and the third N-type transistor, the parasitic parameters of the connecting wires, and the physical parameters of the components in the standard circuit, specifically comprising:
[0041] a P-type transistor with the largest resistance is selected from the first P-type transistor, the second P-type transistor and the third P-type transistor as a first target P-type transistor, and a P-type transistor with the largest capacitance is selected as a second target P-type transistor;
[0042] a first ratio of the resistance of the first target P-type transistor to the resistance of the P-type transistor in the standard circuit is calculated, and a first capacitance is obtained by adding the capacitance of the second target P-type transistor to the capacitance of the first N-type transistor, the capacitance of the second N-type transistor, the capacitance of the third N-type transistor and the parasitic capacitance of the connecting wires, and a second ratio of the first capacitance to the capacitance of the transistor in the standard circuit is calculated, and the product of the first ratio and the second ratio is taken as a first actual fan-out of the target circuit relative to the standard circuit;
[0043] If the ratio of the actual fan-out to the standard fan-out does not reach a target ratio, the resistance and / or capacitance of the components in the target circuit is adjusted until the ratio of the actual fan-out to the standard fan-out reaches the target ratio, specifically comprising:
[0044] If the ratio of the first actual fan-out to a first standard fan-out of the standard circuit does not reach a first target ratio, the resistance and / or capacitance of the transistor in the target circuit is adjusted until the ratio of the first actual fan-out to the first standard fan-out reaches the first target ratio.
[0045] In some embodiments, the actual fan-out of the target circuit relative to the standard circuit is calculated according to the resistance and capacitance of the first P-type transistor, the second P-type transistor and the third P-type transistor, the resistance and capacitance of the first N-type transistor, the second N-type transistor and the third N-type transistor, the parasitic parameters of the connecting wires, and the physical parameters of the components in the standard circuit, specifically comprising:
[0046] a P-type transistor with the largest capacitance is selected from the capacitance of the first P-type transistor, the second P-type transistor and the third P-type transistor as a second target P-type transistor;
[0047] add the resistance of the first N-type transistor, the resistance of the second N-type transistor and the resistance of the third N-type transistor to obtain a first resistance, calculate a third ratio of the first resistance to the resistance of the N-type transistor in the standard circuit; add the capacitance of the second target P-type transistor and the capacitance of the first N-type transistor, the capacitance of the second N-type transistor, the capacitance of the third N-type transistor and the parasitic capacitance of the connecting wire to obtain a first capacitance, calculate a fourth ratio of the first capacitance to the capacitance of the transistor in the standard circuit; take the product of the third ratio and the fourth ratio as the second actual fan-out of the target circuit relative to the standard circuit;
[0048] If the ratio of the actual fan-out and the standard fan-out does not reach a target ratio, adjust the resistance and / or capacitance of the components in the target circuit until the ratio of the actual fan-out and the standard fan-out reaches the target ratio, specifically comprising:
[0049] If the ratio of the second actual fan-out and the second standard fan-out does not reach a second target ratio, adjust the resistance and / or capacitance of the transistors in the target circuit until the ratio of the second actual fan-out and the second standard fan-out reaches the second target ratio.
[0050] In some embodiments, the standard circuit comprises a driving P-type transistor and a driving N-type transistor, the gates of the driving P-type transistor and the driving N-type transistor are connected to each other and receive a driving signal, the drain of the driving P-type transistor is connected to the drain of the driving N-type transistor, the source of the driving P-type transistor is connected to a power voltage, the source of the driving N-type transistor is grounded, the resistance and capacitance of the driving P-type transistor are the resistance and capacitance of the P-type transistor in the standard circuit, and the resistance and capacitance of the driving N-type transistor are the resistance and capacitance of the N-type transistor in the standard circuit.
[0051] The fan-out detection method provided in the present application obtains the physical parameters of the components in the target circuit and the parasitic parameters of the connecting wire, and the physical parameters of the components in the standard circuit, and calculates the actual fan-out of the target circuit relative to the standard circuit according to the physical parameters of the components in the target circuit and the parasitic parameters of the connecting wire, and the physical parameters of the components in the standard circuit, so as to effectively obtain the actual fan-out of the target circuit. When the ratio between the actual fan-out of the target circuit relative to the standard circuit and the standard fan-out of the standard circuit does not reach a target ratio, the resistance and / or capacitance of the components in the target circuit are adjusted until the ratio of the actual fan-out and the standard fan-out reaches the target ratio, so as to make the actual fan-out of the target circuit reach the target fan-out, thereby effectively adjusting the actual fan-out of the target circuit to the target fan-out and effectively adjusting the driving capability of the target circuit. BRIEF DESCRIPTION OF DRAWINGS
[0052] In order to more clearly illustrate the technical solutions in the application or the prior art, the accompanying drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced. Obviously, the accompanying drawings in the following description are some embodiments of the application, and other drawings can be obtained by those of ordinary skill in the art without any creative effort based on these drawings.
[0053] Figure 1 A schematic diagram of a standard circuit provided for an embodiment of the application;
[0054] Figure 2 A schematic diagram of another standard circuit provided for an embodiment of the application;
[0055] Figure 3 A flowchart of a fan-out detection method provided for an embodiment of the application;
[0056] Figure 4 A schematic diagram of a target circuit provided for an embodiment of the application. DETAILED DESCRIPTION
[0057] In order to make the objects, technical solutions and advantages of the application clearer, the technical solutions in the application will be described clearly and completely below with reference to the drawings in the application. Obviously, the described embodiments are some embodiments of the application, rather than all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those of ordinary skill in the art without any creative effort fall within the protection scope of the application.
[0058] Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. The application is intended to cover any variations, uses or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice in the art to which the application pertains or can relate to other fields of endeavor. The specification and examples are to be construed as merely illustrative of the present application and not limitative of the true scope and spirit of the application, which is measured by the book of claims.
[0059] Figure 1 A schematic diagram of a standard circuit provided for an embodiment of the application. Reference is made to Figure 1As shown, the standard circuit can include a first driving unit 101 and the standard circuit is used to drive a first load unit 102, the first driving unit 101 includes a first driving P-type transistor MP1 and a first driving N-type transistor MN1, the gate of the first driving P-type transistor MP1 and the gate of the first driving N-type transistor MN1 are connected to each other, and receive a first driving signal, the source of the first driving P-type transistor MP1 is connected to a first power supply end, the drain of the first driving P-type transistor MP1 is connected to the drain of the first driving N-type transistor MN1, and the source of the first driving N-type transistor MN1 is connected to a second power supply end. The first load unit 102 includes a first load P-type transistor MP2 and a first load N-type transistor MN2, the gates of the first load P-type transistor MP2 and the first load N-type transistor MN2 are connected to each other, and are connected to the drain of the first driving P-type transistor MP1 and the drain of the first driving N-type transistor MN1, the drain of the first load P-type transistor MP2 is connected to the drain of the first load N-type transistor MN2, the source of the first load P-type transistor MP2 is connected to the first power supply end, and the source of the first load N-type transistor MN2 is connected to the second power supply end.
[0060] When the first driving unit 101 drives one first load unit 102, the standard fan-out of the standard circuit is 1, the first driving unit 101 and the first load unit 102 have the same size, for example, the size of the first driving P-type transistor MP1 is the same as the size of the first load P-type transistor MP2, the size of the first driving N-type transistor MN1 is the same as the size of the first load N-type transistor MN2, for example, the length Lp1 of the first driving P-type transistor MP1 is the same as the length Lp2 of the first load P-type transistor MP2, the width Wp1 of the first driving P-type transistor MP1 is the same as the width Wp2 of the first load P-type transistor MP2, the length Ln1 of the first driving N-type transistor MN1 is the same as the length Ln2 of the first load N-type transistor MN2, and the width Wn1 of the first driving N-type transistor MN1 is the same as the width Wn2 of the first load N-type transistor MN2. It should be noted that the standard circuit has fewer transistors and fewer connection wires, and the influence of the parasitic parameters of the connection wires can be ignored.
[0061] Figure 2 Another schematic diagram of a standard circuit provided by the embodiment of the present application is provided. Referring to FIG. 3, the standard circuit includes a first driving unit 301 and a first load unit 302, the first driving unit 301 includes a first driving P-type transistor MP1 and a first driving N-type transistor MN1, the gate of the first driving P-type transistor MP1 and the gate of the first driving N-type transistor MN1 are connected to each other, and receive a first driving signal, the source of the first driving P-type transistor MP1 is connected to a first power supply end, the drain of the first driving P-type transistor MP1 is connected to the drain of the first driving N-type transistor MN1, and the source of the first driving N-type transistor MN1 is connected to a second power supply end. The first load unit 302 includes a first load P-type transistor MP2 and a first load N-type transistor MN2, the gates of the first load P-type transistor MP2 and the first load N-type transistor MN2 are connected to each other, and are connected to the drain of the first driving P-type transistor MP1 and the drain of the first driving N-type transistor MN1, the drain of the first load P-type transistor MP2 is connected to the drain of the first load N-type transistor MN2, the source of the first load P-type transistor MP2 is connected to the first power supply end, and the source of the first load N-type transistor MN2 is connected to the second power supply end. Figure 2As shown, the standard circuit can include a second driving unit 201, and the standard circuit can be used to drive the second load unit 202. The second driving unit 201 includes a second driving P-type transistor MP3 and a second driving N-type transistor MN3. The gate of the second driving P-type transistor MP3 and the gate of the second driving N-type transistor MN3 are connected to each other, and receive a second driving signal. The second driving signal can be the same as the first driving signal. The drain of the second driving P-type transistor MP3 is connected to the drain of the second driving N-type transistor MN3. The source of the second driving P-type transistor MP3 is connected to the first power supply end. The source of the second driving N-type transistor MN3 is connected to the second power supply end. The second load unit 202 includes a second load P-type transistor MP4, a second load N-type transistor MN4, a third load P-type transistor MP5, and a third load N-type transistor MN5. The gate of the second load P-type transistor MP4 and the gate of the second load N-type transistor MN4 are connected to each other, and are connected to the drain of the second driving P-type transistor MP3 and the drain of the second driving N-type transistor MN3. The drain of the second load P-type transistor MP4 is connected to the drain of the second load N-type transistor MN4. The source of the second load P-type transistor MP4 is connected to the first power supply end. The source of the second load N-type transistor MN4 is connected to the second power supply end. The gate of the third load P-type transistor MP5 and the gate of the third load N-type transistor MN5 are connected to each other, and are connected to the drain of the second driving P-type transistor MP3 and the drain of the second driving N-type transistor MN3. The drain of the third load P-type transistor MP5 is connected to the drain of the third load N-type transistor MN5. The source of the third load P-type transistor MP5 is connected to the first power supply end. The source of the third load N-type transistor MN5 is connected to the second power supply end.
[0062] When the second driving unit 201 drives the second load unit 202, the size of the second driving unit 202 is different from the size of the first driving unit 101. For example, the size of the first driving P-type transistor MP1 is different from the size of the second driving P-type transistor MP3, and the size of the first driving N-type transistor MN1 is different from the size of the second driving N-type transistor MN3. Therefore, the driving capability of the second driving unit 202 is different from the driving capability of the first driving unit 101. The size of the second load unit 202 is the same as the size of the first load unit 102. When the second driving unit 201 is driven, the second load unit 202 includes two inverters, that is, two first load units 102. Therefore, the standard fan-out corresponding to the second driving unit 201 is 2.
[0063] In actual applications, the structure of the driving unit of the actual circuit is different, or the structure of the driving unit is the same but the size is different, and the parasitic parameters on the connection lines of the driving unit and the load unit will affect the accuracy of the fan-out result, so that the driving capability of the driving unit cannot be effectively adjusted according to the fan-out result.
[0064] The embodiment of the present application provides a fan-out detection method, referring to Figure 3 The embodiment of the present application provides a fan-out detection method, referring to
[0065] S101, obtaining physical parameters of components in a target circuit and parasitic parameters of connecting wires, and physical parameters of components in a standard circuit.
[0066] The components in the target circuit can include transistors, the transistors can include P-type transistors and N-type transistors, the physical parameters can include resistances and capacitances of the components, and the physical parameters of the components can include resistances and capacitances of the P-type transistors and the N-type transistors. The capacitance of the transistor in the present disclosure refers to the gate capacitance of the transistor. The connecting wires refer to connecting lines between the components, and the parasitic parameters of the connecting wires can include parasitic capacitances between the connecting wires.
[0067] The components in the standard circuit can also include P-type transistors and N-type transistors, and the physical parameters of the components can include resistances and capacitances of the P-type transistors and the N-type transistors. It should be noted that the standard circuit can be Figure 1 The first driving unit 101 shown in Figure 2 The second driving unit 201 shown in Since the connecting wires in the standard circuit are less, the influence of the parasitic capacitances of the connecting wires is not considered. The components in the standard circuit have a predetermined size, that is, have predetermined resistances and capacitances, so that the standard fan-out of the standard circuit can be determined according to the resistances and capacitances of the components in the standard circuit, that is, the driving capability of the standard circuit is determined, and the driving capability of the standard circuit determines the driving speed of the standard circuit.
[0068] In some embodiments, referring to Figure 4As shown, the target circuit can include a first P-type transistor M1, a second P-type transistor M2, a third P-type transistor M3, a first N-type transistor M4, a second N-type transistor M5, and a third N-type transistor M6. The gate of the first P-type transistor M1 and the first N-type transistor M4 receives a first control signal, the gate of the second P-type transistor M2 and the second N-type transistor M5 receives a second control signal, the gate of the third P-type transistor M3 and the third N-type transistor M6 receives a third control signal, the source of the first P-type transistor M1, the source of the second P-type transistor M2, and the source of the third P-type transistor M3 are connected to each other and connected to a first power terminal, the drain of the first P-type transistor M1, the drain of the second P-type transistor M2, and the drain of the third P-type transistor M3 are connected to each other, the drain of the first N-type transistor M4 is connected to the drain of the first P-type transistor M1, the drain of the second P-type transistor M2, and the drain of the third P-type transistor M3, the source of the first N-type transistor M4 is connected to the drain of the second N-type transistor M5, the source of the second N-type transistor M5 is connected to the drain of the third N-type transistor M6, and the source of the third N-type transistor M6 is connected to a second power terminal. The first power terminal can provide a power voltage, and the second power terminal can provide a ground voltage.
[0069] Therefore, obtaining the physical parameters of the components in the target circuit can include the resistance and capacitance of the first P-type transistor M1, the resistance and capacitance of the second P-type transistor M2, the resistance and capacitance of the third P-type transistor M3, the resistance and capacitance of the first N-type transistor M4, the resistance and capacitance of the second N-type transistor M5, and the resistance and capacitance of the third N-type transistor M6.
[0070] For example, after the layout of the target circuit is completed, the physical parameters of the components in the target circuit and the parasitic parameters of the connecting wires can be extracted to obtain the resistance and capacitance of each transistor in the target circuit and the parasitic capacitance between the connecting wires of the transistors.
[0071] Reference Figure 1 As shown, the standard circuit includes a first driving unit 101 for driving a first load unit 102, the first driving unit 101 includes a first driving P-type transistor MP1 and a first driving N-type transistor MN1, and the first load unit 102 includes a first load P-type transistor MP2 and a first load N-type transistor MN2. When obtaining the physical parameters of the components in the standard circuit, the resistance Rp and capacitance Cp of the first driving P-type transistor MP1 and the resistance Rn and capacitance Cn of the first driving N-type transistor MN1 can be included.
[0072] Reference Figure 2As shown, the standard circuit includes a second driving unit 201 for driving the second load unit 202, and the second driving unit 201 includes a second driving P-type transistor MP3, a second driving N-type transistor MN3, a second load P-type transistor MP4, a second load N-type transistor MN4, a third load P-type transistor MP5, and a third load N-type transistor MN5. The physical parameters of the components in the standard circuit can include the resistance Rp and the capacitance Cp of the second driving P-type transistor MP3, and the resistance Rn and the capacitance Cn of the second driving N-type transistor MN3.
[0073] S102, according to the physical parameters of the components in the target circuit and the parasitic parameters of the connecting wires, and the physical parameters of the components in the standard circuit, calculate the actual fan-out of the target circuit relative to the standard circuit.
[0074] After obtaining the resistance and capacitance of the transistors in the target circuit, the parasitic parameters of the connecting wires, and the resistance and capacitance of the transistors in the standard circuit, the actual fan-out of the target circuit relative to the standard circuit can be calculated according to the resistance and capacitance of the transistors in the target circuit, the parasitic parameters of the connecting wires, and the resistance and capacitance of the transistors in the standard circuit.
[0075] In some embodiments, the first actual fan-out of the target circuit relative to the standard circuit can be calculated according to the resistance Rp1 and the capacitance Cp1 of the P-type transistor in the target circuit, the capacitance Cn1 of the N-type transistor, and the resistance Rp and the capacitance Cp of the P-type transistor in the standard circuit, the capacitance Cn of the N-type transistor, which can be understood as the fan-out of the P-type transistor in the target circuit relative to the P-type transistor in the standard circuit, so as to obtain the driving capability of the P-type transistor in the target circuit.
[0076] It should be noted that the size of the P-type transistor in the target circuit can be different from the size of the P-type transistor in the standard circuit, or can be the same. The sizes of the P-type transistors in the target circuit can be the same or different.
[0077] For example, the first ratio of the resistance Rp1 of the P-type transistor in the target circuit to the resistance Rp of the P-type transistor in the standard circuit can be calculated. The first capacitance is obtained by adding the capacitance C1 of the transistor in the target circuit and the parasitic capacitance C2, i.e., the first capacitance is obtained by adding the capacitance Cp1 of the P-type transistor in the target circuit, the capacitance Cn1 of the N-type transistor in the target circuit, and the parasitic capacitance C2. The second capacitance is obtained by adding the capacitance Cp of the P-type transistor in the standard circuit and the capacitance Cn of the N-type transistor in the standard circuit. The second ratio of the first capacitance to the second capacitance is calculated, and the product of the first ratio and the second ratio is taken as the first actual fan-out of the target circuit, so as to accurately obtain the fan-out of the P-type transistor in the target circuit.
[0078] The first actual fan-out (PMOS fan-out) = Rp1 / Rp x (C1+C2) / (Cp+Cn).
[0079] For example, when the P-type transistors in the target circuit are in parallel, the P-type transistor with the largest resistance can be selected as the first target P-type transistor from the P-type transistors in the target circuit, the resistance of the first target P-type transistor is taken as the resistance of the P-type transistor in the target circuit, the first ratio of the resistance of the first target P-type transistor to the resistance of the P-type transistor in the standard circuit is calculated, and the first ratio of the resistance of the P-type transistor in the target circuit to the resistance of the P-type transistor in the standard circuit is obtained. When the P-type transistors in the target circuit are in series, the resistances of the P-type transistors in the target circuit are added, and the added resistance is taken as the resistance of the P-type transistor in the target circuit. When there are P-type transistors in series and P-type transistors in parallel in the target circuit, the P-type transistor with the largest resistance is selected as the first target P-type transistor from the P-type transistors in parallel, and the resistance of each P-type transistor in series and the added resistance of the first target P-type transistor are taken as the resistance of the P-type transistor in the target circuit.
[0080] In other embodiments, the second actual fan-out of the target circuit relative to the standard circuit can be calculated according to the resistance Rn1 and the capacitance Cn1 of the N-type transistor, the capacitance Cp1 of the P-type transistor in the target circuit, and the resistance Rn and the capacitance Cn of the N-type transistor, and the capacitance Cp of the P-type transistor in the standard circuit, the second actual fan-out can be understood as the fan-out of the N-type transistor in the target circuit relative to the N-type transistor in the standard circuit, and thus the driving capability of the N-type transistor in the target circuit is obtained.
[0081] Similarly, the size of the N-type transistor in the target circuit can be different from or the same as the size of the N-type transistor in the standard circuit, and the sizes of the N-type transistors in the target circuit can be the same or different.
[0082] For example, the third ratio of the resistance Rn1 of the N-type transistor in the target circuit to the resistance Rn of the N-type transistor in the standard circuit can be calculated. The first capacitance is obtained by adding the capacitance C1 of the transistor in the target circuit and the parasitic capacitance C2, i.e., the first capacitance is obtained by adding the capacitance Cp1 of the P-type transistor in the target circuit, the capacitance Cn1 of the N-type transistor in the target circuit, and the parasitic capacitance C2. The second capacitance is obtained by adding the capacitance Cp of the P-type transistor and the capacitance Cn of the N-type transistor in the standard circuit. The second ratio of the first capacitance to the second capacitance is calculated, and the product of the third ratio and the second ratio is taken as the second actual fan-out of the target circuit, so that the fan-out of the N-type transistor in the target circuit is accurately obtained.
[0083] The second actual fan-out (NMOS fan-out) = Rn1 / Rn x (C1+C2) / (Cp+Cn).
[0084] For example, when the N-type transistors in the target circuit are in series, the resistance of the N-type transistors in the target circuit can be added to obtain a first resistance, and a third ratio of the first resistance to the resistance of the N-type transistor in the standard circuit is calculated to obtain the third ratio of the resistance of the N-type transistor in the target circuit to the resistance of the N-type transistor in the standard circuit; when the N-type transistors in the target circuit are in parallel, the N-type transistor with the largest resistance among the N-type transistors in the target circuit can be selected as a first target N-type transistor, and the resistance of the first target N-type transistor is taken as the resistance of the N-type transistor in the target circuit, and a third ratio of the resistance of the first target N-type transistor to the resistance of the N-type transistor in the standard circuit is calculated to obtain the third ratio of the resistance of the N-type transistor in the target circuit to the resistance of the N-type transistor in the standard circuit; when the N-type transistors in the target circuit are in series and in parallel, the N-type transistor with the largest resistance among the N-type transistors in parallel can be selected as a first target N-type transistor, and the resistance of each N-type transistor in series and the resistance of the first target N-type transistor after addition are taken as the resistance of the N-type transistor in the target circuit to obtain the third ratio of the resistance of the N-type transistor in the target circuit to the resistance of the N-type transistor in the standard circuit.
[0085] When the P-type transistors in the target circuit are in parallel and the N-type transistors are in series, the P-type transistor with the largest capacitance among the P-type transistors in the target circuit can be selected as a second target P-type transistor, and the first capacitance is obtained by adding the capacitance of the second target P-type transistor to the capacitance of each N-type transistor in the target circuit and the parasitic capacitance, thereby obtaining the first capacitance of the target circuit; when the N-type transistors in the target circuit are in parallel and the P-type transistors are in series, the N-type transistor with the largest capacitance among the N-type transistors in the target circuit can be selected as a second target N-type transistor, and the first capacitance is obtained by adding the capacitance of the second target N-type transistor to the capacitance of each P-type transistor in the target circuit and the parasitic capacitance, thereby obtaining the first capacitance of the target circuit; when the P-type transistors in the target circuit are in parallel and in series, the P-type transistor with the largest capacitance among the P-type transistors in parallel in the target circuit can be selected as a second target P-type transistor, and the N-type transistor with the largest capacitance among the N-type transistors in parallel in the target circuit can be selected as a second target N-type transistor, and the first capacitance is obtained by adding the capacitance of the second target P-type transistor, the capacitance of each P-type transistor in series in the target circuit, the capacitance of the second target N-type transistor and the capacitance of each N-type transistor in series in the target circuit and the parasitic capacitance, thereby obtaining the first capacitance of the target circuit.
[0086] Reference Figure 4As shown, the target circuit includes: a first P-type transistor M1, a second P-type transistor M2, a third P-type transistor M3, a first N-type transistor M4, a second N-type transistor M5 and a third N-type transistor M6. The gate of the first P-type transistor M1 and the first N-type transistor M4 receives a first control signal, the gate of the second P-type transistor M2 and the second N-type transistor M5 receives a second control signal, and the gate of the third P-type transistor M3 and the third N-type transistor M6 receives a third control signal.
[0087] The P-type transistor with the largest resistance can be selected from the first P-type transistor M1, the second P-type transistor M2 and the third P-type transistor M3 as the first target P-type transistor, and the P-type transistor with the largest capacitance can be selected as the second target P-type transistor. The resistance of the first target P-type transistor is taken as the resistance Rp1 of the P-type transistor in the target circuit, and the capacitance of the second target P-type transistor is taken as the capacitance Cp1 of the P-type transistor in the target circuit, then the resistance Rp1 of the P-type transistor in the target circuit = Max(RM1, RM2, RM3), and the capacitance Cp1 of the P-type transistor in the target circuit = Max(CM1, CM2, CM3). The first ratio of the resistance of the first target P-type transistor to the resistance Rp of the P-type transistor in the standard circuit is calculated, the first capacitance is obtained by adding the capacitance CM4 of the first N-type transistor, the capacitance CM5 of the second N-type transistor, the capacitance CM6 of the third N-type transistor and the parasitic capacitance C2 to the capacitance of the second target P-type transistor, the second capacitance is obtained by adding the capacitance Cp of the P-type transistor in the standard circuit to the capacitance Cn of the N-type transistor, and the second ratio of the first capacitance to the second capacitance is calculated. The product of the first ratio and the second ratio is taken as the first actual fan-out of the target circuit.
[0088] The first actual fan-out, i.e. the PMOS fan-out = Max(RM1, RM2, RM3) / Rp × (Max(CM1, CM2, CM3) + CM4 + CM5 + CM6) / (Cp + Cn).
[0089] Further, with reference to Figure 4The P-type transistor with the largest capacitance can be selected from the first P-type transistor M1, the second P-type transistor M2 and the third P-type transistor M3 as a second target P-type transistor, and the capacitance of the second target P-type transistor is taken as the capacitance Cp1 of the P-type transistor in the target circuit. The first resistance is obtained by adding the resistance RM4 of the first N-type transistor, the resistance RM5 of the second N-type transistor and the resistance RM6 of the third N-type transistor, and the first resistance is the resistance Rn1 of the N-type transistor in the target circuit. The third ratio of the first resistance to the resistance Rn of the N-type transistor in the standard circuit is calculated. The first capacitance is obtained by adding the capacitance CM4 of the first N-type transistor, the capacitance CM5 of the second N-type transistor, the capacitance CM6 of the third N-type transistor and the parasitic capacitance C2 to the capacitance of the second target P-type transistor. The second capacitance is obtained by adding the capacitance Cp of the P-type transistor in the standard circuit to the capacitance Cn of the N-type transistor. The second ratio of the first capacitance to the second capacitance is calculated. The product of the third ratio and the second ratio is taken as the second actual fan-out of the target circuit.
[0090] The second actual fan-out, i.e., the NMOS fan-out = (RM1+RM2+RM3) / Rp x (Max(CM1, CM2, CM3)+CM4+CM5+CM6) / (Cp+Cn).
[0091] S103, if the ratio of the actual fan-out to the standard fan-out does not reach the target ratio, the resistance and / or capacitance of the components in the target circuit are adjusted until the ratio of the actual fan-out to the standard fan-out reaches the target ratio, so that the actual fan-out of the target circuit reaches the target fan-out.
[0092] The components in the standard circuit have known sizes, known resistances and capacitances. Since the resistance and capacitance can determine the driving capability, i.e., the fan-out, and the driving capability determines the driving speed, the standard circuit has a standard fan-out and a known driving speed. Therefore, comparing the ratio of the actual fan-out of the target circuit to the standard fan-out of the standard circuit with the target ratio can also be understood as comparing the driving capability of the target circuit with the driving capability of the standard circuit, and comparing the driving speed of the target circuit with the driving speed of the standard circuit.
[0093] If the ratio of the actual fan-out of the target circuit to the standard fan-out of the standard circuit does not reach the target ratio, the target circuit does not reach the target fan-out. At this time, the resistance and / or capacitance of the components in the target circuit can be adjusted, and the actual fan-out of the adjusted target circuit is continuously calculated until the ratio of the actual fan-out of the target circuit to the standard fan-out reaches the target ratio, so that the actual fan-out of the target circuit reaches the target fan-out, thereby effectively adjusting the driving capability of the target circuit.
[0094] When the first actual fan-out of the target circuit is calculated according to the resistance and capacitance of the P-type transistor, the capacitance of the N-type transistor and the parasitic capacitance of the connecting wire in the target circuit, the resistance and capacitance of the P-type transistor, the capacitance of the N-type transistor in the standard circuit, the ratio of the first actual fan-out to the first standard fan-out of the standard circuit can be compared with the first target ratio, if the ratio of the first actual fan-out to the first standard fan-out reaches the first target ratio, the first actual fan-out of the target circuit reaches the first target fan-out, if the ratio of the first actual fan-out to the first standard fan-out does not reach the first target ratio, the first actual fan-out of the target circuit does not reach the first target fan-out, the resistance and / or capacitance of the transistor in the target circuit can be adjusted, for example, the resistance, capacitance of the P-type transistor and / or the capacitance of the N-type transistor in the target circuit is adjusted, so that the ratio of the first actual fan-out of the target circuit to the first standard fan-out of the standard circuit reaches the first target ratio, so that the first actual fan-out of the target circuit reaches the first target fan-out. It can be understood that the first actual fan-out of the target circuit is the fan-out of the P-type transistor in the target circuit, and the first standard fan-out of the standard circuit is the standard fan-out of the P-type transistor in the standard circuit.
[0095] When the second actual fan-out of the target circuit is calculated according to the resistance and capacitance of the N-type transistor, the capacitance of the P-type transistor and the parasitic capacitance of the connecting wire in the target circuit, the resistance and capacitance of the N-type transistor, the capacitance of the P-type transistor in the standard circuit, the ratio of the second actual fan-out to the second standard fan-out of the standard circuit can be compared with the second target ratio, if the ratio of the second actual fan-out to the second standard fan-out reaches the second target ratio, the second actual fan-out of the target circuit reaches the second target fan-out, if the ratio of the second actual fan-out to the second standard fan-out does not reach the second target ratio, the second actual fan-out of the target circuit does not reach the second target fan-out, the resistance and / or capacitance of the transistor in the target circuit can be adjusted, for example, the resistance, capacitance of the N-type transistor and / or the capacitance of the P-type transistor in the target circuit is adjusted, so that the ratio of the second actual fan-out of the target circuit to the second standard fan-out of the standard circuit reaches the second target ratio, so that the second actual fan-out of the target circuit reaches the second target fan-out. It can be understood that the second actual fan-out of the target circuit is the fan-out of the N-type transistor in the target circuit, and the second standard fan-out of the standard circuit is the standard fan-out of the N-type transistor in the standard circuit.
[0096] Therefore, it can be judged whether the actual fan-out reaches the target fan-out according to the ratio of the actual fan-out to the standard fan-out, and when the target fan-out is not reached, the capacitance and / or resistance of the transistor in the target circuit is adjusted to adjust the actual fan-out of the target circuit and the driving capability of the target circuit, so as to optimize the target circuit.
[0097] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for part or all of the technical features. These modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A fan-out detection method, characterized by, The method comprises the following steps: acquiring physical parameters of components in a target circuit and parasitic parameters of connecting wires, and physical parameters of components in a standard circuit, the physical parameters comprising resistance and capacitance of the components, and the standard circuit having a corresponding standard fan-out; calculating an actual fan-out of the target circuit relative to the standard circuit according to the physical parameters of the components in the target circuit and the parasitic parameters of the connecting wires, and the physical parameters of the components in the standard circuit; if a ratio of the actual fan-out to the standard fan-out does not reach a target ratio, adjusting resistance and / or capacitance of the components in the target circuit until the ratio of the actual fan-out to the standard fan-out reaches the target ratio, so that the actual fan-out of the target circuit reaches a target fan-out; the components comprise P-type transistors and N-type transistors, the standard fan-out comprises a first standard fan-out, the first standard fan-out corresponds to a fan-out of the P-type transistors in the standard circuit, and the parasitic parameters comprise parasitic capacitance; the step of calculating the actual fan-out of the target circuit relative to the standard circuit according to the physical parameters of the components in the target circuit and the parasitic parameters of the connecting wires, and the physical parameters of the components in the standard circuit specifically comprises: calculating a first actual fan-out of the target circuit according to resistance and capacitance of the P-type transistors in the target circuit, capacitance of the N-type transistors, and parasitic capacitance of the connecting wires, and resistance and capacitance of the P-type transistors in the standard circuit, and capacitance of the N-type transistors; correspondingly, the step of adjusting the resistance and / or capacitance of the transistors in the target circuit if the ratio of the actual fan-out to the standard fan-out does not reach the target ratio, until the ratio of the actual fan-out to the standard fan-out reaches the target ratio specifically comprises: if a ratio of the first actual fan-out to the first standard fan-out does not reach a first target ratio, adjusting the resistance and / or capacitance of the transistors in the target circuit until the ratio of the first actual fan-out to the first standard fan-out reaches the first target ratio.
2. The method of claim 1, wherein, the step of calculating the first actual fan-out of the target circuit according to resistance and capacitance of the P-type transistors in the target circuit, capacitance of the N-type transistors, and parasitic capacitance of the connecting wires, and resistance and capacitance of the P-type transistors in the standard circuit, and capacitance of the N-type transistors specifically comprises: calculating a first ratio of resistance of the P-type transistors in the target circuit to resistance of the P-type transistors in the standard circuit; adding capacitance of the transistors in the target circuit and parasitic capacitance to obtain a first capacitance, adding capacitance of the P-type transistors and capacitance of the N-type transistors in the standard circuit to obtain a second capacitance, and calculating a second ratio of the first capacitance to the second capacitance; multiplying the first ratio and the second ratio to obtain the first actual fan-out of the target circuit.
3. The method of claim 2, wherein, the step of calculating the first ratio of resistance of the P-type transistors in the target circuit to resistance of the P-type transistors in the standard circuit specifically comprises: when the P-type transistors in the target circuit are in parallel, selecting a P-type transistor with the largest resistance from the P-type transistors in the target circuit as a first target P-type transistor; Calculate a first ratio of resistance of the first target P-type transistor to resistance of the P-type transistor in the standard circuit.
4. The method of claim 2, wherein, The first capacitance is obtained by adding the capacitance of the transistors in the target circuit and the parasitic capacitance. When the P-type transistors in the target circuit are in parallel and the N-type transistors are in series, select a P-type transistor with the largest capacitance from the P-type transistors in the target circuit as a second target P-type transistor. Add the capacitance of the second target P-type transistor and the N-type transistors in the target circuit and the parasitic capacitance to obtain the first capacitance.
5. The method of claim 4, wherein, The target circuit includes a first P-type transistor, a second P-type transistor, a third P-type transistor, a first N-type transistor, a second N-type transistor, and a third N-type transistor. The gate of the first P-type transistor and the first N-type transistor receives a first control signal, the gate of the second P-type transistor and the second N-type transistor receives a second control signal, the gate of the third P-type transistor and the third N-type transistor receives a third control signal, the source of the first P-type transistor, the source of the second P-type transistor, and the source of the third P-type transistor are connected to a power supply voltage, the drain of the first P-type transistor, the drain of the second P-type transistor, and the drain of the third P-type transistor are connected to each other, the drain of the first N-type transistor is connected to the drain of the third P-type transistor, the source of the first N-type transistor is connected to the drain of the second N-type transistor, the source of the second N-type transistor is connected to the drain of the third N-type transistor, and the source of the third N-type transistor is grounded.
6. The method of claim 5, wherein, The actual fan-out of the target circuit relative to the standard circuit is calculated according to the physical parameters of the components in the target circuit and the parasitic parameters of the connecting wires, and the physical parameters of the components in the standard circuit, specifically including: Obtain the resistance and capacitance of the first P-type transistor, the second P-type transistor, and the third P-type transistor, and the resistance and capacitance of the first N-type transistor, the second N-type transistor, and the third N-type transistor. Calculate the actual fan-out of the target circuit relative to the standard circuit according to the resistance and capacitance of the first P-type transistor, the second P-type transistor, and the third P-type transistor, the resistance and capacitance of the first N-type transistor, the second N-type transistor, and the third N-type transistor, the parasitic parameters of the connecting wires, and the physical parameters of the components in the standard circuit.
7. The method of claim 6, wherein, Calculate the actual fan-out of the target circuit relative to the standard circuit according to the resistance and capacitance of the first P-type transistor, the second P-type transistor, and the third P-type transistor, the resistance and capacitance of the first N-type transistor, the second N-type transistor, and the third N-type transistor, the parasitic parameters of the connecting wires, and the physical parameters of the components in the standard circuit, specifically including: The P-type transistor with the largest resistance among the first P-type transistor, the second P-type transistor and the third P-type transistor is selected as a first target P-type transistor, and the P-type transistor with the largest capacitance is selected as a second target P-type transistor; a first ratio of the resistance of the first target P-type transistor to the resistance of the P-type transistor in the standard circuit is calculated, and a first capacitance is obtained by adding the capacitance of the second target P-type transistor to the capacitance of the first N-type transistor, the capacitance of the second N-type transistor, the capacitance of the third N-type transistor and the parasitic capacitance of the connecting wire, and a second ratio of the first capacitance to the capacitance of the transistor in the standard circuit is calculated; and a product of the first ratio and the second ratio is taken as a first actual fan-out of the target circuit relative to the standard circuit; if the ratio of the actual fan-out to the standard fan-out does not reach a target ratio, the resistance and / or capacitance of the components in the target circuit are adjusted until the ratio of the actual fan-out to the standard fan-out reaches the target ratio, and the adjustment specifically includes: if the ratio of the first actual fan-out to a first standard fan-out of the standard circuit does not reach a first target ratio, the resistance and / or capacitance of the transistors in the target circuit are adjusted until the ratio of the first actual fan-out to the first standard fan-out reaches the first target ratio.
8. The method of claim 6, wherein, According to the resistance and capacitance of the first P-type transistor, the second P-type transistor and the third P-type transistor, the resistance and capacitance of the first N-type transistor, the second N-type transistor and the third N-type transistor, the parasitic parameters of the connecting wire, and the physical parameters of the components in the standard circuit, the actual fan-out of the target circuit relative to the standard circuit is calculated, and the calculation specifically includes: the P-type transistor with the largest capacitance among the first P-type transistor, the second P-type transistor and the third P-type transistor is selected as a second target P-type transistor; a first resistance is obtained by adding the resistance of the first N-type transistor, the resistance of the second N-type transistor and the resistance of the third N-type transistor, a third ratio of the first resistance to the resistance of the N-type transistor in the standard circuit is calculated, a first capacitance is obtained by adding the capacitance of the second target P-type transistor to the capacitance of the first N-type transistor, the capacitance of the second N-type transistor, the capacitance of the third N-type transistor and the parasitic capacitance of the connecting wire, and a second ratio of the first capacitance to the capacitance of the transistor in the standard circuit is calculated; and a product of the third ratio and the second ratio is taken as a second actual fan-out of the target circuit relative to the standard circuit; if the ratio of the actual fan-out to the standard fan-out does not reach a target ratio, the resistance and / or capacitance of the components in the target circuit are adjusted until the ratio of the actual fan-out to the standard fan-out reaches the target ratio, and the adjustment specifically includes: If a ratio of the second actual fan-out to a second standard fan-out of the standard circuit does not reach a second target ratio, resistance and / or capacitance of a transistor in the target circuit is adjusted until the ratio of the second actual fan-out to the second standard fan-out reaches the second target ratio.
9. The method of claim 5, wherein, The standard circuit comprises a driving P-type transistor and a driving N-type transistor, gates of the driving P-type transistor and the driving N-type transistor are connected to each other and receive a driving signal, a drain of the driving P-type transistor is connected to a drain of the driving N-type transistor, a source of the driving P-type transistor is connected to a power voltage, a source of the driving N-type transistor is grounded, resistance and capacitance of the driving P-type transistor are resistance and capacitance of a P-type transistor in the standard circuit, and resistance and capacitance of the driving N-type transistor are resistance and capacitance of an N-type transistor in the standard circuit.
10. A fan-out detection method characterized by, The method comprises: acquiring physical parameters of components in a target circuit and parasitic parameters of connecting wires, and physical parameters of components in a standard circuit, the physical parameters comprising resistance and capacitance of the components, and the standard circuit having a corresponding standard fan-out; calculating an actual fan-out of the target circuit relative to the standard circuit according to the physical parameters of the components in the target circuit and the parasitic parameters of the connecting wires, and the physical parameters of the components in the standard circuit; if a ratio of the actual fan-out to the standard fan-out does not reach a target ratio, adjusting resistance and / or capacitance of the components in the target circuit until the ratio of the actual fan-out to the standard fan-out reaches the target ratio, so that an actual fan-out of the target circuit reaches a target fan-out; the components comprise a P-type transistor and an N-type transistor, the standard fan-out comprises a second standard fan-out, the second standard fan-out corresponds to a fan-out of an N-type transistor in the standard circuit, and the parasitic parameters comprise parasitic capacitance; the calculating an actual fan-out of the target circuit relative to the standard circuit according to the physical parameters of the components in the target circuit and the parasitic parameters of the connecting wires, and the physical parameters of the components in the standard circuit specifically comprises: calculating a second actual fan-out of the target circuit according to resistance and capacitance of an N-type transistor in the target circuit, capacitance of a P-type transistor in the target circuit, resistance and capacitance of an N-type transistor in the standard circuit, and capacitance of a P-type transistor in the standard circuit; correspondingly, the if a ratio of the actual fan-out to the standard fan-out does not reach a target ratio, adjusting resistance and / or capacitance of a transistor in the target circuit until the ratio of the actual fan-out to the standard fan-out reaches the target ratio specifically comprises: if a ratio of the second actual fan-out to a second standard fan-out of the standard circuit does not reach a second target ratio, resistance and / or capacitance of a transistor in the target circuit is adjusted until the ratio of the second actual fan-out to the second standard fan-out reaches the second target ratio.
11. The method of claim 10, wherein, The third ratio of the resistance of the N-type transistor in the target circuit to the resistance of the N-type transistor in the standard circuit is calculated, specifically including: The resistance of the N-type transistor in the target circuit is added up to obtain a first resistance when the N-type transistors in the target circuit are in series. The third ratio of the first resistance to the resistance of the N-type transistor in the standard circuit is calculated. The second actual fan-out of the target circuit is calculated according to the resistance and capacitance of the N-type transistor in the target circuit, the capacitance of the P-type transistor, and the parasitic capacitance of the connecting wire, the resistance and capacitance of the N-type transistor, the capacitance of the P-type transistor in the standard circuit, and specifically including:
12. The method of claim 11, wherein, The third ratio of the resistance of the N-type transistor in the target circuit to the resistance of the N-type transistor in the standard circuit is calculated. The capacitance of the transistor in the target circuit is added to the parasitic capacitance to obtain a first capacitance, and the capacitance of the P-type transistor in the standard circuit is added to the capacitance of the N-type transistor to obtain a second capacitance, and the second ratio of the first capacitance to the second capacitance is calculated. The product of the third ratio and the second ratio is taken as the second actual fan-out of the target circuit. The third ratio of the resistance of the N-type transistor in the target circuit to the resistance of the N-type transistor in the standard circuit is calculated, specifically including: The resistance of the N-type transistor in the target circuit is added up to obtain a first resistance when the N-type transistors in the target circuit are in series. The third ratio of the first resistance to the resistance of the N-type transistor in the standard circuit is calculated.
Citation Information
Patent Citations
Active pull-down circuit for driving capacitive load
CN102664617A
Drive signal regulating method
CN107978291A