A method for fabricating the inner layer of a high-density circuit board and its application

Abstract

This invention belongs to the field of PCB and HDI manufacturing technology, and discloses a method for manufacturing inner layers of high-density circuit boards and its application. The method includes: symmetrically arranging the shipping units of the circuit board; mirroring the stack-up data of the circuit board; repeatedly producing multiple identical core boards after layout and stacking processing; taking the repeatedly produced core boards and combining them; pressing the combined core boards together; and completing subsequent processes according to normal production procedures after pressing. This invention halves the types of core boards produced, simplifies manufacturing, facilitates pressing and matching, and reduces waste of excess products. This invention can reduce the types of core boards produced and reduce waste of unused excess core boards. This method can significantly improve the efficiency of inner layer core boards while reducing the scrap rate of inner layer core boards. Therefore, it can improve production efficiency.

Description

Technical Field

[0001] This invention belongs to the field of PCB and HDI manufacturing technology, and particularly relates to a method for manufacturing the inner layer of a high-density circuit board and its application. Background Technology

[0002] With the increasing functionality of electronic products, traditional PCBs are evolving towards more layers and HDI (High-Intensity Distributed) boards to achieve these additional functions. This necessitates multiple core layers to fabricate the inner circuitry. During production, when more than four inner layers need to be fabricated, different core layers must be produced sequentially from top to bottom. For example, a 6-layer PCB... Figure 2 L1 and L6 are the outer layers, and the inner layers are L2, L3, L4, and L5. First, L2 / L3 needs to be produced as a separate core board. After L2 / L3 is produced, the data is switched, and L3 / L4 is produced as a separate core board. These two core boards are then paired, and the finished L2 / 3 and L3 / L4 core boards are laminated using prepreg and copper foil to form a 6-layer board. In the inner layer production, exposure films for both L2 / 3 and L3 / L4 core boards need to be made separately, and the etching parameters for each core board need to be captured separately. An automatic optical inspection machine needs to inspect both L2 / 3 and L3 / L4 core boards separately. If one of the L2 / 3 or L3 / L4 core boards is scrapped, the scrapped core board needs to be remanufactured and then laminated to be paired, resulting in low production efficiency.

[0003] Especially when the pass rates of the core boards are different, some core boards with high pass rates have overflow products, while some core boards with low pass rates are insufficient in number. When the pressing cannot be matched one-to-one, the production will not be smooth, thus affecting the production efficiency.

[0004] Based on the above analysis, the problems and shortcomings of the existing technology are as follows:

[0005] (1) Existing technologies present significant challenges in the pressing and pairing of multiple inner core boards;

[0006] (2) Existing technologies have low production efficiency for multiple inner core boards;

[0007] (3) The high scrap rate in the manufacturing of the inner core board in the existing technology results in high cost. Summary of the Invention

[0008] To overcome the problems existing in related technologies, the present invention discloses a method for fabricating the inner layer of a high-density circuit board and its application.

[0009] The technical solution is as follows: A method for fabricating the inner layer of a high-density circuit board, comprising:

[0010] S1, arrange the circuit board shipping units symmetrically;

[0011] S2, mirror the stack-up data of the circuit board;

[0012] S3. After the layout processing in step S1 and the stacking processing in step S2, the same multiple core boards are repeatedly produced.

[0013] S4: Take multiple core boards that have been repeatedly produced in step S3 and combine them;

[0014] S5, after step S4, the multiple core boards that have been combined and matched are pressed together, and after pressing, the subsequent processes are completed according to the normal production process.

[0015] In one embodiment, the symmetrical arrangement of the circuit board shipping units in step S1 specifically includes:

[0016] Layout method 1: The layout is symmetrical along the Y-axis.

[0017] Layout method 2: The layout is symmetrical along the X-axis.

[0018] Layout method 3: The layout is symmetrical on the left and right, top and bottom of the X and Y axes.

[0019] In one embodiment, step S2, specifically mirroring the stack-up data of the circuit board, includes:

[0020] By adopting a layout method that is symmetrical about the Y-axis, the stacked areas of the circuit board are mirrored, so that the circuit data of the original two core boards are merged into one core board.

[0021] In one embodiment, step S2, specifically mirroring the stack-up data of the circuit board, includes:

[0022] By adopting a layout method that is symmetrical on the X-axis, the stacked areas of the circuit board are mirrored, so that the circuit data of the original two core boards are merged into one core board.

[0023] In one embodiment, step S2, specifically mirroring the stack-up data of the circuit board, includes:

[0024] By adopting a layout method that is symmetrical in the left and right and top and bottom of the X and Y axes, the stacking of the circuit board's stacked areas is mirrored, so that the circuit data of the original two core boards are merged into one core board.

[0025] In one embodiment, step S4, combining and pairing multiple core boards repeatedly produced in step S3, includes:

[0026] Take multiple core boards produced repeatedly. When using a layout method that is symmetrical about the left and right along the Y-axis, the first core board is stacked normally. When stacking the second core board directly below the first core board, the second core board is mirrored and flipped 180 degrees to the left and right.

[0027] The layout adopts a symmetrical arrangement along the X-axis. The first core board is stacked normally. When the second core board is stacked directly below the first core board, the second core board is mirrored vertically and flipped 180 degrees.

[0028] In one embodiment, the method for mirroring the second core board during the combination and pairing process includes:

[0029] Step 1: Establish a reference coordinate system r for calculating the core board flip state, a circuit board coordinate system b, and a reference coordinate system for filtering.

[0030] Step 2: Define the core board flip state error, sample real-time flip points, and construct the real-time flip points corresponding to the global core board flip state.

[0031] Step 3: Transfer the real-time flip point of the core board flip state in the kinematic equation of the core board flip state and construct the real-time flip point of the core board flip state error after transfer.

[0032] Step 4: Perform error calculation and set the core board flipping state error estimate to zero;

[0033] In step one, the establishment of a reference coordinate system r for calculating the core board flip state, a circuit board coordinate system, and a reference coordinate system for filtering are described. include:

[0034] Establish a coordinate system, i.e., a reference coordinate system r, in which the core board flipping state calculation is performed. The reference coordinate system r can be an inertial coordinate system, a geodetic coordinate system, or a local geographic coordinate system.

[0035] Establish an estimated reference coordinate system The estimated reference coordinate system The reference coordinate system estimated in the filtering algorithm, the estimated reference coordinate system The error between the reference coordinate system r and the core board flipping state error is the error between the core board and the reference coordinate system r.

[0036] In step two, the core board flipping state error is defined as follows:

[0037]

[0038] in, Represents the true error matrix. express The corresponding estimated value;

[0039] The process of sampling real-time flip points and constructing the real-time flip points corresponding to the global core board flip state includes:

[0040] Using the variance P of the core board flipping state at the previous moment k-1 Real-time flip point sampling is performed as follows:

[0041]

[0042] The real-time flip points corresponding to the constructed global core board flip state include:

[0043] Convert the real-time flip points of the core board flip state error into matrix form:

[0044]

[0045] The conversion formula defined by so3_exp[·] is:

[0046]

[0047] Using the core board flipping state estimate from the previous moment Construct the real-time flip point corresponding to the global core board flip state.

[0048]

[0049] In step three, the process of transferring the real-time flipping point of the core plate in the kinematic equation of the core plate flipping state includes:

[0050]

[0051] Where Ω(·) represents the kinematic equation of the core plate in the flipping state;

[0052] The real-time reversal point of the core board flipping state error after the structure is transferred.

[0053] Based on the defined core board flipping state error, construct the real-time flipping point of the transferred core board flipping state error:

[0054]

[0055] Convert the matrix-form core board flip state error into a vector-form error:

[0056]

[0057] The transformation formula defined by so3_log[·] is:

[0058]

[0059] In step four, the error calculation is performed as follows:

[0060]

[0061]

[0062] Where w(i) represents the weight corresponding to the real-time flip point, Q k-1 This represents the state variance matrix.

[0063] In one embodiment, in steps S1-S5, the number of core boards is an even number.

[0064] Another object of the present invention is to provide a high-density circuit board manufactured according to the method for manufacturing the inner layer of the high-density circuit board.

[0065] Another object of the present invention is to provide an application of the method for fabricating the inner layer of the high-density circuit board in the design of novel copper conductor circuit boards during the manufacturing process.

[0066] Another object of the present invention is to provide an electronic device HDI board, which is manufactured using the method of manufacturing the inner layer of the high-density circuit board.

[0067] Combining all the above technical solutions, the advantages and positive effects of this invention are as follows:

[0068] First, regarding the technical problems existing in the prior art and the difficulty in solving these problems, this invention, closely combining the technical solution to be protected by this invention with the results and data from the research and development process, provides a detailed and in-depth analysis of how the technical solution of this invention solves the technical problems, and the creative technical effects brought about after solving the problems. Specifically, the invention can reduce the types of core boards produced and reduce waste from unused core board products. This method can significantly improve the efficiency of inner core boards while reducing the scrap rate of inner core boards.

[0069] Secondly, considering the technical solution as a whole or from the perspective of the product, the technical effects and advantages of the technical solution to be protected by this invention are specifically described as follows: This invention improves the efficiency of the inner layers of the circuit board and improves the yield through a special layout design and a special mirrored layer design.

[0070] Third, compared to existing technologies, the advantages of this invention further include: This invention can halve the types of core boards that can be produced. For example, when there are two core boards, one core board can be repeatedly produced; when there are four core boards, two core boards can be repeatedly produced separately. This halves the time for board switching tools, the time for production parameters, and the time for automatic optical inspection and data changing. Therefore, production efficiency can be improved. Halving the types of core boards simplifies manufacturing, facilitates lamination and matching, and reduces waste of excess products. Attached Figure Description

[0071] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure;

[0072] Figure 1 This is a flowchart of a method for fabricating the inner layer of a high-density circuit board according to an embodiment of the present invention;

[0073] Figure 2 This is a schematic diagram of a conventional 6-layer board stack provided in an embodiment of the present invention;

[0074] Figure 3 This is a schematic diagram of a left-right symmetrical layout provided in an embodiment of the present invention, wherein the layout of engineering data is left-right symmetrical along the Y-axis;

[0075] Figure 4 This is a schematic diagram of a vertically symmetrical layout provided in an embodiment of the present invention, wherein the layout of engineering data is vertically symmetrical along the X-axis;

[0076] Figure 5 This is a schematic diagram of a symmetrical layout provided in an embodiment of the present invention. Figure 1 Among them, the layout of engineering data is symmetrical vertically along the X-axis and symmetrical horizontally along the Y-axis.

[0077] Figure 6 This is a schematic diagram of the stacked mirror imaging provided in an embodiment of the present invention; Detailed Implementation

[0078] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of the present invention. However, the present invention can be practiced in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0079] I. Explanation of the Implementation Example:

[0080] The method for manufacturing the inner layers of a high-density circuit board provided in this invention employs two innovative approaches: a novel layout method for engineering data and a novel lamination method. This invention primarily addresses the problems of poor inner layer efficiency and difficulty in matching multiple core boards.

[0081] Specifically, a method for fabricating the inner layer of a high-density circuit board includes:

[0082] Step 1: Arrange the circuit board shipping units symmetrically;

[0083] Step 2: Mirror the stack-up data of the circuit board.

[0084] Step 3: After the layout processing in Step 1 and the stacking processing in Step 2, repeat the production of multiple identical core boards.

[0085] Step four: Take multiple core boards produced in step three and combine them.

[0086] Step 5: After step 4, the multiple core boards that have been combined and matched are pressed together. After pressing, the subsequent processes are completed according to the normal production process.

[0087] Example 1

[0088] like Figure 1 As shown, the method for fabricating the inner layer of a high-density circuit board provided in this embodiment of the invention specifically includes the following steps: (taking a 6-layer circuit board with 2 core boards as an example)

[0089] S101, Arrange the circuit board shipping units symmetrically: Layout method 1, such as... Figure 3 The layout is symmetrical along the Y-axis; Layout method 2, such as... Figure 4 The layout is symmetrical along the X-axis; layout method 3, such as... Figure 5 The layout is symmetrical along the X and Y axes, both horizontally and vertically.

[0090] S102, mirror the circuit board's stack-up data: when using Figure 3 In this layout, the stack-up order of area A1 on the circuit board from top to bottom is L1, L2, L3, L4, L5, L6. Area A2 is a mirror image of area A1, and after mirroring, the stack-up order of area A2 from top to bottom is L6, L5, L4, L3, L2, L1. Figure 6 Through this layered mirroring process, the circuit data of the original two core boards are merged into one core board.

[0091] Similarly, when adopting Figure 4In this layout method, the stack-up order of region B1 on the circuit board from top to bottom is L1, L2, L3, L4, L5, L6. Region B2 is a mirror image of region B1, with the stack-up order of region B2 from top to bottom being L6, L5, L4, L3, L2, L1. Through this stack-up mirroring process, the circuit data from the original two core boards are merged into one core board. Similarly, when using... Figure 5 The layout can be done by mirroring either of the two methods mentioned above, and the original circuit data of two core boards will be merged into one core board.

[0092] S103, originally the inner layer required the production of two core boards L2 / L3 and L4 / 5 respectively. After the above stacking and layout processing, it can now be changed to repeatedly produce the same core board L2 / 3-L4 / 5.

[0093] S104, during the pressing and assembly pairing operation, take this core board that has been produced repeatedly, when using... Figure 3 The layout involves placing the first core board normally on top of the first. When placing the second core board directly below the first, the second core board is mirrored horizontally, i.e., flipped 180 degrees left and right. When using... Figure 4 In terms of layout, the first core board is placed normally on top of the first core board. When the second core board is placed directly below the first core board, the second core board is mirrored vertically, that is, flipped 180 degrees vertically.

[0094] S105, after pressing the two paired core boards together, the order from top to bottom on one side of the symmetrical arrangement after pressing is L1, L2, L3, L4, L5, L6; the other side is L6, L5, L4, L3, L2, L1. 1. After pressing, complete the subsequent processes according to the normal production process.

[0095] Whenever an even number of core boards are used for lamination of the inner layer, the stacking mirror process can be performed in accordance with the method of two core boards. This can reduce the number of core board layers produced by half, thereby improving the production efficiency of the inner layer and reducing waste.

[0096] For example, in the process of combination and pairing, the method for mirroring the second core board includes:

[0097] Step 1: Establish a reference coordinate system r for calculating the core board flip state, a circuit board coordinate system b, and a reference coordinate system for filtering.

[0098] Step 2: Define the core board flip state error, sample real-time flip points, and construct the real-time flip points corresponding to the global core board flip state.

[0099] Step 3: Transfer the real-time flip point of the core board flip state in the kinematic equation of the core board flip state and construct the real-time flip point of the core board flip state error after transfer.

[0100] Step 4: Perform error calculation and set the core board flipping state error estimate to zero;

[0101] In step one, the establishment of a reference coordinate system r for calculating the core board flip state, a circuit board coordinate system, and a reference coordinate system for filtering are described. include:

[0102] Establish a coordinate system, i.e., a reference coordinate system r, in which the core board flipping state calculation is performed. The reference coordinate system r can be an inertial coordinate system, a geodetic coordinate system, or a local geographic coordinate system.

[0103] Establish an estimated reference coordinate system The estimated reference coordinate system The reference coordinate system estimated in the filtering algorithm, the estimated reference coordinate system The error between the reference coordinate system r and the core board flipping state error is the error between the core board and the reference coordinate system r.

[0104] In step two, the core board flipping state error is defined as follows:

[0105]

[0106] in, Represents the true error matrix. express The corresponding estimated value;

[0107] The process of sampling real-time flip points and constructing the real-time flip points corresponding to the global core board flip state includes:

[0108] Using the variance P of the core board flipping state at the previous moment k-1 Real-time flip point sampling is performed as follows:

[0109]

[0110] The real-time flip points corresponding to the constructed global core board flip state include:

[0111] Convert the real-time flip points of the core board flip state error into matrix form:

[0112]

[0113] The conversion formula defined by so3_exp[·] is:

[0114]

[0115] Using the core board flipping state estimate from the previous moment Construct the real-time flip point corresponding to the global core board flip state.

[0116]

[0117] In step three, the process of transferring the real-time flipping point of the core plate in the kinematic equation of the core plate flipping state includes:

[0118]

[0119] Where Ω(·) represents the kinematic equation of the core plate in the flipping state;

[0120] The real-time reversal point of the core board flipping state error after the structure is transferred.

[0121] Based on the defined core board flipping state error, construct the real-time flipping point of the transferred core board flipping state error:

[0122]

[0123] Convert the matrix-form core board flip state error into a vector-form error:

[0124]

[0125] The transformation formula defined by so3_log[·] is:

[0126]

[0127] In step four, the error calculation is performed as follows:

[0128]

[0129]

[0130] Where w(i) represents the weight corresponding to the real-time flip point, Q k-1 This represents the state variance matrix.

[0131] Example 2

[0132] Taking the design of novel copper conductors at the process edge as an example, the method for fabricating the inner layer of a high-density circuit board provided in this embodiment of the invention specifically includes the following steps:

[0133] Step 1: Engineering data design, arrange the circuit board units into a symmetrical layout, and mirror the stacked materials.

[0134] Step 2: Cutting the material: Cut the large copper-clad laminate into the required working boards according to the design requirements.

[0135] Step 3: Lamination. Laminate a layer of blue photosensitive dry film onto the work plate surface.

[0136] Step 4: Draw the original or output LDI board data based on the designed layout and mirrored overlay circuit data.

[0137] Step 5: Inner Layer Exposure. After aligning the film with the circuit board with the pressed dry film, exposure is performed. Exposure is then performed on the work board after the dry film has been pressed. Under the exposure machine's energy, the transparent areas of the film are exposed, while the black areas remain unexposed on the dry film. Alternatively, LDI can be used, where exposure is performed on the work board after the dry film has been pressed. After this process, the copper conductor image is transferred to the dry film. In the exposed areas, the dry film undergoes a polymerization reaction, while in the unexposed areas, the dry film does not undergo a polymerization reaction, completing the image transfer.

[0138] Step 6: Inner layer development. The developer removes the dry film that has not undergone polymerization, while the dry film that has undergone polymerization remains unaffected. This exposes the conductors that do not need to be retained for the next etching process.

[0139] Step 7: Inner layer etching. Using an etching solution, the copper conductors without dry film protection are etched away, while the copper conductors with dry film protection are retained. This process fabricates the inner layer circuitry.

[0140] Step 8: Stripping. The dry film protecting the copper conductor is removed using a stripping solution. At this point, the inner layer circuitry and the inner pad of the target hole are complete.

[0141] Step 9: Optical inspection. Perform an optical inspection on the completed inner circuit board to confirm its quality.

[0142] Step 10: Browning. The surface of the finished circuit board is browned using a browning solution to roughen the surface of the copper conductor.

[0143] Step 11: Lamination. Place a prepreg sheet on top and bottom of the browned inner circuit board, and a copper foil on top and bottom of the prepreg sheet. Then, laminate in a high-temperature environment. During lamination, the core boards are flipped according to the layout requirements to achieve lamination of multiple core boards.

[0144] Step 12: Drill holes. Use a drilling machine to drill holes inside the board and tool holes on the edge of the board.

[0145] Step 13: Electroplating: After drilling, the inner wall of the hole is coated with copper and then electroplated with the required copper thickness to achieve the electrical function.

[0146] Step 14: Outer layer exposure. After aligning the circuit board with the pressed dry film using an exposure machine, expose it to complete the image transfer of the outer layer circuit board.

[0147] Step 15: Produce the PCB board with the final circuit pattern into a finished product according to the normal process; the normal process includes: etching, solder masking, character printing, surface treatment, molding, and testing, with all parameters being normal process parameters;

[0148] This method improves the efficiency of inner layer board production by constructing a new stacking method and symmetrical layout combination. The method is simple and easy to promote in mass production.

[0149] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0150] II. Application Examples:

[0151] Application examples

[0152] This invention provides a computer device, which includes at least one processor and a memory, and can be used in products manufactured using the above-described manufacturing method.

[0153] This invention also provides an information data processing terminal, which can be used in products manufactured using the above-described manufacturing method. The information data processing terminal is not limited to mobile phones, computers, or switches.

[0154] This invention also provides a server that can be used to manufacture products using the above-described manufacturing method.

[0155] The computer device may include: any entity or device capable of carrying computer program code to the camera / terminal device, computer memory, read-only memory (ROM), random access memory (RAM), and software distribution media, such as USB flash drives, portable hard drives, magnetic disks, or optical discs.

[0156] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0157] The information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of the present invention. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.

[0158] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this invention. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments.

[0159] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions and improvements made by those skilled in the art within the scope of the technology disclosed in the present invention and within the spirit and principles of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A method for fabricating the inner layer of a high-density circuit board, characterized in that, The method includes: S1, arrange the circuit board shipping units symmetrically; S2, mirror the stack-up data of the circuit board; S3. After the layout processing in step S1 and the stacking processing in step S2, the same multiple core boards are repeatedly produced. S4: Take multiple core boards that have been repeatedly produced in step S3 and combine them; S5, after step S4, the multiple core boards that have been combined and matched are pressed together, and after pressing, the subsequent processes are completed according to the normal production process. In step S4, the multiple core boards repeatedly produced in step S3 are combined and paired, specifically including: Take multiple core boards produced repeatedly. When using a layout method that is symmetrical about the left and right along the Y-axis, the first core board is stacked normally. When stacking the second core board directly below the first core board, the second core board is mirrored and rotated 180° left and right. The layout adopts a symmetrical arrangement along the X-axis. The first core board is stacked normally. When the second core board is stacked directly below the first core board, the second core board is mirrored vertically and rotated 180° vertically. During the combination and pairing process, the left and right mirroring of the second core board specifically includes: Step 1: Establish a reference coordinate system for calculating the core board flipping state. Circuit board coordinate system and the estimation reference coordinate system used for filtering ; Step 2: Define the core board flip state error, sample real-time flip points, and construct the real-time flip points corresponding to the global core board flip state. Step 3: Transfer the real-time flip point of the core board flip state in the kinematic equation of the core board flip state and construct the real-time flip point of the core board flip state error after transfer. Step 4: Perform error calculation and set the core board flipping state error estimate to zero; In step one, the establishment of a reference coordinate system for calculating the core board flipping state is described. Circuit board coordinate system and the estimation reference coordinate system used for filtering include: Establish the coordinate system in which the core board flipping state is calculated, i.e., the reference coordinate system. The reference coordinate system It can be an inertial coordinate system, a geodetic coordinate system, or a local geographic coordinate system; Establish an estimated reference coordinate system The estimated reference coordinate system The reference coordinate system estimated in the filtering algorithm, the estimated reference coordinate system With the reference coordinate system The error between them is the core board flipping state error; In step two, the core board flipping state error is defined as follows: ； in, Represents the true error matrix. express The corresponding estimated value; The process of sampling real-time flip points and constructing the real-time flip points corresponding to the global core board flip state includes: Using the variance of the core board flipping state at the previous moment Real-time flip point sampling is performed as follows: ； The real-time flip points corresponding to the constructed global core board flip state include: Convert the real-time flip points of the core board flip state error into matrix form: ； in, The defined conversion formula is: ； Using the core board flipping state estimate from the previous moment Construct the real-time flip point corresponding to the global core board flip state. ； In step three, the process of transferring the real-time flipping point of the core plate in the kinematic equation of the core plate flipping state includes: ； in, The kinematic equations representing the core plate flipping state; The real-time reversal point of the core board flipping state error after the structure is transferred. Based on the defined core board flipping state error, construct the real-time flipping point of the transferred core board flipping state error: ； Convert the matrix-form core board flip state error into a vector-form error: ； in, The defined conversion formula is: ； In step four, the error calculation is performed as follows: ； ； in, This represents the weight corresponding to the real-time flip point. This represents the state variance matrix.

2. The method for fabricating the inner layer of a high-density circuit board according to claim 1, characterized in that, In step S1, symmetrically arranging the shipping units of the circuit boards specifically includes: Layout method 1: The layout is symmetrical along the Y-axis. Layout method 2: The layout is symmetrical along the X-axis. Layout method 3: The layout is symmetrical on the left and right, top and bottom of the X and Y axes.

3. The method for fabricating the inner layer of a high-density circuit board according to claim 2, characterized in that, In step S2, the mirroring of the circuit board's stack-up data specifically includes: By adopting a layout method that is symmetrical about the Y-axis, the stacked areas of the circuit board are mirrored, so that the circuit data of the original two core boards are merged into one core board.

4. The method for fabricating the inner layer of a high-density circuit board according to claim 3, characterized in that, In step S2, mirroring the stack-up data of the circuit board also includes: By adopting a layout method that is symmetrical about the X-axis, the stacked areas of the circuit board are mirrored, so that the circuit data of the original two core boards are merged into one core board. By adopting a layout method that is symmetrical in the left and right and top and bottom of the X and Y axes, the stacking of the circuit board's stacked areas is mirrored, so that the circuit data of the original two core boards are merged into one core board.

5. The method for fabricating the inner layer of a high-density circuit board according to claim 1, characterized in that, In steps S1-S5, the number of core boards is an even number.

6. A high-density circuit board manufactured using a method for fabricating the inner layer of a high-density circuit board according to any one of claims 1-5.

7. An HDI board for electronic devices, characterized in that, The HDI board of the electronic device is manufactured using the method for manufacturing the inner layer of a high-density circuit board as described in any one of claims 1-5.

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