A current detection circuit

Abstract

The application provides a current detection circuit applied to the technical field of current detection.The current detection circuit comprises a current mirror unit, a first switch unit, a first current mirror circuit and a second current mirror circuit which are connected in sequence; the source of the first switch unit is connected with a power supply voltage VDD, and the first switch unit is provided with a body potential; a voltage conversion module is connected with the current mirror unit, and the input end of the voltage conversion module is connected with the drain of the first switch unit. The first current mirror circuit and the second current mirror circuit are arranged in the current detection circuit, and the first current mirror circuit and the second current mirror circuit are connected with the first operational amplifier respectively, two-way current mirror is realized through one operational amplifier, and two-way current mirror is realized under the premise of not sacrificing the chip area. Thus, the current detection circuit provided by the application can reduce the cost of the chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of current detection, in particular to a current detection circuit. BACKGROUND

[0002] In a current detection system, the current mirror output power tube current is generally detected to achieve the function. In the traditional architecture, the current mirror and the operational amplifier clamping are used to achieve the current mirror function together, and then the high-precision current detection function is achieved. When the sense current and the limit current two-way mirror are needed to be achieved, two operational amplifiers are needed to clamp the source end or the drain end, which sacrifices the chip area to a certain extent. When the on-resistance is large, the parasitic diode is turned on, which seriously affects the current mirror precision. SUMMARY

[0003] Therefore, the purpose of the present application is to provide a current detection circuit to achieve high-precision current mirroring. In the traditional architecture, the current mirror and the operational amplifier clamping are used to achieve the current mirror function together, and then the high-precision current detection function is achieved. However, when the sense current and the limit current two-way mirror are needed to be achieved, two operational amplifiers are needed to clamp the source end and the drain end, which sacrifices the chip area and power consumption to a certain extent.

[0004] In a first aspect, an embodiment of the present application provides a current detection circuit, which comprises:

[0005] A current mirror unit comprises a first switch unit, a first current mirror circuit and a second current mirror circuit connected in sequence. The source of the first switch unit is connected with a power supply voltage VDD, and the first switch unit is provided with a body potential.

[0006] A voltage conversion module is connected with the current mirror unit. The input end of the voltage conversion module is connected with the drain of the first switch unit, and the output end of the voltage conversion module is used to output an adjusted voltage value.

[0007] A current detection unit is connected with the current mirror unit and outputs the detected current.

[0008] A first operational amplifier is connected with the first switch unit, the first current mirror circuit and the second current mirror circuit in the current mirror unit.

[0009] A potential biasing module is connected with the power supply voltage VDD, the current mirror unit and the ground, and is used to clamp the body potential of the first switch unit.

[0010] As an implementable way, the voltage conversion module comprises:

[0011] a second operational amplifier, comprising a positive input terminal, a negative input terminal and an output terminal; the negative input terminal of the second operational amplifier is connected with a reference voltage VREF; the positive input terminal of the second operational amplifier is connected with a load resistance;

[0012] a second switch unit, the gate of the second switch unit is connected with the output terminal of the second operational amplifier; the source of the second switch unit is connected with the drain of the first switch unit; the drain of the second switch unit is the output terminal LDO-OUT of the voltage conversion module.

[0013] As an implementable manner, the potential biasing module comprises:

[0014] a third switch unit, the source of the third switch unit is connected with a power supply voltage VDD;

[0015] and a biasing current Ibias, the third switch unit is connected in series with the biasing current Ibias, the drain of the third switch unit is electrically connected with the body potential of the first switch unit and the biasing current Ibias.

[0016] As an implementable manner, the first current mirror circuit comprises:

[0017] a first MOS transistor, the source of the first MOS transistor is connected with a power supply voltage VDD, the gate of the first MOS transistor is connected with a control voltage;

[0018] a third MOS transistor, the source of the third MOS transistor is connected with the negative input terminal of the first operational amplifier and the drain of the first MOS transistor, the drain of the third MOS transistor is connected with a SENSE terminal; the gate of the third MOS transistor is connected with the output terminal of the first operational amplifier.

[0019] As an implementable manner, the second current mirror circuit comprises:

[0020] a second MOS transistor, the source of the second MOS transistor is connected with a power supply voltage VDD; the gate of the first MOS transistor is connected with a control voltage;

[0021] a fourth MOS transistor, the source of the fourth MOS transistor is connected with the drain of the second MOS transistor, the drain of the fourth MOS transistor is connected with a LIM terminal; the gate of the fourth MOS transistor is connected with the output terminal of the first operational amplifier.

[0022] As an implementable manner, the potential biasing module is further connected with the body potential of the first MOS transistor in the first current mirror circuit and the body potential of the fourth MOS transistor in the second current mirror circuit.

[0023] As an implementable manner, the first current mirror circuit further comprises a sampling resistor connected with the SENSE terminal.

[0024] As an implementable manner, the current detection circuit further comprises an overcurrent protection circuit comprising a programmable load resistor connected with the LIM terminal.

[0025] As an implementable manner, the size ratio of the first switch unit to the first MOS transistor is N:1.

[0026] As an implementable manner, the size ratio of the first MOS transistor to the second MOS transistor is 1:1, and the size ratio of the third MOS transistor to the fourth MOS transistor is 1:1.

[0027] The embodiment of the present application provides a current detection circuit, which comprises: a current mirror unit comprising a first switch unit, a first current mirror circuit and a second current mirror circuit connected in sequence; a source of the first switch unit is connected with a power supply voltage VDD, and the first switch unit is provided with a body potential; a voltage conversion module connected with the current mirror unit, an input end of the voltage conversion module is connected with a drain of the first switch unit, and an output end of the voltage conversion module is used for outputting an adjusted voltage value; a current detection unit connected with the current mirror unit and used for outputting a detected current; a first operational amplifier connected with the first switch unit, the first current mirror circuit and the second current mirror circuit in the current mirror unit; and a potential biasing module connected with the power supply voltage VDD, the current mirror unit and a ground, and used for clamping the body potential of the first switch unit.

[0028] The current detection circuit is provided with the first current mirror circuit and the second current mirror circuit, and the first current mirror circuit and the second current mirror circuit are respectively connected with the first operational amplifier, so that two-way current mirror is realized through one operational amplifier, and two-way current mirror is realized without sacrificing the chip area. In this way, the current detection circuit provided by the present application can reduce the cost of the chip and reduce the design requirement for the offset voltage. The present application realizes the technical effect that the protection threshold is adjustable in overcurrent protection by setting the programmable load resistor with adjustable resistance, and can flexibly realize overcurrent protection under different working conditions. In addition, the present application can maintain high precision during current mirroring by setting the potential biasing module, improves the current detection precision, clamps the body potential of the switch tube, makes the reverse parasitic Diode not conduct, and realizes reverse polarity protection.

[0029] Other features and advantages of the present application will be set forth in the description that follows, and in part will be apparent from the description, or can be learned by practice of the application. The purposes and other advantages of the application will be realized and attained by the structure particularly pointed out in the description, claims and drawings.

[0030] In order to make the above objectives, features and advantages of the present application more apparent, the following will describe a preferred embodiment in detail, and the accompanying drawings will be referred to, as follows. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings needed to be used in the specific embodiments or the prior art description. Obviously, the drawings described below are some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0032] Figure 1 A current detection circuit schematic diagram provided for the embodiment 1 of the present application;

[0033] Figure 2 A current detection circuit schematic diagram provided for the embodiment 2 of the present application.

[0034] The reference signs are as follows:

[0035] 1-first switch unit, 2-voltage conversion module, 21-second operational amplifier, 22-second switch unit, 3-first operational amplifier, 4-first MOS tube, 5-third MOS tube, 6-second MOS tube, 7-fourth MOS tube, 8-potential biasing module, 81-third switch unit. DETAILED DESCRIPTION

[0036] In order to make the objectives, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the present application will be described clearly and completely in combination with the drawings. Obviously, the described embodiments are some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the present application.

[0037] In order to make the present application better understood by those skilled in the art, the following will first introduce the technical terms involved in the present application.

[0038] MOS transistor: Metal-Oxide-Semiconductor Field-Effect Transistor, commonly known as MOSFET, is a kind of field-effect transistor that can be widely used in analog circuits and digital circuits. MOSFET can be divided into "N-type" and "P-type" according to the polarity of its working carrier, usually represented by NMOSFET and PMOSFET, whose abbreviations include NMOS and PMOS.

[0039] After introducing the technical terms related to the present application, the application scenarios of the embodiments of the present application will be briefly described below.

[0040] At present, power modules such as LDO (Low Dropout Regulator) are used in more and more applications, and the requirements for LDO are also getting higher and higher. For example, it has high-precision current detection function and the like.

[0041] In the related art, although there is a technical means of mirroring the detection circuit by using a current mirror, the current mirroring function is realized by current mirror and operational amplifier clamping, and then the function of monitoring high-precision current is realized. However, one current mirror needs to be equipped with one operational amplifier, that is, two operational amplifiers are needed to realize the simultaneous detection of two currents. This will increase the chip area and the production cost.

[0042] In order to solve the above technical problems, the present application provides a current detection circuit which can realize the function of detecting two currents without increasing the chip area.

[0043] Embodiment 1

[0044] In combination with Figure 1 The embodiment provides a current detection circuit, which comprises a current mirroring unit, a voltage conversion module 2, a current detection unit, a first operational amplifier 3 and a potential biasing module.

[0045] The current mirroring unit comprises a first switching unit 1, a first current mirroring circuit and a second current mirroring circuit connected in sequence. The source (S terminal) of the first switching unit 1 is connected with a power supply voltage VDD. Two diodes in opposite polarity are arranged in the first switching unit 1, and the output end of the first switching unit 1 is a body potential.

[0046] The first current mirroring circuit comprises a first MOS transistor 4 and a third MOS transistor 5 connected in series. The gate (G terminal) of the third MOS transistor 5 is connected with the output end of the first operational amplifier 3, and the source (S terminal) of the third MOS transistor 5 is connected with the negative input end of the first operational amplifier 3.

[0047] The second current mirror circuit comprises a second MOS tube 6 and a fourth MOS tube 7 connected in series. The gate (G terminal) of the fourth MOS tube 7 is connected with the output terminal of the first operational amplifier 3, and the source (S terminal) of the fourth MOS tube 7 is connected with the drain (D terminal) of the second MOS tube 6.

[0048] In the embodiment, the voltage conversion module 2 comprises a second operational amplifier 21 and a second switch unit 22.

[0049] The second operational amplifier 21 comprises a positive input terminal, a negative input terminal and an output terminal. The negative input terminal of the second operational amplifier 21 is connected with a reference voltage VREF. The positive input terminal of the second operational amplifier 21 is connected with a load resistance.

[0050] The gate of the second switch unit 22 is connected with the output terminal of the second operational amplifier 21. The source of the second switch unit 22 is connected with the drain of the first switch unit 1. The drain of the second switch unit 22 is connected with an output load LDO-OUT.

[0051] The current detection unit is connected with the current mirror unit and outputs the detected current.

[0052] The first operational amplifier 3 comprises a positive input terminal, a negative input terminal and an output terminal. The first operational amplifier 3 is connected with the first switch unit 1, the first current mirror circuit and the second current mirror circuit in the current mirror unit.

[0053] The input terminal of the potential biasing module 8 is connected with a power supply voltage VDD. The output terminal of the potential biasing module 8 is connected with the output terminal of the voltage conversion module 2, for biasing the output body potential of the voltage conversion module 2.

[0054] In the embodiment, the first current mirror circuit and the second current mirror circuit are respectively connected with the first operational amplifier 3, so that the function of clamping two circuit current mirrors by using one operational amplifier is realized, the area of the chip is saved, and the source of the third MOS tube 5 and the fourth MOS tube 7 can be clamped through the loop formed between the negative input terminal, the output terminal of the first operational amplifier and the third MOS tube 5. In the embodiment, two diodes of opposite polarity are arranged in the first switch unit 1, so that reverse battery polarity protection can be provided. The body potential can be clamped by the potential biasing module, so that the influence of the parasitic Diode on the current mirror precision can be avoided.

[0055] Optionally, the first current mirror circuit comprises a first MOS tube 4 and a third MOS tube 5.

[0056] The source of the first MOS tube 4 is connected with the power supply voltage VDD. The gate of the first MOS tube is connected with an input voltage VGS.

[0057] The source of the third MOS transistor 5 is connected with the negative input terminal of the first operational amplifier 3 and the drain of the first MOS transistor 4, and the drain of the third MOS transistor 5 is connected with the SENSE terminal; the gate of the third MOS transistor 5 is connected with the output terminal of the first operational amplifier 3.

[0058] Optionally, the second current mirror circuit comprises a second MOS transistor 6 and a fourth MOS transistor 7.

[0059] The source of the second MOS transistor 6 is connected with the power voltage VDD, and the gate of the first MOS transistor is connected with the input voltage VGS.

[0060] The source of the fourth MOS transistor 7 is connected with the drain of the second MOS transistor 6, and the drain of the fourth MOS transistor 7 is connected with the LIM terminal; the gate of the fourth MOS transistor 7 is connected with the output terminal of the first operational amplifier 3.

[0061] Optionally, the first current mirror circuit further comprises a sampling resistor connected with the SENSE terminal, and the sampling resistor has a fixed resistance value.

[0062] Optionally, the second current mirror circuit further comprises a programmable load resistor connected with the LIM terminal, and the programmable load resistor can be adjusted according to the threshold value of the overcurrent protection.

[0063] Thus, in the embodiment, the voltage conversion module 2 is an LDO module, and a high-precision current detection circuit suitable for the LDO module is provided. The two current mirror circuits are respectively electrically connected with the first operational amplifier, so as to realize the mirroring of the sense and limit currents. The chip area is saved, and the overcurrent protection function is realized by configuring and editing the programmable resistor.

[0064] Optionally, the size (width-length ratio) of the first switch unit 1 is N:1 compared with the size (width-length ratio) of the first MOS transistor 4.

[0065] Optionally, the size (width-length ratio) of the first MOS transistor 4 is 1:1 compared with the size (width-length ratio) of the second MOS transistor 6, and the size (width-length ratio) of the third MOS transistor 5 is 1:1 compared with the size (width-length ratio) of the fourth MOS transistor 7.

[0066] The first operational amplifier 3 clamps the drain terminal of the first switch unit 1 and the first MOS transistor 4, and the input offset voltage of the first operational amplifier 3 is related to the width-length ratio of the first switch unit 1 and the first MOS transistor 4. When the load current of the voltage conversion module 2 is NmA, the current flowing out of the first MOS transistor 4 is 1mA.

[0067] In this embodiment, the mirroring principle is the same as in embodiment 1. The voltage is clamped by the first operational amplifier 3, and the voltage is mirrored by the aspect ratio. The current value to be detected can be obtained by comparing the mirrored voltage with the resistance on the circuit to be detected.

[0068] Example 2

[0069] Combination Figure 2 As shown, this embodiment provides another current detection circuit, including: a current mirror unit, a voltage conversion module 2, a current detection unit, a first operational amplifier 3, and a potential bias module 8.

[0070] The current mirror unit includes a first switching unit 1, a first current mirror circuit, and a second current mirror circuit connected in sequence; the source (S) of the first switching unit 1 is connected to the power supply voltage VDD; the first switching unit 1 contains two diodes connected in series with opposite polarities, and the output terminal of the first switching unit 1 is the body potential.

[0071] The first current mirror circuit includes a first MOSFET 4 and a third MOSFET 5 connected in series. The gate (G) of the third MOSFET 5 is connected to the output terminal of the first operational amplifier 3, and the source (S) of the third MOSFET 5 is connected to the negative input terminal of the first operational amplifier 3.

[0072] The second current mirror circuit includes a second MOSFET 6 and a fourth MOSFET 7 connected in series. The gate (G) of the fourth MOSFET 7 is connected to the output terminal of the first operational amplifier 3, and the source (S) of the fourth MOSFET 7 is connected to the drain (D) of the second MOSFET 6.

[0073] In this embodiment, the voltage conversion module 2 includes a second operational amplifier 21 and a second switching unit 22.

[0074] The second operational amplifier 21 includes a positive input terminal, a negative input terminal, and an output terminal; the negative input terminal of the second operational amplifier 21 is connected to the reference voltage VREF; the positive input terminal of the second operational amplifier 21 is connected to the load resistor.

[0075] The gate of the second switching unit 22 is connected to the output terminal of the second operational amplifier 21; the source of the second switching unit 22 is connected to the drain of the first switching unit 1; and the drain of the second switching unit 22 is connected to the output load LDO-OUT.

[0076] The current detection unit is connected to the current mirror unit and outputs the detected current.

[0077] In this embodiment, the potential bias module 8 includes a third switching unit 81.

[0078] The source of the third switch unit is connected with the power voltage VDD; the drain of the third switch unit is electrically connected with the body potential of the first switch unit 1 and the bias current Ibias.

[0079] The bias current Ibias ranges from 1uA to 50uA.

[0080] In the embodiment, the first current mirror circuit and the second current mirror circuit are respectively connected with the first operational amplifier, so that the function of two-way circuit current mirroring is realized by using one operational amplifier, and the area of the chip is saved. In the embodiment, two diodes in reverse polarity are arranged in the first switch unit 1, so that reverse battery polarity protection can be provided; the body potential is clamped by the potential biasing module, so that the influence of the reverse parasitic diode on the current accuracy can be avoided.

[0081] Optionally, the first current mirror circuit comprises a first MOS tube 4 and a third MOS tube 5.

[0082] The source of the first MOS tube 4 is connected with the power voltage VDD, and the gate of the first MOS tube is connected with a control voltage, and the value of the control voltage is VDD-VGS.

[0083] The source of the third MOS tube 5 is connected with the negative input end of the first operational amplifier 3 and the drain of the first MOS tube 4, the drain of the third MOS tube 5 is connected with a SENSE terminal, and is used for outputting the detected current; and the gate of the third MOS tube 5 is connected with the output end of the first operational amplifier 3.

[0084] Optionally, the second current mirror circuit comprises a second MOS tube 6 and a fourth MOS tube 7.

[0085] The source of the second MOS tube 6 is connected with the power voltage VDD; and the gate of the second MOS tube 6 is connected with the control voltage.

[0086] The source of the fourth MOS tube 7 is connected with the drain of the second MOS tube 6, the drain of the fourth MOS tube 7 is connected with an LIM terminal, and is used for overcurrent protection when the current exceeds a certain threshold; and the gate of the fourth MOS tube 7 is connected with the output end of the first operational amplifier 3.

[0087] Optionally, the first current mirror circuit further comprises a sampling resistor, the sampling resistor is connected with the SENSE terminal, and the resistance value of the sampling resistor is a fixed resistance value.

[0088] Optionally, the second current mirror circuit further comprises a programmable load resistor, and the programmable load resistor is connected with the LIM terminal.

[0089] Thus, in the embodiment, the voltage conversion module is an LDO module, and a high-precision current detection circuit suitable for the LDO module is provided, two current mirror circuits are electrically connected with the first operational amplifier respectively, and the sense and limit currents are mirrored.

[0090] Optionally, the size ratio of the first switch unit 1 to the first MOS tube 4 is N:1.

[0091] Optionally, the size ratio of the first MOS tube 4 to the second MOS tube 6 is 1:1, and the size ratio of the third MOS tube 5 to the fourth MOS tube 7 is 1:1.

[0092] The size ratio is the width-length ratio.

[0093] The first operational amplifier 3 clamps the drain end of the first switch unit 1 and the first MOS tube 4, the input offset voltage of the first operational amplifier 3 is related to the width-length ratio of the first switch unit 1 and the first MOS tube 4, when the load current of the voltage conversion module 2 is NmA, the current flowing out of the first MOS tube 4 is 1mA.

[0094] In the embodiment, a high-precision current detection circuit suitable for an LDO or other power supply module is provided, which can reduce the chip area to a certain extent compared with the traditional current detection architecture, and realizes reverse polarity protection and reduces the reverse tube area through the potential biasing module 8.

[0095] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system and device described above can refer to the corresponding process in the foregoing method embodiments, which will not be described here.

[0096] In addition, in the description of the embodiments of the present application, unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting" should be understood in a broad sense, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0097] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0098] Finally, it should be noted that the above-described embodiments are only specific embodiments of the present application, which are used to illustrate the technical solutions of the present application, and are not limiting. The protection scope of the present application is not limited thereto. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can make modifications or easily think of changes to the technical solutions recorded in the foregoing embodiments within the technical range disclosed by the present application, or make equivalent replacements to some technical features; and these modifications, changes or replacements do not cause the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A current detection circuit, characterized in that, The current detection circuit includes: The current mirror unit includes a first switching unit, a first current mirror circuit, and a second current mirror circuit connected in sequence; the source of the first switching unit is connected to the power supply voltage VDD, and the first switching unit is provided with a body potential; A voltage conversion module is connected to a current mirror unit. The input terminal of the voltage conversion module is connected to the drain of the first switching unit, and the output terminal of the voltage conversion module is used to output the regulated voltage value. The current detection unit is connected to the current mirror unit and outputs the detected current; The first operational amplifier is connected to the first switching unit, the first current mirror circuit, and the second current mirror circuit in the current mirror unit. A potential bias module is connected to the power supply voltage VDD, the current mirror unit and ground, and is used to clamp the body potential of the first switching unit. The first current mirror circuit includes: The first MOSFET has its source connected to the power supply voltage VDD and its gate connected to the control voltage. The third MOS transistor has its source connected to the negative input terminal of the first operational amplifier and the drain of the first MOS transistor, and its drain connected to the SENSE terminal; the gate of the third MOS transistor is connected to the output terminal of the first operational amplifier. The second current mirror circuit includes: The second MOSFET has its source connected to the power supply voltage VDD and its gate connected to the control voltage. The fourth MOS transistor has its source connected to the drain of the second MOS transistor, and its drain connected to the LIM terminal; the gate of the fourth MOS transistor is connected to the output terminal of the first operational amplifier.

2. The current detection circuit according to claim 1, characterized in that, The voltage conversion module includes: The second operational amplifier includes a positive input terminal, a negative input terminal, and an output terminal; the negative input terminal of the second operational amplifier is connected to the reference voltage VREF; the positive input terminal of the second operational amplifier is connected to the load resistor. The second switching unit has its gate connected to the output terminal of the operational amplifier; its source is connected to the drain of the first switching unit; and its drain serves as the output terminal LDO-OUT of the voltage conversion module.

3. The current detection circuit according to claim 1, characterized in that, The potential bias module includes: The third switching unit, wherein the source of the third switching unit is connected to the power supply voltage VDD; The third switching unit is connected in series with the bias current Ibias, and the drain of the third switching unit is electrically connected to the body potential of the first switching unit and the bias current Ibias.

4. The current detection circuit according to claim 1, characterized in that, The potential bias module is also connected to the body potential of the first MOS transistor in the first current mirror circuit and the body potential of the fourth MOS transistor in the second current mirror circuit.

5. The current detection circuit according to claim 1, characterized in that, The first current mirror circuit also includes a sampling resistor, which is connected to the SENSE terminal.

6. The current detection circuit according to claim 1, characterized in that, The current detection circuit also includes an overcurrent protection circuit, which includes a programmable load resistor connected to the LIM terminal.

7. The current detection circuit according to claim 1, characterized in that, The size ratio of the first switching unit to the first MOSFET is N:

1.

8. The current detection circuit according to claim 1, characterized in that, The size ratio of the first MOSFET to the second MOSFET is 1:1; the size ratio of the third MOSFET to the fourth MOSFET is 1:1.

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