A low-power, simple-structure voltage detection circuit

Abstract

The application discloses a low-power-consumption voltage detection circuit with simple structure, which comprises MOS tubes NM1, NM2 and NM3, resistors R1 and R2, inverters INV1 and INV2, bias currents I1, I2 and I3 and a stabilizing diode Z1. The voltage detection circuit uses the reverse breakdown voltage of the stabilizing diode as the judgment threshold of the voltage detection circuit, and does not need an additional circuit to generate a reference voltage. The simple comparator is composed of a constant current source and a current mirror structure MOS tube, and the circuit structure is simple, small in area and low in power consumption. The bias current in the application is small, at the nA level, and the power consumption is greatly reduced compared with a traditional comparator. The application rationally uses the simple comparator composed of the stabilizing diode, the constant current source and the current mirror, so that the circuit structure is simple, easy to integrate, small in bias current and low in power consumption.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of analog integrated circuit, and particularly relates to a low-power and simple-structured voltage detection circuit. BACKGROUND

[0002] The voltage detection circuit is widely used in many power management circuit systems, such as DC-DC, charge pump and battery protection chip, etc. The basic function of the voltage detection circuit is to change the working state of some circuit modules in the circuit system by detecting whether the voltage in the circuit exceeds the safe working voltage, so as to realize the protection of the device.

[0003] The common way of voltage detection is to use a traditional comparator, but the traditional comparator uses many devices and needs an additional bias circuit to generate a reference voltage, so the circuit complexity is large and the power consumption is also large.

[0004] In the existing system applied to the pump circuit, the pump circuit needs to output a voltage higher than the power supply voltage for driving the subsequent circuit, but the voltage cannot exceed the gate-source voltage of the MOS tube, and the MOS tube usually adopts a thin gate oxide device with a gate-source voltage of about 5.5V. In order to make the output voltage of the pump circuit not exceed the gate-source voltage of the MOS tube, a voltage detection circuit is used to detect the output voltage of the pump circuit, and when the output voltage reaches the set threshold, the comparator output jumps from high to low, shielding the clock signal, so that the output voltage of the pump circuit no longer continues to rise. The schematic diagram is shown in Figure 2

[0005] Mainly includes a voltage detection module 100, a pump circuit, and a gate AND.

[0006] The voltage detection module 100 includes a comparator comp, resistors R1 and R2, and the output VOUT changes by comparing the relationship between VIN and the reference voltage VREF, changing the working state of the pump circuit.

[0007] Pump circuit: The pump circuit realizes the function of pressure increase, that is, VOUT_H can reach 2*VDD at most.

[0008] VDD is the power supply voltage of the above-mentioned system, VREF is the bias voltage as the reference voltage of the comparator comp, Clk is the clock signal, and the voltage domain is VDD-GND.

[0009] Since the output VOUT_H of the pump circuit can reach 2*VDD at most, when the VDD voltage changes in a large range, the output voltage VOUT_H may exceed the device voltage, so the comparator needs to detect the output voltage to control the working of the pump circuit.

[0010] Working principle: ​

[0011] In the above circuit, When VIN < VREF, the comparator output VOUT is high. When VIN > VREF, the comparator output VOUT is low.

[0012] When VDD voltage is low, and That is, When VIN is always less than VREF, the comparator comp output VOUT is always high, and the output VIN_L is the clock signal Clk after AND operation with Clk, and the pump circuit always works normally, and the output VOUT_H = 2*VDD.

[0013] When The output voltage of the pump circuit continues to rise, and when it rises to The comparator comp output VOUT is from high to low, and the clock is shielded after AND operation with Clk, and the output VIN_L is low, and the output VOUT_H of the pump circuit no longer continues to rise. When the output VOUT_H falls to The comparator output jumps high, and the pump circuit is opened again, and the output VOUT_H rises again. So repeatedly, the output VOUT_H of the pump circuit will finally stabilize near the set threshold ;

[0014] In the traditional voltage detection circuit, the detection method of the comparator and the resistance voltage division is adopted, and there are the defects of large power consumption, complex circuit structure and high cost. Therefore, we propose a low-power and simple-structure voltage detection circuit. SUMMARY

[0015] The purpose of the present application is to provide a low-power and simple-structure voltage detection circuit to solve the problems in the background art.

[0016] To achieve the above purpose, the present application provides the following technical scheme: a low-power and simple-structure voltage detection circuit, comprising MOS tube NM1, MOS tube NM2, MOS tube NM3, resistor R1, resistor R2, inverter INV1, inverter INV2, bias current I1, bias current I2, bias current I3 and zener diode Z1.

[0017] One end of the MOS tube NM1 is electrically connected to the output end of the inverter INV1, and the anode of the zener diode Z1 is also electrically connected to the other end of the MOS tube NM1.

[0018] ​The MOS NM2 and the MOS NM3 are electrically connected through one end pin, the other end pin of the MOS NM2 is electrically connected with the resistor R1, the other end pin of the MOS NM3 is electrically connected with the resistor R2, the resistor R2 and the MOS NM3 are provided with a connecting point B, the connecting point B is electrically connected with one end pin of the MOS NM1;

[0019] The other end of the MOS NM3 is provided with a connecting point C, the connecting point C is electrically connected with the input end of the inverter INV2.

[0020] Preferably, the input end of the inverter INV1 and the negative pole of the voltage stabilizing diode Z1 are commonly electrically connected with a signal input end VIN to be detected, the output end of the inverter INV2 is electrically connected with a detection result output end VOUT.

[0021] Preferably, the MOS NM2 and the MOS NM3 are of the same size, the gate and the drain of the MOS NM2 are electrically connected and electrically connected with the gate of the MOS NM3, which is the connection mode of the current mirror, the gate ends of the MOS NM2 and the MOS NM3 are equal in voltage.

[0022] Preferably, the drain of the MOS NM2 and the drain of the MOS NM3 are electrically connected with one end of the bias current I1 and the bias current I2 respectively, the source of the MOS NM2 and the source of the MOS NM3 are electrically connected with one end of the resistor R1 and the resistor R2 respectively, the other end of the resistor R1 and the resistor R2 is electrically connected with the ground end GND.

[0023] Preferably, the input end of the inverter INV1 is connected with the signal input end VIN to be detected, the output end of the inverter INV1 is electrically connected with the gate of the MOS NM1, the drain of the MOS NM1 is electrically connected with the positive pole of the voltage stabilizing diode Z1, the drain of the MOS NM1 is electrically connected with one end of the resistor R2, the power supply end of the inverter INV1 is electrically connected with the power supply voltage input end VDD, the ground end of the inverter INV1 and the source of the MOS NM1 are electrically connected with the ground end GND.

[0024] Preferably, the bias current I1, the bias current I2 and the bias current I3 flow into the MOS NM2, the MOS NM3 and the inverter INV2 from the power supply voltage input end VDD respectively, the bias current I1, the bias current I2 and the bias current I3 are all nA level currents.

[0025] Preferably, the bias current I1 and the bias current I2 have the same magnitude, and the resistance R1 has a greater resistance value than the resistance R2.

[0026] Compared with the prior art, the present application has the following advantages:

[0027] The voltage detection circuit of the present application uses the reverse breakdown voltage of the voltage stabilizing diode as the judgment threshold of the voltage detection circuit, and does not need an additional circuit to generate a reference voltage; a simple comparator is formed by using a constant current source and a current mirror structure MOS tube, and the circuit structure is more simple and the area is smaller; the bias current in the present application is small, at the nA level, and compared with the traditional comparator, the power consumption is greatly reduced.

[0028] The present application uses the reasonable use of the simple comparator formed by the voltage stabilizing diode, the constant current source and the current mirror, so that the circuit structure is simple, easy to integrate, and the overall power consumption is very low.

[0029] The present application is not only applicable to the pump circuit system as an example, but also applicable to all electronic circuits that meet the requirements of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 The present application is not only applicable to the pump circuit system as an example, but also applicable to all electronic circuits that meet the requirements of the present application.

[0031] Figure 2 The present application is not only applicable to the pump circuit system as an example, but also applicable to all electronic circuits that meet the requirements of the present application. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of the present application.

[0033] Please refer to Figure 1 The present application provides a technical solution: a low-power, simple-structure voltage detection circuit, comprising MOS tube NM1, MOS tube NM2, MOS tube NM3, resistance R1, resistance R2, inverter INV1, inverter INV2, bias current I1, bias current I2, bias current I3 and voltage stabilizing diode Z1.

[0034] One end of the MOS tube NM1 is electrically connected to the output end of the inverter INV1, and the positive electrode of the voltage stabilizing diode Z1 is also electrically connected to the other end of the MOS tube NM1.

[0035] The MOS NM2 and the MOS NM3 are electrically connected through one end pin, the other end pin of the MOS NM2 is electrically connected with the resistor R1, the other end pin of the MOS NM3 is electrically connected with the resistor R2, the resistor R2 and the MOS NM3 are provided with a connecting point B, and the connecting point B is electrically connected with one end pin of the MOS NM1.

[0036] The other end of the MOS NM3 is provided with a connecting point C, and the connecting point C is electrically connected with the input end of the inverter INV2.

[0037] In order to realize input and output of the detection signal, preferably, the negative electrode of the voltage stabilizing diode Z1 is electrically connected with a signal input end VIN to be detected, and the output end of the inverter INV2 is electrically connected with a detection result output end VOUT.

[0038] In order to realize current mirror connection of the MOS NM2 and the MOS NM3, preferably, the MOS NM2 and the MOS NM3 are of the same size, the gate and the drain of the MOS NM2 are electrically connected, and the gate of the MOS NM3 is electrically connected, which is a current mirror connection mode, and the gate ends of the MOS NM2 and the MOS NM3 are equal in voltage.

[0039] In order to realize that the MOS with current mirror structure and the constant current source constitute a simple comparator, preferably, the drain of the MOS NM2 and the drain of the MOS NM3 are electrically connected with one end of the bias current I1 and one end of the bias current I2 respectively, the source of the MOS NM2 and the source of the MOS NM3 are electrically connected with one end of the resistor R1 and one end of the resistor R2 respectively, and the other end of the resistor R1 and the other end of the resistor R2 are electrically connected with the ground end GND.

[0040] In order to realize stable information transmission of the system and solve the misjudgment caused by input step, preferably, the input end of the inverter INV1 is connected with the signal input end VIN to be detected, the output end of the inverter INV1 is electrically connected with the gate of the MOS NM1, the drain of the MOS NM1 is electrically connected with the anode of the voltage stabilizing diode Z1, the drain of the MOS NM1 is electrically connected with one end of the resistor R2, the power supply end of the inverter INV1 is electrically connected with the power supply voltage input end VDD, and the ground end of the inverter INV1 and the source of the MOS NM1 are electrically connected with the ground end GND.

[0041] In order to achieve the input and control of bias current for the system, in this embodiment, preferably, the bias current I1, the bias current I2 and the bias current I3 flow from the power supply voltage input terminal VDD into the MOSFET NM2, the MOSFET NM3 and the inverter INV2 respectively, and the bias current I1, the bias current I2 and the bias current I3 are all in the nA level.

[0042] In order to set the initial state of the system and maintain stability, in this embodiment, preferably, the bias current I1 and the bias current I2 are the same, and the resistance of resistor R1 is greater than the resistance of resistor R2.

[0043] The working principle and usage of this invention are as follows: The voltage detection circuit includes bias currents I1, I2, and I3 connected to the power supply voltage VDD. Bias current I1 is connected in series with the drain and gate of MOSFET NM2. The source of MOSFET NM2 is connected in series with one end of resistor R1 at point A. The other end of resistor R1 is connected to GND. Bias current I2 is connected in series with the drain of MOSFET NM3 at point C. The gate of MOSFET NM3 is connected to the gate of MOSFET NM2. The source of MOSFET NM3 is connected to one end of resistor R2 at point B. The other end of resistor R2 is connected to GND. The bias current I3 is connected in series with the input terminal of inverter INV2. The input terminal of inverter INV2 is connected to the drain of MOSFET NM3. The output terminal is connected to the output terminal VOUT. The negative terminal of Zener diode Z1 is connected to the signal input terminal VIN. The positive terminal is connected to resistor R2 at point B. The input terminal of inverter INV1 is connected to the signal input terminal VIN. The output terminal is connected to the gate of MOSFET NM1. The drain of MOSFET NM1 is connected to the positive terminal of Zener diode Z1. The source is connected to GND.

[0044] When the voltage at the signal input terminal VIN is low and less than the reverse breakdown voltage V of the Zener diode Z1 Z1 At this time, Zener diode Z1 will not conduct, meaning no current flows through it. MOSFETs NM2 and NM3 are the same size and connected as current mirrors, so their gate voltages are equal. Since bias current I1 = bias current I2 and resistance R1 > resistance R2, the voltage at point A is greater than the voltage at point B (V). A >V B That is, the gate-source voltage (VGS3) of MOSFET NM3 is greater than the gate-source voltage (VGS2) of MOSFET NM2. At this time, the drain voltage (VGS3) of MOSFET NM3 is greater than the drain voltage (VGS2) of MOSFET NM2. C When the output is low, the output terminal VOUT is high.

[0045] When the voltage at the signal input terminal VIN rises and exceeds the reverse breakdown voltage V of the Zener diode Z1...Z1 When the voltage at B point rises to V B >V A , the gate-source voltage (VGS3) of MOS NM3 is less than that of MOS NM2 (VGS2), and the drain voltage (V C ) of MOS NM3 starts to rise. When it reaches the flip threshold of inverter INV2, the output VOUT jumps to low level. Bias current I3 is used to limit the current during the transition of inverter INV2, reducing power consumption.

[0046] When the voltage at signal input VIN just starts to jump from low to high, a small voltage will be coupled to B point through Z1, which may cause a short V A <V B , making the output VOUT misjudge. By adding inverter INV1 and MOS NM1, the voltage at B point can be pulled to GND when the signal input VIN is low, effectively solving the misjudgment of the voltage detection circuit caused by the step of signal input VIN.

[0047] Although the embodiments of the present application have been shown and described, it is to be understood that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present application, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A low-power, simple-structure voltage detection circuit, characterized in that: MOS transistor NM1, MOS transistor NM2, MOS transistor NM3, resistor R1, resistor R2, inverter INV1, inverter INV2, bias current I1, bias current I2, bias current I3 and voltage stabilizing diode Z1 are included; One end of the MOS transistor NM1 is electrically connected to the output end of the inverter INV1, and the positive electrode of the voltage stabilizing diode Z1 is also electrically connected to the other end of the MOS transistor NM1; The MOS transistor NM2 and the MOS transistor NM3 are electrically connected through one end pin, the other end pin of the MOS transistor NM2 is electrically connected with the resistor R1, the other end pin of the MOS transistor NM3 is electrically connected with the resistor R2, and the resistor R2 and the MOS transistor NM3 are provided with a connection point B, and the connection point B is electrically connected with one end pin of the MOS transistor NM1; The other end of the MOS transistor NM3 is provided with a connection point C, and the connection point C is electrically connected with the input end of the inverter INV2.

2. The low-power, simple-structure voltage detection circuit according to claim 1, characterized by: The input end of the inverter INV1 and the negative electrode of the voltage stabilizing diode Z1 are commonly electrically connected with the signal input end VIN to be detected, and the output end of the inverter INV2 is electrically connected with the output end VOUT of the detection result.

3. The low-power, simple-structure voltage detection circuit according to claim 1, characterized by: The MOS transistor NM2 and the MOS transistor NM3 are the same size, the gate and the drain of the MOS transistor NM2 are electrically connected, and the gate of the MOS transistor NM3 is electrically connected, which is the connection mode of the current mirror, and the gate voltage of the MOS transistor NM2 and the MOS transistor NM3 is equal.

4. The low-power, simple-structure voltage detection circuit according to claim 1, characterized by: The drain of the MOS transistor NM2 and the drain of the MOS transistor NM3 are electrically connected with one end of the bias current I1 and one end of the bias current I2 respectively, the source of the MOS transistor NM2 and the source of the MOS transistor NM3 are electrically connected with one end of the resistor R1 and one end of the resistor R2 respectively, and the other end of the resistor R1 and the other end of the resistor R2 are electrically connected with the ground end GND.

5. The low power consumption, simple structure voltage detection circuit according to claim 1, characterized in that: The input end of the inverter INV1 is connected with the signal input end VIN to be detected, the output end of the inverter INV1 is electrically connected with the gate of the MOS transistor NM1, the drain of the MOS transistor NM1 is electrically connected with the positive electrode of the voltage stabilizing diode Z1, the drain of the MOS transistor NM1 is electrically connected with one end of the resistor R2, the power supply end of the inverter INV1 is electrically connected with the power supply voltage input end VDD, and the ground end of the inverter INV1 and the source of the MOS transistor NM1 are electrically connected with the ground end GND.

6. The low power consumption, simple structure voltage detection circuit according to claim 1, characterized in that: The bias current I1, the bias current I2 and the bias current I3 flow into the MOS transistor NM2, the MOS transistor NM3 and the inverter INV2 from the power supply voltage input end VDD respectively, and the bias current I1, the bias current I2 and the bias current I3 are all nA level currents.

7. The low power consumption, simple structure voltage detection circuit according to claim 1, characterized in that: The bias current I1 and the bias current I2 are the same size, and the resistance value of the resistor R1 is greater than the resistance value of the resistor R2.

Images