Bandgap reference circuit

Abstract

The application provides a band gap reference circuit, which comprises a feedback type starting and biasing module, a negative temperature coefficient current generating module, a positive temperature coefficient current generating module and a reference voltage output module, the positive temperature coefficient current generated by the positive temperature coefficient current generating module comprises a first order term and a high order term of temperature, the negative temperature coefficient current generating module for generating the negative temperature coefficient current comprises a first order term and a high order term of temperature, the first order term of temperature in the positive temperature coefficient current and the first order term of temperature in the negative temperature coefficient current generating module offset each other, the high order term of temperature in the positive temperature coefficient current and the high order term of temperature in the negative temperature coefficient current generating module offset each other, the band gap reference voltage output by the reference voltage output module is subjected to first order temperature compensation and high order temperature compensation, and the temperature drift of the band gap reference voltage is effectively reduced; and a compensation current is introduced through a base current compensation module to perform current self-compensation on at least part of the triodes in the circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of microelectronics, in particular to a bandgap reference circuit. BACKGROUND

[0002] The bandgap reference circuit is an important module of modern analog integrated circuits and digital-analog hybrid integrated circuits, and its performance characteristics directly affect the performance of the entire circuit, which requires improving the performance characteristics of the bandgap reference circuit.

[0003] However, the conventional first-order bandgap reference circuit needs to use a transistor, and the basic idea is to obtain a reference voltage with zero temperature characteristics by weighting and adding the voltages generated by the current with a negative temperature coefficient and the current with a positive temperature coefficient on the resistor. Among them, since the base-emitter voltage V BE has nonlinearity, therefore, the output voltage of the conventional first-order bandgap reference circuit has the disadvantage of high temperature coefficient, which greatly limits the application of the conventional first-order bandgap reference circuit in high-precision systems.

[0004] Therefore, there is an urgent need for a high-order temperature compensation technical solution for the bandgap reference circuit. SUMMARY

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a bandgap reference circuit technical solution, which realizes low temperature drift of the reference output voltage in a wider temperature range by using high-order temperature compensation.

[0006] To achieve the above-mentioned objects and other related objects, the technical solution provided by the present application is as follows.

[0007] A bandgap reference circuit, comprising:

[0008] A feedback type starting and biasing module generates a first bias voltage, a second bias voltage and a third bias voltage;

[0009] A negative temperature coefficient current generating module is connected to the feedback type starting and biasing module and generates a negative temperature coefficient current under the action of the third bias voltage and a fourth bias voltage;

[0010] A positive temperature coefficient current generating module is connected to the feedback type starting and biasing module and the negative temperature coefficient current generating module, generates the fourth bias voltage, and generates a positive temperature coefficient current under the action of the first bias voltage, the second bias voltage, the third bias voltage and the fourth bias voltage in combination with the negative temperature coefficient current;

[0011] A reference voltage output module connected to the feedback type starting and biasing module, the negative temperature coefficient current generating module and the positive temperature coefficient current generating module, and generating a band gap reference voltage under the action of the third bias voltage and the fourth bias voltage in combination with the positive temperature coefficient current and the negative temperature coefficient current generating module.

[0012] Wherein, the positive temperature coefficient current includes a first order term and a high order term of temperature, the negative temperature coefficient current generating module includes a first order term and a high order term of temperature, the first order term of temperature in the positive temperature coefficient current and the first order term of temperature in the negative temperature coefficient current generating module offset each other, the high order term of temperature in the positive temperature coefficient current and the high order term of temperature in the negative temperature coefficient current generating module offset each other, and the band gap reference voltage is first order temperature compensated and high order temperature compensated.

[0013] Optionally, the feedback type start-up and bias module comprises a first PMOS, a second PMOS, a third PMOS, a fourth PMOS, a fifth PMOS, a sixth PMOS, a first NMOS, a second NMOS, a third NMOS, a fourth NMOS, a fifth NMOS, and a first resistor, a gate of the first PMOS is connected to the fourth bias voltage, a source of the first PMOS is connected to a working voltage, a drain of the first PMOS is connected to a source of the second PMOS, a gate of the second PMOS is connected to the third bias voltage, a drain of the second PMOS is connected to a drain of the first NMOS, a gate of the first NMOS is connected to the drain of the first NMOS and outputs the first bias voltage, a source of the first NMOS is connected to ground, a source of the third PMOS is connected to the working voltage, a gate of the third PMOS is connected to ground, a drain of the third PMOS is connected to a drain of the second NMOS, a gate of the second NMOS is connected to an enable signal, a source of the second NMOS is connected to a drain of the third NMOS, a gate of the third NMOS is connected to the gate of the first NMOS, a source of the third NMOS is connected to ground, the drain of the third NMOS outputs the second bias voltage, the gate of the third NMOS is connected to the first bias voltage, a source of the fourth PMOS is connected to the working voltage, a gate of the fourth PMOS is connected to a drain of the fourth PMOS and outputs the third bias voltage, the drain of the fourth PMOS is connected to a gate of the second PMOS, the drain of the fourth PMOS is connected to a drain of the fourth NMOS, a gate of the fourth NMOS is connected to a source of the second NMOS, a source of the fourth NMOS is connected to ground, a drain of the fifth NMOS is connected to the drain of the fourth NMOS, a gate of the fifth NMOS is connected to the gate of the first NMOS, a source of the fifth NMOS is connected to ground, a source of the fifth PMOS is connected to the working voltage, a drain of the fifth PMOS is connected to a source of the sixth PMOS, a gate of the fifth PMOS is connected to the gate of the first PMOS, a gate of the sixth PMOS is connected to the gate of the fourth PMOS, and the drain of the sixth PMOS is connected to ground through the first resistor in series.

[0014] Optionally, the negative temperature coefficient current generating module comprises a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a first PNP transistor and a second resistor, a source of the seventh PMOS transistor is connected to the working voltage, a gate of the seventh PMOS transistor is connected to a drain of the eighth PMOS transistor, a drain of the seventh PMOS transistor is connected to a source of the eighth PMOS transistor, a gate of the eighth PMOS transistor is connected to a drain of the fourth PMOS transistor, a drain of the eighth PMOS transistor is also connected to a drain of the sixth NMOS transistor, a source of the sixth NMOS transistor is connected to the ground through the second resistor in series, a source of the ninth PMOS transistor is connected to the working voltage, a gate of the ninth PMOS transistor is connected to a gate of the fifth PMOS transistor, a drain of the ninth PMOS transistor is connected to a source of the tenth PMOS transistor, a gate of the tenth PMOS transistor is connected to a drain of the fourth PMOS transistor, a drain of the tenth PMOS transistor is connected to a drain of the seventh NMOS transistor, a gate of the seventh NMOS transistor is connected to a gate of the sixth NMOS transistor, the gate of the seventh NMOS transistor is also connected to the drain of the seventh NMOS transistor, a source of the seventh NMOS transistor is connected to an emitter of the first PNP transistor, a base of the first PNP transistor is connected to a collector of the first PNP transistor, the collector of the first PNP transistor is connected to the ground, wherein the source of the sixth NMOS transistor outputs the negative temperature coefficient current.

[0015] Optionally, the positive temperature coefficient current generating module comprises an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a nineteenth PMOS tube, a twentieth PMOS tube, a second PNP transistor, a third PNP transistor, a fourth PNP transistor, a fifth PNP transistor, a third resistor, an operational amplifier and a positive temperature coefficient trimming unit, a source electrode of the eleventh PMOS tube is connected to the working voltage, a gate electrode of the eleventh PMOS tube is connected to a gate electrode of the first PMOS tube, a drain electrode of the eleventh PMOS tube is connected to a source electrode of the twelfth PMOS tube, a gate electrode of the twelfth PMOS tube is connected to a gate electrode of the second PMOS tube, a drain electrode of the twelfth PMOS tube is connected to a first input end of the positive temperature coefficient trimming unit, a source electrode of the thirteenth PMOS tube is connected to the working voltage, a gate electrode of the thirteenth PMOS tube is connected to a gate electrode of the seventh PMOS tube, a drain electrode of the thirteenth PMOS tube is connected to a source electrode of the fourteenth PMOS tube, a gate electrode of the fourteenth PMOS tube is connected to a gate electrode of the twelfth PMOS tube, a drain electrode of the fourteenth PMOS tube is connected to a second input end of the positive temperature coefficient trimming unit, the drain electrode of the fourteenth PMOS tube is also connected to an emitter electrode of the second PNP transistor, a base electrode of the second PNP transistor is connected to a collector electrode of the second PNP transistor, the collector electrode of the second PNP transistor is grounded, a source electrode of the fifteenth PMOS tube is connected to the working voltage, a gate electrode of the fifteenth PMOS tube is connected to a gate electrode of the seventh PMOS tube, a drain electrode of the fifteenth PMOS tube is connected to a source electrode of the sixteenth PMOS tube, a gate electrode of the sixteenth PMOS tube is connected to a gate electrode of the twelfth PMOS tube, a drain electrode of the sixteenth PMOS tube is connected to a third input end of the positive temperature coefficient trimming unit, the drain electrode of the sixteenth PMOS tube is also connected to an emitter electrode of the third PNP transistor, a base electrode of the third PNP transistor is connected to a collector electrode of the third PNP transistor, the collector electrode of the third PNP transistor is grounded, a source electrode of the seventeenth PMOS tube is connected to the working voltage, a gate electrode of the seventeenth PMOS tube is connected to a gate electrode of the first PMOS tube, a drain electrode of the seventeenth PMOS tube is connected to a source electrode of the eighteenth PMOS tube, a gate electrode of the eighteenth PMOS tube is connected to a gate electrode of the twelfth PMOS tube, a drain electrode of the eighteenth PMOS tube is connected to a non-inverting input end of the operational amplifier, the drain electrode of the eighteenth PMOS tube is also connected to an emitter electrode of the fourth PNP transistor through the third resistor in series, an emitter electrode of the fourth PNP transistor is connected to an emitter electrode of the second PNP transistor, a base electrode of the fourth PNP transistor is grounded, a source electrode of the nineteenth PMOS tube is connected to the working voltage, a gate electrode of the nineteenth PMOS tube is connected to a gate electrode of the first PMOS tube,The drain of the nineteenth PMOS tube is connected to the source of the twentieth PMOS tube, the gate of the twentieth PMOS tube is connected to the gate of the twelfth PMOS tube, the drain of the twentieth PMOS tube is connected to the inverting input of the operational amplifier, the output of the operational amplifier is connected to the gate of the first PMOS tube, and the drain of the twentieth PMOS tube is also connected to the emitter of the fifth PNP transistor, the base of the fifth PNP transistor is connected to the emitter of the third PNP transistor, and the collector of the fifth PNP transistor is grounded, wherein the drain of the eighteenth PMOS tube outputs the positive temperature coefficient current.

[0016] Optionally, the second input of the positive temperature coefficient trimming unit and the third input of the positive temperature coefficient trimming unit provide adjustable currents respectively to trim the temperature coefficient of the positive temperature coefficient current.

[0017] Optionally, the ratio of the emitter junction area of the second PNP transistor to the emitter junction area of the third PNP transistor is m:1, and the ratio of the emitter junction area of the fourth PNP transistor to the emitter junction area of the fifth PNP transistor is n:1, wherein m and n are integers greater than or equal to 1.

[0018] Optionally, the reference voltage output module comprises twenty-first, twenty-second, twenty-third, twenty-fourth PMOS tubes, a fourth resistor and a digital trimming unit, the source of the twenty-first PMOS tube is connected to the working voltage, the gate of the twenty-first PMOS tube is connected to the gate of the first PMOS tube, the drain of the twenty-first PMOS tube is connected to the source of the twenty-second PMOS tube, the gate of the twenty-second PMOS tube is connected to the gate of the second PMOS tube, the drain of the twenty-second PMOS tube is connected to the emitter of the first PNP transistor through the fourth resistor in series, the source of the twenty-third PMOS tube is connected to the working voltage, the gate of the twenty-third PMOS tube is connected to the gate of the first PMOS tube, the drain of the twenty-third PMOS tube is connected to the source of the twenty-fourth PMOS tube, the gate of the twenty-fourth PMOS tube is connected to the gate of the second PMOS tube, the drain of the twenty-fourth PMOS tube is connected to the input of the digital trimming unit, and the output of the digital trimming unit is connected to the drain of the twenty-second PMOS tube, wherein the drain of the twenty-second PMOS tube outputs the bandgap reference voltage.

[0019] Optionally, the control end of the digital trimming unit is connected to a multi-bit digital code, and the output current size of the output end of the digital trimming unit is adjusted and controlled by the multi-bit digital code.

[0020] Optionally, the bandgap reference circuit further comprises:

[0021] A base current compensation module is connected with the feedback type starting and biasing module, the negative temperature coefficient current generating module and the positive temperature coefficient current generating module. Under the action of the third bias voltage and the fourth bias voltage, the base current compensation module generates a compensation current with a size equal to the base current of the triode. The compensation current is used for current self-compensation of at least part of the triodes in the negative temperature coefficient current generating module, the positive temperature coefficient current generating module and the base current compensation module, so as to eliminate the influence of the current gain of the triode on the bandgap reference voltage.

[0022] Optionally, the base current compensation module comprises a twenty-fifth PMOS tube, a twenty-sixth PMOS tube, a twenty-seventh PMOS tube, a twenty-eighth PMOS tube, a twenty-ninth PMOS tube, a thirtieth PMOS tube, a thirty-first PMOS tube, an eighth NMOS tube, a ninth NMOS tube and a sixth PNP transistor, a source of the twenty-fifth PMOS tube is connected to the working voltage, a drain of the twenty-fifth PMOS tube is connected to an emitter of the fourth PNP transistor, a source of the twenty-sixth PMOS tube is connected to the working voltage, a gate of the twenty-sixth PMOS tube is connected to a gate of the twenty-fifth PMOS tube, a drain of the twenty-sixth PMOS tube is connected to an emitter of the fifth PNP transistor, a source of the twenty-seventh PMOS tube is connected to the working voltage, a gate of the twenty-seventh PMOS tube is connected to a drain of the twenty-seventh PMOS tube, a drain of the twenty-seventh PMOS tube is connected to a gate of the twenty-sixth PMOS tube, the drain of the twenty-seventh PMOS tube is also connected to a drain of the eighth NMOS tube, a source of the eighth NMOS tube is connected to the ground, a source of the twenty-eighth PMOS tube is connected to the working voltage, a gate of the twenty-eighth PMOS tube is connected to a gate of the twenty-seventh PMOS tube, a drain of the twenty-eighth PMOS tube is connected to an emitter of the sixth PNP transistor, a source of the twenty-ninth PMOS tube is connected to the working voltage, a gate of the twenty-ninth PMOS tube is connected to a gate of the twenty-seventh PMOS tube, a drain of the twenty-ninth PMOS tube is connected to an emitter of the first PNP transistor, a source of the thirtieth PMOS tube is connected to the working voltage, a gate of the thirtieth PMOS tube is connected to a gate of the first PMOS tube, a drain of the thirtieth PMOS tube is connected to a source of the thirty-first PMOS tube, a gate of the thirty-first PMOS tube is connected to a gate of the second PMOS tube, a drain of the thirty-first PMOS tube is connected to an emitter of the sixth PNP transistor, the base of the sixth PNP transistor outputs the compensation current.

[0023] As described above, the bandgap reference circuit provided by the application has at least the following beneficial effects:

[0024] The bandgap reference circuit is designed by combining the feedback type start and bias module, the positive temperature coefficient current generating module, the negative temperature coefficient current generating module and the reference voltage output module. The positive temperature coefficient current generated by the positive temperature coefficient current generating module includes the first order term and the high order term of temperature, the negative temperature coefficient current generated by the negative temperature coefficient current generating module includes the first order term and the high order term of temperature, the first order term of temperature in the positive temperature coefficient current and the first order term of temperature in the negative temperature coefficient current generating module offset each other, the high order term of temperature in the positive temperature coefficient current and the high order term of temperature in the negative temperature coefficient current generating module offset each other, the bandgap reference voltage output by the reference voltage output module is first order temperature compensated and high order temperature compensated, and the temperature drift of the bandgap reference voltage is effectively reduced. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 A traditional first order bandgap reference circuit is shown.

[0026] Figure 2 A structure block diagram of the bandgap reference circuit in the present application is shown.

[0027] Figure 3 A circuit diagram of the bandgap reference circuit in an optional embodiment of the present application is shown.

[0028] Figure 4 A circuit diagram of the operational amplifier A in the present application is shown. Figure 3

[0029] A circuit diagram of the positive temperature coefficient current generating module in the present application is shown. Figure 5 Figure 3 A circuit diagram of the positive temperature coefficient trimming unit in the positive temperature coefficient current generating module in the present application is shown.

[0030] Figure 6 Figure 3 A circuit diagram of the digital trimming unit in the reference voltage output module in the present application is shown.

[0031] Figure 7 A transient simulation diagram of the bandgap reference voltage output by the bandgap reference circuit in an optional embodiment of the present application is shown.

[0032] Figure 8 A simulation diagram of the relationship between the bandgap reference voltage and temperature output by the bandgap reference circuit in an optional embodiment of the present application is shown. DETAILED DESCRIPTION

[0033] The embodiments of the present application are described in detail by specific, concrete examples below, and other advantages and effects of the present application can be easily understood by those skilled in the art from the disclosure of the present specification. The present application can also be implemented or applied by other different specific embodiments, and each detail in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present application.​​

[0034] Reference is made to Figures 1 to 8 . It is to be noted that the drawings provided in the present embodiment only schematically illustrate the basic concept of the present application, and thus the drawings only show the components related to the present application, rather than being drawn according to the number, shape and size of the components in actual implementation. The shape, number and proportion of each component in actual implementation can be arbitrarily changed, and the layout pattern of the components can be more complicated. The structure, proportion and size shown in the drawings attached to the present specification are only used to cooperate with the content disclosed in the present specification, so as to be understood and read by those skilled in the art, and do not have technical substantive significance. Any modification of the structure, change of the proportional relationship or adjustment of the size, without affecting the effect and purpose that can be achieved by the present application, should still fall within the scope covered by the disclosed technical content of the present application.

[0035] As described in the background section, the inventors have found that, for a conventional first-order bandgap reference circuit as shown in Figure 1 , the basic idea is to obtain a reference voltage with zero temperature characteristic by weighting and adding the voltages generated by the resistors by the current with negative temperature coefficient and the current with positive temperature coefficient. In the circuit, the first resistor R1 and the second resistor R2 are made of the same material, the first PMOS transistor P1 and the third PMOS transistor P3 have the same channel width and length, the second PMOS transistor P2 and the fourth PMOS transistor P4 have the same channel width and length, the fifth PMOS transistor P5 and the seventh PMOS transistor P7 have the same channel width and length, the sixth PMOS transistor P6 and the eighth PMOS transistor P8 have the same channel width and length, the channel width and length ratio of the first PMOS transistor P1 and the second PMOS transistor P2 is α1 times that of the fifth PMOS transistor P5 and the sixth PMOS transistor P6, the channel width and length ratio of the ninth PMOS transistor P9 and the tenth PMOS transistor P10 is α2 times that of the fifth PMOS transistor P5 and the sixth PMOS transistor P6, the ratio of the emitter area of the first PNP transistor Q1 and the second PNP transistor Q2 is m:1, the ratio of the emitter area of the third PNP transistor Q3 and the fourth PNP transistor Q4 is n:1, and the influence of the current gain β of the transistor is ignored. Then, the difference between the base-emitter voltage of the first PNP transistor Q1 and the base-emitter voltage of the second PNP transistor Q2 can be expressed as:

[0036]

[0037] The difference between the base-emitter voltage of the third PNP transistor Q3 and the base-emitter voltage of the fourth PNP transistor Q4 can be expressed as:

[0038]

[0039] Due to the clamping of the operational amplifier A, the voltages of nodes a and b are equal, and the current flowing through the first resistor R1 can be represented as:

[0040]

[0041] The bandgap reference voltage can be represented as:

[0042] However, due to the base-emitter voltage V BE,Q5 has nonlinearity, therefore, the output voltage of the conventional first-order bandgap reference circuit has the disadvantage of high temperature coefficient, making the bandgap reference voltage V REF output by the conventional first-order bandgap reference circuit has a large temperature drift, which greatly limits its application in high-precision systems. At the same time, due to the difference in the emitter area of the first PNP transistor Q1, the second PNP transistor Q2, the third PNP transistor Q3, the fourth PNP transistor Q4 and the fifth PNP transistor Q5, the corresponding current gain β will be different, and in the standard CMOS process, due to the small current gain β of the transistor, the base current of the third PNP transistor Q3 and the fourth PNP transistor Q4 will bring errors to the emitter current of the first PNP transistor Q1 and the second PNP transistor Q2, and further bring errors to the bandgap reference voltage V REF output finally.

[0043] Based on this, the present application provides a bandgap reference circuit technical scheme, which realizes low temperature drift of the reference output voltage in a wider temperature range by using high-order temperature compensation.

[0044] As shown in Figure 2 , the present application provides a bandgap reference circuit, which comprises:

[0045] a feedback-type starting and biasing module for generating a first biasing voltage Vb1, a second biasing voltage Vb2 and a third biasing voltage Vb3;

[0046] a negative temperature coefficient current generating module connected to the feedback-type starting and biasing module, for generating a negative temperature coefficient current I c under the action of the third biasing voltage Vb3 and a fourth biasing voltage Vb4;

[0047] a positive temperature coefficient current generating module connected to the feedback-type starting and biasing module and the negative temperature coefficient current generating module, for generating the fourth biasing voltage Vb4, and generating a positive temperature coefficient current I p under the action of the first biasing voltage Vb1, the second biasing voltage Vb2, the third biasing voltage Vb3 and the fourth biasing voltage Vb4, in combination with the negative temperature coefficient current Ic;

[0048] The reference voltage output module, the feedback type starting and biasing module, the negative temperature coefficient current generating module and the positive temperature coefficient current generating module generate the band gap reference voltage V p under the action of the third bias voltage Vb3 and the fourth bias voltage Vb4, in combination with the positive temperature coefficient current I REF ;

[0049] The positive temperature coefficient current I p includes the first order term and the high order term of temperature, the negative temperature coefficient current generating module includes the first order term and the high order term of temperature, the positive temperature coefficient current I p The first order term of temperature in the positive temperature coefficient current I p The high order term of temperature in the positive temperature coefficient current I REF The high order term of temperature in the positive temperature coefficient current I REF performs the first order temperature compensation and the high order temperature compensation on the band gap reference voltage V REF .

[0050] In detail, in an optional example of the present application, as Figure 3As shown, the feedback type start-up and bias module comprises a first PMOS P1, a second PMOS P2, a third PMOS P3, a fourth PMOS P4, a fifth PMOS P5, a sixth PMOS P6, a first NMOS N1, a second NMOS N2, a third NMOS N3, a fourth NMOS N4, a fifth NMOS N5, and a first resistor R1. The gate of the first PMOS P1 is connected to a fourth bias voltage Vb4, the source of the first PMOS P1 is connected to a working voltage VDD, the drain of the first PMOS P1 is connected to the source of the second PMOS P2, the gate of the second PMOS P2 is connected to a third bias voltage Vb3, the drain of the second PMOS P2 is connected to the drain of the first NMOS N1, the gate of the first NMOS N1 is connected to the drain of the first NMOS N1 and outputs a first bias voltage Vb1, the source of the first NMOS N1 is connected to ground GND, the source of the third PMOS P3 is connected to the working voltage VDD, the gate of the third PMOS P3 is connected to ground, the drain of the third PMOS P3 is connected to the drain of the second NMOS N2, the gate of the second NMOS N2 is connected to an enable signal EN, the source of the second NMOS N2 is connected to the drain of the third NMOS N3, the gate of the third NMOS N3 is connected to the gate of the first NMOS N1, the source of the third NMOS N3 is connected to ground GND, the drain of the third NMOS N3 outputs a second bias voltage Vb2, the gate of the third NMOS N3 is connected to the first bias voltage Vb1, the source of the fourth PMOS P4 is connected to the working voltage VDD, the gate of the fourth PMOS P4 is connected to the drain of the fourth PMOS P4 and outputs the third bias voltage Vb3, the drain of the fourth PMOS P4 is connected to the gate of the second PMOS P2, the drain of the fourth PMOS P4 is connected to the drain of the fourth NMOS N4, the gate of the fourth NMOS N4 is connected to the source of the second NMOS N2, the source of the fourth NMOS N4 is connected to ground GND, the drain of the fifth NMOS N5 is connected to the drain of the fourth NMOS N4, the gate of the fifth NMOS N5 is connected to the gate of the first NMOS N1, the source of the fifth NMOS N5 is connected to ground GND, the source of the fifth PMOS P5 is connected to the working voltage VDD, the drain of the fifth PMOS P5 is connected to the source of the sixth PMOS P6, the gate of the fifth PMOS P5 is connected to the gate of the first PMOS P1, the gate of the sixth PMOS P6 is connected to the gate of the fourth PMOS P4, and the drain of the sixth PMOS P6 is connected to ground GND through the first resistor R1 in series.

[0051] In detail, in an optional example of the present application, as shown in Figure 3As shown, the negative temperature coefficient current generating module comprises a seventh PMOS transistor P7, an eighth PMOS transistor P8, a ninth PMOS transistor P9, a tenth PMOS transistor P10, a sixth NMOS transistor N6, a seventh NMOS transistor N7, a first PNP transistor Q1 and a second resistor R2, a source of the seventh PMOS transistor P7 is connected to a working voltage VDD, a gate of the seventh PMOS transistor P7 is connected to a drain of the eighth PMOS transistor P8, a drain of the seventh PMOS transistor P7 is connected to a source of the eighth PMOS transistor P8, a gate of the eighth PMOS transistor P8 is connected to a drain of the fourth PMOS transistor P4, a drain of the eighth PMOS transistor P8 is also connected to a drain of the sixth NMOS transistor N6, a source of the sixth NMOS transistor N6 is connected to the ground GND through the second resistor R2 in series, a source of the ninth PMOS transistor P9 is connected to the working voltage VDD, a gate of the ninth PMOS transistor P9 is connected to a gate of the fifth PMOS transistor P5, a drain of the ninth PMOS transistor P9 is connected to a source of the tenth PMOS transistor P10, a gate of the tenth PMOS transistor P10 is connected to the drain of the fourth PMOS transistor P4, a drain of the tenth PMOS transistor P10 is connected to a drain of the seventh NMOS transistor N7, a gate of the seventh NMOS transistor N7 is connected to a gate of the sixth NMOS transistor N6, the gate of the seventh NMOS transistor N7 is also connected to the drain of the seventh NMOS transistor N7, a source of the seventh NMOS transistor N7 is connected to an emitter of the first PNP transistor Q1, a base of the first PNP transistor Q1 is connected to a collector of the first PNP transistor Q1, the collector of the first PNP transistor Q1 is connected to the ground GND, wherein a source of the sixth NMOS transistor N6 outputs a negative temperature coefficient current I8 (i.e. Figure 2 the negative temperature coefficient current I c ) in the formula (1).

[0052] In detail, in an optional example of the present application, as Figure 3As shown, the positive temperature coefficient current generating module includes eleventh PMOS tube P11, twelfth PMOS tube P12, thirteenth PMOS tube P13, fourteenth PMOS tube P14, fifteenth PMOS tube P15, sixteenth PMOS tube P16, seventeenth PMOS tube P17, eighteenth PMOS tube P18, nineteenth PMOS tube P19, twentieth PMOS tube P20, second PNP transistor Q2, third PNP transistor Q3, fourth PNP transistor Q4, fifth PNP transistor Q5, third resistor R3, operational amplifier A and positive temperature coefficient trimming unit, the source electrode of the eleventh PMOS tube P11 is connected with working voltage VDD, the gate electrode of the eleventh PMOS tube P11 is connected with the gate electrode of the first PMOS tube P1, the drain electrode of the eleventh PMOS tube P11 is connected with the source electrode of the twelfth PMOS tube P12, the gate electrode of the twelfth PMOS tube P12 is connected with the gate electrode of the second PMOS tube P2, the drain electrode of the twelfth PMOS tube P12 is connected with the first input end c of the positive temperature coefficient trimming unit, the source electrode of the thirteenth PMOS tube P13 is connected with working voltage VDD, the gate electrode of the thirteenth PMOS tube P13 is connected with the gate electrode of the seventh PMOS tube P7, the drain electrode of the thirteenth PMOS tube P13 is connected with the source electrode of the fourteenth PMOS tube P14, the gate electrode of the fourteenth PMOS tube P14 is connected with the gate electrode of the twelfth PMOS tube P12, the drain electrode of the fourteenth PMOS tube P14 is connected with the second input end of the positive temperature coefficient trimming unit, the drain electrode of the fourteenth PMOS tube P14 is also connected with the emitter electrode of the second PNP transistor Q2, the base electrode of the second PNP transistor Q2 is connected with the collector electrode of the second PNP transistor Q2, the collector electrode of the second PNP transistor Q2 is connected with ground GND, the source electrode of the fifteenth PMOS tube P15 is connected with working voltage VDD, the gate electrode of the fifteenth PMOS tube P15 is connected with the gate electrode of the seventh PMOS tube P7, the drain electrode of the fifteenth PMOS tube P15 is connected with the source electrode of the sixteenth PMOS tube P16, the gate electrode of the sixteenth PMOS tube P16 is connected with the gate electrode of the twelfth PMOS tube P12, the drain electrode of the sixteenth PMOS tube P16 is connected with the third input end of the positive temperature coefficient trimming unit, the drain electrode of the sixteenth PMOS tube P16 is also connected with the emitter electrode of the third PNP transistor Q3, the base electrode of the third PNP transistor Q3 is connected with the collector electrode of the third PNP transistor Q3, the collector electrode of the third PNP transistor Q3 is connected with ground GND, the source electrode of the seventeenth PMOS tube P17 is connected with working voltage VDD, the gate electrode of the seventeenth PMOS tube P17 is connected with the gate electrode of the first PMOS tube P1, the drain electrode of the seventeenth PMOS tube P17 is connected with the source electrode of the eighteenth PMOS tube P18, the gate electrode of the eighteenth PMOS tube P18 is connected with the gate electrode of the twelfth PMOS tube P12, the drain electrode of the eighteenth PMOS tube P18 is connected with the non-inverting input end of the operational amplifier A, the drain electrode of the eighteenth PMOS tube P18 is also connected with the emitter electrode of the fourth PNP transistor Q4 after passing through the third resistor R3 in series, the base electrode of the fourth PNP transistor Q4 is connected with the emitter electrode of the second PNP transistor Q2,The collector of the fourth PNP transistor Q4 is connected to the ground GND, the source of the nineteenth PMOS transistor P19 is connected to the working voltage VDD, the gate of the nineteenth PMOS transistor P19 is connected to the gate of the first PMOS transistor P1, the drain of the nineteenth PMOS transistor P19 is connected to the source of the twentieth PMOS transistor P20, the gate of the twentieth PMOS transistor P20 is connected to the gate of the twelfth PMOS transistor P12, the drain of the twentieth PMOS transistor P20 is connected to the inverting input of the operational amplifier A, the output of the operational amplifier A is connected to the gate of the first PMOS transistor P1, and the drain of the twentieth PMOS transistor P20 is also connected to the emitter of the fifth PNP transistor Q5, the base of the fifth PNP transistor Q5 is connected to the emitter of the third PNP transistor Q3, and the collector of the fifth PNP transistor Q5 is connected to the ground GND, wherein the drain of the eighteenth PMOS transistor P18 outputs the positive temperature coefficient current I1 (i.e. Figure 2 the positive temperature coefficient current I p ) in the formula (1).

[0053] The second input of the positive temperature coefficient trimming unit and the third input of the positive temperature coefficient trimming unit respectively provide the adjustable currents I6 and I7 to trim the temperature coefficient of the positive temperature coefficient current I1, the ratio of the emitter junction area of the second PNP transistor Q2 to the emitter junction area of the third PNP transistor Q3 is m:1, and the ratio of the emitter junction area of the fourth PNP transistor Q4 to the emitter junction area of the fifth PNP transistor Q5 is n:1, wherein m and n are integers greater than or equal to 1.

[0054] In detail, in an optional example of the present application, as Figure 3As shown, the reference voltage output module comprises the twenty-first PMOS P21, the twenty-second PMOS P22, the twenty-third PMOS P23, the twenty-fourth PMOS P24, the fourth resistor R4 and the digital trimming unit, the source of the twenty-first PMOS P21 is connected with the working voltage VDD, the gate of the twenty-first PMOS P21 is connected with the gate of the first PMOS P1, the drain of the twenty-first PMOS P21 is connected with the source of the twenty-second PMOS P22, the gate of the twenty-second PMOS P22 is connected with the gate of the second PMOS P2, the drain of the twenty-second PMOS P22 is connected with the emitter of the first PNP transistor Q1 through the fourth resistor R4 in series, the source of the twenty-third PMOS P23 is connected with the working voltage VDD, the gate of the twenty-third PMOS P23 is connected with the gate of the first PMOS P1, the drain of the twenty-third PMOS P23 is connected with the source of the twenty-fourth PMOS P24, the gate of the twenty-fourth PMOS P24 is connected with the gate of the second PMOS P2, the drain of the twenty-fourth PMOS P24 is connected with the input end d of the digital trimming unit, and the output end of the digital trimming unit is connected with the drain of the twenty-second PMOS P22, wherein the drain of the twenty-second PMOS P22 outputs the bandgap reference voltage V REF .

[0055] The drain of the twenty-second PMOS P22 outputs the current I9, and the output end of the digital trimming unit outputs the current I 10 The control end of the digital trimming unit is connected with the multi-bit digital code, and the multi-bit digital code adjusts and controls the size of the output current I 10 of the output end of the digital trimming unit.

[0056] In detail, as shown in the figure, Figures 2-3 The bandgap reference circuit further comprises:

[0057] The base current compensation module is connected with the feedback type starting and biasing module, the negative temperature coefficient current generating module and the positive temperature coefficient current generating module, and under the action of the third bias voltage Vb3 and the fourth bias voltage Vb4, generates a compensation current with a size equal to the base current of the transistor, and the compensation current is used for performing current self-compensation on at least part of the transistors in the negative temperature coefficient current generating module, the positive temperature coefficient current generating module and the base current compensation module, so as to eliminate the influence of the current gain of the transistor on the bandgap reference voltage.

[0058] In detail, in an optional example of the present application, as shown in the figure, Figure 3As shown, the base current compensation module includes the twenty-fifth PMOS tube P25, the twenty-sixth PMOS tube P26, the twenty-seventh PMOS tube P27, the twenty-eighth PMOS tube P28, the twenty-ninth PMOS tube P29, the thirtieth PMOS tube P30, the thirty-first PMOS tube P31, the eighth NMOS tube N8, the ninth NMOS tube N9, and the sixth PNP transistor Q6, the source of the twenty-fifth PMOS tube P25 is connected to the working voltage VDD, the drain of the twenty-fifth PMOS tube P25 is connected to the emitter of the fourth PNP transistor Q4, the source of the twenty-sixth PMOS tube P26 is connected to the working voltage VDD, the gate of the twenty-sixth PMOS tube P26 is connected to the gate of the twenty-fifth PMOS tube P25, the drain of the twenty-sixth PMOS tube P26 is connected to the emitter of the fifth PNP transistor Q5, the source of the twenty-seventh PMOS tube P27 is connected to the working voltage VDD, the gate of the twenty-seventh PMOS tube P27 is connected to the drain of the twenty-seventh PMOS tube P27, the drain of the twenty-seventh PMOS tube P27 is connected to the gate of the twenty-sixth PMOS tube P26, the drain of the twenty-seventh PMOS tube P27 is also connected to the drain of the eighth NMOS tube N8, the source of the eighth NMOS tube N8 is connected to the ground GND, the source of the twenty-eighth PMOS tube P28 is connected to the working voltage VDD, the gate of the twenty-eighth PMOS tube P28 is connected to the gate of the twenty-seventh PMOS tube P27, the drain of the twenty-eighth PMOS tube P28 is connected to the emitter of the sixth PNP transistor Q6, the source of the twenty-ninth PMOS tube P29 is connected to the working voltage VDD, the gate of the twenty-ninth PMOS tube P29 is connected to the gate of the twenty-seventh PMOS tube P27, the drain of the twenty-ninth PMOS tube P29 is connected to the emitter of the first PNP transistor Q1, the source of the thirtieth PMOS tube P30 is connected to the working voltage VDD, the gate of the thirtieth PMOS tube P30 is connected to the gate of the first PMOS tube P1, the drain of the thirtieth PMOS tube P30 is connected to the source of the thirty-first PMOS tube P31, the gate of the thirty-first PMOS tube P31 is connected to the gate of the second PMOS tube P2, the drain of the thirty-first PMOS tube P31 is connected to the emitter of the sixth PNP transistor Q6, the base of the sixth PNP transistor Q6 is connected to the drain of the ninth NMOS tube N9, the collector of the sixth PNP transistor Q6 is connected to the ground GND, the gate of the ninth NMOS tube N9 is connected to the drain of the ninth NMOS tube N9, the gate of the ninth NMOS tube N9 is also connected to the gate of the eighth NMOS tube N8, the source of the ninth NMOS tube N9 is connected to the ground GND, wherein the base of the sixth PNP transistor Q6 outputs a compensation current (not shown in the figure).

[0059] In more detail, as Figures 2-3As shown, the present application adopts a feedback type start-up and bias module and a positive temperature coefficient current generation module to generate a closed loop feedback, so that the bandgap reference circuit can get rid of the degenerate bias point and quickly stabilize the output at power-up. The first bias voltage Vb1 generated is used as the bias voltage of the operational amplifier A; the second bias voltage Vb2 is low after the start-up is completed; the third bias voltage Vb3 and the fourth bias voltage Vb4 generated by the output of the operational amplifier are respectively used as the bias voltages of the positive temperature coefficient current generation module, the base current compensation module, the negative temperature coefficient current generation module and the reference voltage output module.

[0060] In more detail, as shown in Figures 2-3 In order to overcome the error caused by the current gain β of the transistor, the present application adopts a base current compensation module, the principle of which is to introduce a compensation current whose size is equal to the base current of the transistor, so that the collector current flowing through the transistor is stable and completely equal. The present application generates a base current through the sixth PNP transistor Q6, replicates the base current by using the good current replication capability of the current mirror, obtains compensation currents, and performs current self-compensation on the fourth PNP transistor Q4, the fifth PNP transistor Q5, the sixth PNP transistor Q6 and the first PNP transistor Q1 by using the compensation currents, so as to eliminate the influence of the current gain β of the transistor on the output bandgap reference voltage V REF .

[0061] Among them, the channel width-length ratios of the thirteenth PMOS tube P13 and the fourteenth PMOS tube P14 are α1 times of the channel width-length ratios of the seventh PMOS tube P7 and the eighth PMOS tube P8, the channel width-length ratios of the fifteenth PMOS tube P15 and the sixteenth PMOS tube P16 are α2 times of the channel width-length ratios of the seventh PMOS tube P7 and the eighth PMOS tube P8, and the channel width-length ratios of the twenty-first PMOS tube P21 and the twenty-second PMOS tube P22 are α3 times of the channel width-length ratios of the seventeenth PMOS tube P17 and the eighteenth PMOS tube P18. Then, due to the mirror replication effect of the corresponding current mirror, the sizes of the current I3 flowing through the thirteenth PMOS tube P13 and the current I4 flowing through the fifteenth PMOS tube P15 are α1 and α2 times of the size of the current I8 flowing through the seventh PMOS tube P7, and the current I9 flowing through the twenty-first PMOS tube P21 is α3 times of the current I1 flowing through the seventeenth PMOS tube P17, that is, I3 = α1I8, I4 = α2I8, and I9 = α3I1.

[0062] In more detail, as shown in Figure 3 The current I8 can be expressed as which exhibits a negative temperature coefficient, so the current I3 flowing through the thirteenth PMOS tube P13 and the current I4 flowing through the fifteenth PMOS tube P15 exhibit a negative temperature coefficient.

[0063] When the transistor is positively biased, its base-emitter voltage can be expressed as

[0064] Due to the compensation effect of the base current, the collector currents of the fourth PNP transistor Q4 and the fifth PNP transistor Q5 are I1, and the collector currents of the second PNP transistor Q2 and the third PNP transistor Q3 are I3-I6-I B4 , I4-I7-I B5 , I4-I7-I B4 , I4-I7-I B5 , I4-I7-I NL , I4-I7-I

[0065] Therefore, the difference between the base-emitter voltages of the fourth PNP transistor Q4 and the fifth PNP transistor Q5 can be expressed as:

[0066]

[0067] The difference between the base-emitter voltages of the second PNP transistor Q2 and the third PNP transistor Q3 can be expressed as:

[0068]

[0069] Assuming I6=k1I1, I7=k2I1 (0<k1<1, 0<k2<1), and I B4 =I B5 =I1 / β, let then

[0070] (assuming α1<α2)

[0071] Since I1 is a positive temperature coefficient current, I8 is a negative temperature coefficient current, and η varies with temperature.

[0072] I1 can be expressed as which exhibits a positive temperature coefficient.

[0073] Since Therefore, the positive temperature coefficient current I1 can be expressed as:

[0074]

[0075] Since I9=α3I1, the output bandgap reference voltage can be expressed as:

[0076]

[0077] where, η is related to temperature T, and V NL is a high-order term of temperature T.

[0078] because V BE The temperature coefficient is temperature-dependent and contains higher-order temperature terms. Meanwhile, V BE The temperature coefficient also contains a first-order term related to temperature. Therefore, by selecting and adjusting the parameters, the first-order term related to temperature in the positive temperature coefficient current I1 can be optimized. or With V BE,Q1 The first-order terms related to temperature cancel each other out, which allows the higher-order terms related to temperature in the positive temperature coefficient current I1 to be reduced. Or V NL With V BE,Q1 The higher-order terms related to temperature cancel each other out, affecting the bandgap reference voltage V. REF Performing first-order and higher-order temperature compensation reduces the bandgap reference voltage V. REF Temperature drift.

[0079] More specifically, in an optional embodiment of the present invention, the circuit structure of operational amplifier A in the positive temperature coefficient current generation module is as follows: Figure 4 As shown, it includes NMOS transistors N01 to N07 and PMOS transistors P01 to P04. (As...) Figure 4 As shown, operational amplifier A adopts a common-source, common-gate structure, which improves the output impedance of operational amplifier A. The bias voltage of operational amplifier A consists of the first bias voltage Vb1 and the second bias voltage Vb2 generated by the feedback-type startup and bias module, as well as the externally provided enable signal EN. The gate of NMOS transistor N01 is the non-inverting input Vip of operational amplifier A, the gate of NMOS transistor N02 is the inverting input Vin of operational amplifier A, and the drain of PMOS transistor P04 is the output Vout of operational amplifier A.

[0080] More specifically, in an optional embodiment of the present invention, the circuit structure of the positive temperature coefficient adjustment unit in the positive temperature coefficient current generation module is as follows: Figure 5 As shown, it includes NMOS transistors N10-N58, inverters, AND gates, and OR gates. The inverters, AND gates, and OR gates form a logic operation circuit. The NMOS transistors N10-N58 form multiple parallel current mirror switching selection units. The input terminal of the current mirror is the first input terminal c of the positive temperature coefficient adjustment unit. Figure 3The channel width-length ratio of the eleventh PMOS transistor P11 and the twelfth PMOS transistor P12 is α4 times that of the seventeenth PMOS transistor P17 and the eighteenth PMOS transistor P18, α4 is less than 1, then the mirror-reduced current of the input current I1 of the current mirror, each current mirror switching selection unit has two output ends, the first output ends of each current mirror switching selection unit are connected in parallel and serve as the second input ends of the positive temperature coefficient trimming unit, the input current I6=N×IB0, the second output ends of each current mirror switching selection unit are connected in parallel and serve as the third input ends of the positive temperature coefficient trimming unit, the input current I7=N×IB1, each current mirror switching selection unit corresponds to a logic operation circuit unit, the input ends of the logic operation circuit unit are connected to the digital code B3B2B1B0, the output ends of the logic operation circuit unit output two opposite control signals, the first output end or the second output end of each current mirror switching selection unit is controlled to output through the two opposite control signals, and the operation logic of each logic operation circuit unit is different, therefore, the sizes of the currents I6 and I7 can be changed by changing the digital code B3B2B1B0, and then the size of η is changed, so as to trim the positive temperature coefficient.

[0081] The current flowing through the eleventh PMOS transistor P11 is equal to the sum of the currents I6 and I7 flowing through the positive temperature coefficient trimming unit, the width-length ratios of the NMOS transistors N10-N58 can be set arbitrarily, for example, the width-length ratio of the MOS transistor N10 is 16 times that of the MOS transistor N11, the MOS transistors N11-N26 are completely the same, and the MOS transistors N27-N58 are completely the same.

[0082] It should be noted that the circuit structure of the positive temperature coefficient trimming unit is not limited to that shown in Figure 5 , but can also have other numbers and other structures of current mirror switching selection units, and the width-length ratios of the corresponding NMOS transistors can be adjusted accordingly, which is not limited herein.

[0083] In more detail, in an optional embodiment of the present application, the circuit structure of the digital trimming unit in the reference voltage output module is as shown in Figure 6 , which includes PMOS transistors N33-P48, the current flowing through the twenty-third PMOS transistor P23 is equal to the sum of the currents I 10 and I 11 in Figure 6 . Figure 3 In the twenty-third PMOS transistor P23 and the twenty-fourth PMOS transistor P24, the channel width-length ratios are α5 times that of the seventeenth PMOS transistor P17 and the eighteenth PMOS transistor P18, respectively; at the same time, the width-length ratios of the PMOS transistors P33-P40 are 1:1:2:4:8:16:32:64, then the current I 10 can be represented as:

[0084]

[0085] Wherein, D6D5D4D3D2D1 is a digital code.

[0086] The current I 10 can be changed by adjusting the digital code D6D5D4D3D2D1, the current I 10 is superimposed with the current I I9 and then applied to the fourth resistor R4, the size of the current I 10 is changed, that is, the size of the bandgap reference voltage V REF is changed, and the digital adjustment of the bandgap reference voltage V REF is realized.

[0087] In order to further verify the above advantages of the bandgap reference circuit of the present application, in an optional embodiment of the present application, a circuit is constructed and simulated, the transient simulation diagram of the bandgap reference voltage thereof is shown in Figure 7 , the simulation diagram of the relationship between the bandgap reference voltage and temperature is shown in Figure 8 . As shown in Figure 7 , when the power is powered on, the bandgap reference voltage is quickly stabilized, and the stable voltage is 1.22V; as shown in Figure 8 , in the temperature range of-50℃ to 100℃, the change of the bandgap reference voltage is about 0.2mV, and the temperature coefficient is about 0.9ppm / ℃.

[0088] In summary, in the bandgap reference circuit provided by the application, the structure design of the feedback type starting and biasing module, the negative temperature coefficient current generating module, the positive temperature coefficient current generating module, the reference voltage output module and the base current compensation module is combined, the positive temperature coefficient current generated by the positive temperature coefficient current generating module includes the first order term and the high order term of temperature, the negative temperature coefficient current generating module generating the negative temperature coefficient current includes the first order term and the high order term of temperature, the first order term of temperature in the positive temperature coefficient current and the first order term of temperature in the negative temperature coefficient current generating module offset each other, the high order term of temperature in the positive temperature coefficient current and the high order term of temperature in the negative temperature coefficient current generating module offset each other, the bandgap reference voltage output by the reference voltage output module is first order temperature compensated and high order temperature compensated, and the temperature drift of the bandgap reference voltage is effectively reduced; the multiple bias voltages provided by the feedback type starting and biasing module are used to realize the rapid starting of the whole circuit, so that the bandgap reference circuit is out of the degenerate bias point at power-on and rapidly and stably outputs; through the base current compensation module, a compensation current equal to the base current of the transistor is introduced, the mirror copied compensation current is used for current self-compensation of at least part of the transistors in the negative temperature coefficient current generating module, the positive temperature coefficient current generating module and the base current compensation module, and the influence of the current gain of the transistor on the output bandgap reference voltage is effectively eliminated; through the digital trimming unit in the reference voltage output gate, the trimming of the bandgap reference voltage is realized, the deviation between the actual output and the theoretical design output caused by the error of the manufacturing process is effectively compensated and corrected, and the precision of the output bandgap reference voltage is improved.

[0089] The above embodiments only exemplarily illustrate the principles and effects of the application, and are not used to limit the application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought of the application should be covered by the claims of the application.

Claims

1. A bandgap reference circuit, characterized in that, include: The feedback-type startup and bias module generates a first bias voltage, a second bias voltage, and a third bias voltage; The negative temperature coefficient current generating module is connected to the feedback-type start-up and bias module, and generates a negative temperature coefficient current under the action of the third bias voltage and the fourth bias voltage. A positive temperature coefficient current generating module is connected to the feedback-type start-up and bias module and the negative temperature coefficient current generating module to generate the fourth bias voltage. Under the action of the first bias voltage, the second bias voltage, the third bias voltage and the fourth bias voltage, a positive temperature coefficient current is generated in combination with the negative temperature coefficient current. The reference voltage output module is connected to the feedback-type start-up and bias module, the negative temperature coefficient current generation module and the positive temperature coefficient current generation module. Under the action of the third bias voltage and the fourth bias voltage, it generates a bandgap reference voltage in combination with the positive temperature coefficient current and the negative temperature coefficient current generation module. The positive temperature coefficient current includes a first-order term and a higher-order term of temperature, and the negative temperature coefficient current generating module includes a first-order term and a higher-order term of temperature. The first-order term of temperature in the positive temperature coefficient current cancels out the first-order term of temperature in the negative temperature coefficient current generating module, and the higher-order term of temperature in the positive temperature coefficient current cancels out the higher-order term of temperature in the negative temperature coefficient current generating module, thereby performing first-order temperature compensation and higher-order temperature compensation on the bandgap reference voltage. The feedback-type startup and bias module includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a first resistor. The gate of the first PMOS transistor is connected to the fourth bias voltage, the source of the first PMOS transistor is connected to the operating voltage, the drain of the first PMOS transistor is connected to the source of the second PMOS transistor, and the gate of the second PMOS transistor is connected to the third bias voltage. The drain of the OS transistor is connected to the drain of the first NMOS transistor. The gate of the first NMOS transistor is connected to the drain of the first NMOS transistor and outputs the first bias voltage. The source of the first NMOS transistor is grounded. The source of the third PMOS transistor is connected to the operating voltage. The gate of the third PMOS transistor is grounded. The drain of the third PMOS transistor is connected to the drain of the second NMOS transistor. The gate of the second NMOS transistor is connected to an enable signal. The source of the second NMOS transistor is connected to the drain of the third NMOS transistor. The gate of the third NMOS transistor is connected to the gate of the first NMOS transistor. The source of the third NMOS transistor is grounded, the drain of the third NMOS transistor outputs the second bias voltage, and the gate of the third NMOS transistor is connected to the first bias voltage. The source of the fourth PMOS transistor is connected to the operating voltage, the gate of the fourth PMOS transistor is connected to the drain of the fourth PMOS transistor and outputs the third bias voltage, the drain of the fourth PMOS transistor is connected to the gate of the second PMOS transistor, the drain of the fourth PMOS transistor is connected to the drain of the fourth NMOS transistor, and the gate of the fourth NMOS transistor is connected to the source of the second NMOS transistor. The source of the NMOS transistor is grounded, the drain of the fifth NMOS transistor is connected to the drain of the fourth NMOS transistor, the gate of the fifth NMOS transistor is connected to the gate of the first NMOS transistor, the source of the fifth NMOS transistor is grounded, the source of the fifth PMOS transistor is connected to the operating voltage, the drain of the fifth PMOS transistor is connected to the source of the sixth PMOS transistor, the gate of the fifth PMOS transistor is connected to the gate of the first PMOS transistor, the gate of the sixth PMOS transistor is connected to the gate of the fourth PMOS transistor, and the drain of the sixth PMOS transistor is grounded after being connected in series with the first resistor. The negative temperature coefficient current generating module includes a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a first PNP transistor, and a second resistor. The source of the seventh PMOS transistor is connected to the operating voltage, the gate of the seventh PMOS transistor is connected to the drain of the eighth PMOS transistor, the drain of the seventh PMOS transistor is connected to the source of the eighth PMOS transistor, the gate of the eighth PMOS transistor is connected to the drain of the fourth PMOS transistor, the drain of the eighth PMOS transistor is also connected to the drain of the sixth NMOS transistor, the source of the sixth NMOS transistor is grounded through the second resistor connected in series, and the source of the ninth PMOS transistor is connected to the operating voltage. The gate of the MOS transistor is connected to the gate of the fifth PMOS transistor, the drain of the ninth PMOS transistor is connected to the source of the tenth PMOS transistor, the gate of the tenth PMOS transistor is connected to the drain of the fourth PMOS transistor, the drain of the tenth PMOS transistor is connected to the drain of the seventh NMOS transistor, the gate of the seventh NMOS transistor is connected to the gate of the sixth NMOS transistor, the gate of the seventh NMOS transistor is also connected to the drain of the seventh NMOS transistor, the source of the seventh NMOS transistor is connected to the emitter of the first PNP transistor, the base of the first PNP transistor is connected to the collector of the first PNP transistor, and the collector of the first PNP transistor is grounded. The source of the sixth NMOS transistor outputs the negative temperature coefficient current. The positive temperature coefficient current generation module includes an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth PMOS transistor, a nineteenth PMOS transistor, a twentieth PMOS transistor, a second PNP transistor, a third PNP transistor, a fourth PNP transistor, a fifth PNP transistor, a third resistor, an operational amplifier, and a positive temperature coefficient adjustment unit. The source of the eleventh PMOS transistor is connected to the operating voltage, the gate of the eleventh PMOS transistor is connected to the gate of the first PMOS transistor, and the drain of the eleventh PMOS transistor is connected to the source of the twelfth PMOS transistor. The gate of the twelfth PMOS transistor is connected to the gate of the second PMOS transistor. The drain of the twelfth PMOS transistor is connected to the first input terminal of the positive temperature coefficient adjustment unit. The source of the thirteenth PMOS transistor is connected to the operating voltage. The gate of the thirteenth PMOS transistor is connected to the gate of the seventh PMOS transistor. The drain of the thirteenth PMOS transistor is connected to the source of the fourteenth PMOS transistor. The gate of the fourteenth PMOS transistor is connected to the gate of the twelfth PMOS transistor. The drain of the fourteenth PMOS transistor is connected to the second input terminal of the positive temperature coefficient adjustment unit. The drain of the fourteenth PMOS transistor is also connected to the emitter of the second PNP transistor. The base of the second PNP transistor is connected to the collector of the second PNP transistor. The collector of the second PNP transistor is grounded. The source of the fifteenth PMOS transistor is connected to the operating voltage. The gate of the fifteenth PMOS transistor is connected to the gate of the seventh PMOS transistor. The drain of the fifteenth PMOS transistor is connected to the source of the sixteenth PMOS transistor. The gate of the sixteenth PMOS transistor is connected to the gate of the twelfth PMOS transistor. The drain of the sixteenth PMOS transistor is connected to the third input terminal of the positive temperature coefficient adjustment unit. The drain of the sixteenth PMOS transistor is also connected to the emitter of the third PNP transistor. The base of the third PNP transistor is connected to the collector of the third PNP transistor. The collector of the third PNP transistor is grounded. The source of the seventeenth PMOS transistor is connected to the operating voltage. The gate of the seventeenth PMOS transistor is connected to the gate of the first PMOS transistor. The drain of the seventeenth PMOS transistor is connected to the source of the eighteenth PMOS transistor. The gate of the eighteenth PMOS transistor is connected to the gate of the twelfth PMOS transistor. The drain of the eighteenth PMOS transistor is connected to the non-inverting input of the operational amplifier. The drain of the eighteenth PMOS transistor is also connected to the emitter of the fourth PNP transistor via the third resistor connected in series. The base of the fourth PNP transistor is connected to the emitter of the second PNP transistor. The collector of the fourth PNP transistor is grounded. The source of the nineteenth PMOS transistor is connected to the operating voltage. The gate of the nineteenth PMOS transistor is connected to the gate of the first PMOS transistor.The drain of the nineteenth PMOS transistor is connected to the source of the twentieth PMOS transistor, the gate of the twentieth PMOS transistor is connected to the gate of the twelfth PMOS transistor, the drain of the twentieth PMOS transistor is connected to the inverting input of the operational amplifier, the output of the operational amplifier is connected to the gate of the first PMOS transistor, the drain of the twentieth PMOS transistor is also connected to the emitter of the fifth PNP transistor, the base of the fifth PNP transistor is connected to the emitter of the third PNP transistor, and the collector of the fifth PNP transistor is grounded. The drain of the eighteenth PMOS transistor outputs the positive temperature coefficient current.

2. The bandgap reference circuit according to claim 1, characterized in that, The second input terminal and the third input terminal of the positive temperature coefficient adjustment unit respectively provide an adjustable current to adjust the temperature coefficient of the positive temperature coefficient current.

3. The bandgap reference circuit according to claim 1, characterized in that, The ratio of the emitter junction area of ​​the second PNP transistor to that of the third PNP transistor is m:1, and the ratio of the emitter junction area of ​​the fourth PNP transistor to that of the fifth PNP transistor is n:1, where m and n are integers greater than or equal to 1.

4. The bandgap reference circuit according to claim 1, characterized in that, The reference voltage output module includes a 21st PMOS transistor, a 22nd PMOS transistor, a 23rd PMOS transistor, a 24th PMOS transistor, a fourth resistor, and a digital adjustment unit. The source of the 21st PMOS transistor is connected to the operating voltage, the gate of the 21st PMOS transistor is connected to the gate of the first PMOS transistor, the drain of the 21st PMOS transistor is connected to the source of the 22nd PMOS transistor, the gate of the 22nd PMOS transistor is connected to the gate of the second PMOS transistor, and the drain of the 22nd PMOS transistor is connected to the emitter of the first PNP transistor via the fourth resistor connected in series. The source of the 23rd PMOS transistor is connected to the operating voltage, the gate of the 23rd PMOS transistor is connected to the gate of the first PMOS transistor, the drain of the 23rd PMOS transistor is connected to the source of the 24th PMOS transistor, the gate of the 24th PMOS transistor is connected to the gate of the second PMOS transistor, and the drain of the 24th PMOS transistor is connected to the input terminal of the digital adjustment unit. The output terminal of the digital adjustment unit is connected to the drain of the 22nd PMOS transistor. The drain of the 22nd PMOS transistor outputs the bandgap reference voltage.

5. The bandgap reference circuit according to claim 4, characterized in that, The control terminal of the digital adjustment unit is connected to a multi-digit code, and the output current of the digital adjustment unit is adjusted and controlled by the multi-digit code.

6. The bandgap reference circuit according to claim 5, characterized in that, The bandgap reference circuit further includes a base current compensation module, connected to the feedback-type startup and bias module, the negative temperature coefficient current generation module, and the positive temperature coefficient current generation module. Under the action of the third bias voltage and the fourth bias voltage, it generates a compensation current equal to the base current of the transistor. The compensation current performs current self-compensation on at least some of the transistors in the negative temperature coefficient current generation module, the positive temperature coefficient current generation module, and the base current compensation module to eliminate the influence of the current gain of the transistor on the bandgap reference voltage.

7. The bandgap reference circuit according to claim 6, characterized in that, The base current compensation module includes a 25th PMOS transistor, a 26th PMOS transistor, a 27th PMOS transistor, a 28th PMOS transistor, a 29th PMOS transistor, a 30th PMOS transistor, a 31st PMOS transistor, an 8th NMOS transistor, a 9th NMOS transistor, and a 6th PNP transistor. The source of the 25th PMOS transistor is connected to the operating voltage, and the drain of the 25th PMOS transistor is connected to the emitter of the 4th PNP transistor. The source of the 26th PMOS transistor is connected to the operating voltage, and the gate of the 26th PMOS transistor is connected to the gate of the 25th PMOS transistor. The drain of the 26th PMOS transistor is connected to the emitter of the 5th PNP transistor. The source of the 27th PMOS transistor is connected to the operating voltage, and the gate of the 27th PMOS transistor is connected to the drain of the 27th PMOS transistor. The drain of the 27th PMOS transistor is connected to the gate of the 26th PMOS transistor, and the drain of the 27th PMOS transistor is also connected to the drain of the 8th NMOS transistor. The source of the 8th NMOS transistor is grounded. The source of the 28th PMOS transistor is connected to the operating voltage, and the gate of the 28th PMOS transistor is connected to the 8th PMOS transistor. The drain of the 28th PMOS transistor is connected to the gate of the 27th PMOS transistor, the drain of the 29th PMOS transistor is connected to the emitter of the 6th PNP transistor, the source of the 29th PMOS transistor is connected to the operating voltage, the gate of the 29th PMOS transistor is connected to the gate of the 27th PMOS transistor, the drain of the 29th PMOS transistor is connected to the emitter of the 6th PNP transistor, the source of the 30th PMOS transistor is connected to the operating voltage, the gate of the 30th PMOS transistor is connected to the gate of the 1st PMOS transistor, and the drain of the 30th PMOS transistor is connected to the emitter of the 6th PNP transistor. The source of the S-channel transistor is connected to the source of the S-channel transistor. The gate of the thirty-first PMOS transistor is connected to the gate of the second PMOS transistor. The drain of the thirty-first PMOS transistor is connected to the emitter of the sixth PNP transistor. The base of the sixth PNP transistor is connected to the drain of the ninth NMOS transistor. The collector of the sixth PNP transistor is grounded. The gate of the ninth NMOS transistor is connected to the drain of the ninth NMOS transistor. The gate of the ninth NMOS transistor is also connected to the gate of the eighth NMOS transistor. The source of the ninth NMOS transistor is grounded. The base of the sixth PNP transistor outputs the compensation current.

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