Data access system, data access method, and storage medium

Abstract

This disclosure provides a data access system, a data access method, and a storage medium. The data access system includes a host, a memory controller, and flash memory. The memory controller includes: a flash translation layer configured to receive a read command from the host, including a logical block address, for the flash memory, and to determine a region identifier and a logical block address offset based on the logical block address; a random access memory configured to store a mapping table including multiple flash memory physical addresses arranged in multiple regions corresponding to multiple superblocks; and an address management circuit configured to determine the flash memory physical address corresponding to the logical block address by accessing the mapping table according to the region identifier and the logical block address offset, and to determine a page number and a block identifier corresponding to the flash memory physical address. The page number and block identifier are used to execute the read command by accessing data stored in the page corresponding to the page number in the block corresponding to the block identifier. This disclosure improves the overall efficiency of performing memory access operations.

Description

Technical Field

[0001] This disclosure generally relates to data access to flash memory, and more specifically, to a data access system, a data access method, and a storage medium. Background Technology

[0002] Memory access to flash memory includes read and write operations. While write operations are typically performed serially, read operations usually involve random access to the flash memory and require valuable hardware processing resources to calculate the physical location on the flash memory corresponding to the logical address. Such calculations can become particularly cumbersome as bad blocks begin to accumulate in the flash memory, leading to computational complexity. This significant bottleneck in performing read operations on flash drives such as solid-state drives (SSDs) needs to be reduced. Summary of the Invention

[0003] In view of this, one object of this disclosure is to improve the throughput of read operations performed on flash memory and the overall efficiency of memory access operations.

[0004] According to one aspect, a system includes: a host; a memory controller communicatively coupled to the host; and flash memory communicatively coupled to the memory controller; the flash memory includes multiple blocks, the multiple blocks are grouped into multiple superblocks, and each of the multiple blocks includes multiple pages. The memory controller includes: a flash translation layer configured to: receive read commands for flash memory from the host, wherein the read commands include a logical block address (LBA), and determine a region identifier and a logical block address offset based on the logical block address; random access memory (RAM) configured to store a mapping table, wherein the mapping table includes multiple flash physical addresses (FPAs) arranged in multiple regions corresponding to multiple superblocks; and an address management circuit configured to: receive a region identifier and a logical block address offset from the flash translation layer, determine the flash physical address corresponding to the logical block address by accessing the mapping table stored in the random access memory according to the region identifier and the logical block address offset, and determine the page number and block identifier corresponding to the flash physical address, the page number and block identifier being used to execute the read command by accessing data in the page corresponding to the page number in multiple pages of the block corresponding to the block identifier stored in multiple blocks.

[0005] In some embodiments, the address management circuitry is implemented on a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC).

[0006] In some embodiments, the flash memory includes a solid-state drive (SSD).

[0007] In some embodiments, in response to the flash memory being powered on, a mapping table is generated and stored in random access memory.

[0008] In some embodiments, the mapping table is generated by skipping one or more bad blocks among a plurality of superblocks.

[0009] In some embodiments, the random access memory is one or more double data rate (DDR) synchronous dynamic random access memories (SDRAM).

[0010] In some embodiments, the address management circuitry is also configured to determine, in parallel, multiple flash physical addresses corresponding to multiple logic block address offsets.

[0011] In some embodiments, the memory controller is an open channel controller for flash memory.

[0012] According to another aspect, a method includes: receiving a read command for flash memory from a host via a flash translation layer in a memory controller, wherein the read command includes a logical block address (LBA), the flash memory includes multiple blocks, the multiple blocks are grouped into multiple superblocks, and each of the multiple blocks includes multiple pages; determining a region identifier and a logical block address offset based on the logical block address via the flash translation layer; determining a flash physical address (FPA) corresponding to the logical block address by accessing a mapping table stored in random access memory according to the region identifier and the logical block address offset via address management circuitry, wherein the mapping table includes multiple flash physical addresses arranged in multiple regions corresponding to the multiple superblocks; and determining a page number and a block identifier corresponding to the flash physical address via the address management circuitry, wherein the page number and block identifier are used to execute the read command by accessing data in the page corresponding to the page number in the multiple pages of the block corresponding to the block identifier in the multiple blocks.

[0013] According to another aspect, a non-transitory computer-readable storage medium stores instructions that, when executed by one or more processors, cause the one or more processors to perform an operation comprising: receiving a read command for flash memory from a host via a flash translation layer in a memory controller, wherein the read command includes a logical block address (LBA), the flash memory comprising multiple blocks grouped into multiple superblocks, and each of the multiple blocks comprising multiple pages; determining a region identifier and a logical block address offset based on the logical block address via the flash translation layer; determining a flash physical address (FPA) corresponding to the logical block address by accessing a mapping table stored in random access memory according to the region identifier and the logical block address offset via address management circuitry, wherein the mapping table includes multiple flash physical addresses arranged in multiple regions corresponding to the multiple superblocks; and determining a page number and a block identifier corresponding to the flash physical address via the address management circuitry, wherein the page number and block identifier are used to execute the read command by accessing data in a page corresponding to the page number in one of multiple pages in the block corresponding to the block identifier in the multiple blocks.

[0014] In this embodiment, each region is mapped to a corresponding superblock. Identical pages in all blocks within a superblock form a superpage. The physical addresses within each region are abstracted using the concept of superpages. The block number, channel, and other information corresponding to the same offset position within each superpage are consistent. Based on this, region identifiers and LBA offset identifiers (FPAs) are used in the mapping table to compress the entries for converting LBAs to FPAs. Using the mapping table, and by determining the page number and block identifier corresponding to the flash memory physical address with the logical block address through simple calculation, data stored in the corresponding page within the corresponding block is accessed using the page number and block identifier, and a read command is executed. This eliminates the need to invest valuable computing resources (e.g., CPU) to perform address translation calculations for each LBA in the read operation, even considering the presence of bad blocks in the superblock. Furthermore, the CPU is spared from performing mapping table lookups, resulting in higher throughput for flash memory read operations and improved overall efficiency of memory access operations. Furthermore, because a mapping table is generated each time the NAND flash memory is powered on or becomes available to the host, the hardware system can flexibly work with NAND flash memory drives of different types and with different bad block distributions, improving compatibility with various NAND flash memory types. Attached Figure Description

[0015] These and other features of the systems, methods, and hardware devices of this disclosure, the operation and function of related elements of the structure, and the economy of combination and manufacture of components will become more apparent when considered in conjunction with the accompanying drawings and the appended claims. The drawings form part of this specification, wherein similar reference numerals denote related portions in the drawings. However, it should be understood that the drawings are for illustrative and descriptive purposes only and are not intended to define limitations of the invention.

[0016] Figure 1 A schematic diagram illustrating the architecture of an exemplary flash drive memory system with zoned namespaces according to some embodiments of the present disclosure is shown.

[0017] Figure 2 A schematic diagram illustrating an exemplary workflow of a flash drive with partitioned namespaces according to some embodiments of the present disclosure is shown.

[0018] Figure 3 A schematic diagram illustrating an exemplary physical address arrangement of a flash drive with partitioned namespaces according to some embodiments of the present disclosure is shown.

[0019] Figure 4 A flowchart illustrating an exemplary method for performing address translation using hardware memory according to some embodiments of the present disclosure is shown.

[0020] Figure 5 A schematic diagram illustrating an exemplary mapping table stored in hardware memory according to some embodiments of the present disclosure is shown.

[0021] Figure 6 A schematic diagram illustrating an exemplary architecture of a solid-state drive controller having a partitioned namespace and a cache mapping table according to some embodiments of the present disclosure is shown.

[0022] Figure 7 A flowchart illustrating an exemplary method for performing address translation using a physical address manager and hardware memory according to some embodiments of the present disclosure is shown. Specific Implementation

[0023] This disclosure is provided in the context of a particular application and its requirements, and is intended to enable any person skilled in the art to make and use the embodiments. Various modifications to the embodiments of this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this disclosure. Therefore, this disclosure is not limited to the embodiments shown, but should be accorded the widest scope consistent with the principles and features of this disclosure.

[0024] NAND flash memory is a type of non-volatile memory that uses floating-gate transistors. In NAND flash memory, data is stored in bits, typically one bit per cell. These cells are grouped into bit lines. Multiple bit lines are then grouped into pages, and multiple pages are grouped to form blocks. NAND flash memory comprises multiple blocks, and the exact number of blocks in a NAND flash memory depends on its specifications. For write operations, NAND flash memory uses pages as the unit for writing. For erase operations, NAND flash memory erases one block at a time. The number of erase operations that can be performed on a block is limited. The maximum number of erases allowed on a block is called a program erase cycle.

[0025] A superblock is a logical block composed of multiple blocks in NAND flash memory. Within a superblock, write and erase operations can be performed on all blocks simultaneously. In other words, the lifecycle of data is essentially the same across all blocks within a superblock.

[0026] A superpage is a logical page formed by identical pages from all blocks within a superblock. For example, the first page of each block in a superblock can be grouped to form a superpage.

[0027] Bad blocks are blocks in NAND flash memory that have undergone too many erase operations, and therefore are no longer functional.

[0028] A logical block address (LBA) is a general scheme used to specify the location of data at the application or host level. The LBA is visible to the application or host, and to access the data pointed to by an LBA in a flash drive, the LBA needs to be translated into a physical address within the flash drive. When the host stores data in a specific LBA (e.g., LBA 0) and subsequently rewrites it to the same LBA, the new data can be stored at a different physical address in the flash drive, but the NAND flash memory's mapping table is modified, causing the LBA to now point to the new physical address where the new data is stored. The new data is still written to the NAND memory serially.

[0029] A solid-state drive (SSD) is a type of memory drive that uses NAND flash memory for persistent data storage. The SSD controller is an embedded processor on the SSD, configured to execute the firmware-level software of the SSD and accelerate data access and processing on the SSD.

[0030] Synchronous Dynamic Random-Access Memory (SDRAM) is a type of dynamic random access memory (DRAM) that provides faster data access.

[0031] The flash translation layer (FTL) is an intermediate layer configured to manage the operation of solid-state drives. The FTL can be hardware, software, or both, and is configured to perform functions such as logical address to physical address translation, garbage collection, wear leveling, error correction code (ECC), and bad block management.

[0032] A flash physical address (FPA) refers to a physical address on NAND flash memory. For example, a flash physical address includes the block number, channel number, page number, etc., of a specific physical address on the NAND flash memory.

[0033] Partition namespaces are part of a set of commands for managing solid-state drive (SSD) resources. Partition namespaces allow a host to provide a partitioned block storage interface and divide the interface into multiple zones. Each zone allows for both random read and serial write operations. This simplifies data storage within the SSD, allowing written data to align with the physical storage medium, thus improving the overall throughput, storage capacity, and lifespan of the SSD. SSDs that support partition namespaces are also known as zoned namespaces SSDs (ZNS SSDs). Each zone within a partition namespace can cover a large storage capacity (e.g., 16GB) on the SSD. Because data in each zone can be reclaimed together (e.g., through garbage collection), the lifespan of data before it is reclaimed or erased can be significantly extended. For example, if a zone covers 16GB of data, all 16GB can be reclaimed together, rather than the amount of data covered by an LBA (e.g., a few MB). Overall, fewer erase operations are performed on the SSD, thus extending its lifespan.

[0034] Figure 1 A schematic diagram illustrating the architecture of an exemplary flash drive memory system with partitioned namespaces according to some embodiments of the present disclosure is shown. Figure 1 As shown, the flash memory system 100 includes a host 110, a solid-state drive controller 120, and a NAND 130. Figure 1The diagrams shown are for illustrative purposes only and may vary depending on the implementation. Figure 1 The flash drive memory system 100 shown can have fewer, more, and alternative components and connections.

[0035] like Figure 1 As shown, the solid-state drive controller 120 is communicatively coupled to the host 110 and the NAND flash memory 130. In some embodiments, the host 110 is configured to interact with the solid-state drive controller 120 via a partitioned block storage interface, which is divided into multiple regions. Each region allows random read operations and serial write operations. In some embodiments, the NAND flash memory 130 includes one or more dies 131, each die 131 being configured to store data. In some embodiments, the NAND flash memory 130 has a large storage capacity (e.g., 30TB) managed and accessed by a single solid-state drive controller 120.

[0036] In some embodiments, the solid-state drive controller 120 includes a frontend (FE) 121, a flash conversion layer 122, and a backend (BE) 123.

[0037] In some embodiments, front-end 121 is configured to receive memory access commands from host 110 and decode the memory access commands according to one or more memory protocols. Memory access commands include read operations, write operations, erase operations, garbage collection operations, etc. Decoding includes converting the memory access commands for processing by flash memory translation layer 122, and decomposing the memory access commands into a set of commands for processing by flash memory translation layer 122.

[0038] In some embodiments, the flash memory translation layer 122 is configured to receive decoded memory access commands from the front end 121, perform logical address to physical address conversion, garbage collection, wear leveling, error correction codes, bad block management, etc., and send physical memory access information to the back end 123.

[0039] In some embodiments, the backend 123 is configured to perform condition management of the flash drive memory system 100, issue decoding commands, receive physical memory access information from the flash conversion layer 122, and perform memory access on the NAND 130 based on the physical memory access information, etc.

[0040] In some embodiments, the solid-state drive controller 120 further includes a cache 124 or a double data rate (DDR) synchronous dynamic random access memory (SDRAM) 125 configured to accelerate the execution of memory access commands to the NAND 130. In some embodiments, the solid-state drive controller 120 is an open-channel controller for the NAND 130.

[0041] Figure 2 This diagram illustrates an exemplary workflow of a flash drive with partitioned namespaces according to some embodiments of the present disclosure. It should be understood that... Figure 2 The workflow shown can be generated by Figure 1 The flash drive memory system 100 shown is used for execution. Figure 2 As shown, Figure 2 The workflows described are for illustrative purposes only, and may vary depending on the implementation. Figure 2 The workflow shown can have fewer, more, and alternative steps, components, and connections.

[0042] like Figure 2 As shown, in a solid-state drive with partitioned namespaces, each region supports random read operations and serial-only write operations. An erase operation can be performed on a region as a unit, and the erase operation can be referred to as a reset of that region. The order of LBAs in write operations from the host can be the same as the order in which the data corresponding to the LBAs is written to each region. Furthermore, a region is mapped to a superblock. Therefore, data from the host (e.g., ...) Figure 1 The LBAs of the host (110) are serially mapped to one or more regions, and no additional mapping table is required to track the mapping between LBAs and physical addresses within the regions. Therefore, no dedicated memory (e.g., within the solid-state drive controller 120) is needed to store the mapping table. For example, as... Figure 2 As shown, LBA0 to LBAM-1 are serially mapped between regions 0 and N. Each region includes a written portion, an unwritten portion, and an unmapped portion, and provides a write pointer to indicate the location of the written portion. For example, as... Figure 2As shown, region 0 includes written LBA portions, unwritten LBA portions, and unmapped LBAs. The write pointer points to the end of the written LBA portions and the beginning of the unwritten LBA portions. For example, when the system (e.g., from the host) requests a memory block smaller than the region size, unmapped LBA portions are created or indicated. For instance, when each region captures 16GB of physical storage capacity, and the system only requests 10GB of storage capacity, the physical storage capacity of one region is still provided to the system, but 6GB of that storage capacity is in the unmapped LBA portions.

[0043] like Figure 2 As shown, LBA0 to LBAM-1 are mapped to regions 0 to N. Each region, such as region 0, maps X+1 LBAs. Since the mapping is sequential, the first X+1 LBAs are mapped to LBA0 to LBAX in region 0, the second X+1 LBAs are mapped to LBA0 to LBAX in region 1, and so on.

[0044] When a region's storage space is mapped to a flash physical address (FPA), one or more factors may come into play. These factors may include determining whether the superblock has bad blocks, which blocks are used within the superblock, and how data is arranged on the superblock. For example, ... Figure 2 As shown, FPAs are arranged serially in superblock 0. Each LBA is mapped to four FPAs (e.g., for read operations). For example, LBA0 is mapped to FPA0, FPA1, FPA2, and FPA3, which are located in the first row of block 0 (or NAND die 0). Next, LBA1 is mapped serially to FPA4, FPA5, FPA6, and FPA7, which are located in the first row of block 1 (or NAND die 1). Since the next block is bad, the next LBA (i.e., LBA2) is mapped to FPA8, which is located in block 3 (or NAND die 3).

[0045] Due to one or more of the factors mentioned above, when sending an LBA (e.g., from the host) Figure 2When using the LBA X (as shown), there may not be a readily available mapping table (e.g., a logical address to physical address mapping table or an L2P mapping table) from which the physical location corresponding to the LBA address can be easily identified. Therefore, hardware resources (e.g., the CPU on a solid-state drive controller) are required to calculate or determine the FPA. This calculation or determination process includes the following steps: First, based on the determination of how the data is arranged on the superblock, determine the initial physical location from the LBA X. Second, based on the determined initial physical location, determine the block number corresponding to the LBA X. Third, based on the determined block number, determine whether the block corresponding to the block number is a bad block. If the block is a bad block, it needs to be skipped, and the above steps are repeated until a non-bad block is found.

[0046] Performing the above steps can consume significant hardware processing resources, especially when these steps are repeated with each memory access operation. Furthermore, processors such as CPUs tend to execute steps serially, which further reduces the efficiency of determining the FPA from the LBA. This inefficiency becomes a major bottleneck when performing read operations on flash drives (such as solid-state drives).

[0047] Embodiments of this disclosure provide systems and methods for improved FPA lookup using hardware memory. Figure 3 A schematic diagram illustrating an exemplary physical address arrangement of a flash drive with partitioned namespaces according to some embodiments of the present disclosure is shown. Figure 3 As shown, Figure 3 The arrangement shown is for illustrative purposes only, and according to the implementation method, Figure 3 The arrangement shown can have fewer, more, and alternative steps, components, and connections.

[0048] like Figure 3 As shown, superblock 0 comprises multiple blocks, such as block 0, block 1, bad block 2, and block 3. FPAs are arranged serially within different blocks in superblock 0. For example, FPA0, FPA1, FPA2, and FPA3 are in block 0, FPA4, FPA5, FPA6, and FPA7 are in block 1, and so on. Each row of FPAs within a block is called a page. For example, FPA0, FPA1, FPA2, and FPA3 form a page in block 0. Multiple pages along the same row in a superblock form a superpage. For example, FPA0 through FPA11 form a superpage in superblock 0. In the case of a bad block (e.g., bad block 2), the bad block is skipped, and the FPAs are moved to the next good block. Bad blocks also affect the size of the superpage. For example, as... Figure 3 As shown, due to the presence of bad block 2, the size of the superpage is reduced to 12 FPAs instead of 16 FPAs.

[0049] Figure 4A flowchart illustrating an exemplary method for performing address translation using hardware memory according to some embodiments of the present disclosure is provided. It should be understood that... Figure 4 The method 400 shown can be derived from Figure 1 The flash drive memory system 100 shown is used for execution. Figure 4 As shown, Figure 4 Method 400 is for illustrative purposes only, and according to the implementation, Figure 4 The method 400 shown can have fewer, more, and alternative steps, components, and connections.

[0050] Step 410 includes determining the corresponding superblock based on the region number. For example, if a region is mapped to a superblock, then (e.g., as...) Figure 2 (As shown) Region 0 is mapped to superblock 0, Region 1 is mapped to superblock 1, and so on.

[0051] Step 420 includes determining the offset based on the size of the superpage in the superblock. For example, as Figure 3 As shown, the size of the superpage in superblock 0 is 12. Therefore, for LBA20, the offset is determined to be 21%12, or 9. In some embodiments, the superpages in different superblocks can have different sizes. For example, as... Figure 3 As shown, region 0 has one bad block. Therefore, the superpage size in region 0 is 12. Region 1 may not have any bad blocks. Therefore, the superpage size in region 1 is 16. Region 2 may have two bad blocks. Therefore, the superpage size in region 2 is 8. In some embodiments, information about bad blocks can be stored in the solid-state drive controller (e.g., Figure 1 The cache of the solid-state drive controller 120 in the system (e.g., Figure 1 In the high-speed cache (124 or DDR 125).

[0052] Step 430 includes determining the block index or block identifier based on the offset. For example, such as Figure 3 As shown, for LBA 20, the offset is 9. Since each page in a block contains 4 FPAs, the block index for LBA 20 is ceiling(9 / 4), which is 3.

[0053] Step 440 includes determining whether the current block corresponding to the block index is a bad block. For example, such as Figure 3 As shown, for LBA20, the block index is 3, which corresponds to bad block 2. In some embodiments, information about bad blocks is stored in the solid-state drive controller (e.g., Figure 1 The cache of the solid-state drive controller 120 (e.g., Figure 1The block is stored in the cache (124). If it is determined that the block is bad, proceed to step 450. If it is determined that the block is not bad, proceed to step 460.

[0054] Step 450 includes, in response to determining that the current block is a bad block, moving the block index to the next block, and repeating step 440 until a good block is found. For example, as Figure 3 As shown, FPA 20 is identified as being located in bad block 2, which is indeed a bad block. Therefore, the block index is moved to the next block, which corresponds to block 3, a good block.

[0055] Step 460 includes determining the physical address corresponding to the LBA in the current block in the absence of page information, in response to determining that the current block is not a bad block. For example, as Figure 3 As shown, FPA 20 is identified as the first FPA of the page in block 3.

[0056] Step 470 includes determining the page information corresponding to the LBA. For example, such as... Figure 3 As shown, the superpage has 12 FPAs. Page information is determined by calculating ceiling(2¹ / ¹²), which is 2. Therefore, the page information (page number) corresponding to the LBA is 1. Thus, LBA 20 is converted to the first FPA in the second page of block 3.

[0057] Figure 5 A schematic diagram illustrating an exemplary mapping table stored in hardware memory according to some embodiments of the present disclosure is shown. Figure 5 For illustrative purposes only, and according to the implementation method, Figure 5 The mapping table 500 shown can have fewer, more, and alternative components, arrangements, and connections.

[0058] like Figure 5 As shown, the M regions are arranged sequentially. For example, region 0 is followed by region 1, region 1 is followed by region 2, and so on. Each region has a different size. For example, as shown... Figure 5 As shown, region 0 has X FPAs, region 1 has Y FPAs, and region M has Z FPAs. Based on the superblocks corresponding to each region, there can be different numbers of bad blocks (e.g., Figure 3 Given that superblock 0 shown has a bad block, the size of the regions differs. A mapping table 500 is generated by the solid-state drive controller, and the mapping table 500 is stored in the memory (e.g., DDR) within the solid-state drive controller. For example, when the solid-state drive is powered on, the solid-state drive controller (e.g., using...) Figure 4 Step 440) shows how to determine where the bad blocks are located (e.g., using...). Figure 4The method 400 shown determines where each FPA is located in each of the M regions and generates a mapping table 500 to be stored in high-speed memory (e.g., DDR) in the solid-state drive controller. When the solid-state drive controller performs a random read operation on the solid-state drive, it quickly looks up the physical location of each FPA in the mapping table. For example, entries in the mapping table include information such as channel, die number, block number, plane number, page number, etc. Therefore, the solid-state drive controller no longer needs to devote valuable computing resources (e.g., CPU) to perform address translation calculations for each LBA in a read operation. Thus, the overall efficiency of performing memory access operations is significantly improved.

[0059] Figure 6 A schematic diagram illustrating an exemplary architecture of a solid-state drive controller having a partitioned namespace and a cache mapping table according to some embodiments of the present disclosure is provided. It should be understood that... Figure 6 The solid-state drive controller 600 shown may include, with Figure 1 The solid-state drive controller 120 shown is a similar component. For example, the solid-state drive controller 600 may also include a front end (e.g., similar to...). Figure 1 Front end 121), flash memory conversion layer 610 (similar to Figure 1 In the flash conversion layer 122), the back end (e.g., similar to Figure 1 The back-end 123) and cache memory 630 (e.g., similar to Figure 1 (The cache is 124 or DDR 125). In addition, the solid-state drive controller 600 may also include a physical address manager 620. Figure 6 The diagrams shown are for illustrative purposes only and may vary depending on the implementation. Figure 6 The solid-state drive controller 600 shown can have fewer, more, and alternative components and connections.

[0060] like Figure 6 As shown, the physical address manager 620 is communicatively coupled to the flash translation layer 610 and the cache memory 630. When the flash translation layer 610 is accessed from the host (e.g., Figure 1 When host 110 receives a memory access command including LBA, command scheduler 611 determines whether the memory access command is a read command or a write command. Based on the determination, command scheduler 611 sends the read command to read command processing 613 and the write command to write command processing 612. Since the read command involves access to NAND flash memory (e.g., ...), ... Figure 1For random access to the NAND 130, the flash translation layer 610 requires additional resources (e.g., physical address manager 620 and cache memory 630) to look up the physical location of the LBA. Therefore, the read command processing 613 sends a process input, including the LBA, to the physical address manager 620.

[0061] The physical address manager 620 receives and processes inputs and LBAs, and stores them in a mapping table (e.g., cache memory 630) in the cache memory 630. Figure 5 The physical address manager 620 looks up the FPA corresponding to the LBA in the mapping table 500 shown. In some embodiments, this mapping is a linear mapping to the FPA. Therefore, the lookup process can be easily performed. For example, the FPA can be looked up using the LBA as an array index (e.g., by performing one or more division calculations). In some embodiments, the physical address manager 620 is configured to process multiple LBAs in parallel to further improve the efficiency of the solid-state drive controller 600 in executing data processing commands. For example, a calculator or positioning engine processes more than one request at a time. In some embodiments, the physical address manager 620 is implemented on an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).

[0062] Cache memory 630 stores a mapping table and, based on cache input from physical address manager 620, returns FPA information corresponding to LBAs from the mapping table to physical address manager 620. Physical address manager receives FPA information from cache memory 630 via cache output and sends the FPA information to flash translation layer 610 via process output. Read command processing 613 receives the FPA information and sends the read command along with the FPA information to command transmission 614. Command transmission 614 sends the FPA information to backend (e.g., ...). Figure 1 The backend (123) performs operations on NAND flash memory (e.g., in...). Figure 1 Data access to NAND130.

[0063] Figure 7 A flowchart illustrating an exemplary method for performing address translation using a physical address manager and hardware memory according to some embodiments of the present disclosure is provided. It should be understood that... Figure 7 The method 700 shown can be derived from Figure 6 The system 600 shown is executing. Figure 7 For illustrative purposes only, and depending on the implementation, Figure 7The method 700 shown can have fewer, more, and alternative steps, components, and connections.

[0064] Step 710 includes sending a read command from the command scheduler to the read command processing module. In some embodiments, the command scheduler is similar to... Figure 6 The command scheduler 611 shown has a read command processing module similar to... Figure 6 The read command processing module 613 is shown. In some embodiments, the command scheduler and the read command processing module are memory controllers (e.g., Figure 1 This is part of the solid-state drive controller 120. In some embodiments, the read command includes an LBA. In some embodiments, the read command is used to read from flash memory (e.g., ...). Figure 1 Read data from NAND 130.

[0065] Step 720 includes determining the region identifier and LBA offset via the read command processing module. For example, as... Figure 5 As shown, the FPAs are arranged sequentially in different regions. Each region has a different size. Therefore, the read command processing module processes the LBA and determines which region the corresponding FPA belongs to and its LBA offset within that specific region.

[0066] Step 730 includes determining the superpage offset based on the LBA offset via the address management module. In some embodiments, the superpage offset is used to determine the array index. For example, the LBA-offset mapping may store only one superpage, and a superblock may store multiple superpages (e.g., 1000 superpages). Multiple superpages may follow the same mapping scheme but have different page addresses. Therefore, the array index can be determined by dividing the superpage offset by the LBA. In some embodiments, the address management module is similar to... Figure 6 The physical address manager is shown. (As shown in the image) Figure 3 As shown, each region or corresponding superblock has a different number of bad blocks. Therefore, the superpage size may also differ between different regions. Based on the superpage size in the region corresponding to the region identifier, the superpage offset is determined by finding the remainder when the LBA offset is divided by the superpage size (e.g., similar to...). Figure 4 Step 420 (as shown in the figure).

[0067] Step 740 includes the address management module determining the FPA corresponding to the LBA based on the region identifier and LBA offset by accessing the cache memory. For example, as Figure 5 As shown, region identifiers (e.g., region 0, region 1, etc.) and LBA offsets (e.g., LBA offset 0, LBA offset 1, etc.) identify the FPA in mapping table 500. In some embodiments, the cache memory is similar to Figure 1 The cache 124 or DDR 125 is shown. In some embodiments, the address management module determines multiple FPAs in parallel.

[0068] Step 750 includes determining the page number and block identifier corresponding to the FPA via the address management module. In some embodiments, the page number and block identifier are used to execute a read command by accessing data stored in the page corresponding to the page number of a plurality of pages in a plurality of blocks corresponding to the block identifier. In some embodiments, the address management module processes multiple FPAs in parallel.

[0069] Step 760 includes retrieving data corresponding to the LBA from the flash memory based on the page number and block identifier via a solid-state drive controller. In some embodiments, the memory controller is an open-channel controller for the flash memory.

[0070] Embodiments of this disclosure provide methods and systems for creating and utilizing a mapping table that converts LBAs to FPAs using regions and offsets. By using the mapping table, bad blocks within the superblock are taken into account, and physical addresses are obtained efficiently without tedious calculations on the CPU. The CPU is spared from performing mapping table lookups, resulting in higher throughput for read operations on the flash memory. Furthermore, because the mapping table is generated each time the NAND flash is powered on or becomes available to the host, the hardware system can flexibly work with NAND flash drives of different types and with different bad block distributions.

[0071] Each process, method, and algorithm described in the preceding sections can be embodied in a code module executed by one or more computer systems or computer processors including computer hardware, and can be fully or partially automated by that code module. These processes and algorithms can be implemented, partially or entirely, in dedicated circuitry.

[0072] When the functions disclosed herein are implemented as software functional units and sold or used as independent products, they may be stored in a processor-executable, non-volatile, computer-readable storage medium. Specific technical solutions (all or part) disclosed herein, or aspects contributing to the present technology, may be embodied in the form of a software product. The software product includes multiple instructions that may be stored in the storage medium to cause a computing device (which may be a personal computer, server, network device, etc.) to perform all or some steps of the methods of the embodiments of this disclosure. The storage medium may include a flash drive, portable hard disk drive, ROM, RAM, magnetic disk, optical disk, another medium operable for storing program code, or any combination thereof.

[0073] Specific embodiments also provide a system including a processor and a non-transitory computer-readable storage medium storing processor-executable instructions to cause the system to perform operations corresponding to the steps in any of the methods of the above embodiments. Specific embodiments also provide a non-transitory computer-readable storage medium configured with instructions executable by one or more processors to cause one or more processors to perform operations corresponding to the steps in any of the methods of the above embodiments.

[0074] The embodiments disclosed herein can be implemented through a cloud platform, server, or group of servers (collectively referred to as the "service system") that interacts with a client. The client can be a terminal device or a client registered by a user on the platform, wherein the terminal device can be a mobile terminal, a personal computer (PC), or any device on which the platform application can be installed.

[0075] The various features and processes described above can be used independently of each other or combined in various ways. All possible combinations and sub-combinations are within the scope of this disclosure. Furthermore, in some embodiments, certain method or process blocks may be omitted. The methods and processes described herein are not limited to any particular order, and the associated blocks or states may be executed in other suitable orders. For example, the described blocks or states may be executed in an order other than the order specified in this disclosure, or multiple blocks or states may be combined in a single block or state. Example blocks or states may be executed serially, in parallel, or in some other manner. Blocks or states may be added to or removed from the example embodiments of this disclosure. The exemplary systems and components described herein may be configured differently than those described. For example, elements may be added, removed, or reset in the example embodiments of this disclosure compared to those described in the example embodiments of this disclosure.

[0076] The various operations of the example methods described herein can be performed at least partially by an algorithm. This algorithm may include program code or instructions stored in memory (e.g., the aforementioned non-transitory computer-readable storage medium). Such an algorithm may include a machine learning algorithm. In some embodiments, the machine learning algorithm may not explicitly program the computer to perform the function, but may learn from training data to build a predictive model for performing that function.

[0077] The various operations of the example methods described herein can be performed at least partially by one or more processors, which can be temporarily configured (e.g., by software) or permanently configured to perform the relevant operations. Whether temporarily or permanently configured, these processors can constitute the engine of a processor implementation that runs to perform one or more of the operations or functions described herein.

[0078] Similarly, the methods described herein can be implemented at least in part by a processor, where a specific processor or one or more processors are examples of hardware. For example, at least some operations of the methods can be performed by one or more processors or an engine implemented by a processor. Furthermore, one or more processors can also be used to support the performance of related operations in a “cloud computing” environment or as “software as a service” (SaaS). For example, at least some operations can be performed by a set of computers (as an example of a machine including processors) that can be accessed via a network (e.g., the Internet) and through one or more appropriate interfaces (e.g., Application Program Interfaces (APIs)).

[0079] The performance of certain operations can be distributed across processors, rather than residing within a single machine, but deployed across multiple machines. In some example embodiments, the processor or processor-implemented engine may reside in a single geographic location (e.g., in a home environment, office environment, or server farm). In other example embodiments, the processor or processor-implemented engine may be distributed across multiple geographic locations.

[0080] In this specification, multiple instances can implement components, operations, or structures described as a single instance. Although individual operations of one or more methods are shown and described as separate operations, one or more separate operations may be performed simultaneously, and the order in which they are performed is not required. Structures and functions presented as separate components in the example configuration can be implemented as composite structures or components. Similarly, structures and functions presented as single components can be implemented as separate components. These, and other variations, modifications, additions, and improvements fall within the scope of this document.

[0081] Although an overview of the subject matter has been described with reference to specific example embodiments, various modifications and changes can be made to these embodiments without departing from the broader scope of embodiments of this disclosure. These embodiments of this disclosure may be referred to individually or collectively by the term "this disclosure" merely for convenience, and are not intended to voluntarily limit the scope of this disclosure to any single disclosure or concept, if in fact more than one disclosure or concept is disclosed.

[0082] The embodiments illustrated herein have been described in sufficient detail to enable those skilled in the art to practice the disclosed teachings. Other embodiments may be used and derived therefrom, allowing for structural and logical substitutions and changes without departing from the scope of this disclosure. Therefore, the Specific Embodiments section should not be construed as limiting, and the scope of the various embodiments is defined only by the appended claims and all their equivalents.

[0083] Any process description, element, or block in the flowcharts described herein and / or the accompanying drawings should be understood to potentially represent a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or step in the process. As will be understood by those skilled in the art, alternative implementations are included within the scope of the embodiments described herein, wherein elements or functions may be removed depending on the functionality involved, and elements or functions may be performed in an order different from the order shown or discussed (including substantially simultaneous or reverse order).

[0084] As used herein, “or” is inclusive, not exclusive, unless otherwise expressly indicated or indicated by the context. Therefore, here, “A, B, or C” means “A, B, C, A and B, A and C, B and C, or A, B, and C”, unless otherwise expressly indicated or indicated by the context. Furthermore, “and” is both consequential and individual, unless otherwise expressly indicated or indicated by the context. Therefore, here, “A and B” means “A and B, jointly or separately”, unless otherwise expressly indicated or indicated by the context. Furthermore, multiple instances may be provided for a resource, operation, or structure described herein as a single instance. Moreover, the boundaries between various resources, operations, engines, and data stores are arbitrary and specific operations are described within the context of a particular illustrative configuration. Other allocations of functionality may be contemplated and may fall within the scope of various embodiments of this disclosure. Generally, structures and functions presented as separate resources in the example configuration may be implemented as combined structures or resources. Similarly, structures and functions presented as a single resource may be implemented as separate resources. These and other variations, modifications, additions, and improvements fall within the scope of embodiments of this disclosure as represented by the appended claims. Therefore, the specification and drawings are to be regarded as illustrative rather than restrictive.

[0085] The terms “comprising” or “including” are used to indicate the presence of a subsequently stated feature, but do not preclude the addition of other features. Conditional language, such as “may” or “may”, unless explicitly stated otherwise or otherwise understood in the context in which they are used, is generally intended to convey that certain embodiments include certain features, elements, and / or steps that are not included in other embodiments. Therefore, such conditional language generally does not imply that features, elements, and / or steps are required in any way by one or more embodiments, or that one or more embodiments must include logic for determining whether such features, elements, and / or steps are included or will be performed in any particular embodiment, with or without user input or prompting.

Claims

1. A data access system, comprising: a host; a memory controller communicatively coupled with the host; and a flash memory communicatively coupled with the memory controller, the flash memory comprising a plurality of blocks grouped into a plurality of super blocks, each block of the plurality of blocks comprising a plurality of pages; wherein the memory controller comprises: a flash translation layer configured to: receive a read command for the flash memory from the host, wherein the read command comprises a logical block address; and determine a zone identification and a logical block address offset based on the logical block address; a random access memory configured to store a mapping table, wherein the mapping table comprises a plurality of flash physical addresses arranged in a plurality of zones corresponding to the plurality of super blocks; and an address management circuit configured to: receive the zone identification and the logical block address offset from the flash translation layer; determine a flash physical address corresponding to the logical block address by accessing the mapping table stored in the random access memory according to the zone identification and the logical block address offset; and determine a page number and a block identification corresponding to the flash physical address, the page number and the block identification used to execute the read command by accessing data in a page corresponding to the page number in a block corresponding to the block identification stored in the block corresponding to the block identification in the plurality of blocks; wherein the host is configured to interact with the memory controller through a partitioned block storage interface, the partitioned block storage interface divided into a plurality of zones, each zone allowing random read operations and serial write operations. The address management circuit is implemented on a field programmable gate array or an application specific integrated circuit.

2. The data access system of claim 1, wherein, The flash memory comprises a solid state drive.

3. The data access system of claim 1, wherein, The mapping table is generated and stored in the random access memory in response to the flash memory being powered on.

4. The data access system of claim 1, wherein, The mapping table is generated by skipping one or more bad blocks in the plurality of super blocks.

5. The data access system of claim 1, wherein, The random access memory is one or more double data rate synchronous dynamic random access memories.

6. The data access system of claim 1, wherein, The address management circuit is further configured to determine a plurality of flash physical addresses corresponding to a plurality of logical block address offsets in parallel.

7. The data access system of claim 1, wherein, The memory controller is an open channel controller for the flash memory.

8. The data access system of claim 1, wherein, 9. A data access method, comprising: receiving, by a flash translation layer in a memory controller, a read command for a flash memory from a host, wherein the read command comprises a logical block address, the flash memory comprising a plurality of blocks grouped into a plurality of super blocks, each block of the plurality of blocks comprising a plurality of pages; determining, by the flash translation layer, a zone identification and a logical block address offset based on the logical block address; determining, by an address management circuit, a flash physical address corresponding to the logical block address by accessing a mapping table stored in a random access memory according to the zone identification and the logical block address offset, wherein the mapping table comprises a plurality of flash physical addresses arranged in a plurality of zones corresponding to the plurality of super blocks; and ​ ​ determining, by the address management circuit, a page number and a block identification corresponding to the flash memory physical address, wherein the page number and the block identification are used to execute the read command by accessing data stored in a page corresponding to the page number in a page corresponding to the page number in a block corresponding to the block identification in the plurality of blocks; wherein the host interacts with the memory controller through a block partitioned storage interface, the block partitioned storage interface is divided into a plurality of regions, each of the regions allows random read operation and serial write operation.

10. The data access method of claim 9, wherein, The address management circuit is implemented on a field programmable gate array or an application specific integrated circuit.

11. The data access method of claim 9, wherein, The flash memory includes a solid state drive.

12. The data access method of claim 9, wherein, The mapping table is generated and stored in the random access memory in response to the flash memory being powered on.

13. The data access method of claim 9, wherein, The mapping table is generated by skipping one or more bad blocks in the plurality of super blocks.

14. The data access method of claim 9, wherein, The random access memory is one or more double data rate synchronous dynamic random access memories.

15. The data access method of claim 9, wherein, The method further includes: determining, by the address management circuit, a plurality of flash memory physical addresses corresponding to a plurality of logical block address offsets in parallel.

16. The data access method of claim 9, wherein, The memory controller is an open channel controller for the flash memory.

17. A non-transitory computer-readable storage medium storing instructions for execution by one or more processors such that the one or more processors perform operations comprising: receiving, by a flash translation layer in a memory controller, a read command for a flash memory from a host, wherein the read command includes a logical block address, the flash memory includes a plurality of blocks, the plurality of blocks are grouped into a plurality of super blocks, each of the plurality of blocks includes a plurality of pages; determining, by the flash translation layer, a region identification and a logical block address offset based on the logical block address; determining, by an address management circuit, a flash memory physical address corresponding to the logical block address by accessing a mapping table stored in a random access memory according to the region identification and the logical block address offset, wherein the mapping table includes a plurality of flash memory physical addresses arranged in a plurality of regions corresponding to the plurality of super blocks; and determining, by the address management circuit, a page number and a block identification corresponding to the flash memory physical address, wherein the page number and the block identification are used to execute the read command by accessing data stored in a page corresponding to the page number in a page corresponding to the page number in a block corresponding to the block identification in the plurality of blocks; wherein the host interacts with the memory controller through a block partitioned storage interface, the block partitioned storage interface is divided into a plurality of regions, each of the regions allows random read operation and serial write operation.

18. The non-transitory computer-readable storage medium of claim 17, wherein, The address management circuit is implemented on a field programmable gate array or an application specific integrated circuit.

19. The non-transitory computer-readable storage medium of claim 17, wherein, The mapping table is generated and stored in the random access memory in response to the flash memory being powered on.

20. The non-transitory computer-readable storage medium of claim 17, wherein, The operations further include: determining, by the address management circuit, a plurality of flash memory physical addresses corresponding to a plurality of logical block address offsets in parallel.

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