A PCIE link connection method, system, device and storage medium

Abstract

This invention discloses a PCIe link connection method, comprising the following steps: connecting each port of each CPU to each slot of a PCIe switch; performing a margin test on each slot of the PCIe switch and saving the test results to a register; and, in response to detecting a PCIe device inserted into a slot, selecting the corresponding port to establish a connection based on the test results. This invention also discloses a system, a computer device, and a readable storage medium. The proposed solution connects all the PCIe ports of the CPUs in the server to a single PCIe switch. For external PCIe devices, the origin of the PCIe link is not specified. The PCIe control chip can automatically match the PCIe link based on the PCIe device inserted by the customer, using the PCIe margin of the PCIe device recorded in the register. The PCIe switch can automatically switch PCIe links, reducing the impact on services.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of servers, and in particular to a PCIE link connection method, system, device and storage medium. BACKGROUND

[0002] At present, AI products are applied more and more in servers, and the performance and stability of PCIE devices of servers are required more and more, and the PCIE slots supported by servers are more and more, and the PCIE devices supported by servers are various, and there are many GPUs, network cards, FPAG cards, ASIC cards and the like of different manufacturers, and server products need to be compatible with various PCIE devices, and the compatibility test of components of servers is a challenge, how to meet the requirements of various PCIE devices supported by different customers and guarantee the performance and stability of server products become current problems to be solved urgently.

[0003] With the increase of PCIE slots, PCIE Margin on each PCIE link is good or bad, when a server product introduces a PCIE device, compatibility test of the PCIE device on the slot supporting the device is performed, and PCIE Margin of the PCIE device on some PCIE links is poor, and the compatibility is not good, when a customer selects to insert a slot into these PCIE links with poor Margin, speed reduction or PCIE CE, UCE error is easy to occur, which affects the use of the server. SUMMARY

[0004] Therefore, in order to overcome at least one aspect of the above problems, the embodiments of the present application provide a PCIE link connection method, which comprises the following steps:

[0005] connecting each port of each CPU to each slot of a PCIE switch;

[0006] performing Margin test on each slot of the PCIE switch and saving the test result into a register;

[0007] in response to detecting that a PCIE device is inserted into a slot, establishing connection according to the corresponding port selected according to the test result.

[0008] In some embodiments, performing Margin test on each slot of the PCIE switch and saving the test result into a register further comprises:

[0009] performing Margin test on each slot of the PCIE switch to obtain a port priority list corresponding to each slot;

[0010] save the priority list into the register.

[0011] In some embodiments, in response to detecting that a PCIE device is inserted into a slot, the selecting the corresponding port to establish a connection according to the test result further comprises:

[0012] In response to detecting that a PCIE device is inserted into a slot, determining the port with the highest priority from the unused ports according to the port priority list, and establishing a connection between the PCIE device and the port with the highest priority.

[0013] In some embodiments, the method further comprises:

[0014] In response to detecting a port error, determining whether there is a free port currently;

[0015] In response to there being no free port currently, selecting the corresponding PCIE device to perform width processing and reporting an alarm information according to the traffic monitoring.

[0016] Based on the same inventive concept, according to another aspect of the present application, embodiments of the present application further provide a PCIE link connection system, comprising:

[0017] A connection module configured to connect each port of each CPU to each slot of a PCIE switch;

[0018] A test module configured to perform a Margin test on each slot of the PCIE switch and save the test result into a register;

[0019] A selection module configured to, in response to detecting that a PCIE device is inserted into a slot, select the corresponding port to establish a connection according to the test result.

[0020] In some embodiments, the test module is further configured to:

[0021] perform a Margin test on each slot of the PCIE switch to obtain a port priority list corresponding to each slot;

[0022] save the priority list into the register.

[0023] In some embodiments, the selection module is further configured to:

[0024] In response to detecting that a PCIE device is inserted into a slot, determine the port with the highest priority from the unused ports according to the port priority list, and establish a connection between the PCIE device and the port with the highest priority.

[0025] In some embodiments, a detection module is also included, configured to:

[0026] In response to a detected port error, determine if there is a free port currently available;

[0027] If no free ports are available, select the appropriate PCIe device based on traffic monitoring to reduce the bandwidth and report alarm information.

[0028] Based on the same inventive concept, according to another aspect of the present invention, embodiments of the present invention also provide a computer device, comprising:

[0029] At least one processor; and

[0030] A memory storing a computer program executable on the processor, characterized in that the processor performs the following steps when executing the program:

[0031] Connect each port of each CPU to each slot of the PCIe switch;

[0032] Perform a margin test on each slot on the PCIe switch and save the test results to a register;

[0033] In response to the detection of a PCIe device inserted into the slot, a connection is established by selecting the corresponding port based on the test results.

[0034] In some embodiments, performing a margin test on each slot on the PCIe switch and saving the test results to a register further includes:

[0035] Perform a margin test on each slot of the PCIe switch to obtain a list of port priorities for each slot.

[0036] Save the priority list to the register.

[0037] In some embodiments, in response to detecting a PCIe device inserted into the slot, selecting the corresponding port to establish a connection based on the test result further includes:

[0038] In response to detecting the insertion of a PCIe device into the slot, the highest priority port among multiple currently unused ports is determined according to the port priority list, and a connection is established between the PCIe device and the highest priority port.

[0039] In some embodiments, it also includes:

[0040] In response to a detected port error, determine if there is a free port currently available;

[0041] If no free ports are available, select the appropriate PCIe device based on traffic monitoring to reduce the bandwidth and report alarm information.

[0042] Based on the same inventive concept, according to another aspect of the present invention, embodiments of the present invention also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the following steps:

[0043] Connect each port of each CPU to each slot of the PCIe switch;

[0044] Perform a margin test on each slot on the PCIe switch and save the test results to a register;

[0045] In response to the detection of a PCIe device inserted into the slot, a connection is established by selecting the corresponding port based on the test results.

[0046] In some embodiments, performing a margin test on each slot on the PCIe switch and saving the test results to a register further includes:

[0047] Perform a margin test on each slot of the PCIe switch to obtain a list of port priorities for each slot.

[0048] Save the priority list to the register.

[0049] In some embodiments, in response to detecting a PCIe device inserted into the slot, selecting the corresponding port to establish a connection based on the test result further includes:

[0050] In response to detecting the insertion of a PCIe device into the slot, the highest priority port among multiple currently unused ports is determined according to the port priority list, and a connection is established between the PCIe device and the highest priority port.

[0051] In some embodiments, it also includes:

[0052] In response to a detected port error, determine if there is a free port currently available;

[0053] If no free ports are available, select the appropriate PCIe device based on traffic monitoring to reduce the bandwidth and report alarm information.

[0054] The present invention has one of the following beneficial technical effects: The solution proposed in this invention connects the CPU's PCIe PORT in the server to a unified PCIe switch. The PCIe external device does not indicate which PCIe link it comes from. The PCIe control chip can automatically match the PCIe link according to the PCIe device inserted by the customer by using the PCIe marging of the PCIe device under each PCIe link recorded in the register. The PCIe switch can realize automatic switching of PCIe links, reducing the impact on business. Attached Figure Description

[0055] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0056] Figure 1 A flowchart illustrating a PCIE link connection method provided in an embodiment of the present invention;

[0057] Figure 2 A schematic diagram of the structure of a PCIE link connection system provided for an embodiment of the present invention;

[0058] Figure 3 A schematic diagram of the structure of a computer device provided for an embodiment of the present invention;

[0059] Figure 4 A schematic diagram of the structure of a computer-readable storage medium provided for an embodiment of the present invention. Detailed Implementation

[0060] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0061] It should be noted that all uses of "first" and "second" in the embodiments of the present invention are for the purpose of distinguishing two entities or parameters with the same name but different names. It is clear that "first" and "second" are only for the convenience of expression and should not be construed as limiting the embodiments of the present invention. Subsequent embodiments will not explain this in detail.

[0062] According to one aspect of the present invention, embodiments of the present invention provide a PCIe link connection method, such as... Figure 1 As shown, it may include the following steps:

[0063] S1 connects each port of each CPU to each slot of the PCIe switch;

[0064] S2, Perform a margin test on each slot on the PCIe switch and save the test results to a register;

[0065] S3, in response to detecting a PCIe device inserted in the slot, select the corresponding port to establish a connection based on the test result.

[0066] The proposed solution connects all the PCIe ports of the CPU in the server to a single PCIe switch. This eliminates the distinction between PCIe links for external PCIe devices. The PCIe control chip can automatically match the PCIe link based on the PCIe device inserted by the customer, using the PCIe margins of the PCIe devices recorded in its registers. The PCIe switch can then automatically switch PCIe links, minimizing the impact on business operations.

[0067] In some embodiments, performing a margin test on each slot on the PCIe switch and saving the test results to a register further includes:

[0068] Perform a margin test on each slot of the PCIe switch to obtain a list of port priorities for each slot.

[0069] Save the priority list to the register.

[0070] In some embodiments, in response to detecting a PCIe device inserted into the slot, selecting the corresponding port to establish a connection based on the test result further includes:

[0071] In response to detecting the insertion of a PCIe device into the slot, the highest priority port among multiple currently unused ports is determined according to the port priority list, and a connection is established between the PCIe device and the highest priority port.

[0072] In some embodiments, it also includes:

[0073] In response to a detected port error, determine if there is a free port currently available;

[0074] If no free ports are available, select the appropriate PCIe device based on traffic monitoring to reduce the bandwidth and report alarm information.

[0075] Specifically, connect all the CPU's PCIe ports in the server to a PCIe switch, which in turn connects to the PCIe slots. When introducing external PCIe devices, test the PCIe margin on each PCIe slot and record the test device and margin data in the registers of the PCIe controller chip. This PCIe controller chip can record the PCIe device and PCIe margin data in its registers and use this data to automatically match the PCIe link for the external PCIe device. When the machine powers on, the PCIe controller chip automatically matches the PCIe link for the external PCIe device based on the margin data in the register. If one of the PCIe links reports a CE error, the switch chip can identify that the PCIe port is faulty and automatically switch to an idle PCIe link. If there is no idle PCIe port at this time, select a low-traffic PCIe device based on the PCIe device traffic monitoring to reduce bandwidth and minimize the impact on services. A BMC alarm should be issued promptly to prompt repair of the PCIe link.

[0076] As the number of PCIe slots increases, the PCIe margin of each PCIe link varies. All PCIe links are connected to a PCIe switch, which contains a PCIe control chip that records the PCIe margin data of different components on each PCIe link in its registers. When the server powers on, the PCIe control chip automatically calculates the link allocation scheme of the PCIe devices in the PCIe configuration, so that external devices are automatically matched to the PCIe links. This ensures that the product's PCIe devices can be matched with the optimal PCIe margin, thereby enabling the PCIe devices to obtain greater performance and stability.

[0077] In some embodiments, the Switch includes a PCIe controller chip, registers, multiple upstream ports and several downstream ports, which are connected via a virtual PCI-PCI bridge.

[0078] The solution provided by this invention connects all CPU ports in the server to a unified PCIe switch, without revealing which PCIe link it originates from. When a PCIe device is inserted into a fixed slot, the PCIe switch can automatically switch to the PCIe link with the better margin based on the PCIe device's margin test results in the register, and mark this PCIe link as used. When a second PCIe device is inserted into the next fixed slot, the PCIe switch can automatically switch to the PCIe link with the better margin from the remaining PCIe links based on the PCIe device's margin test results in the register, and mark this PCIe link as used, and so on. This ensures that PCIe devices prioritize using the PCIe link with the best margin. For customers, the optimal PCIe link can be obtained no matter which slot is used, improving PCIe performance and product stability.

[0079] Based on the same inventive concept, according to another aspect of the present invention, embodiments of the present invention also provide a PCIE link connection system 400, such as... Figure 2 As shown, it includes:

[0080] Connection module 401 is configured to connect each port of each CPU to each slot of the PCIe switch;

[0081] Test module 402 is configured to perform a margin test on each slot on the PCIe switch and save the test results to a register;

[0082] Select module 403, configured to select the corresponding port to establish a connection in response to detecting a PCIe device inserted in the slot, based on the test results.

[0083] In some embodiments, the test module 402 is further configured to:

[0084] Perform a margin test on each slot of the PCIe switch to obtain a list of port priorities for each slot.

[0085] Save the priority list to the register.

[0086] In some embodiments, the selection module 403 is further configured to:

[0087] In response to detecting the insertion of a PCIe device into the slot, the highest priority port among multiple currently unused ports is determined according to the port priority list, and a connection is established between the PCIe device and the highest priority port.

[0088] In some embodiments, a detection module is also included, configured to:

[0089] In response to a detected port error, determine if there is a free port currently available;

[0090] If no free ports are available, select the appropriate PCIe device based on traffic monitoring to reduce the bandwidth and report alarm information.

[0091] Based on the same inventive concept, according to another aspect of the present invention, such as Figure 3 As shown, embodiments of the present invention also provide a computer device 501, comprising:

[0092] At least one processor 520; and

[0093] Memory 510 stores a computer program 511 that can run on a processor. When the processor 520 executes the program, it performs the following steps:

[0094] S1 connects each port of each CPU to each slot of the PCIe switch;

[0095] S2, Perform a margin test on each slot on the PCIe switch and save the test results to a register;

[0096] S3, in response to detecting a PCIe device inserted in the slot, select the corresponding port to establish a connection based on the test result.

[0097] The proposed solution connects all the PCIe ports of the CPU in the server to a single PCIe switch. This eliminates the distinction between PCIe links for external PCIe devices. The PCIe control chip can automatically match the PCIe link based on the PCIe device inserted by the customer, using the PCIe margins of the PCIe devices recorded in its registers. The PCIe switch can then automatically switch PCIe links, minimizing the impact on business operations.

[0098] In some embodiments, performing a margin test on each slot on the PCIe switch and saving the test results to a register further includes:

[0099] Perform a margin test on each slot of the PCIe switch to obtain a list of port priorities for each slot.

[0100] Save the priority list to the register.

[0101] In some embodiments, in response to detecting a PCIe device inserted into the slot, selecting the corresponding port to establish a connection based on the test result further includes:

[0102] In response to detecting the insertion of a PCIe device into the slot, the highest priority port among multiple currently unused ports is determined according to the port priority list, and a connection is established between the PCIe device and the highest priority port.

[0103] In some embodiments, it also includes:

[0104] In response to a detected port error, determine if there is a free port currently available;

[0105] If no free ports are available, select the appropriate PCIe device based on traffic monitoring to reduce the bandwidth and report alarm information.

[0106] Specifically, connect all the CPU's PCIe ports in the server to a PCIe switch, which in turn connects to the PCIe slots. When introducing external PCIe devices, test the PCIe margin on each PCIe slot and record the test device and margin data in the registers of the PCIe controller chip. This PCIe controller chip can record the PCIe device and PCIe margin data in its registers and use this data to automatically match the PCIe link for the external PCIe device. When the machine powers on, the PCIe controller chip automatically matches the PCIe link for the external PCIe device based on the margin data in the register. If one of the PCIe links reports a CE error, the switch chip can identify that the PCIe port is faulty and automatically switch to an idle PCIe link. If there is no idle PCIe port at this time, select a low-traffic PCIe device based on the PCIe device traffic monitoring to reduce bandwidth and minimize the impact on services. A BMC alarm should be issued promptly to prompt repair of the PCIe link.

[0107] As the number of PCIe slots increases, the PCIe margin of each PCIe link varies. All PCIe links are connected to a PCIe switch, which contains a PCIe control chip that records the PCIe margin data of different components on each PCIe link in its registers. When the server powers on, the PCIe control chip automatically calculates the link allocation scheme of the PCIe devices in the PCIe configuration, so that external devices are automatically matched to the PCIe links. This ensures that the product's PCIe devices can be matched with the optimal PCIe margin, thereby enabling the PCIe devices to obtain greater performance and stability.

[0108] In some embodiments, the Switch includes a PCIe controller chip, registers, multiple upstream ports and several downstream ports, which are connected via a virtual PCI-PCI bridge.

[0109] The solution provided by this invention connects all CPU ports in the server to a unified PCIe switch, without revealing which PCIe link it originates from. When a PCIe device is inserted into a fixed slot, the PCIe switch can automatically switch to the PCIe link with the better margin based on the PCIe device's margin test results in the register, and mark this PCIe link as used. When a second PCIe device is inserted into the next fixed slot, the PCIe switch can automatically switch to the PCIe link with the better margin from the remaining PCIe links based on the PCIe device's margin test results in the register, and mark this PCIe link as used, and so on. This ensures that PCIe devices prioritize using the PCIe link with the best margin. For customers, the optimal PCIe link can be obtained no matter which slot is used, improving PCIe performance and product stability.

[0110] Based on the same inventive concept, according to another aspect of the present invention, such as Figure 4 As shown, embodiments of the present invention also provide a computer-readable storage medium 601, which stores a computer program 610. When the computer program 610 is executed by a processor, it performs the following steps:

[0111] S1 connects each port of each CPU to each slot of the PCIe switch;

[0112] S2, Perform a margin test on each slot on the PCIe switch and save the test results to a register;

[0113] S3, in response to detecting a PCIe device inserted in the slot, select the corresponding port to establish a connection based on the test result.

[0114] The proposed solution connects all the PCIe ports of the CPU in the server to a single PCIe switch. This eliminates the distinction between PCIe links for external PCIe devices. The PCIe control chip can automatically match the PCIe link based on the PCIe device inserted by the customer, using the PCIe margins of the PCIe devices recorded in its registers. The PCIe switch can then automatically switch PCIe links, minimizing the impact on business operations.

[0115] In some embodiments, performing a margin test on each slot on the PCIe switch and saving the test results to a register further includes:

[0116] Perform a margin test on each slot of the PCIe switch to obtain a list of port priorities for each slot.

[0117] Save the priority list to the register.

[0118] In some embodiments, in response to detecting a PCIe device inserted into the slot, selecting the corresponding port to establish a connection based on the test result further includes:

[0119] In response to detecting the insertion of a PCIe device into the slot, the highest priority port among multiple currently unused ports is determined according to the port priority list, and a connection is established between the PCIe device and the highest priority port.

[0120] In some embodiments, it also includes:

[0121] In response to a detected port error, determine if there is a free port currently available;

[0122] If no free ports are available, select the appropriate PCIe device based on traffic monitoring to reduce the bandwidth and report alarm information.

[0123] Specifically, connect all the CPU's PCIe ports in the server to a PCIe switch, which in turn connects to the PCIe slots. When introducing external PCIe devices, test the PCIe margin on each PCIe slot and record the test device and margin data in the registers of the PCIe controller chip. This PCIe controller chip can record the PCIe device and PCIe margin data in its registers and use this data to automatically match the PCIe link for the external PCIe device. When the machine powers on, the PCIe controller chip automatically matches the PCIe link for the external PCIe device based on the margin data in the register. If one of the PCIe links reports a CE error, the switch chip can identify that the PCIe port is faulty and automatically switch to an idle PCIe link. If there is no idle PCIe port at this time, select a low-traffic PCIe device based on the PCIe device traffic monitoring to reduce bandwidth and minimize the impact on services. A BMC alarm should be issued promptly to prompt repair of the PCIe link.

[0124] As the number of PCIe slots increases, the PCIe margin of each PCIe link varies. All PCIe links are connected to a PCIe switch, which contains a PCIe control chip that records the PCIe margin data of different components on each PCIe link in its registers. When the server powers on, the PCIe control chip automatically calculates the link allocation scheme of the PCIe devices in the PCIe configuration, so that external devices are automatically matched to the PCIe links. This ensures that the product's PCIe devices can be matched with the optimal PCIe margin, thereby enabling the PCIe devices to obtain greater performance and stability.

[0125] In some embodiments, the Switch includes a PCIe controller chip, registers, multiple upstream ports and several downstream ports, which are connected via a virtual PCI-PCI bridge.

[0126] The solution provided by this invention connects all CPU ports in the server to a unified PCIe switch, without revealing which PCIe link it originates from. When a PCIe device is inserted into a fixed slot, the PCIe switch can automatically switch to the PCIe link with the better margin based on the PCIe device's margin test results in the register, and mark this PCIe link as used. When a second PCIe device is inserted into the next fixed slot, the PCIe switch can automatically switch to the PCIe link with the better margin from the remaining PCIe links based on the PCIe device's margin test results in the register, and mark this PCIe link as used, and so on. This ensures that PCIe devices prioritize using the PCIe link with the best margin. For customers, the optimal PCIe link can be obtained no matter which slot is used, improving PCIe performance and product stability.

[0127] Finally, it should be noted that those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods.

[0128] Furthermore, it should be understood that the computer-readable storage medium (e.g., memory) described herein may be volatile memory or non-volatile memory, or may include both volatile memory and non-volatile memory.

[0129] Those skilled in the art will also understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the functionality of various illustrative components, blocks, modules, circuits, and steps has been generally described. Whether this functionality is implemented as software or as hardware depends on the specific application and the design constraints imposed on the system as a whole. Those skilled in the art can implement the functionality in various ways for each specific application, but such implementation decisions should not be construed as departing from the scope of the embodiments disclosed herein.

[0130] The above are exemplary embodiments disclosed in this invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments of this invention as defined by the claims. The functions, steps, and / or actions of the methods according to the disclosed embodiments described herein do not need to be performed in any particular order. Furthermore, although the elements disclosed in the embodiments of this invention may be described or claimed individually, they may be understood as multiple unless explicitly limited to a singular number.

[0131] It should be understood that, as used herein, the singular form “a” is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, “and / or” refers to any and all possible combinations of one or more of the associated listed items.

[0132] The embodiment numbers disclosed in the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0133] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0134] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. A PCIe link connection method, characterized in that, Includes the following steps: Connect each port of each CPU to each slot of the PCIe switch; Perform a margin test on each slot on the PCIe switch and save the test results to a register; In response to the detection of a PCIe device inserted into the slot, a connection is established by selecting the corresponding port based on the test results; Performing a margin test on each slot of the PCIe switch and saving the test results to a register further includes: Perform a margin test on each slot of the PCIe switch to obtain a list of port priorities for each slot. Save the priority list to the register; In response to detecting a PCIe device inserted into the slot, the system selects the corresponding port to establish a connection based on the test result, further including: In response to detecting the insertion of a PCIe device into the slot, the highest priority port among multiple currently unused ports is determined according to the port priority list, and a connection is established between the PCIe device and the highest priority port. Specifically, when a PCIe device is inserted into a slot, the PCIe Switch automatically selects and switches to the PCIe link with the better margin based on the PCIe device's margin test results in the register, and marks this PCIe link as used in the register. When a second PCIe device is inserted into the next slot, the PCIe Switch automatically switches to the PCIe link with the better margin from the remaining PCIe links based on the PCIe device's margin test results in the register, and marks this PCIe link as used in the register, and so on, ensuring that PCIe devices always prioritize using the PCIe link with the best margin.

2. The method as described in claim 1, characterized in that, Also includes: In response to a detected port error, determine if there is a free port currently available; If no free ports are available, select the appropriate PCIe device based on traffic monitoring to reduce the bandwidth and report alarm information.

3. A PCIe link connection system, characterized in that, include: The connection module is configured to connect each port of each CPU to each slot of the PCIe switch; The test module is configured to perform a margin test on each slot on the PCIe switch and save the test results to a register. The module is configured to select the corresponding port to establish a connection in response to the detection of a PCIe device inserted into the slot, based on the test results. The test module is also configured as follows: Perform a margin test on each slot of the PCIe switch to obtain a list of port priorities for each slot. Save the priority list to the register; The selection module is also configured as follows: In response to detecting the insertion of a PCIe device into the slot, the highest priority port among multiple currently unused ports is determined according to the port priority list, and a connection is established between the PCIe device and the highest priority port. Specifically, when a PCIe device is inserted into a slot, the PCIe Switch automatically selects and switches to the PCIe link with the better margin based on the PCIe device's margin test results in the register, and marks this PCIe link as used in the register. When a second PCIe device is inserted into the next slot, the PCIe Switch automatically switches to the PCIe link with the better margin from the remaining PCIe links based on the PCIe device's margin test results in the register, and marks this PCIe link as used in the register, and so on, ensuring that PCIe devices always prioritize using the PCIe link with the best margin.

4. The system as described in claim 3, characterized in that, It also includes a detection module, configured as follows: In response to a detected port error, determine if there is a free port currently available; If no free ports are available, select the appropriate PCIe device based on traffic monitoring to reduce the bandwidth and report alarm information.

5. A computer device, comprising: At least one processor; as well as A memory storing a computer program executable on the processor, characterized in that the processor executes the steps of the method as described in any one of claims 1-2 when executing the program.

6. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it performs the steps of the method as described in any one of claims 1-2.

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