RFSOC-based vpX high-performance digital synthesis board

Abstract

This invention discloses a VPX high-performance digital integrated board based on RFSOC, belonging to the technical field of signal acquisition, processing, and playback. It includes 2 RFSOCs, 3 clock chips, 8 DDR4 SDDRAMs, 1 FPGA, 1 DSP, 4 DDR3 SDDRAMs, 7 Flash chips, 1 GBE PHY, 1 PCIE switch, 1 MCU chip, and external physical interfaces. This invention can realize functions such as multi-channel ADC synchronous acquisition, multi-channel DAC synchronous playback, high-speed data processing, large-capacity high-speed data buffer, and high-speed data transmission.

Description

Technical Field

[0001] This invention belongs to the technical field of signal acquisition, processing and playback, and specifically relates to a VPX high-performance digital integrated board based on RFSOC. Background Technology

[0002] The VPX high-performance digital integrated board integrates ADC sampling, signal processing, and DAC playback functions, primarily used in wideband signal processing, wideband signal generation, and wideband signal reconnaissance and analysis. RFSOC, developed by Xilinx, is a radio frequency system-on-a-chip (SoC) with a multi-core ARM processor, multi-channel ADC, multi-channel DAC, numerous DSP slices, and high-speed interfaces such as GTY. With the continuous increase in radar signal bandwidth and the number of transceiver channels, the increasing complexity of processing algorithms, and the diversification of operating modes, the requirements for the number and performance of ADC and DAC channels, signal processing capabilities, data transmission capabilities, and data buffering capabilities are constantly increasing. Harsh operating environments such as airborne and shipborne applications place higher demands on the integration, reliability, and environmental adaptability of digital integrated boards. The VPX structure improves the board's shock resistance; the VPX backplane uses high-performance, high-speed serial connectors, improving the board's external interface capabilities; the VPX specification provides a larger current capacity for single boards, supporting the integration of more ADC acquisition, DAC playback, and signal processing resources.

[0003] Therefore, it is necessary to develop a VPX high-performance digital integrated board based on RFSOC. Summary of the Invention

[0004] In view of this, the present invention provides a VPX high-performance digital integrated board based on RFSOC, which can realize functions such as multi-channel ADC synchronous acquisition, multi-channel DAC synchronous playback, high-speed data processing, large-capacity high-speed data buffer, and high-speed data transmission.

[0005] The technical solution for implementing this invention is as follows: A high-performance digital integrated board based on RFSOC, comprising 2 RFSOC chips, 3 clock chips, 8 DDR4 SDDRAM chips, 1 FPGA chip, 1 DSP chip, 4 DDR3 SDDRAM chips, 7 Flash chips, 1 GBE PHY chip, 1 PCIE Switch chip, 1 MCU chip, and external physical interfaces; the Flash chips include 6 QSPI Flash chips and 1 SPI Flash chip; the external physical interfaces include a set of VPX interfaces, which include P0, P1, P2, P3, P4, P5, and P6.

[0006] The two RFSOC chips are RFSOC chip I and RFSOC chip II, and are interconnected via 12x LVDS.

[0007] The RFSOC chip I is externally connected to four DDR4 SDRAM chips to achieve high-speed caching of large-capacity data; the RFSOC chip I is externally connected to two QSPI Flash chips to store the program in the RFSOC chip; the RFSOC chip I is interconnected with the GBE PHY chip through the RGMII interface; the RFSOC chip I is connected to eight ADC synchronous acquisition channels and four DAC synchronous playback channels; the RFSOC chip I is interconnected with the FPGA chip through one 8xGTY and one 24xLVDS interface; the RFSOC chip I is interconnected with the PCIe switch through one 4x PCIe Gen2.0 interface.

[0008] The RFSOC chip II is equipped with four external DDR4 SDRAM chips for high-speed caching of large-capacity data; two external QSPI Flash chips are used to store the RFSOC program; the RFSOC chip II is interconnected with the GBE PHY chip through the RGMII interface; the RFSOC chip II implements eight ADC synchronous acquisition channels and four DAC synchronous playback channels; the RFSOC chip II is interconnected with the FPGA chip through one 8xGTY and one 24x LVDS interface; the RFSOC chip II is interconnected with the PCIe switch through one 4x PCIe Gen2.0 interface.

[0009] The DSP chip is externally connected to an SPI Flash chip to store the DSP program; the DSP chip is externally connected to four DDR3 SDRAM chips to implement high-speed cache for large-capacity data; the DSP chip is interconnected with a PCIe switch through a 2x PCIe Gen2.0 interface; the DSP chip is interconnected with a GBE PHY through an SGMII interface to implement a 1000BASE-T gigabit Ethernet port; the DSP chip is interconnected with the FPGA through a 4x SRIO interface and an EMIF interface respectively.

[0010] The PCIe switch chip is interconnected with two RFSOC chips and one FPGA chip via three 4x PCIe Gen2.0 interfaces, and with the DSP chip via one 2x PCIe Gen2.0 interface.

[0011] The GBE PHY chip interconnects with the DSP chip through an SGMII interface, and the GBE PHY chip interconnects with the RGSOC chip through an RGMII interface, realizing a 1000BASE-T gigabit Ethernet interface and outputting it through a VPX P4 connector.

[0012] Two QSPI Flash chips are connected to the FPGA chip to realize program storage and loading in the FPGA chip; the FPGA chip is interconnected with two RFSOC chips through one 8x GTY interface and one 24x LVDS interface respectively; the FPGA chip is interconnected with the DSP chip through one 4x SRIO interface and one EMIF interface respectively; the FPGA chip is interconnected with the PCIe switch chip through one 4x PCIe Gen2.0 interface.

[0013] The FPGA chip is interconnected with the VPX interface P1 through one 8x GTY, one 6x LVDS and two RS422 full-duplex interfaces; the FPGA chip is interconnected with P2 through one 8x GTY, one 6x LVDS and two RS422 full-duplex interfaces; the FPGA chip is interconnected with P3, P4 and P5 through one 8x GTY and one 8x LVDS respectively.

[0014] The MCU chip is interconnected with the VPX connector P0 via I2C to realize the IPMI management bus.

[0015] Furthermore, the external physical interfaces also include 25 JSMP interfaces.

[0016] The signal of each ADC synchronous acquisition channel is input through a JSMP interface, and after being converted from single-ended to differential by a balun, it is input to the corresponding pin of the RFSOC chip.

[0017] Each DAC synchronous playback channel output by the RFSOC chip is converted from differential to single-ended by a balun before being output through a JSMP interface.

[0018] Furthermore, the ADC and DAC sampling use a low-speed reference clock provided by the clock chip LMK04828, or a high-speed sampling clock generated by the clock chip LMX2594 and driven by ADCLK944.

[0019] Furthermore, the external physical interface also includes a J30J-21ZKW-J interface, which defines DSP JTAG signals, FPGA JTAG signals and RS232 signals for board debugging and program updates.

[0020] Beneficial effects:

[0021] 1. This invention discloses a VPX high-performance digital integrated board based on RFSOC, comprising 2 RFSOCs, 3 clock chips, 8 DDR4 SDDRAMs, 1 FPGA, 1 DSP, 4 DDR3 SDDRAMs, 7 Flash chips, 1 GBE PHY, 1 PCIE switch, 1 MCU chip, and external physical interfaces; this invention can realize functions such as multi-channel ADC synchronous acquisition, multi-channel DAC synchronous playback, high-speed data processing, large-capacity high-speed data buffer, and high-speed data transmission.

[0022] 2. The present invention discloses a VPX high-performance digital integrated board based on RFSOC, which has the capability of multi-channel ADC synchronous acquisition. It adopts two Xilinx RFSOC chips XCZU47DR-2FFVE1156I, each of which supports 8 channels of 14-bit ADC synchronous acquisition, and the ADC sampling rate can reach up to 5Gsps. Through synchronous clock design, a total of 16 channels of ADC synchronous acquisition can be realized.

[0023] 3. This invention discloses a VPX high-performance digital integrated board based on RFSOC, which has multi-channel DAC synchronous playback capability. It uses two Xilinx RFSOC chips XCZU47DR-2FFVE1156I, each of which supports 8 channels of 14-bit DAC synchronous playback, and the DAC sampling rate can reach up to 9.85Gsps. In this design, due to the limitation of the PCB area, each RFSOC chip only uses 4 channels of DAC, so a total of 8 channels of DAC synchronous playback can be realized.

[0024] 4. This invention discloses a high-performance digital synthesis board based on RFSOC, possessing high-speed data processing capabilities. It employs two Xilinx RFSOC chips (XCZU47DR-2FFVE1156I), one TI TMS320C6678 DSP, and one Xilinx XCVU13P-2FHGB2104I FPGA. Each RFSOC chip has 4272 DSP slices, providing very powerful processing capabilities. The TI TMS320C6678 DSP has 8 cores with a core clock speed of up to 1.4GHz, and each DSP theoretically has a processing capacity of 358.4 GMAC fixed-point operations per second or 179.2 GFLOP floating-point operations per second. The FPGA (model XCVU13P-2FHGB2104I FPGA) has 12288 DSP slices, also possessing very powerful processing capabilities.

[0025] 5. This invention discloses a VPX high-performance digital integrated board based on RFSOC, which has a large-capacity, high-speed data cache capability. Each RFSOC chip has four external 1GB DDR4 SDRAM chips, achieving a total data cache capacity of 8GB. The DDR4 interface of each RFSOC chip has a speed of 2.4Gbps and a bit width of 64bits, with a theoretical access bandwidth of 19.2GB / s. The DSP has four external 1GB DDR3 SDRAM chips, achieving a data cache capacity of 4GB. The DSP's DDR3 interface has a speed of 1.6Gbps and a bit width of 64bits, with a theoretical access bandwidth of 12.8GB / s, resulting in a very high memory access speed.

[0026] 6. The present invention discloses a VPX high-performance digital integrated board based on RFSOC, which has high-speed data transmission capability. Each RFSOC chip and FPGA are interconnected by 8x GTY, and the peak baud rate of GTY is 28.21Gbound. There is one 8x GTY between the FPGA and VPX connectors P1, P2, P3, P4 and P5 for board interconnection. Each 8x GTY can achieve a theoretical transmission rate of 10GB / s. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the digital integrated board of the present invention. Detailed Implementation

[0028] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0029] This invention provides a high-performance digital integrated board based on RFSOC, comprising 2 RFSOC chips, 3 clock chips, 8 DDR4 SDDRAM chips, 1 FPGA chip, 1 DSP chip, 4 DDR3 SDDRAM chips, 7 Flash chips, 1 GBE PHY chip, 1 PCIE Switch chip, 1 MCU chip, and external physical interfaces; the Flash chips include 6 QSPI Flash chips and 1 SPI Flash chip; the external physical interfaces include a set of VPX interfaces, which include P0, P1, P2, P3, P4, P5, and P6.

[0030] The two RFSOC chips are RFSOC chip I and RFSOC chip II, and are interconnected via 12x LVDS.

[0031] The RFSOC chip I is externally connected to four DDR4 SDRAM chips to achieve high-speed caching of large-capacity data; the RFSOC chip I is externally connected to two QSPI Flash chips to store the program in the RFSOC chip; the RFSOC chip I is interconnected with the GBE PHY chip through the RGMII interface; the RFSOC chip I is connected to eight ADC synchronous acquisition channels and four DAC synchronous playback channels; the RFSOC chip I is interconnected with the FPGA chip through one 8xGTY and one 24xLVDS interface; the RFSOC chip I is interconnected with the PCIe switch through one 4x PCIe Gen2.0 interface.

[0032] The RFSOC chip II is equipped with four external DDR4 SDRAM chips for high-speed caching of large-capacity data; two external QSPI Flash chips are used to store the RFSOC program; the RFSOC chip II is interconnected with the GBE PHY chip through the RGMII interface; the RFSOC chip II implements eight ADC synchronous acquisition channels and four DAC synchronous playback channels; the RFSOC chip II is interconnected with the FPGA chip through one 8xGTY and one 24x LVDS interface; the RFSOC chip II is interconnected with the PCIe switch through one 4x PCIe Gen2.0 interface.

[0033] The DSP chip is externally connected to an SPI Flash chip to store the DSP program; the DSP chip is externally connected to four DDR3 SDRAM chips to implement high-speed cache for large-capacity data; the DSP chip is interconnected with a PCIe switch through a 2x PCIe Gen2.0 interface; the DSP chip is interconnected with a GBE PHY through an SGMII interface to implement a 1000BASE-T gigabit Ethernet port; the DSP chip is interconnected with the FPGA through a 4x SRIO interface and an EMIF interface respectively.

[0034] The PCIe switch chip is interconnected with two RFSOC chips and one FPGA chip via three 4x PCIe Gen2.0 interfaces, and with the DSP chip via one 2x PCIe Gen2.0 interface.

[0035] The GBE PHY chip interconnects with the DSP chip through an SGMII interface, and the GBE PHY chip interconnects with the RGSOC chip through an RGMII interface, realizing a 1000BASE-T gigabit Ethernet interface and outputting it through a VPX P4 connector.

[0036] Two QSPI Flash chips are connected to the FPGA chip to realize program storage and loading in the FPGA chip; the FPGA chip is interconnected with two RFSOC chips through one 8x GTY interface and one 24x LVDS interface respectively; the FPGA chip is interconnected with the DSP chip through one 4x SRIO interface and one EMIF interface respectively; the FPGA chip is interconnected with the PCIe switch chip through one 4x PCIe Gen2.0 interface.

[0037] The FPGA chip is interconnected with the VPX interface P1 through one 8x GTY, one 6x LVDS and two RS422 full-duplex interfaces; the FPGA chip is interconnected with P2 through one 8x GTY, one 6x LVDS and two RS422 full-duplex interfaces; the FPGA chip is interconnected with P3, P4 and P5 through one 8x GTY and one 8x LVDS respectively.

[0038] The MCU chip is interconnected with the VPX connector P0 via I2C to realize the IPMI management bus.

[0039] This invention uses RFSOC, clock chip, DSP, FPGA, PCIE switch chip, GBE PHY chip, large-capacity DDR3 SDRAM, large-capacity DDR4 SDRAM, SPI Flash and other components to build a VPX high-performance digital integrated board, which realizes functions such as multi-channel ADC synchronous acquisition, multi-channel DAC synchronous playback, high-speed data processing, large-capacity high-speed data buffer and high-speed data transmission.

[0040] The structure of the present invention (see) Figure 1The main components include two Xilinx RFSOC chips XCZU47DR-2FFVE1156I, one TI LMK04828 clock chip, one TI LMX2594 clock chip, one ADI ADCLK946 clock driver chip, eight Micron DDR4 SDRAM chips (model MT40A512M16HA-83E), one TI TMS320C6678 DSP, four Micron DDR3 SDRAM chips (model MT41K512M16TW-107IT), seven Micron SPI Flash chips (model MT25QU02GCBB8E12-0SIT), one PLX PCIe switch (model PEX8619), one Marvell GBE PHY chip (model 88E1111), and one Xilinx Virtex chip. The system consists of an UltraScale+ series FPGA (model XCVU13P-2FHGB2104I), an STMicroelectronics MCU chip (model STM32L071CZT6), and external physical interfaces (one J30J-21ZKP interface, 25 JSMP interfaces, and a set of VPX interfaces, including P0, P1, P2, P3, P4, P5, and P6) and other auxiliary circuits. Its software mainly includes: clock chip configuration, ADC configuration and data acquisition, DAC configuration and data playback, GBE data transmission, PCIE Switch configuration, PCIE data transmission, SRIO data transmission, GTY data transmission, LVDS data transmission, DDR3 SDRAM memory access, and DDR4 SDRAM memory access. The board type is the VPX 6U standard board. The operating platform is an industrial control computer platform.

[0041] The functions of multi-channel ADC synchronous acquisition, multi-channel DAC synchronous playback, high-speed data processing, large-capacity high-speed data buffer, and high-speed data transmission of this invention are achieved through the following technical solutions:

[0042] To achieve multi-channel ADC synchronous acquisition capability, two Xilinx RFSOC chips XCZU47DR-2FFVE1156I are used. Each RFSOC supports 8 channels of 14-bit ADC synchronous acquisition, and the ADC sampling rate can reach up to 5Gsps. Through synchronous clock design, a total of 16 channels of ADC synchronous acquisition can be achieved.

[0043] To achieve multi-channel DAC synchronous playback capability, two Xilinx RFSOC chips XCZU47DR-2FFVE1156I are used. Each RFSOC supports 8 channels of 14-bit DAC synchronous playback, and the DAC sampling rate can reach up to 9.85Gsps. Due to the limitation of PCB area in this design, each RFSOC chip only uses 4 channels of DAC, so a total of 8 channels of DAC synchronous playback can be achieved.

[0044] To achieve high-speed data processing capabilities, two Xilinx RFSOC chips (XCZU47DR-2FFVE1156I), one TI TMS320C6678 DSP, and one Xilinx XCVU13P-2FHGB2104I FPGA are used. Each RFSOC chip has 4272 DSP slices, providing very powerful processing capabilities. The TI TMS320C6678 DSP has 8 cores with a core clock speed of up to 1.4GHz, and each DSP has a theoretical processing capacity of 358.4 GMAC fixed-point operations per second or 179.2 GFLOP floating-point operations per second. The FPGA (model XCVU13P-2FHGB2104I FPGA) has 12288 DSP slices, also providing very powerful processing capabilities.

[0045] To achieve high-capacity, high-speed data caching capabilities, each RFSOC chip is externally coupled with four 1GB DDR4 SDRAM chips, resulting in a total data caching capacity of 8GB. Each RFSOC chip has a DDR4 interface speed of 2.4Gbps and a bit width of 64 bits, with a theoretical access bandwidth of 19.2GB / s. The DSP is externally coupled with four 1GB DDR3 SDRAM chips, achieving a 4GB data caching capacity. The DSP's DDR3 interface speed is 1.6Gbps and a bit width of 64 bits, with a theoretical access bandwidth of 12.8GB / s, resulting in very high memory access speeds.

[0046] To achieve high-speed data transmission capability, each RFSOC chip and FPGA are interconnected using 8x GTY, with a peak baud rate of 28.21 Gbound. There is one 8x GTY between the FPGA and each of the VPX connectors P1, P2, P3, P4, and P5 for board-to-board interconnection. Each 8x GTY can achieve a theoretical transmission rate of 10 GB / s.

[0047] This invention constructs a high-performance digital integrated board using the following hardware structure on a standard VPX 6U board: Two Xilinx RFSOC chips XCZU47DR-2FFVE1156I are used to achieve 16-channel ADC synchronous acquisition and 8-channel DAC synchronous playback; each ADC signal is input through a JSMP and then converted from single-ended to differential by a balun before being input to the corresponding pin of the RFSOC chip; each DAC signal output from the RFSOC chip is converted from differential to single-ended by a balun before being output through a JSMP; each RFSOC chip is externally connected to two Micron Flash chips (model MT25QU02). The GCBB8E12-0SIT chip stores the program; each RFSOC chip is externally connected to four Micron DDR4 SDRAM chips (model MT40A512M16HA-83E) to achieve high-speed caching of large-capacity data; RFSOC chip I can configure the LMK04828 clock chip to output the reference clock frequency required for the operation of the internal PLL of the RFSOC, and the LMK04828 can use the clock provided by the TXCO or JSMP connector as the reference clock; RFSOC chip I can configure the LMX2594 clock chip to output a sampling clock that meets the sampling rate requirements; RFSOC chip I communicates with GBE via the RGMII interface. The PHY interconnect can achieve a 1000BASE-T gigabit Ethernet port via the VPX P4 interface; the two RFSOC chips are interconnected via 12x LVDS; the two RFSOC chips are connected to the FPGA via 8x GTY and 24x LVDS respectively; the two RFSOC chips are interconnected to the PCIe switch via a 4x PCIe Gen2.0 interface respectively; the board uses a TI TMS320C6678 DSP to implement high-performance digital signal processing functions; the DSP is externally connected to a Micron Flash chip (model MT25QU02GCBB8E12-0SIT) to store the DSP program; the DSP is externally connected to four Micron DDR3 SDRAM chips (model MT41K512M16TW-107IT); the DSP is interconnected to the FPGA via a 4x SRIO and EMIF, the SRIO interface operates in 5Gbound full-duplex mode with a theoretical transmission bandwidth of 2GB / s; the DSP is connected via a 2x PCIe Gen2 interface.The DSP is interconnected with a PCIe switch. The PCIe interface operates in 5Gbound full-duplex mode with a theoretical transmission bandwidth of 1GB / s. The DSP is interconnected with a GBE PHY chip (model 88E1111) via an SGMII interface. A 1000BASE-T gigabit Ethernet port can be implemented via VPX P4. The SGMII interface operates in 1Gbound full-duplex mode with a theoretical transmission bandwidth of 125MB / s. A Xilinx FPGA (model XCVU13P-2FHGB2104I) is used. Two external SPI Flash chips (model MT41K512M16TW-107IT) are used for program storage. The FPGA is interconnected with VPX connectors P1, P2, P3, P4, and P5 via an 8x GTY interface. The GTY interface operates in 12.5Gbound full-duplex mode with a theoretical transmission bandwidth of 10GB / s. The FPGA is interconnected with two full-duplex RS422 interfaces and one 6x GTY interface. The LVDS is interconnected with VPX connectors P1 and P2, with a line rate of 1Gbps. The FPGA is interconnected with VPX connectors P3, P4, and P5 via one 8x LVDS, with a line rate of 1Gbps. The MCU is interconnected with VPX connector P0 to implement the IPMI management bus.

[0048] In summary, the above are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A RFSOC-based VPX high performance digital hybrid board, characterized in that, The system comprises two RFSOC chips, three clock chips, eight DDR4 SDDRAM chips, one FPGA chip, one DSP chip, four DDR3 SDDRAM chips, seven Flash chips, one GBE PHY chip, one PCIE Switch chip, one MCU chip, and external physical interfaces; the Flash chips comprise six QSPI Flash chips and one SPI Flash chip; the external physical interfaces comprise a set of VPX interfaces, including P0, P1, P2, P3, P4, P5 and P6; The two RFSOC chips are RFSOC chip I and RFSOC chip II, and are connected through 12x LVDS; The RFSOC chip I is externally connected with four DDR4 SDRAM chips to realize high-speed caching of large-capacity data, and is externally connected with two QSPI Flash chips to realize storage of programs in the RFSOC chip; the RFSOC chip I is connected with the GBE PHY chip through an RGMII interface; the RFSOC chip I is connected with eight ADC synchronous acquisition channels and four DAC synchronous playback channels; the RFSOC chip I is connected with the FPGA chip through an 8x GTY and a 24x LVDS interface; and the RFSOC chip I is connected with the PCIE switch through a 4x PCIE Gen2.0 interface; The RFSOC chip II is externally connected with four DDR4 SDRAM chips to realize high-speed caching of large-capacity data, and is externally connected with two QSPI Flash chips to realize storage of RFSOC programs; the RFSOC chip II is connected with the GBE PHY chip through an RGMII interface; the RFSOC chip II realizes eight ADC synchronous acquisition channels and four DAC synchronous playback channels; the RFSOC chip II is connected with the FPGA chip through an 8x GTY and a 24x LVDS interface; and the RFSOC chip II is connected with the PCIE switch through a 4x PCIE Gen2.0 interface; The DSP chip is externally connected with one SPI Flash chip to realize storage of DSP programs, and is externally connected with four DDR3 SDRAM chips to realize high-speed caching of large-capacity data; the DSP chip is connected with the PCIE switch through a 2x PCIE Gen2.0 interface; the DSP chip is connected with the GBE PHY through an SGMII interface to realize a 1000BASE-T gigabit Ethernet port; and the DSP chip is connected with the FPGA through a 4x SRIO interface and an EMIF interface, respectively; The PCIE switch chip is interconnected with two pieces of RFSOC chips and one piece of FPGA chip through three 4x PCIE Gen2.0 interfaces, and is interconnected with a DSP chip through a 2x PCIE Gen2.0 interface; The GBE PHY chip is interconnected with a DSP chip through an SGMII interface, and is interconnected with an RFSOC chip I through an RGMII interface, realizes a 1000BASE-T gigabit Ethernet interface and outputs through a VPX P4 connector; The FPGA chip is externally connected with two pieces of QSPI Flash chips, realizes program storage and loading in the FPGA chip, is interconnected with two pieces of RFSOC chips through one 8x GTY and one 24x LVDS interface respectively, is interconnected with a DSP chip through one 4x SRIO interface and one EMIF interface respectively, and is interconnected with a PCIE switch chip through one 4x PCIE Gen2.0 interface; The FPGA chip is interconnected with a VPX interface P1 through one 8x GTY, one 6x LVDS and two RS422 full-duplex interfaces, is interconnected with P2 through one 8x GTY, one 6x LVDS and two RS422 full-duplex interfaces, and is interconnected with P3, P4 and P5 through one 8x GTY and one 8x LVDS respectively; The MCU chip is interconnected with a VPX connector P0 through I2C, and realizes an IPMI management bus.

2. A RFSOC-based VPX high performance digital integrated board according to claim 1, wherein, The external physical interface further includes 25 JSMP interfaces; The signal of each ADC synchronous acquisition channel is input through a JSMP interface, and is converted from single-ended to differential by a balun and then input to the corresponding pin of the RFSOC chip; Each DAC synchronous playback channel output by the RFSOC chip is converted from differential to single-ended by a balun and then output through a JSMP interface.

3. A RFSOC-based VPX high performance digital integrated board according to claim 1, wherein, The ADC and DAC sampling use a low-speed reference clock provided by a clock chip LMK04828, or use a high-speed sampling clock generated by a clock chip LMX2594 and driven by an ADCLK944.

4. A RFSOC-based VPX high performance digital integrated board according to claim 1, wherein, The external physical interface further includes one J30J-21ZKW-J interface, and the J30J-21ZKW-J interface defines DSP JTAG signals, FPGA JTAG signals and RS232 signals, and is used for board debugging and program updating.

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