Method, device and equipment for arranging digital circuits

Abstract

The application relates to a digital circuit arrangement method, device and equipment, which comprises the following steps: obtaining a first CDL circuit net list corresponding to a circuit schematic diagram; the first CDL circuit net list contains at least one MOS tube of the circuit schematic diagram and connection relationship data of the at least one MOS tube; selecting at least one MOS tube combination from the first CDL circuit net list; the MOS tube combination is composed of MOS tubes with connection relationship; generating a target circuit schematic diagram according to the MOS tube combination and the circuit schematic diagram; each MOS tube of the target circuit schematic diagram contains each MOS tube of the circuit schematic diagram, and each MOS tube of each MOS tube combination is located in a region corresponding to the MOS tube combination. Based on the above, the application realizes the automation of the digital circuit arrangement process, and improves the efficiency and accuracy of processing the digital circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit computer-aided design, in particular to a digital circuit arrangement method, device and equipment. BACKGROUND

[0002] At present, in some digital circuit schematic diagrams, the connection relationship between MOS transistors is not represented by actual connection lines, but is represented by label names of line networks. Specifically, if the label names of two line networks are the same, the MOS transistors connected by the two line networks have a connection relationship. In such a digital circuit schematic diagram, although the MOS transistors are arranged in order, the connection relationship is not intuitive, and it is not convenient for the staff to analyze the circuit schematic diagram. Therefore, the circuit schematic diagram needs to be processed, and the staff moves the MOS transistors according to the connection relationship between the MOS transistors in the circuit schematic diagram, so that the MOS transistors having a connection relationship are placed together in the circuit schematic diagram.

[0003] However, the efficiency and accuracy of the method for processing the digital circuit are low. SUMMARY

[0004] In order to solve the problems of low arrangement efficiency and high labor cost of the digital circuit in the prior art, the present application provides a digital circuit arrangement method, device and equipment.

[0005] The technical solutions of the embodiments of the present application are as follows:

[0006] The embodiment of the present application provides a digital circuit arrangement method, which comprises the following steps:

[0007] Obtain a first CDL circuit netlist corresponding to the circuit schematic diagram; the first CDL circuit netlist comprises at least one MOS transistor of the circuit schematic diagram and connection relationship data of the at least one MOS transistor;

[0008] Select at least one MOS transistor combination from the first CDL circuit netlist; the MOS transistor combination is composed of MOS transistors having a connection relationship;

[0009] Generate a target circuit schematic diagram according to the MOS transistor combination and the circuit schematic diagram; the target circuit schematic diagram comprises each MOS transistor of the circuit schematic diagram, and each MOS transistor of each MOS transistor combination is located in a region corresponding to the MOS transistor combination.

[0010] The embodiment of the present application also provides a digital circuit arrangement device, which comprises:

[0011] The first CDL circuit netlist module is configured to acquire a first CDL circuit netlist corresponding to the circuit schematic diagram, wherein the first CDL circuit netlist comprises at least one MOS transistor of the circuit schematic diagram and connection relationship data of the at least one MOS transistor.

[0012] The MOS transistor combination selection module is configured to select at least one MOS transistor combination from the first CDL circuit netlist, wherein the MOS transistor combination is composed of MOS transistors having connection relationship.

[0013] The target circuit schematic diagram generation module is configured to generate a target circuit schematic diagram according to the MOS transistor combination and the circuit schematic diagram, wherein the target circuit schematic diagram comprises each MOS transistor of the circuit schematic diagram, and each MOS transistor of each MOS transistor combination is located in a corresponding region of the MOS transistor combination.

[0014] The embodiment of the present application further provides a digital circuit arrangement device, which comprises:

[0015] at least one processor; and

[0016] a memory in communication connection with the at least one processor; wherein

[0017] the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to:

[0018] acquire a first CDL circuit netlist corresponding to the circuit schematic diagram, wherein the first CDL circuit netlist comprises at least one MOS transistor of the circuit schematic diagram and connection relationship data of the at least one MOS transistor;

[0019] select at least one MOS transistor combination from the first CDL circuit netlist, wherein the MOS transistor combination is composed of MOS transistors having connection relationship.

[0020] generate a target circuit schematic diagram according to the MOS transistor combination and the circuit schematic diagram, wherein the target circuit schematic diagram comprises each MOS transistor of the circuit schematic diagram, and each MOS transistor of each MOS transistor combination is located in a corresponding region of the MOS transistor combination.

[0021] The embodiment of the present application adopts the technical solution, acquires the first CDL circuit netlist corresponding to the circuit schematic diagram; the first CDL circuit netlist contains at least one MOS tube of the circuit schematic diagram and connection relationship data of the at least one MOS tube; at least one MOS tube combination is selected from the first CDL circuit netlist; the MOS tube combination is composed of MOS tubes with connection relationship; the target circuit schematic diagram is generated according to the MOS tube combination and the circuit schematic diagram; each MOS tube of the target circuit schematic diagram contains each MOS tube of the circuit schematic diagram, and each MOS tube of each MOS tube combination is located in the area corresponding to each MOS tube combination. Based on this, the present application realizes the automation of the digital circuit arrangement process, so that the present application improves the efficiency and accuracy of processing digital circuits. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only a part of the embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of the provided drawings.

[0023] Figure 1 Figure 1 is a flowchart of a digital circuit arrangement method provided by the embodiment of the present application;

[0024] Figure 2 is a structural schematic diagram of a digital circuit arrangement device provided by the embodiment of the present application;

[0025] Figure 3 is a structural schematic diagram of a digital circuit arrangement device provided by the embodiment of the present application. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0027] Figure 1 is a flowchart of a digital circuit arrangement method provided by the embodiment of the present application. As shown in Figure 1 , the present flowchart includes:

[0028] Step 101: obtaining a first CDL circuit netlist corresponding to the circuit schematic; the first CDL circuit netlist contains at least one MOS tube of the circuit schematic and connection relationship data of the at least one MOS tube.

[0029] In the embodiment of the application, the circuit schematic is specifically a circuit schematic of a digital circuit. After obtaining a certain circuit schematic to be arranged, the circuit schematic can be input into the prior art virtuoso software, and the virtuoso software can generate a corresponding first circuit description language (CDL) circuit netlist according to the obtained circuit schematic. The first CDL circuit netlist can contain at least one MOS tube of the circuit schematic and connection relationship data of the at least one MOS tube. The connection relationship data includes the tag name of the wire net corresponding to the drain, gate, source and substrate of the MOS tube. In addition, the first CDL circuit netlist can also include the basic parameters of the at least one MOS tube, such as the device name, the device type (P-type MOS tube or N-type MOS tube), the L channel length and the W channel length, etc.

[0030] Step 102: selecting at least one MOS tube combination from the first CDL circuit netlist; the MOS tube combination is composed of MOS tubes with connection relationship.

[0031] In the embodiment of the application, the MOS tube combination can be divided into a simple MOS tube combination and a complex MOS tube combination; the number of MOS tubes in the simple MOS tube combination is small, and the connection relationship between the MOS tubes is relatively simple, so the simple MOS tube combination can be easily selected from the first CDL circuit netlist; on the contrary, the number of MOS tubes in the complex MOS tube combination is large, and the connection relationship between the MOS tubes is relatively complex, so the simple MOS tube combination is not easy to be selected from the first CDL circuit netlist.

[0032] Based on this, if the first CDL circuit netlist contains both the simple MOS tube combination and the complex MOS tube combination, the simple MOS tube combinations in the first CDL circuit netlist can be selected first, and the data related to the simple MOS tube combinations can be removed from the first CDL circuit netlist, and then the complex MOS tube combination can be selected from the first CDL circuit netlist from which the data related to the simple MOS tube combinations is removed. In this way, the difficulty of selecting the complex MOS tube combination is reduced.

[0033] It should be noted that each MOS tube combination corresponds to a logic gate unit (a certain MOS tube combination is composed of MOS tubes of the corresponding logic gate unit), and those skilled in the art can divide various existing logic gate units according to actual conditions, and divide the logic gate unit into a simple logic gate unit and a complex logic gate unit, the MOS tube combination corresponding to the simple logic gate unit is a simple MOS tube combination, and the MOS tube combination corresponding to the complex logic gate unit is a complex MOS tube combination.

[0034] Step 103: generating a target circuit schematic diagram according to the MOS tube combination and the circuit schematic diagram; each MOS tube in the circuit schematic diagram is contained in the target circuit schematic diagram, and each MOS tube of each MOS tube combination is located in the region corresponding to the MOS tube combination.

[0035] In the embodiment of the application, after the MOS tube combination is selected, the MOS tubes in the circuit schematic diagram need to be moved according to the selected MOS tube combination, so that each MOS tube of each MOS tube combination is located in the region corresponding to the MOS tube combination. Specifically, the position coordinates of each MOS tube can be reset, and then the MOS tubes in the circuit schematic diagram are arranged according to the reset position coordinates, so as to move each MOS tube of each MOS tube combination to the region corresponding to the MOS tube combination.

[0036] The embodiment of the present application adopts the above technical solution to obtain a first CDL circuit netlist corresponding to the circuit schematic diagram; the first CDL circuit netlist contains at least one MOS tube of the circuit schematic diagram and connection relationship data of the at least one MOS tube; at least one MOS tube combination is selected from the first CDL circuit netlist; the MOS tube combination is composed of MOS tubes having a connection relationship; a target circuit schematic diagram is generated according to the MOS tube combination and the circuit schematic diagram; each MOS tube of the circuit schematic diagram is contained in the target circuit schematic diagram, and each MOS tube of each MOS tube combination is located in the region corresponding to the MOS tube combination. Based on this, the present application realizes the automation of the digital circuit arrangement process, and improves the efficiency and accuracy of processing digital circuits.

[0037] In the embodiment of the present application, step 102: at least one MOS tube combination is selected from the first CDL circuit netlist, which can specifically include:

[0038] Obtaining the MOS tube connection relationship corresponding to at least one first logic gate unit.

[0039] According to the connection relationship data in the first CDL circuit netlist, MOS tubes having the MOS tube connection relationship corresponding to each first logic gate unit are selected from the first CDL circuit netlist, to obtain the MOS tube combination.

[0040] In the embodiments of the present specification, the first logic gate unit can be a simple logic gate unit. Those skilled in the art can divide several logic gate units in the prior art into first logic gate units according to actual conditions, for example, it can be preset that the first logic gate unit includes an inverter (inv) and a transmission gate (TG) and the like.

[0041] In the specific application process, if the first CDL circuit netlist contains a simple MOS tube combination, at least one MOS tube connection relationship corresponding to a first logic gate unit can be obtained through a preset database, and then, for each MOS tube connection relationship corresponding to a first logic gate unit, the MOS tube connection relationship is matched with the first CDL circuit netlist, and each MOS tube combination corresponding to the MOS tube connection relationship in the first CDL circuit netlist is selected out, wherein if the connection relationship between each MOS tube constituting a MOS tube combination is the same as the MOS tube connection relationship, it is said that the MOS tube combination corresponds to the MOS tube connection relationship.

[0042] For example, it is assumed that the MOS tube connection relationship corresponding to the inverter (inv) is matched with the first CDL circuit netlist, and the matching result indicates that in the first CDL circuit netlist, MOS tube 1, MOS tube 2, MOS tube 3 and MOS tube 4 have the MOS tube connection relationship corresponding to the inverter (inv); and MOS tube 11, MOS tube 12 and MOS tube 13 also have the MOS tube connection relationship corresponding to the inverter (inv); therefore, the MOS tube combination corresponding to the MOS tube connection relationship corresponding to the inverter (inv) selected from the first CDL circuit netlist is [MOS tube 1, MOS tube 2, MOS tube 3 and MOS tube 4]; and [MOS tube 11, MOS tube 12 and MOS tube 13].

[0043] In the embodiments of the present specification, step 102: selecting at least one MOS tube combination from the first CDL circuit netlist can specifically include:

[0044] According to the connection relationship data in the first CDL circuit netlist, a target MOS tube having a connection relationship is selected from the first CDL circuit netlist.

[0045] The target MOS tube is divided into the same combination to obtain the MOS tube combination.

[0046] In the embodiments of the present specification, if the first CDL circuit netlist only contains one simple MOS tube combination or a complex MOS tube combination, the MOS tubes with connection relationship in the first CDL circuit netlist can be selected according to the connection relationship data in the first CDL circuit netlist to obtain a MOS tube combination.

[0047] The target MOS tube with connection relationship can be selected from the first CDL circuit netlist according to the connection relationship data in the first CDL circuit netlist, and specifically can include:

[0048] One MOS tube is randomly selected from the MOS tubes in the first CDL circuit netlist as a first MOS tube.

[0049] A second MOS tube connected with the source and the drain of the first MOS tube is selected from the MOS tubes other than the first MOS tube in the first CDL circuit netlist.

[0050] A third MOS tube connected with the gate of the first MOS tube and a fourth MOS tube connected with the gate of the second MOS tube are selected from the MOS tubes other than the first MOS tube in the first CDL circuit netlist.

[0051] It is determined whether there is a first target MOS tube connected with a specified end of a first specified MOS tube in the MOS tubes in the first CDL circuit netlist to obtain a first determination result; the first specified MOS tube includes the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube; and the specified end includes the source, the drain, the gate and the substrate.

[0052] If the first determination result is yes, the first target MOS tube is selected as a fifth MOS tube.

[0053] It is determined whether there is a second target MOS tube with connection relationship in a second specified MOS tube to obtain a second determination result; the second specified MOS tube includes the third MOS tube and the fourth MOS tube.

[0054] If the second determination result is yes, the second target MOS tube is selected as a sixth MOS tube.

[0055] It is determined whether there is a third target MOS tube with connection relationship with the first MOS tube or the second MOS tube in the sixth MOS tube to obtain a third determination result.

[0056] If the third determination result is yes, the third target MOS transistor is selected as a seventh MOS transistor; the target MOS transistor includes the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor, and the seventh MOS transistor.

[0057] In the embodiments of the present specification, if the first CDL circuit netlist includes one complex MOS transistor combination and at least one simple MOS transistor combination, step 102: selecting at least one MOS transistor combination from the first CDL circuit netlist can specifically include:

[0058] Obtaining the MOS transistor connection relationship corresponding to at least one first logic gate unit.

[0059] For the MOS transistor connection relationship corresponding to each first logic gate unit, according to the connection relationship data in the first CDL circuit netlist, selecting a MOS transistor having the MOS transistor connection relationship corresponding to the first logic gate unit from the first CDL circuit netlist to obtain a first MOS transistor combination.

[0060] For other MOS transistors in the first CDL circuit netlist except the first MOS transistor combination, according to the connection relationship data in the first CDL circuit netlist, selecting a target MOS transistor having a connection relationship from the other MOS transistors.

[0061] Dividing the target MOS transistor into the same combination to obtain a second MOS transistor combination; each MOS transistor of the second MOS transistor combination is used to constitute a second logic gate unit; the number of MOS transistors of the first logic gate unit is less than the number of MOS transistors of the second logic gate unit; the MOS transistor combination includes the first MOS transistor combination and the second MOS transistor combination.

[0062] In the embodiments of the present specification, the first MOS transistor combination is a simple MOS transistor combination; the second MOS transistor combination is a complex MOS transistor combination. For specific selection processes of the first MOS transistor combination and the second MOS transistor combination, refer to the above embodiments, which will not be described here.

[0063] In the embodiments of the present specification, after step 102: selecting at least one MOS transistor combination from the first CDL circuit netlist, the method of the present specification can further include:

[0064] Determining the logic gate unit type corresponding to each MOS transistor combination.

[0065] Correspondingly, after step 103: generating a target circuit schematic diagram according to the MOS transistor combination and the circuit schematic diagram, the method of the present specification can further include:

[0066] For each MOS tube combination, the logic gate unit type information of the MOS tube combination is generated in the designated area corresponding to the MOS tube combination in the target circuit schematic diagram.

[0067] In the embodiments of the present specification, the determination of the logic gate unit type corresponding to each MOS tube combination can specifically include:

[0068] For the first MOS tube combination, the logic gate unit type corresponding to the first MOS tube combination is determined as the first logic gate unit corresponding to the first MOS tube combination.

[0069] For the second MOS tube combination, the second MOS tube combination is matched with a plurality of second logic gate units in connection relationship to obtain a matching result; the matching result includes the logic gate unit type corresponding to the second MOS tube combination.

[0070] In the embodiments of the present specification, the matching of the second MOS tube combination with a plurality of second logic gate units in connection relationship to obtain a matching result can specifically include:

[0071] A second CDL circuit netlist is constructed according to the second MOS tube combination; the second CDL circuit netlist includes at least one MOS tube of the second MOS tube combination and connection relationship data of the at least one MOS tube.

[0072] A third CDL circuit netlist is obtained; the third CDL circuit netlist includes MOS tube connection relationship corresponding to a plurality of second logic gate units.

[0073] The second CDL circuit netlist and the third CDL circuit netlist are matched in connection relationship to obtain a matching result.

[0074] In the embodiments of the present specification, after the second MOS tube combination is selected, the basic parameters and connection relationship data of each MOS tube in the second MOS tube combination are written into a preset netlist to obtain a second CDL circuit netlist. Then, a third CDL circuit netlist can be obtained from a preset database, and the third CDL circuit netlist includes MOS tube connection relationship corresponding to a plurality of logic gate units at present. Finally, the second CDL circuit netlist and the third CDL circuit netlist are matched in connection relationship to obtain a matching result.

[0075] In a specific application process, the LVS (Layout Versus Schematics) module in the calibre software of the prior art can be used to match the connection relationship of the second CDL circuit netlist and the third CDL circuit netlist. Specifically, the configuration of the LVS module is modified, so that the LVS module only compares the MOS tube connection relationship when comparing the logic of the logic gate unit in the second CDL circuit netlist with the logic of the logic gate unit in the third CDL circuit netlist, and does not compare the basic parameters of the MOS tube.

[0076] In the embodiments of the present specification, the MOS tubes in each MOS tube combination are arranged based on the same arrangement rule.

[0077] In the embodiments of the present specification, the MOS tubes in each MOS tube combination are arranged based on the same arrangement rule.

[0078] Based on one general inventive concept, the embodiments of the present application also provide a digital circuit arrangement device, Figure 2 is a structural schematic diagram of a digital circuit arrangement device provided by the embodiments of the present application. As shown in Figure 2 The device comprises:

[0079] The first CDL circuit netlist module 21 is configured to obtain a first CDL circuit netlist corresponding to a circuit schematic diagram; the first CDL circuit netlist comprises at least one MOS tube of the circuit schematic diagram and connection relationship data of the at least one MOS tube.

[0080] The MOS tube combination selection module 22 is configured to select at least one MOS tube combination from the first CDL circuit netlist; the MOS tube combination is composed of MOS tubes having a connection relationship.

[0081] The target circuit schematic diagram generation module 23 is configured to generate a target circuit schematic diagram according to the MOS tube combination and the circuit schematic diagram; the target circuit schematic diagram comprises each MOS tube of the circuit schematic diagram, and each MOS tube of each MOS tube combination is located in a region corresponding to the MOS tube combination.

[0082] In the embodiments of the present specification, the MOS tube combination selection module 22 can be specifically configured to:

[0083] obtain the MOS tube connection relationship corresponding to at least one first logic gate unit.

[0084] According to the connection relationship data in the first CDL circuit netlist, MOS tubes having the MOS tube connection relationship corresponding to each first logic gate unit are selected from the first CDL circuit netlist, to obtain the MOS tube combination.

[0085] In the embodiments of the present specification, the MOS tube combination selection module 22 can be further used for:

[0086] According to the connection relationship data in the first CDL circuit netlist, target MOS tubes having the connection relationship are selected from the first CDL circuit netlist.

[0087] The target MOS tubes are divided into the same combination to obtain the MOS tube combination.

[0088] In the embodiments of the present specification, the MOS tube combination selection module 22 can be further used for:

[0089] At least one MOS tube connection relationship corresponding to a first logic gate unit is obtained.

[0090] According to the connection relationship data in the first CDL circuit netlist, MOS tubes having the MOS tube connection relationship corresponding to each first logic gate unit are selected from the first CDL circuit netlist, to obtain a first MOS tube combination.

[0091] According to the connection relationship data in the first CDL circuit netlist, target MOS tubes having the connection relationship are selected from the other MOS tubes.

[0092] The target MOS tubes are divided into the same combination to obtain a second MOS tube combination; each MOS tube of the second MOS tube combination is used to constitute a second logic gate unit; the number of MOS tubes of the first logic gate unit is less than the number of MOS tubes of the second logic gate unit; and the MOS tube combination includes the first MOS tube combination and the second MOS tube combination.

[0093] In the embodiments of the present specification, the apparatus of the present specification can further include:

[0094] A logic gate unit type determination module is configured to determine the logic gate unit type corresponding to each MOS tube combination.

[0095] The logic gate unit type information generation module is configured to generate, for each MOS transistor combination, logic gate unit type information of the MOS transistor combination in a designated area corresponding to the MOS transistor combination in the target circuit schematic diagram.

[0096] In the embodiments of the present specification, the logic gate unit type determination module can specifically include:

[0097] The first logic gate unit type determination submodule is configured to determine, for the first MOS transistor combination, that the logic gate unit type corresponding to the first MOS transistor combination is a first logic gate unit corresponding to the first MOS transistor combination.

[0098] The second logic gate unit type determination submodule is configured to, for the second MOS transistor combination, perform connection relationship matching between the second MOS transistor combination and a plurality of second logic gate units to obtain a matching result; the matching result includes the logic gate unit type corresponding to the second MOS transistor combination.

[0099] In the embodiments of the present specification, the second logic gate unit type determination submodule can be specifically configured to:

[0100] construct a second CDL circuit netlist according to the second MOS transistor combination; the second CDL circuit netlist includes at least one MOS transistor of the second MOS transistor combination and connection relationship data of the at least one MOS transistor.

[0101] obtain a third CDL circuit netlist; the third CDL circuit netlist includes MOS transistor connection relationships corresponding to a plurality of second logic gate units.

[0102] perform connection relationship matching between the second CDL circuit netlist and the third CDL circuit netlist to obtain a matching result.

[0103] In the embodiments of the present specification, in the generated target circuit schematic diagram, the MOS transistors in each MOS transistor combination can be arranged based on the same arrangement rule.

[0104] Based on the same overall inventive concept, the embodiments of the present application also provide a digital circuit arrangement device, Figure 3 is a structural schematic diagram of a digital circuit arrangement device provided by the embodiments of the present application, as Figure 3 shown, the device 300 can include:

[0105] at least one processor 310; and

[0106] a memory 330 in communication connection with the at least one processor; wherein

[0107] The memory 330 stores instructions 320 executable by the at least one processor 310, and the instructions are executed by the at least one processor 310 to enable the at least one processor 310 to:

[0108] Obtain a first CDL circuit netlist corresponding to the circuit schematic diagram; the first CDL circuit netlist contains at least one MOS tube of the circuit schematic diagram and connection relationship data of the at least one MOS tube;

[0109] Select at least one MOS tube combination from the first CDL circuit netlist; the MOS tube combination is composed of MOS tubes having a connection relationship;

[0110] Generate a target circuit schematic diagram according to the MOS tube combination and the circuit schematic diagram; the target circuit schematic diagram contains each MOS tube of the circuit schematic diagram, and each MOS tube of each MOS tube combination is located in a region corresponding to the MOS tube combination.

[0111] For each method embodiment described above, in order to simply describe, it is expressed as a series of action combinations, but those skilled in the art should know that the present application is not limited by the described action sequence, because according to the present application, some steps can be performed in other order or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the actions and modules involved are not necessarily necessary for the present application.

[0112] It should be noted that each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments, and the same and similar parts of each embodiment can be referred to. For device embodiments, since they are basically similar to method embodiments, the description is relatively simple, and the relevant parts refer to the part of the method embodiment.

[0113] The steps in the method of each embodiment of the present application can be adjusted, combined and reduced in sequence according to actual needs, and the technical features recorded in each embodiment can be replaced or combined.

[0114] The modules and sub-modules in the device and terminal of each embodiment of the present application can be combined, divided and reduced according to actual needs.

[0115] It should be understood that the disclosed terminal, device and method can be implemented in other manners in other embodiments. For example, the terminal embodiment described above is merely illustrative. For example, the division of the modules or the sub-modules is merely a logical function division. In actual implementation, another division manner can be used. For example, a plurality of sub-modules or modules can be combined or integrated into another module, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the modules or the displayed or discussed mutual couplings or direct couplings or communication connections can be indirect couplings or communication connections through some interfaces, devices or modules, and can be electrical, mechanical or in other forms.

[0116] The modules or the sub-modules which are described as separate components can or can not be physically separate, and the components which are modules or sub-modules can or can not be physical modules or sub-modules, i.e., can be located in one place, or can be distributed on a plurality of network modules or sub-modules. Some or all of the modules or sub-modules can be selected according to actual needs to achieve the purpose of the embodiment.

[0117] In addition, each functional module or sub-module in each embodiment of the present application can be integrated into a processing module, or each module or sub-module can exist physically separately, or two or more modules or sub-modules can be integrated into one module. The integrated module or sub-module can be realized in the form of hardware or in the form of a software functional module or sub-module.

[0118] The skilled person can further realize that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be realized in electronic hardware, computer software or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, each example has been described in the above description in a general manner in terms of its function. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0119] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein can be directly implemented by hardware, a software unit executed by a processor, or a combination of both. The software unit can be located in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art.

[0120] Finally, it should be noted that, in this document, the term "only" is used simply to set off from another element, and not to necessarily require or imply that only that element is present. Also, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0121] The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method of organizing a digital circuit, characterized by, The method comprises the following steps: obtaining a first CDL circuit netlist corresponding to a circuit schematic diagram; the first CDL circuit netlist contains at least one MOS transistor of the circuit schematic diagram and connection relationship data of the at least one MOS transistor; selecting at least one MOS transistor combination from the first CDL circuit netlist; the MOS transistor combination is composed of MOS transistors having connection relationship; generating a target circuit schematic diagram according to the MOS transistor combination and the circuit schematic diagram; each MOS transistor of the target circuit schematic diagram contains each MOS transistor of the circuit schematic diagram, and each MOS transistor of each MOS transistor combination is located in a region corresponding to each MOS transistor combination; wherein, the step of selecting at least one MOS transistor combination from the first CDL circuit netlist comprises: obtaining MOS transistor connection relationship corresponding to at least one first logic gate unit; for the MOS transistor connection relationship corresponding to each first logic gate unit, selecting MOS transistors having the MOS transistor connection relationship corresponding to the first logic gate unit from the first CDL circuit netlist according to the connection relationship data in the first CDL circuit netlist, to obtain a first MOS transistor combination; for other MOS transistors in the first CDL circuit netlist except the first MOS transistor combination, selecting target MOS transistors having connection relationship from the other MOS transistors according to the connection relationship data in the first CDL circuit netlist; dividing the target MOS transistors into the same combination to obtain a second MOS transistor combination; each MOS transistor of the second MOS transistor combination is used to constitute a second logic gate unit; the number of MOS transistors of the first logic gate unit is less than the number of MOS transistors of the second logic gate unit; the MOS transistor combination includes the first MOS transistor combination and the second MOS transistor combination.

2. The method of claim 1, wherein, The step of selecting at least one MOS transistor combination from the first CDL circuit netlist comprises: obtaining MOS transistor connection relationship corresponding to at least one first logic gate unit; for the MOS transistor connection relationship corresponding to each first logic gate unit, selecting MOS transistors having the MOS transistor connection relationship corresponding to the first logic gate unit from the first CDL circuit netlist according to the connection relationship data in the first CDL circuit netlist, to obtain the MOS transistor combination.

3. The method of claim 1, wherein, The step of selecting at least one MOS transistor combination from the first CDL circuit netlist comprises: selecting target MOS transistors having connection relationship from the first CDL circuit netlist according to the connection relationship data in the first CDL circuit netlist; dividing the target MOS transistors into the same combination to obtain the MOS transistor combination.

4. The method of claim 1, wherein, After the step of selecting at least one MOS transistor combination from the first CDL circuit netlist, further comprising: determining the type of logic gate unit corresponding to each MOS transistor combination; after the step of generating a target circuit schematic diagram according to the MOS transistor combination and the circuit schematic diagram, further comprising: For each MOS tube combination, the logic gate unit type information of the MOS tube combination is generated in the designated area corresponding to the MOS tube combination in the target circuit schematic diagram.

5. The method of claim 4, wherein, The determination of the logic gate unit type corresponding to each MOS tube combination specifically includes: For the first MOS tube combination, the logic gate unit type corresponding to the first MOS tube combination is determined as the first logic gate unit corresponding to the first MOS tube combination. For the second MOS tube combination, the second MOS tube combination is matched with a plurality of second logic gate units in terms of connection relationship to obtain a matching result; the matching result includes the logic gate unit type corresponding to the second MOS tube combination.

6. The method of claim 5, wherein, The matching of the second MOS tube combination with a plurality of second logic gate units in terms of connection relationship to obtain a matching result specifically includes: A second CDL circuit netlist is constructed according to the second MOS tube combination; the second CDL circuit netlist includes at least one MOS tube of the second MOS tube combination and connection relationship data of the at least one MOS tube; A third CDL circuit netlist is obtained; the third CDL circuit netlist includes MOS tube connection relationships corresponding to a plurality of second logic gate units; The second CDL circuit netlist and the third CDL circuit netlist are matched in terms of connection relationship to obtain a matching result.

7. The method of claim 1, wherein, Each MOS tube in each MOS tube combination is arranged based on the same arrangement rule.

8. An arrangement for sorting digital circuits, characterized in that It includes: A first CDL circuit netlist module is configured to obtain a first CDL circuit netlist corresponding to a circuit schematic diagram; The first CDL circuit netlist includes at least one MOS tube of the circuit schematic diagram and connection relationship data of the at least one MOS tube; A MOS tube combination selection module is configured to select at least one MOS tube combination from the first CDL circuit netlist; the MOS tube combination is composed of MOS tubes having connection relationship; A target circuit schematic diagram generation module is configured to generate a target circuit schematic diagram according to the MOS tube combination and the circuit schematic diagram; The target circuit schematic diagram includes each MOS tube of the circuit schematic diagram, and each MOS tube of each MOS tube combination is located in a region corresponding to the MOS tube combination; The MOS tube combination selection module is specifically configured to: Obtain MOS tube connection relationship corresponding to at least one first logic gate unit; For the MOS tube connection relationship corresponding to each first logic gate unit, select MOS tubes having the MOS tube connection relationship corresponding to the first logic gate unit from the first CDL circuit netlist according to the connection relationship data in the first CDL circuit netlist to obtain a first MOS tube combination; For other MOS tubes in the first CDL circuit netlist except the first MOS tube combination, select target MOS tubes having connection relationship from the other MOS tubes according to the connection relationship data in the first CDL circuit netlist. The target MOS tube is divided into the same combination to obtain a second MOS tube combination; each MOS tube of the second MOS tube combination is used to constitute a second logic gate unit; the number of MOS tubes of the first logic gate unit is less than the number of MOS tubes of the second logic gate unit; and the MOS tube combination includes the first MOS tube combination and the second MOS tube combination.

9. An arrangement for digital circuits, characterized in that Comprise: At least one processor; And, The memory connected in communication with the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to: Obtain a first CDL circuit netlist corresponding to a circuit schematic diagram; the first CDL circuit netlist contains at least one MOS tube of the circuit schematic diagram and connection relationship data of the at least one MOS tube; Select at least one MOS tube combination from the first CDL circuit netlist; the MOS tube combination is composed of MOS tubes having connection relationship; According to the MOS tube combination and the circuit schematic diagram, a target circuit schematic diagram is generated; each MOS tube of the target circuit schematic diagram contains each MOS tube of the circuit schematic diagram, and each MOS tube of each MOS tube combination is located in the corresponding area of each MOS tube combination; Wherein, the at least one MOS tube combination is selected from the first CDL circuit netlist, specifically including: Obtain the MOS tube connection relationship corresponding to at least one first logic gate unit; For the MOS tube connection relationship corresponding to each first logic gate unit, according to the connection relationship data in the first CDL circuit netlist, select the MOS tube having the MOS tube connection relationship corresponding to the first logic gate unit from the first CDL circuit netlist to obtain a first MOS tube combination; For other MOS tubes in the first CDL circuit netlist except the first MOS tube combination, according to the connection relationship data in the first CDL circuit netlist, select target MOS tubes having connection relationship from the other MOS tubes; The target MOS tube is divided into the same combination to obtain a second MOS tube combination; each MOS tube of the second MOS tube combination is used to constitute a second logic gate unit; the number of MOS tubes of the first logic gate unit is less than the number of MOS tubes of the second logic gate unit; and the MOS tube combination includes the first MOS tube combination and the second MOS tube combination.

Images