Propagation method, processing method and medium for timing exception constraint and timing constraint

Abstract

The application discloses a timing exception constraint and timing constraint propagation method, processing method and medium. The timing exception constraint propagation method comprises the following steps: capturing pin or port information of a timing exception constraint to be replaced; analyzing positions of pins or ports of the timing exception constraint to be replaced relative to instances; if positions of pins or ports of the timing exception constraint to be replaced in a certain option are inconsistent relative to the instances, or if fan-in of a pin or port of the timing exception constraint to be replaced can be traced to an input pin of an instance, and fan-out of the pin or port can be traced to an output pin of the instance, then a DFS replacement step is selected to replace the timing exception constraint to be replaced, otherwise a BFS replacement step is selected to be downward propagated. The application analyzes specific conditions of the timing exception constraint, and selects a corresponding propagation replacement method, so that the replacement efficiency is improved.

Description

Technical Field

[0001] This invention relates to the technical field of time constraint propagation, and more particularly to a method for propagating time exception constraints. Background Technology

[0002] In the integrated circuit design process, a hierarchical design approach is typically used to facilitate circuit design and maintenance. A hierarchical circuit consists of a top-level circuit and multiple sub-modules contained within it. In hierarchical architecture circuit design, timing constraints for the top-level circuit and sub-modules are often completed independently by the designer. Both top-level and module timing constraints require manual configuration. However, with continuous advancements in design and manufacturing processes, while advanced technologies drive exponential leaps in IC precision and integration, they also bring new challenges to timing constraints and timing convergence. To maintain consistency between top-level and module timing constraints, modifications to either top-level or module timing constraints must be synchronously inherited to the next level. This repetitive manual iteration reduces chip design efficiency to some extent.

[0003] Static timing analysis is a crucial step in integrated circuit design. Timing constraint files describe the information related to the timing constraints given in the design. To ensure the circuit can operate correctly under different performance and operating environments, corresponding timing constraints need to be set for the top-level module and each sub-module. Downward propagation of static timing constraints refers to effectively replacing a set of timing constraint files originally configured in the top-level module with a set configured in the sub-modules, ensuring that the timing analysis environment for each sub-module remains consistent with the timing analysis performed within the top-level module.

[0004] The default analysis rule in static timing analysis is to analyze all timing paths in a single clock cycle. However, in actual design, not all paths need to be analyzed, and the delay of not all timing paths is specified within one clock cycle. Therefore, timing exceptions are defined to make special declarations for special timing paths so that the timing analysis can correctly analyze special timing paths. Such special declarations are called timing exceptions.

[0005] How to efficiently propagate timing exception constraints is a persistent technical problem in existing technologies. Therefore, providing a method that enables the efficient propagation of timing exception constraints is a technical problem that the industry urgently needs to solve. Summary of the Invention

[0006] To address the technical problem of low propagation efficiency of temporal exception constraints due to the single propagation method in existing technologies, this invention proposes a propagation method, processing method, and medium for temporal exception constraints and temporal constraints.

[0007] The method for propagating timing exception constraints proposed in this invention includes:

[0008] Retrieve pin or port information for the timing exception constraint to be replaced;

[0009] Analyze the relative position of the pin or port of the timing exception constraint to be replaced to the instance;

[0010] If the timing exception constraint to be replaced has a pin or port whose position relative to the instance is inconsistent, or if the fan-in of a pin or port of the timing exception constraint to be replaced can be traced to the instance's input pin, and the fan-out of the pin or port can be traced to the instance's output pin, then the DFS replacement step is selected to replace the timing exception constraint to be replaced; otherwise, the BFS replacement step is selected to propagate downwards.

[0011] Furthermore, the DFS replacement step includes:

[0012] All time-series paths were found using a depth-first search algorithm;

[0013] Based on each timing path, the timing exception constraints to be replaced in each timing path are replaced to generate the replaced timing path;

[0014] Generate corresponding options for the replaced timing path;

[0015] The generated options are combined with the replaced timing paths to produce new timing constraints.

[0016] Furthermore, the generation of the replaced timing path includes the following steps:

[0017] All found timing paths are split according to the options;

[0018] Each option is replaced one by one, and the replacement rules are classified according to the type of pin, port or clock of the timing path and its relative position to the instance.

[0019] Combine the replaced options according to the original timing path.

[0020] Furthermore, the BFS replacement step includes:

[0021] Based on the characteristics of each matching object, match all options for timing exception constraints to be replaced, as well as the pin, and / or port, and / or clock in the options;

[0022] Check if there is a pin or port in the options. If so, replace the pin and / or port in the options and then generate the -from and -to options for the new command. If not, directly generate the -from and -to options for the new command.

[0023] Generate new timing constraint instructions.

[0024] The method for propagating static timing constraints proposed in this invention includes:

[0025] Determine whether the current timing constraint to be replaced is a timing exception constraint;

[0026] If so, then the propagation method of the timing exception constraint according to any one of claims 1 to 4 shall be used for propagation;

[0027] If not, then proceed with the normal propagation process of static timing constraints.

[0028] The method for propagating static timing constraints proposed in this invention includes:

[0029] Configure parameters related to static timing constraint propagation, serial-parallel execution mode, and module names of submodules for downward propagation;

[0030] Determine if the current target instance has already been generated;

[0031] If no module is generated, then configure the module.

[0032] If it has already been generated, determine whether the parallel execution mode is parallel mode or serial mode;

[0033] In parallel mode, multiple PT environments are opened to execute the static timing constraint propagation method described in the above technical solution in parallel.

[0034] If it is a serial module, the propagation method of static timing constraints described in the above technical solution is executed serially.

[0035] The present invention proposes a computer-readable storage medium for storing a computer program, which, when executed, performs the timing exception constraint propagation method described in the above technical solution.

[0036] Compared with existing technologies, this patent has the following beneficial effects:

[0037] 1. In the downward propagation process of static timing constraints, a single module may instantiate multiple instances. Using a serial method requires performing the static timing constraint propagation process on each instance individually, which consumes a significant amount of time. To address this issue, this patent proposes a parallel method to simultaneously perform the static timing constraint propagation process on multiple instances, which can save a significant amount of runtime compared to the serial method.

[0038] 2. A replacement method based on DFS is proposed, which can perform replacement operations for each time path individually during the downward propagation of static time constraints. It has high scalability and ensures the correctness of the downward propagation of static time constraints.

[0039] 3. A replacement method based on BFS is proposed, which can replace a single option during the downward propagation of static temporal constraints. Its scalability is relatively limited compared to the DFS method, but it can save a lot of time costs compared to the DFS method.

[0040] 4. A matching and replacement algorithm based on a combination of DFS and BFS is proposed. This algorithm can judge the current timing constraint instruction during the downward propagation of static timing constraints and select the matching and replacement algorithm based on DFS or BFS. This ensures the correctness of the static timing constraint propagation process and also ensures that the propagation time of static timing constraints is not too long. Attached Figure Description

[0041] The present invention will now be described in detail with reference to the embodiments and accompanying drawings, wherein:

[0042] Figure 1 This is a flowchart of the propagation method selection for timing exception constraints according to an embodiment of the present invention.

[0043] Figure 2 This is a flowchart of a DFS replacement process according to an embodiment of the present invention.

[0044] Figure 3 This is a circuit diagram of an embodiment of the present invention.

[0045] Figure 4 This is a flowchart of a BFS replacement process according to an embodiment of the present invention.

[0046] Figure 5 This is an overall flowchart of an embodiment of the present invention. Detailed Implementation

[0047] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0048] Therefore, a feature pointed out in this specification is used to describe one feature of one embodiment of the invention, and does not imply that every embodiment of the invention must have the described feature. Furthermore, it should be noted that this specification describes many features. Although certain features may be combined to illustrate possible system designs, these features may also be used in other combinations not explicitly stated. Therefore, unless otherwise stated, the described combinations are not intended to be limiting.

[0049] The propagation method for time-series exception constraints in this invention refers to the specific method used when time-series exception constraints propagate downwards. Unlike existing technologies, the propagation method for time-series exception constraints in this invention selects either a depth-first search and replacement step or a breadth-first search and replacement step based on the characteristics of the options for the time-series exception constraints.

[0050] The propagation method of timing exception constraints of the present invention includes the following steps.

[0051] First, capture the pin or port information of the timing exception constraint to be replaced;

[0052] Analyze the relative position of the pin or port of the timing exception constraint to be replaced to the instance;

[0053] If the timing exception constraint to be replaced has a pin or port whose position relative to the instance is inconsistent, or if the fan-in of a pin or port of the timing exception constraint to be replaced can be traced to the input pin of the corresponding instance, and the fan-out of the pin or port can be traced to the output pin of the corresponding instance, then the depth-first search replacement step (DFS replacement step) is selected to replace the timing constraint to be replaced; otherwise, the breadth-first search replacement step (BFS replacement step) is selected to perform a downward propagation replacement.

[0054] This invention proposes a matching and replacement algorithm based on a combination of DFS and BFS to replace temporal exception constraints. It can judge the current temporal constraint instruction during the downward propagation of static temporal constraints and select to use either the matching and replacement algorithm based on DFS or BFS. This ensures both the correctness of the propagation process of static temporal constraints and that the propagation time of static temporal constraints is not too long.

[0055] Figure 1 This is a flowchart illustrating the temporal path matching algorithm based on a combination of BFS and DFS provided by the present invention.

[0056] Step S101: Analyze and judge the temporal constraints to be replaced. If the current downward propagation temporal constraint is a temporal exception type constraint (i.e., temporal exception constraint), the matching and replacement algorithm selector identifies the characteristics of the current temporal exception constraint. Based on the characteristics of the current temporal exception constraint, it selects either the DFS-based matching and replacement process (i.e., the DFS replacement step) or the BFS-based matching and replacement process (i.e., the BFS replacement step) for the current temporal exception constraint.

[0057] Step S102: Perform the DFS replacement step.

[0058] Step S103: Perform the BFS replacement step.

[0059] For example, in the option -through{A1 A2 A3}, A1 is a pin located inside the instance, and A2 is a pin located outside the instance. Since the positions of the two pins relative to the instance are inconsistent, the DFS-based replacement process is selected.

[0060] The above technical solution first analyzes the timing exception constraints to be replaced, captures the pin and / or port information of the timing exception constraints, analyzes the position of the pins and / or ports relative to the instance, and selects either a DFS-based replacement process or a BFS-based replacement process for downward propagation. If a DFS-based replacement process is selected, the timing constraints are traversed using the DFS method to find all constrained timing paths, and each timing path is replaced one by one to generate new timing paths and corresponding options. Finally, new timing constraints are generated based on the corresponding option combinations. If a BFS-based replacement process is selected, the timing paths are traversed using the BFS method to match and capture all options, and then the pin and / or port information is captured from each option. The captured pin and / or port information is used for replacement or to generate new timing constraint instructions.

[0061] Figure 2 A specific embodiment of the DFS replacement step of the present invention is shown. The DFS replacement step mainly includes the following steps.

[0062] Step S201: Use a depth-first search algorithm to find all time-series paths;

[0063] Step S202: Replace the timing exception constraints to be replaced in each timing path according to each timing path to generate the replaced timing path. The timing constraint (including timing exception constraints) itself is composed of many different options to form a complete timing constraint, and the order between different options is not fixed and can be arbitrarily combined. Therefore, this step is to replace the different options in the timing constraint respectively.

[0064] Step S203: Generate corresponding options based on the replaced timing path;

[0065] Step S204: Based on the generated options, merge the replaced timing paths and combine them to generate new timing constraints.

[0066] In step S201, during the downward propagation of static timing constraints, a depth-first search (DFS) method is used to traverse all pins, ports, and clocks included in the timing constraints to find all timing paths constrained in the timing constraints.

[0067] If the timing constraint set_false_path-through{A1 A2 A3}-through{B1 B2 B3}-through{C1 C2 C3} is applied... Figure 3 The circuit structure is such that the timing constraint instruction constrains the timing paths from level A to level B, and then to level C. In the current circuit, the actual constrained timing paths are A1->B1->C1, A1->B2->C1, A1->B2->C2, A2->B2->C1, A2->B2->C2, and A3->B3->C3. Step S201 uses a Depth-First Search (DFS) to find all of the above-mentioned constrained timing paths. Not all adjacent levels have a timing path between any two pins. For example, there is no timing path between the path A2->B3->C3, so this path is not constrained and does not need to be selected for replacement. Therefore, step S201 will not select such a timing path.

[0068] In step S202, each timing path among all the timing paths found in step S201 is split according to options to ensure the correct timing order, and each timing path is replaced one by one. The replacement algorithm is based on the type of pin, port, or clock of the timing path and its relative position to the instance.

[0069] If the current timing path to be replaced is A1->B1->C1, the corresponding replacement algorithm (replacement steps) is used to replace the current timing path and generate a new timing path. If pins A1, B1, and C1 in the timing path A1->B1->C1 are all within an instance, the corresponding replacement algorithm will remove the instance prefix from each of the three pins A1, B1, and C1, i.e., remove "<instance> / ", generating a new timing path A1_new->B1_new->C1_new. If pins A1, B1, and C1 in the timing path A1->B1->C1 are all outside an instance, the corresponding replacement algorithm determines whether the complete timing path A1->B1->C1 passes through an instance. If it passes through the instance's input pin PI1, a new timing path -from PI1 is generated; if it passes through the instance's output pin PO1, a new timing path -to PO1 is generated.

[0070] During the replacement process in step S202, the hierarchical levels of the newly generated timing paths are not necessarily consistent. For example, the options for the three newly generated paths -from PI1, -to PO1, or A1_new->B1_new->C1_new are {-from}, {-to}, and {-through-through-through}, respectively. These three new paths cannot be simply merged into a single timing constraint; they need to be described separately using three timing constraints.

[0071] In step S203, corresponding options are generated for the timing path generated in step S202. Step S202 yields the replaced timing path, not the timing options. Step S203 derives the replaced timing options from the replaced timing path obtained in step S202. (See reference) Figure 3 Obtaining the replaced timing path is a necessary condition for performing timing option replacement.

[0072] In step S203, the corresponding options for generating all the timing paths generated in step S202 are processed so that step S204 can merge all the generated timing paths and reduce the number of timing constraints.

[0073] In step S204, the new timing path generated in step S202 is merged using the options generated in S203 to produce a new timing path.

[0074] In step S204, paths with the same options generated in step S203 are merged. If the newly generated path 1 is -from PI1 and the newly generated path 2 is -from PI2, and both paths have the option {-from}, process S203 merges the two paths with the same option to generate -from{PI1 PI2}, thereby avoiding the generation of too many timing constraints.

[0075] Figure 4 A specific embodiment of the BFS replacement step of the present invention is shown. The BFS replacement step mainly includes the following steps.

[0076] Step S401: Based on the characteristics of each matching object, match all timing exception constraints to be replaced with options, including pins, and / or ports, and / or clocks in the options; the matching objects referred to here include at least one of pins, ports, and clocks. The characteristics of the matching objects can be data summarized in advance based on experience.

[0077] Step S402: Generate the -from and -to options for the new command;

[0078] Step S403: Replace pin and / or port in the options;

[0079] Step S404: Generate new timing constraint instructions.

[0080] In step S401, when a BFS-based downpropagation algorithm is needed to apply timing exception constraints, a matching algorithm is first used to capture all options in the timing constraint instruction, including at least one of -from, -through, and -to. Then, the pin, and / or port, and / or clock information in each -from, -through, and -to option is captured one by one. For example, by calling the regexp matching function, which can perform matching based on different features, different matching features are designed for different timing constraints and different timing options in this invention.

[0081] Assume the current top-level setting is the timing constraint `set_false_path -through{A1 A2 A3} -through{B1B2B3} -through{C1 C2 C3}`. A BFS-based matching and replacement algorithm is used for downward propagation. The BFS algorithm first extracts three options: `-through{A1 A2 A3}`, `-through{B1 B2 B3}`, and `-through{C1 C2 C3}`. Then, it extracts the pins from each of these three options. For example, it extracts pins A1, A2, and A3 from `-through{A1 A2 A3}` and passes them to steps S402 and S403 for replacement and generation of new options.

[0082] In step S403, the matching and replacement algorithm performs the replacement operation based on the pin, and / or port, and / or clock obtained in step S401. The replacement method is as follows:

[0083] If the path between all pins or ports in the current option and all pins or ports in adjacent options does not pass through an instance, the matching replacement algorithm will delete the entire option.

[0084] If the path between the current option and the previous option passes through the output port of the instance submodule, the intersection of the previous option and the current option on the instance output pin will be found, and the content of the intersection will be sent to step S402 to generate the -to option. It can be understood that steps S401 and S403 are both inputs to step S402. In step S401, a judgment will be made. The clock is directly input to step S402, while the pin or port needs to execute step S403 first and then input to step S402. However, step S402 is only executed once for the pin, port or clock in the option.

[0085] If the path between the current option and the next option passes through the input port of the instance submodule, then all pins or ports in the current option will be fan-out to the input pin of the instance, and all the traced instance input pins will be saved so that the next option can extract the path to the current option, i.e., take the intersection to extract the path between the two options.

[0086] If all pins or ports in the option are within the instance, determine whether the current option is a -from option or a -to option. If so, delete the current option and save the pins in the -from and -to options for step S402 to generate the -from and -to options of the new instruction; otherwise, the matching and replacement algorithm will retain the current option and replace the pins or ports in the option one by one.

[0087] If the previous option of the current option is outside the instance, the intersection of the current option and the previous option on the instance input pin will be found, and the content of the intersection will be sent to step S402 to generate the -from option. When the generated -from option is traversed, step S403 will continue to be executed.

[0088] If the next option after the current option is outside the instance, then all pins or ports in the current option will be fan-out to the output pins of the instance's submodules, and all the output pins of the tracked submodules will be saved for the next option to perform an intersection.

[0089] In step S402, based on the input and output pins of the sub-modules through which the timing path is obtained in step S403, and combined with the clock captured in step S401, the -from and -to options of the new instruction are generated.

[0090] This can be understood as having three options: pin, port, and clock. The pin or port option requires processing in step 403, while the clock option only needs processing in step 401. After steps 401 and 403 are completed, step 402 is executed only once. Therefore, the order of the above steps can be either 401 → 403 → 402 → 404, or 401 → 402 → 404. Whether step 403 is executed depends on whether there is a pin or port option.

[0091] In step S404, the -from and -to options generated in step S402, along with the retained and replaced -through option portion from step S403, are combined to generate a new timing constraint instruction. Simply put, based on the original timing constraints, the options generated in step S402 are recombine to form a new and equivalent timing constraint instruction. The recombination principle is primarily equivalence, ensuring the actual effect is consistent with the original timing constraint instruction.

[0092] During the downward propagation of static temporal constraints, the efficiency of DFS-based and BFS-based matching and replacement algorithms is not equivalent. Experiments show that the DFS-based matching and replacement algorithm has a wider coverage than the BFS-based algorithm, capable of propagating downwards for all types of temporal exception constraints. The BFS-based algorithm, however, has significant limitations in propagating downwards for temporal exception constraints and cannot effectively handle various types of constraints. Nevertheless, the BFS-based matching and replacement algorithm has a significantly shorter runtime than the DFS-based algorithm; that is, when propagating the same temporal exception constraint downwards, the BFS-based algorithm takes far less time than the DFS-based algorithm.

[0093] Given the characteristics of the two algorithms mentioned above, this invention selects the appropriate matching and replacement algorithm from the DFS-based matching and replacement algorithm and the BFS-based matching and replacement algorithm to execute the downward propagation process.

[0094] The method for propagating static timing constraints of the present invention includes the propagation of timing exception constraints and the propagation of ordinary timing constraints.

[0095] The propagation method for static timing constraints requires first determining whether the current timing constraint to be replaced is a timing exception constraint;

[0096] If it is a timing exception constraint, then it is propagated according to the timing exception constraint propagation method of the above technical solution;

[0097] If it is not a timing exception constraint, but only a normal timing constraint, then the propagation process of the regular static timing constraint is carried out. The propagation process of the regular static timing constraint refers to the propagation process of the static timing constraint in the prior art.

[0098] The method for propagating static timing constraints according to the present invention includes the following steps.

[0099] Configure parameters related to static timing constraint propagation, serial-parallel execution mode, and module names of submodules for downward propagation;

[0100] Determine if the current target instance has already been generated;

[0101] If no module is generated, then configure the module.

[0102] If it has already been generated, determine whether the parallel execution mode is parallel mode or serial mode;

[0103] In parallel mode, multiple PT environments (static timing analysis tools) are opened to execute the propagation method of static timing constraints of the above technical solution in parallel.

[0104] If it is a serial module, the propagation method of static timing constraints as described in claim 5 is executed serially.

[0105] In other embodiments, the serial-parallel execution mode may not require configuration; the present invention can automatically configure it. During automatic configuration, the system can automatically determine serial or parallel execution by judging the number of servers, the load saturation level of each server, and the number of instantiated instances. For example, when the number of servers is too high, or there are few idle servers, or too few instantiated instances, it will automatically configure to serial execution; otherwise, it will automatically configure to parallel execution. The threshold for instantiated instances to enter parallel execution is pre-defined and managed; for example, the number of idle servers, load saturation level, and number of instantiated instances that meet the parallel execution conditions can be pre-defined.

[0106] Figure 5 A flowchart of a method for propagating static timing constraints according to an embodiment of the present invention is shown.

[0107] The propagation processing method for static timing constraints mainly includes the following five steps.

[0108] Step S501, parameter configuration;

[0109] Step S502: Serial-parallel control;

[0110] Step S503, Module Configuration;

[0111] Step S504: Execute the propagation method of static timing constraints in serial mode;

[0112] Step S505: Execute the propagation method of static timing constraints in parallel mode.

[0113] In step S501, the relevant parameters for static timing constraint propagation (such as module name, working directory, path of timing constraint file to be replaced, whether to parallelize, etc.), serial-parallel execution mode, and module name of the sub-module to be propagated downward are configured.

[0114] In step S502, the serial-parallel control receives the parameters of the serial-parallel execution mode in step S501, and determines whether the current propagation target instance has been generated. If the propagation target instance has not yet been obtained, it jumps to step S503 to configure the module. If the current propagation target instance has been obtained, it determines whether the execution mode of the process is parallel execution. If so, it starts multiple PT environments and performs the static time-series propagation process step S505 in parallel.

[0115] In step S503, one or more instances of the same module within the circuit are extracted based on the module name, and the extracted instance parameters are stored in a configuration file for use in steps S504 and S505. The parameters of the serial-parallel execution mode in the configuration file are used to determine whether the execution mode is serial. If the parameter is serial, step S504 iterates through all instances, performing the static timing constraint propagation process one by one. If the parameter is parallel, the process jumps back to step S502 and proceeds to step S505 to perform parallel computation by calling the LSF system.

[0116] In step S504, all instances are looped through, and the propagation method of static timing constraints is executed.

[0117] In step S505, all instances are submitted to the LSF system (distributed cluster management system) simultaneously and in parallel. Resources are automatically allocated according to requirements, and the propagation method of static timing constraints of the above technical solution is executed.

[0118] Below, we will use specific examples to illustrate... Figure 5 The method shown will be explained in detail.

[0119] Suppose the top-level module contains multiple instances generated by a submodule, denoted as instance 1, instance 2, and instance 3. The parameter configuration process sets the execution mode and the module name of the submodules that propagate downwards.

[0120] If the execution mode is serial, upon entering the serial-to-parallel controller, it checks whether all instantiated units (instances) of the submodule have been obtained. If the instantiated unit information has not yet been obtained, the Prime Time environment (static timing analysis tool) is activated, the module configuration flow is entered, the module name of the submodule in the parameter configuration flow is obtained, and all instantiated instances of the submodule are obtained, namely instance 1, instance 2, and instance 3. Since the current execution mode is serial, the above three instances are looped directly in the current Prime Time environment, and the propagation method of static timing constraints is applied one by one.

[0121] If the execution mode is parallel, upon entering the serial-parallel controller, it checks whether all instantiated units of the submodule have been obtained. If the instantiation unit information has not yet been obtained, the Prime Time environment is started, the module configuration process is entered, the module name of the submodule in the parameter configuration process is obtained, and all instances of the submodule after instantiation are obtained, namely instance 1, instance 2, and instance 3. Since the current execution mode is parallel, the Prime Time environment is exited and the serial-parallel control process is entered, and three Prime Time environments are started in parallel. In the three Prime Time environments, the static timing propagation method is executed simultaneously on instance 1, instance 2, and instance 3.

[0122] The detailed implementation process of this invention is described below.

[0123] Step 101: Provide the required input files, including design files (supporting RTL format and netlist format), timing constraint files (top-level SDC or module SDC), timing library files, and user configuration files (for personalized configuration).

[0124] Step 102: Start the automated propagation process of timing constraints through the process control script.

[0125] Step 103: Based on the input file, automatically determine the design file type. If it is in RTL format, proceed to step 104; if it is in netlist format, proceed to step 105.

[0126] Step 104: The RTL design file and timing constraint file are synthesized using a synthesis tool to generate a netlist design file and a timing constraint SDC file. These are used as inputs for step 105 in the RTL process.

[0127] Step 105: The timing constraint propagation main script reads in the netlist, timing constraint SDC, and timing library, and connects the netlist and timing library.

[0128] Step 106: Call the user configuration file, which includes the path to the timing library, the name of the target module, the selection of the timing constraint propagation method (upward or downward propagation), the selection of port constraints, and other configurations.

[0129] Step 107: Call the IP configuration script to extract information about the target module, including the module's input port, output port, and path information between the port and the top layer.

[0130] Step 108: Call the timing path information configuration script to analyze the path of interaction between the port and the top layer, extract the critical path, and extract the starting point information of the critical path of the input port and the ending point information of the critical path of the output port, including the fan-in and fan-out status of the port, the arrival time of the target module port in the critical path, etc.

[0131] Step 109: Call the general function configuration script.

[0132] Step 110: Redefine the boundaries using the boundary setting script. In the upward propagation process, remove the target module's port boundary definition and redefine the top-level port boundary according to the user's configuration file. In the downward propagation process, remove the top-level port boundary definition and redefine the target module's port boundary according to the user's configuration file.

[0133] Step 111: The uppropagation instruction recognition script and the downpropagation instruction recognition script can filter the initial SDC according to certain rules, filter out irrelevant timing constraints, and output the timing constraint text in the format required in step 112.

[0134] In step 112, the temporal constraint text identified in step 111 is sorted through a case setting script. Six types of universal case analyses are set (two of which are case analyses of the temporal exception constraints of this invention). The script sorts the temporal constraints one by one and delivers them to the relevant case analysis script for equivalent propagation of the corresponding temporal constraints.

[0135] Step 113: In Cases 1-6, different matching and replacement configurations were set for different options of various time constraints according to their different time constraints. A complete time constraint was split according to the corresponding option, and the parameters required in Step 114 were extracted. The time exceptions involved in this invention include, for example, set_false_path, set_multicycle_path, set_max_delay, and set_min_delay.

[0136] Step 114: Based on the parameters extracted in step 113, select the optimal algorithm from the BFS and DFS algorithms according to the replacement selector shown in S501. Then, through the matching replacement algorithm, replace the split options according to the replacement rules, and recombine the replaced options to form new time constraints.

[0137] Step 115: Based on the difference between upward and downward propagation, the recombined timing constraints are stored in the corresponding files.

[0138] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for propagating temporal exception constraints, characterized in that, include: Retrieve pin or port information for the timing exception constraint to be replaced; Analyze the relative position of the pin or port of the timing exception constraint to be replaced to the instance; If the timing exception constraint to be replaced exists in a certain option where the positions of multiple pins or ports relative to the instance are inconsistent, or if the fan-in of a pin or port of the timing exception constraint to be replaced can be traced to the input pin of the instance, and the fan-out of the pin or port can be traced to the output pin of the instance, then the DFS replacement step is selected to replace the timing exception constraint to be replaced; otherwise, the BFS replacement step is selected to propagate downwards. The DFS replacement step includes: All time-series paths were found using a depth-first search algorithm; For each timing path, the timing exception constraints to be replaced in the timing path are replaced one by one to generate the replaced timing path; Generate replacement timing options based on the replaced timing path; Based on the generated timing options, merge and replace the timing paths to generate new timing constraints; The BFS replacement step includes: Based on the characteristics corresponding to each matching object, match all options of timing exception constraints to be replaced, as well as pins, and / or ports, and / or clocks in the options. The matching objects include at least one of pins, ports, and clocks. Determine if a pin or port is present in the options. If so, replace the pin and / or port in the options and then generate the -from and -to options for the new timing constraint instruction. If not, directly generate the -from and -to options for the new timing constraint instruction. Generate new timing constraint instructions.

2. The propagation method for timing exception constraints as described in claim 1, characterized in that, The generation of the replaced timing path includes the following steps: All found timing paths are split according to the options; Each option is replaced one by one based on the timing path. The replacement rules are classified according to the type of pin, port or clock of the timing path and its relative position to the instance. Combine the replaced options according to the original timing path.

3. A method for propagating static timing constraints, characterized in that, include: Determine whether the current timing constraint to be replaced is a timing exception constraint; If so, then the propagation of the timing exception constraint according to claim 1 or 2 shall be carried out; If not, then proceed with the normal propagation process of static timing constraints.

4. A method for propagating static timing constraints, characterized in that, Configure parameters related to static timing constraint propagation, serial-parallel execution mode, and module name of the submodule to propagate downwards; the parameters include module name, working directory, path of the timing constraint file to be replaced, and whether to use parallelism; Determine if the current target instance has already been generated; If no generation occurs, configure the submodules that propagate downwards; If it has already been generated, determine whether the parallel execution mode is parallel mode or serial mode; If in parallel mode, multiple static timing analysis tools are activated to execute the propagation method of static timing constraints as described in claim 3 in parallel. If in serial mode, the propagation method of static timing constraints as described in claim 3 is executed serially.

5. A computer-readable storage medium for storing a computer program, characterized in that, The computer program executes the propagation method of timing exception constraints as described in claim 1 or 2 when it runs.

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