Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the method comprises: providing a substrate, including a device unit area, the device unit area comprises a plurality of adjacent sub-device areas, and one or more stacked channel layers are respectively formed on the substrate of the sub-device areas; an isolation wall is formed on the substrate between adjacent sub-device areas; the first sacrificial layer is removed through the gate opening to form a through slot; a second channel layer is formed on the top surface, bottom surface and side surface of the first channel layer exposed by the gate opening and the through slot, and the included angle between the end surface of the second channel layer and the exposed isolation wall side wall of the first channel layer is an acute angle at the junction of the top surface of the first channel layer and the isolation wall side wall, and at the junction of the bottom surface of the first channel layer and the isolation wall side wall; compared with the scheme without forming the second channel layer, the gate structure improves the covering capacity of the channel layer, and further improves the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration, and semiconductor process nodes are continuously shrinking in accordance with Moore's Law. Transistors, as the most basic semiconductor devices, are currently widely used. Therefore, as the component density and integration of semiconductor devices increase, the channel length of transistors must be continuously shortened to adapt to the shrinking process nodes.

[0003] To better adapt to the requirement of proportionally shrinking device dimensions, semiconductor processes have gradually begun to transition from planar transistors to three-dimensional transistors with higher efficiency, such as gate-all-around (GAA) transistors and forksheet transistors. Summary of the Invention

[0004] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the performance of the semiconductor structure.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate including discrete device cell regions, each device cell region including a plurality of adjacent sub-device regions in a first direction; a plurality of channel structure layers extending along a second direction, respectively located on the substrate of the sub-device regions and spaced apart from the substrate, the second direction being perpendicular to the first direction, each channel structure layer including one or more spaced first channel layers; an isolation wall located on the substrate between adjacent sub-device regions and extending along the second direction, the isolation wall covering the sidewalls of the channel structure layers on both sides, the top of the isolation wall being higher than the top of the channel structure layers; and a second channel layer located on the top surface, bottom surface, and side surface of the first channel layers exposed by the isolation wall, the second channel layer being located on the top surface of the first channel layer and the side surface of the isolation wall. The junction of the walls, and the junction of the bottom surface of the first channel layer and the sidewall of the isolation wall, the angle between the end face of the second channel layer and the exposed sidewall of the isolation wall of the first channel layer is an acute angle, the second channel layer and the first channel layer are used to form a channel layer; a gate structure, located on the substrate of the sub-device region and spanning the channel structure layer along the first direction, the gate structure covers the top and sidewall of the channel structure layer of the sub-device region, the gate structure includes a gate dielectric layer surrounding the second channel layer covering the sub-device region, and a gate electrode layer covering the gate dielectric layer; source and drain doped layers, located on the substrates on both sides of the gate structure of the sub-device region, and covering the end face of the channel structure layer below the gate structure, the source and drain doped layers of adjacent sub-device regions are isolated by the isolation wall.

[0006] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate including discrete device cell regions, each device cell region including a plurality of sub-device regions adjacent in a first direction, wherein stacked structures extending in a second direction are respectively formed on the substrate of the plurality of sub-device regions, the second direction being perpendicular to the first direction, the stacked structures including one or more stacked channel stacks, each channel stack including a first sacrificial layer and a first channel layer located on the first sacrificial layer, and an isolation wall extending in the second direction being formed on the substrate between adjacent sub-device regions, the isolation wall covering the sidewalls of the stacked structures on both sides; forming a dielectric layer covering a portion of the stacked structures on the substrate, wherein a gate opening is formed in the dielectric layer penetrating the dielectric layer and extending in the first direction, the gate opening... A gate opening spans the stacked structure and isolation wall of the device cell region, exposing a portion of the top and sidewalls of the stacked structure. The first sacrificial layer is removed through the gate opening to form a through-slot communicating with the gate opening. After forming the through-slot, a second channel layer is formed on the top, bottom, and side surfaces of the first channel layer exposed by the gate opening and the through-slot. At the junction of the top surface of the first channel layer and the sidewall of the isolation wall, and at the junction of the bottom surface of the first channel layer and the sidewall of the isolation wall, the angle between the end face of the second channel layer and the exposed sidewall of the isolation wall of the first channel layer is an acute angle. The second channel layer and the first channel layer constitute a channel layer. A gate structure is formed in the gate opening and the through-slot. The gate structure includes a gate dielectric layer surrounding and covering the second channel layer, and a gate electrode layer covering the gate dielectric layer.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] In the semiconductor structure provided by this invention, a second channel layer is formed on the top surface, bottom surface, and side surface of the first channel layer exposed by the isolation wall. At the junction of the top surface of the first channel layer and the side wall of the isolation wall, and at the junction of the bottom surface of the first channel layer and the side wall of the isolation wall, the angle between the end face of the second channel layer and the exposed side wall of the isolation wall is acute. The second channel layer and the first channel layer constitute a channel layer. Compared with a scheme without a second channel layer, in this invention, at the junction of the top surface of the channel layer and the side wall of the isolation wall, the angle between the end face of the second channel layer and the exposed side wall of the isolation wall is acute. At the junction of the bottom surface of the channel layer and the sidewall of the isolation wall, the channel layer is recessed inward. On the one hand, this helps to reduce the channel width near the isolation wall. On the other hand, it allows the gate structure to cover the end face of the second channel layer facing the isolation wall, increasing the contact surface area between the gate structure and the channel layer near the isolation wall. This improves the gate structure's ability to encapsulate the channel layer. Both of these aspects help to improve the gate structure's control over the channel near the sidewall of the isolation wall, thereby improving the leakage current problem and correspondingly improving the performance of the semiconductor structure.

[0009] In the semiconductor structure formation method provided by this embodiment of the invention, after removing the first sacrificial layer through the gate opening, a second channel layer is formed on the top, bottom, and side surfaces of the first channel layer exposed by the gate opening and the via. At the junction of the top surface of the first channel layer and the sidewall of the isolation wall, and at the junction of the bottom surface of the first channel layer and the sidewall of the isolation wall, the angle between the end face of the second channel layer and the exposed sidewall of the isolation wall of the first channel layer is an acute angle. Compared with a scheme where no second channel layer is formed, in this embodiment of the invention, the second channel layer and the first channel layer are used to constitute the channel layer. That is, in the channel layer... At the junction of the top surface and the sidewall of the isolation wall, and at the junction of the bottom surface of the channel layer and the sidewall of the isolation wall, the channel layer is recessed inward. On the one hand, this helps to reduce the channel width near the isolation wall. On the other hand, it allows the gate structure to cover the end face of the second channel layer facing the isolation wall, increasing the contact surface area between the gate structure and the channel layer near the isolation wall. This improves the gate structure's ability to encapsulate the channel layer. Both of these aspects help to improve the gate structure's control over the channel near the sidewall of the isolation wall, thereby improving the leakage current problem and correspondingly improving the performance of the semiconductor structure. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a semiconductor structure.

[0011] Figures 2 to 3 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0012] Figure 4This is a schematic diagram of another embodiment of the semiconductor structure of the present invention;

[0013] Figures 5 to 14 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure of the present invention;

[0014] Figures 15 to 16 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming the semiconductor structure of the present invention. Detailed Implementation

[0015] The performance of current semiconductor structures still needs improvement. This paper analyzes the reasons why the performance of one particular semiconductor structure needs further improvement.

[0016] Figure 1 This is a schematic diagram of a semiconductor structure.

[0017] The semiconductor structure includes: a substrate, comprising discrete device cell regions 10A, wherein the device cell regions 10A are included in a first direction (e.g., Figure 1 Multiple adjacent sub-device regions 10d on the substrate (as shown in the X direction), the substrate including a substrate (not shown) and fins 10 protruding from the substrate; along the second direction (as shown in the X direction) Figure 1 A channel structure layer 20 extending in the Y direction (as shown in the middle) is located on the fins 10 of the sub-device regions 10d and spaced apart from the fins 10, with the second direction perpendicular to the first direction. The channel structure layer 20 includes one or more spaced channel layers 25; an isolation structure 30 is located on the substrate on the side of the fins 10, the isolation structure 30 covers the sidewalls of the fins 10 and exposes the channel structure layer 20; an isolation wall 50 is located on the substrate between adjacent sub-device regions 10d and extends along the second direction, the isolation wall 50 covers the sidewalls of the channel structure layer 20 on both sides, and the top of the isolation wall 50 is higher than the top of the channel structure layer 20; a gate structure 40 is located on the isolation structure 30, the gate structure 40 spans the channel structure layer 20 and surrounds and covers a portion of the top, a portion of the sidewalls and a portion of the bottom of the channel structure layer 20.

[0018] The isolation wall 50 is located on the substrate between adjacent sub-device regions 10d. The isolation wall 50 covers the sidewalls of the channel structure layer 20 on both sides. Therefore, the gate structure 40 cannot completely cover all surfaces of the channel layer 25. That is, under the shielding of the isolation wall 50, the gate structure 40 only covers the top surface, bottom surface, and sidewall facing away from the isolation wall 50 of the channel layer 25. The sidewall of the channel layer 25 in contact with the isolation wall 50 is difficult to be covered by the gate structure 40. This results in poor control of the channel near the sidewall of the isolation wall 50 by the gate structure 40, which in turn leads to a large leakage current in the device and consequently poor performance of the semiconductor structure.

[0019] To address the aforementioned technical problem, embodiments of the present invention provide a semiconductor structure including a second channel layer. The second channel layer is located on the top, bottom, and side surfaces of a first channel layer exposed by an isolation wall. At the junction of the top surface of the first channel layer and the sidewall of the isolation wall, and at the junction of the bottom surface of the first channel layer and the sidewall of the isolation wall, the angle between the end face of the second channel layer and the exposed sidewall of the isolation wall is acute. The second channel layer and the first channel layer constitute a channel layer. Compared to solutions without a second channel layer, embodiments of the present invention provide a semiconductor structure with a second channel layer. At the junction of the top surface of the layer and the sidewall of the isolation wall, and at the junction of the bottom surface of the channel layer and the sidewall of the isolation wall, the channel layer is recessed inward. On the one hand, this helps to reduce the channel width near the isolation wall. On the other hand, it allows the gate structure to cover the end face of the second channel layer facing the isolation wall, increasing the contact surface area between the gate structure and the channel layer near the isolation wall, thereby improving the gate structure's ability to encapsulate the channel layer. Both of these aspects help to improve the gate structure's control over the channel near the sidewall of the isolation wall, thus improving the leakage current problem and correspondingly improving the performance of the semiconductor structure.

[0020] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0021] Figures 2 to 3 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention. Figure 2 It is a top view. Figure 3 (a) is Figure 2 A cross-sectional view along the AA1 direction. Figure 3 (b) is Figure 2 A cross-sectional view along the BB1 ​​direction.

[0022] The semiconductor structure includes: a substrate (not shown), comprising discrete device cell regions 300A, wherein the device cell regions 300A include a first direction (e.g., Figure 2Multiple adjacent sub-device regions 300a along the Y direction (as shown in the middle); multiple regions along the second direction (such as...) Figure 2 A channel structure layer 330 extending in the X direction (as shown in the middle X direction) is located on the substrate of the sub-device area 300a and spaced apart from the substrate. The second direction is perpendicular to the first direction. The channel structure layer 330 includes one or more spaced first channel layers 332; an isolation wall 370 is located on the substrate between adjacent sub-device areas 300a and extends along the second direction. The isolation wall 370 covers the sidewalls of the channel structure layer 330 on both sides, and the top of the isolation wall 370 is higher than the top of the channel structure layer 330; a second channel layer 333 is located on the top, bottom, and side surfaces of the first channel layer 332 exposed by the isolation wall 370. At the junction of the top surface of the first channel layer 332 and the sidewall of the isolation wall 370, and at the junction of the bottom surface of the first channel layer 332 and the sidewall of the isolation wall 370, the included angle α between the end face of the second channel layer 333 and the sidewall of the isolation wall 370 exposed by the first channel layer 332 is (e.g., ...). Figure 3 (As shown) is an acute angle. The second channel layer 333 and the first channel layer 332 are used to form the channel layer 335. The gate structure 400 is located on the substrate of the sub-device region 300a and spans the channel structure layer 330 along the first direction. The gate structure 400 covers the top and sidewalls of the channel structure layer 330 of the sub-device region 300a. The gate structure includes a gate dielectric layer 410 surrounding the second channel layer 333 covering the sub-device region 300a and a gate electrode layer 420 covering the gate dielectric layer 410. The source and drain doped layers 350 are located on the substrates on both sides of the gate structure 400 of the sub-device region 300a and cover the end face of the channel structure layer 330 below the gate structure 400. The source and drain doped layers 350 of adjacent sub-device regions 300a are isolated by the isolation wall 370.

[0023] The substrate is used to provide a process platform for the formation of semiconductor structures.

[0024] In this embodiment, the semiconductor structure is a forksheet transistor.

[0025] Therefore, the substrate includes discrete device cell regions 300A, each comprising a plurality of adjacent sub-device regions 300a in a first direction. In the fork-type gate transistor, adjacent sub-device regions 300a are isolated by dielectric walls.

[0026] In this embodiment, the device unit region 300A includes two sub-device regions 300a. Specifically, the sub-device region 300a includes a first sub-device region 300n for forming a first type transistor and a second sub-device region 300p for forming a second type transistor, wherein the first type transistor and the second type transistor have different channel conductivity types.

[0027] As an example, the first sub-device region 300n is used to form an NMOS transistor, and the second sub-device region 300p is used to form a PMOS transistor. In other embodiments, the first sub-device region is used to form a PMOS transistor, and the second sub-device region is used to form an NMOS transistor. In other embodiments, the device cell region may also include other numbers of sub-device regions, and the types of transistors formed in each sub-device region may be the same or different.

[0028] In this embodiment, the substrate has a three-dimensional structure, including a substrate 300 and fins 310 protruding from the substrate 300 of the device unit region 300A. In other embodiments, the substrate may also be a planar substrate.

[0029] In this embodiment, the substrate 300 is made of silicon. In other embodiments, the substrate may be made of one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium bismuth. The substrate may also be other types of substrates such as silicon-on-insulator substrate or germanium-on-insulator substrate.

[0030] In this embodiment, the fin 310 is made of the same material as the substrate 300, and the material of the fin 310 is silicon.

[0031] Accordingly, in this embodiment, the channel structure layer 330 is located on the fin portion 310 of the sub-device area 300a and is spaced apart from the fin portion 310, and the channel structure layer 330 and the fin portion 310 extend in the same direction.

[0032] Along a direction perpendicular to the surface of the substrate 300, the channel structure layer 330 includes one or more first channel layers 332 spaced apart, that is, in the channel structure layer 330, the stacking direction of the first channel layers 332 is perpendicular to the surface of the substrate 300.

[0033] The first channel layer 332 is used as part of the channel layer 335 to provide a conductive channel for the transistor.

[0034] The material of the first channel layer 332 includes silicon, silicon germanide, germanium, or group III-V semiconductor materials. The material of the first channel layer 332 is determined according to the channel conductivity type and performance requirements of the transistor in the sub-device region 300a.

[0035] As an example, the first channel layer 332 of the first sub-device region 300n and the second sub-device region 300p is made of the same material, namely silicon. In other embodiments, the first channel layer materials of the first sub-device region and the second sub-device region may be different.

[0036] In this embodiment, each channel structure layer 330 is described using the example of two stacked first channel layers 332. In other embodiments, the number of first channel layers in each channel structure layer may also be other.

[0037] In this embodiment, the semiconductor structure further includes an isolation structure 301 located on the substrate 300 on the side of the fin 310. The isolation structure 301 covers the sidewall of the fin 310 and exposes the channel structure layer 330.

[0038] The isolation structure 301 is used to isolate adjacent fins 310. The isolation structure 301 is also used to isolate the gate structure 400 from the substrate 300.

[0039] The isolation structure 301 is made of an insulating material. As an example, the material of the isolation structure 301 is silicon oxide. Silicon oxide has good insulation properties and generates relatively low stress, which is beneficial for improving process reliability. In other embodiments, the material of the isolation structure can also be a suitable insulating material such as silicon oxynitride.

[0040] The isolation wall 370 is located between the channel structure layers 330 of adjacent sub-device regions 300a. The isolation wall 370 covers the sidewalls of the channel structure layers 330 on both sides. The isolation wall 370 is used to isolate the channel structure layers 330 of adjacent sub-device regions 300a, thereby isolating the transistors in adjacent sub-device regions 300a, and thus enabling a smaller spacing between the transistors in adjacent sub-device regions 300a.

[0041] In this embodiment, the substrate includes an adjacent first sub-device region 300n and a second sub-device region 300p. Therefore, the isolation wall 370 is located on the substrate between the first sub-device region 300n and the second sub-device region 300p. Specifically, the isolation wall 370 is located between the channel structure layer 330 of the first sub-device region 300n and the channel structure layer 330 of the second sub-device region 300p.

[0042] The material of the isolation wall 370 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, and silicon carbonitride-boronide. In this embodiment, the material of the isolation wall 370 is silicon nitride.

[0043] In this embodiment, the top of the isolation wall 370 is higher than the top of the trench structure layer 330, thereby improving the isolation effect of the isolation wall 370. In other embodiments, the top surface of the isolation wall may also be flush with the top surface of the trench structure layer.

[0044] As an example, the bottom of the isolation wall 370 extends into the fin 310, that is, the isolation wall 370 is embedded in the fin 310, and the bottom of the isolation wall 370 is lower than the top of the fin 310, thereby further improving the isolation effect of the isolation wall 370.

[0045] The first channel layer 332 and the second channel layer 333 located on the surface of the first channel layer 332 constitute a channel layer 335, thereby jointly providing a conductive channel for the transistor. That is, each channel layer 335 includes a first channel layer 332 and a second channel layer 333 covering the top, bottom and side surfaces of the first channel layer 332.

[0046] The second channel layer 333 is located on the top, bottom, and side surfaces of the first channel layer 332 exposed by the isolation wall 370. At the junction of the top surface of the first channel layer 332 and the side wall of the isolation wall 370, and at the junction of the bottom surface of the first channel layer 332 and the side wall of the isolation wall 370, the angle α between the end face of the second channel layer 333 and the side wall of the isolation wall 370 exposed by the first channel layer 332 is an acute angle. That is, at the junction of the top surface of the channel layer 335 and the side wall of the isolation wall 370, and at the junction of the bottom surface of the channel layer 335 and the side wall of the isolation wall 370, the channel layer 335 extends towards... Compared to designs without a second channel layer, the recessed design has several advantages. First, it reduces the channel width near the isolation wall. Second, it allows the gate structure 400 to cover the end face of the second channel layer 333 facing the isolation wall 370, increasing the contact surface area between the gate structure 400 and the channel layer 335 near the isolation wall 370. This improves the gate structure 400's ability to encapsulate the channel layer 335. Both of these aspects enhance the gate structure 400's control over the channel near the sidewall of the isolation wall 370, thus mitigating leakage current and improving the performance of the semiconductor structure.

[0047] By providing a second channel layer 333 on the surface of the first channel layer 332, the channel layer 335 can be recessed inwards while reducing process risks (e.g., avoiding the introduction of etching processes).

[0048] Specifically, the second channel layer 333 is epitaxially grown on the surface of the first channel layer 332. The epitaxial growth process is described in... <111> The growth rate of one crystal face is typically greater than that of other crystal faces (e.g., crystal facets). <100> The growth rate of the crystal planes (crystal planes) means that, at the corners of the end and top faces of the first channel layer 332, the corners of the end and bottom faces of the first channel layer 332, the junction of the top face of the first channel layer 132 and the sidewall of the isolation wall 370, and the junction of the bottom face of the first channel layer 332 and the sidewall of the isolation wall 170, the surface of the second channel layer 333 is closer to the growth rate of the crystal planes. <111> The crystal plane, that is, the second channel layer 333, has a bevel, such that at the junction of the top surface of the first channel layer 332 and the side wall of the isolation wall 370, and at the junction of the bottom surface of the first channel layer 332 and the side wall of the isolation wall 370, the included angle α between the end face of the second channel layer 333 and the exposed side wall of the isolation wall 370 of the first channel layer 332 is an acute angle.

[0049] The angle α between the end face of the second channel layer 333 and the exposed sidewall of the isolation wall 370 of the first channel layer 332 should not be too small or too large. If the angle α is too small, the filling ability of the gate structure 400 between the end face of the second channel layer 333 and the sidewall of the isolation wall 370 will be poor, resulting in poor coverage of the channel layer 335 near the isolation wall 370. If the angle α is too large, the end face of the second channel layer 333 will be difficult to obtain a significant slope near the isolation wall 370, resulting in poor inward indentation of the channel layer 335 and thus poor control of the channel near the isolation wall 370 by the gate structure 400. Therefore, in this embodiment, the angle α between the end face of the second channel layer 333 and the exposed sidewall of the isolation wall 370 of the first channel layer 332 is 35 degrees to 75 degrees. For example, the angle α between the end face of the second channel layer 333 and the exposed sidewall of the isolation wall 370 of the first channel layer 332 is 45 degrees or 55 degrees.

[0050] It should be noted that, in the actual process, appropriate epitaxial process parameters can be adjusted according to the material properties of the first channel layer 332 to obtain the required included angle α.

[0051] The second channel layer 333 and the first channel layer 332 together constitute the channel layer 335. Therefore, the material of the second channel layer 333 includes silicon, silicon germanide, germanium, or group III-V semiconductor materials.

[0052] Specifically, the material of the second channel layer 333 is determined according to the type of transistor and performance requirements. For example, if the first sub-device region 300n is used to form an NMOS transistor and the second sub-device region 300p is used to form a PMOS transistor, then the material of the second channel layer 333 located in the first sub-device region 300n is silicon, and the material of the second channel layer 333 located in the second sub-device region 300p is silicon germanide.

[0053] It should be noted that, since the second channel layer 333 is located on the surface of the first channel layer 332 exposed by the isolation wall 370, the thickness of the channel layer 335 is equal to the sum of the thickness of the first channel layer 332 and twice the thickness of the second channel layer 333 in the direction perpendicular to the substrate surface, and the width of the channel layer 335 is equal to the width of the first channel layer 332 and the thickness of the second channel layer 333 in the direction perpendicular to the sidewall of the isolation wall 370.

[0054] The thickness of the second channel layer 333 should not be too small or too large.

[0055] If the thickness of the second channel layer 333 is too small, it is easy for the end face of the second channel layer 333 to have a sufficiently obvious slope at the junction of the top surface of the first channel layer 332 and the side wall of the isolation wall 370, and at the junction of the bottom surface of the first channel layer 332 and the side wall of the isolation wall 370. This results in poor coverage of the end face of the second channel layer 333 towards the isolation wall 370 by the gate structure 400, which is detrimental to improving the control capability of the gate structure 400 over the channel near the side wall of the isolation wall 370. Moreover, the smaller the thickness of the second channel layer 333, the smaller the formation process window of the second channel layer 333, which is more likely to result in poor formation quality of the second channel layer 333. Both of these aspects can easily lead to poor performance of the semiconductor structure.

[0056] If the thickness of the second channel layer 333 is too large, along the direction perpendicular to the substrate surface, it is easy to cause the distance between adjacent channel layers 335 to be too small, thereby easily reducing the window of the formation process of the gate electrode layer 420 in the gate structure 400. Alternatively, when the thickness of the channel layer 335 meets the process requirements, it will result in the thickness of the first channel layer 332 being too small. This will not only easily reduce the mechanical properties of the first channel layer 332 and increase the probability of deformation of the first channel layer 332, but also affect the height of the source / drain doped layer 350, thereby affecting the volume of the source / drain doped layer 350 and consequently affecting the performance of the source / drain doped layer 350.

[0057] Therefore, in this embodiment, the thickness of the second trench layer 333 is to For example, the thickness of the second channel layer 333 is or

[0058] It is understandable that, based on actual process requirements, compared with the scheme without a second channel layer, this embodiment can appropriately reduce the thickness of the first channel layer 332 so that the thickness and width of the channel layer 335 meet the process requirements.

[0059] The gate structure 400 is used to control the opening or closing of the conductive channel of the corresponding transistor.

[0060] Specifically, the gate structure 400 includes a gate dielectric layer 410 and a gate electrode layer 420 covering the gate dielectric layer 410.

[0061] The gate dielectric layer 410 is used to isolate the gate electrode layer 420 and the conductive channel.

[0062] The material of the gate dielectric layer 410 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0063] In this embodiment, the gate structure 400 is a metal gate structure. Therefore, the gate dielectric layer 410 includes a high-k gate dielectric layer.

[0064] The high-k gate dielectric layer is made of a high-k dielectric material, which refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc. As an example, the material of the high-k gate dielectric layer is HfO2.

[0065] It should be noted that the gate dielectric layer 410 may further include a gate oxide layer located between the high-k gate dielectric layer and the second channel layer 333. As an example, the material of the gate oxide layer may be silicon oxide.

[0066] The gate electrode layer 420 is used to draw out the electrical properties of the gate structure 400.

[0067] The material of the gate electrode layer 420 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0068] In this embodiment, the gate electrode layer 420 includes a work function layer 421 and an electrode layer 422 covering the work function layer 421. The work function layer 421 is used to adjust the threshold voltage of the corresponding transistor.

[0069] In other embodiments, the gate electrode layer may also consist only of a work function layer.

[0070] As an example, the first sub-device region 300n is used to form an NMOS transistor, and the second sub-device region 300p is used to form a PMOS transistor. Therefore, the work function layer 421 located in the first sub-device region 300n and the work function layer 421 located in the second sub-device region 300p are made of different materials. The work function layer 421 located in the first sub-device region 300n is used to adjust the threshold voltage of the NMOS transistor, and the work function layer 421 located in the second sub-device region 300p is used to adjust the threshold voltage of the PMOS transistor.

[0071] It should be noted that an isolation wall 370 is provided on the substrate between adjacent sub-device regions 300a, which helps to reduce the probability of mutual influence between the work function layers 421 of adjacent sub-device regions 300a (for example, reducing the probability of ions diffusing into each other in the work function layers 421), thereby helping to further improve the performance of the semiconductor structure.

[0072] It should also be noted that the top of the isolation wall 370 is higher than the top of the channel structure layer 330. Therefore, the gate structure 400 also covers the sidewall of the isolation wall 370, which is higher than the top surface of the channel structure layer 330.

[0073] As an example, the top of the gate structure 400 is flush with the top of the isolation wall 370, so that the gate structures 400 of adjacent sub-device regions 300a are isolated from each other by the isolation wall 370, thereby further reducing the probability of mutual interference between the gate structures 400 of adjacent sub-device regions 300a.

[0074] In other embodiments, each sub-device region may share an electrode layer within the same device unit region.

[0075] The source / drain doped layer 350 is used as the source or drain region of a transistor.

[0076] Specifically, the doping type of the source / drain doped layer 350 is the same as the channel conductivity type of the corresponding transistor. When the transistor is a PMOS transistor, the material of the source / drain doped layer 350 includes silicon germanide doped with P-type ions or silicon doped with P-type ions, where the P-type ions include B, Ga, or In. When the transistor is an NMOS transistor, the material of the source / drain doped layer 350 includes silicon doped with N-type ions or silicon carbide doped with N-type ions, where the N-type ions include P, As, or Sb.

[0077] In this embodiment, in the first direction, the source and drain doped layers 350 of adjacent sub-device regions 300a are isolated by the isolation wall 370, thereby reducing the probability of bridging between the source and drain doped layers 350 of adjacent sub-device regions 300a.

[0078] In this embodiment, the semiconductor structure further includes a gate sidewall 405, which covers the sidewall of the gate structure 400. The gate sidewall 405 is used to protect the sidewall of the gate structure 400 and also to define the formation location of the source / drain doped layer 350.

[0079] The gate sidewall 405 can be a single-layer structure or a multilayer structure, and the material of the gate sidewall 405 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the gate sidewall 405 is a single-layer structure, and the material of the gate sidewall 405 is silicon nitride.

[0080] It should be noted that the gate structure 400 surrounds the second channel layer 333 covering the sub-device region 300a. Therefore, the portion of the gate structure 400 located between adjacent channel layers 335 and between the channel layer 335 and the substrate constitutes the first portion 400a (e.g., Figure 3 (b) shows that the remaining portion of the gate structure 400 serves as the second portion 400b (as shown in [b]). Figure 3 (b) is shown.

[0081] In this embodiment, the semiconductor structure further includes an inner spacer 360 located between the source / drain doped layer 350 and the first portion 400a.

[0082] The inner wall 360 serves to isolate the gate structure 400 and the source / drain doped layer 350, increasing the distance between the first part 400a and the source / drain doped layer 350, thereby helping to reduce the parasitic capacitance between the gate structure 400 and the source / drain doped layer 350.

[0083] The material of the inner wall 360 may include one or more of silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric materials (low-k dielectric materials refer to dielectric materials with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9), and ultra-low-k dielectric materials (ultra-low-k dielectric materials refer to dielectric materials with a relative permittivity less than 2.6). In this embodiment, the material of the inner wall 360 is silicon nitride.

[0084] In this embodiment, the top surface of the source / drain doped layer 350 is higher than the top surface of the channel structure layer 330, and the inner sidewall 360 is located between the source / drain doped layer 350 and the second part 400b.

[0085] During the formation of the semiconductor structure, in order for the gate structure 400 to surround the second channel layer 333 covering the sub-device region 300a, a first sacrificial layer is formed between adjacent first channel layers 332 and between the first channel layer 332 and the substrate, and a second sacrificial layer is also formed on top of the topmost first channel layer 332. During the process of removing the first and second sacrificial layers, the second sacrificial layer can protect the top of the first channel layer 332. Typically, after laterally etching a portion of the width of the first and second sacrificial layers to form an inner groove, the inner sidewall 360 is formed in the inner groove. Therefore, the presence of the second sacrificial layer means that the inner sidewall 360 is also located between the source / drain doped layer 350 and the second portion 400b.

[0086] In other embodiments, the second sacrificial layer may not be formed, and correspondingly, the inner wall may be located only between the source / drain doped layer and the first portion.

[0087] In this embodiment, the semiconductor structure further includes an interlayer dielectric layer 302 located on the substrate on the side of the gate structure 400. The interlayer dielectric layer 302 covers the source / drain doped layer 350 and also covers the sidewall of the gate structure 400. Specifically, the interlayer dielectric layer 302 covers the sidewall of the gate sidewall 405.

[0088] The interlayer dielectric layer 302 is used to achieve electrical isolation between adjacent devices.

[0089] The interlayer dielectric layer 302 is made of an insulating material. As an example, the interlayer dielectric layer 302 is made of silicon oxide.

[0090] Figure 4 This is a schematic diagram of another embodiment of the semiconductor structure of the present invention. Figure 4 (a) is a sectional view along the direction perpendicular to the sidewall of the isolation wall. Figure 4 (b) is a cross-sectional view located on one side of the partition wall and along the direction of the partition wall's extension.

[0091] The similarities between this embodiment and the previous embodiments will not be repeated here. The difference between this embodiment and the previous embodiments is that the semiconductor structure further includes an isolation layer 580, located below the channel structure layer (not shown) and between the bottom of the gate structure (not shown) and the top of the substrate.

[0092] Specifically, the isolation layer 580 is located on top of the fin 510. Correspondingly, the isolation wall 570 penetrates the isolation layer 580.

[0093] As an example, the isolation structure 501 is located on a substrate (not shown) on the side of the fin 510 and covers the sidewalls of the fin 510 and the sidewalls of the isolation layer 580. Specifically, the top of the isolation structure 501 is flush with the top of the isolation layer 580.

[0094] The isolation layer 580 is used to isolate the gate structure and the substrate, thereby reducing the probability of leakage current between the gate structure and the substrate, and helping to suppress the formation of parasitic devices.

[0095] Specifically, the second channel layer (not shown) is epitaxially grown on the surface of the first channel layer exposed by the isolation wall (not shown). Since the isolation layer 580 covers the substrate below the channel structure layer, the second channel layer will not be formed on the surface of the isolation layer 580 during the epitaxial growth of the second channel layer, thereby making the bottom of the gate structure 500 contact the isolation layer 580.

[0096] The insulating layer 580 is made of a dielectric material. Specifically, the dielectric material includes one or more of silicon oxide, silicon oxynitride, and silicon nitride. As an example, the insulating layer 580 is made of silicon oxide.

[0097] In this embodiment, the isolation layer 580 is a film structure. Compared with the scheme of forming the isolation layer by ion implantation of the substrate (that is, the isolation layer is an ion-doped layer), this embodiment can avoid the problem of increased parasitic capacitance caused by ion implantation of the substrate.

[0098] In this embodiment, the isolation layer 580 extends between the bottom of the source / drain doped layer 550 and the top of the substrate, thereby effectively isolating the source / drain doped layer 550 and reducing the probability of punch-through between the source / drain doped layers 550.

[0099] In other embodiments, the source / drain doped layer may also be located only between the bottom of the gate structure and the top of the substrate, that is, the source / drain doped layer is in contact with the substrate, thereby increasing the growth rate of the source / drain doped layer and improving the growth quality of the source / drain doped layer, and reducing defects generated during the growth process.

[0100] Figures 5 to 14 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0101] Reference Figure 5 and Figure 6 , Figure 5 It is a top view. Figure 6 (a) is Figure 5 A cross-sectional view along the AA1 direction. Figure 6 (b) is Figure 5A cross-sectional view along the BB1 ​​direction provides a substrate (not shown) including discrete device cell regions 100A, said device cell regions 100A including in a first direction (e.g. Figure 5 Multiple adjacent sub-device regions 100a are formed on the substrate of the multiple sub-device regions 100a along the second direction (as shown in the Y direction). Figure 5 A stacked structure 120 extending in the X direction (as shown in the first direction) is perpendicular to the second direction. The stacked structure 120 includes one or more stacked channel stacks 130. The channel stack 130 includes a first sacrificial layer 131 and a first channel layer 132 located on the first sacrificial layer 131. An isolation wall 170 extending in the second direction is formed on the substrate between adjacent sub-device regions 100a. The isolation wall 170 covers the sidewalls of the stacked structure 120 on both sides.

[0102] The substrate is used to provide a process platform for the formation of semiconductor structures.

[0103] In this embodiment, the substrate is used to provide a process platform for forming a forksheet transistor.

[0104] Therefore, the substrate includes discrete device cell regions 100A, each comprising a plurality of adjacent sub-device regions 100a in a first direction. In the fork-type gate transistor, adjacent sub-device regions 100a are isolated by an isolation wall 170.

[0105] In this embodiment, the device unit region 100A includes two sub-device regions 100a. Specifically, the sub-device region 100a includes a first sub-device region 100n for forming a first type transistor and a second sub-device region 100p for forming a second type transistor, wherein the first type transistor and the second type transistor have different channel conductivity types.

[0106] As an example, the first sub-device region 100n is used to form an NMOS transistor, and the second sub-device region 100p is used to form a PMOS transistor. In other embodiments, the first sub-device region is used to form a PMOS transistor, and the second sub-device region is used to form an NMOS transistor. In other embodiments, the device cell region may also include other numbers of sub-device regions, and the types of transistors formed in each sub-device region may be the same or different.

[0107] In this embodiment, the substrate has a three-dimensional structure, including a substrate 100 and fins 110 protruding from the substrate 100 of the device unit region 100A. In other embodiments, the substrate may also be a planar substrate.

[0108] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may be made of one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium bismuth. The substrate may also be other types of substrates such as silicon-on-insulator substrate or germanium-on-insulator substrate.

[0109] In this embodiment, the fin 110 is made of the same material as the substrate 100, and the material of the fin 110 is silicon.

[0110] Accordingly, in this embodiment, the stacked structure 120 is located on top of the fin 110, and the stacked structure 120 extends in the same direction as the fin 110.

[0111] The stacked structure 120 includes one or more stacked channel stacks 130, each channel stack 130 including a first sacrificial layer 131 and a first channel layer 132 located on the first sacrificial layer 131. Within the same stacked structure 120, the stacking direction of the channel stacks 130 is perpendicular to the surface of the substrate 100.

[0112] The channel stack 130 provides a process basis for the subsequent formation of the first channel layer 132 with suspended space separation.

[0113] Specifically, the first sacrificial layer 131 is used to support the first channel layer 132, so that the first channel layer 132 can be suspended after the first sacrificial layer 131 is removed. The first sacrificial layer 131 is also used to occupy space for the subsequent formation of the gate structure.

[0114] The first channel layer 132 is used as part of the channel layer to provide a conductive channel for the transistor.

[0115] Specifically, along the extending direction of the stacked structure 120, the stacked structure 120 includes a channel region (not shown), the channel layer of the channel region being used to provide a conductive channel for the transistor, that is, the channel region being used to define the location for subsequent formation of the gate structure.

[0116] The material of the first channel layer 132 includes silicon, silicon germanide, germanium, or group III-V semiconductor materials. The material of the first channel layer 132 is determined according to the channel conductivity type and performance requirements of the transistor.

[0117] Accordingly, based on the material of the first channel layer 132, the first sacrificial layer 131 is selected from materials that have an etching selectivity ratio with the first channel layer 132, and the material of the first sacrificial layer 131 satisfies the following: it can alternately form the first sacrificial layer 131 and the first channel layer 132.

[0118] In this embodiment, the first channel layer 132 of the first sub-device region 100n and the second sub-device region 100p is made of the same material, and the first sacrificial layer 131 of the first sub-device region 100n and the second sub-device region 100p is also made of the same material.

[0119] As an example, the material of the first channel layer 132 is silicon, and the material of the first sacrificial layer 131 is silicon germanide. In the subsequent removal of the first sacrificial layer 131, the etching selectivity of silicon germanide and silicon is relatively high. By setting the material of the first sacrificial layer 131 to silicon germanide, the impact of the removal process of the first sacrificial layer 131 on the first channel layer 132 can be effectively reduced, thereby helping to ensure the quality of the first channel layer 132.

[0120] In other embodiments, depending on the material of the first channel layer in each sub-device region, the first sacrificial layer may also be made of other types of materials. For example, in the same stacked structure, when the material of the first channel layer is silicon germanide, the material of the first sacrificial layer is silicon.

[0121] In other embodiments, the materials of the first channel layer in the first sub-device region and the second sub-device region may be different, and the materials of the first sacrificial layer in the first sub-device region and the second sub-device region may also be different accordingly.

[0122] In this embodiment, the stacked structure 120 is described using two stacked channel stacks 130 as an example. In other embodiments, the number of channel stacks in each stacked structure may also be other.

[0123] In this embodiment, during the step of providing the substrate, the laminated structure 120 further includes a second sacrificial layer 140 located on top of the topmost channel laminate 130, and the second sacrificial layer 140 is made of the same material as the first sacrificial layer 131.

[0124] During the subsequent removal of the pseudo-gate structure, the second sacrificial layer 140 is used to protect the top of the first channel layer 132, thereby reducing the probability of damage to the first channel layer 132.

[0125] Furthermore, the second sacrificial layer 140 and the first sacrificial layer 131 are made of the same material, so that the second sacrificial layer 140 and the first sacrificial layer 131 can be removed in the same step, thereby simplifying the process steps.

[0126] In this embodiment, during the step of providing the substrate, an isolation structure 101 is also formed on the substrate 100 on the side of the fin 110. The isolation structure 101 covers the sidewall of the fin 110 and exposes the stacked structure 120.

[0127] The isolation structure 101 is used to isolate adjacent fins 110. The isolation structure 101 is also used to isolate the subsequently formed gate structure from the substrate 100.

[0128] The isolation structure 101 is made of an insulating material. As an example, the material of the isolation structure 101 is silicon oxide. Silicon oxide has good insulation properties and generates relatively low stress, which is beneficial for improving process reliability. In other embodiments, the material of the isolation structure can also be a suitable insulating material such as silicon oxynitride.

[0129] The isolation wall 170 is located between the stacked structures 120 of adjacent sub-device areas 100a. The isolation wall 170 covers the sidewalls of the stacked structures 120 on both sides. The isolation wall 170 is used in a first direction (e.g., Figure 5 The stacked structure 120 (shown in the Y direction) isolates the transistors of adjacent sub-device regions 100a, thereby isolating the transistors of adjacent sub-device regions 100a and thus achieving a smaller spacing between the transistors in adjacent sub-device regions 100a.

[0130] Furthermore, during the subsequent process of removing the second sacrificial layer 140 and the first sacrificial layer 131 through the gate opening to form a through-cell, the through-cells of adjacent sub-device regions 100a are isolated from each other by the isolation wall 170 along the first direction, and the adjacent channel layers are isolated from each other by the isolation wall 170. This is beneficial to prevent the process from interfering with each other when forming corresponding gate structures in different sub-device regions (for example, reducing the probability of ions diffusing into each other in the work function layers of adjacent sub-device regions).

[0131] In this embodiment, the substrate includes an adjacent first sub-device region 100n and a second sub-device region 100p. Therefore, the isolation wall 170 is formed on the substrate between the first sub-device region 100n and the second sub-device region 100p. Specifically, the isolation wall 170 is located between the stacked structure 120 of the first sub-device region 100n and the stacked structure 120 of the second sub-device region 100p.

[0132] The material of the isolation wall 170 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, and silicon boron carbonitride to ensure that the isolation wall 170 can achieve a better isolation effect. In this embodiment, the material of the isolation wall 170 is silicon nitride.

[0133] In this embodiment, the top of the isolation wall 170 is higher than the top of the stacked structure 120, thereby improving the isolation effect of the isolation wall.

[0134] Specifically, before the isolation wall 170 is formed, a mask layer is formed on the top of the stacked structure 120. The mask layer is used as an etching mask during the formation of the stacked structure 120. During the formation of the isolation wall 170, the top of the isolation wall 170 is flush with the mask layer. After the isolation wall 170 is formed, the mask layer is removed (for example, during the formation of the isolation structure 101, the mask layer is removed). Therefore, the top of the isolation wall 170 is higher than the top of the stacked structure 120.

[0135] In other embodiments, the top of the isolation wall may also be flush with the top of the stacked structure. Therefore, the top of the isolation wall is higher than the top of the first channel layer of the top layer, thereby improving the isolation effect of the isolation wall.

[0136] As an example, the bottom of the isolation wall 170 extends into the fin 110, thereby further improving the isolation effect of the isolation wall 170.

[0137] Continue to refer to Figure 5 and Figure 6 The forming method further includes: forming on the substrate along the first direction (e.g. Figure 5 The pseudo-gate structure 200 (shown in the Y direction) spans the stacked structure 120 and the isolation wall 170.

[0138] The dummy gate structure 200 covers the top and sidewalls of the stacked structure 120 of the channel region (not shown), and the dummy gate structure 200 is used to occupy space for the subsequent formation of the gate structure.

[0139] In this embodiment, the pseudo-gate structure 200 spans the stacked structure 120 and the isolation wall 170. That is, the pseudo-gate structure 200 covers part of the top of the stacked structure 120 and the isolation wall 170, part of the sidewall of the isolation wall 170, and part of the sidewall of the stacked structure 120 facing away from the isolation wall 170.

[0140] In this embodiment, the pseudo-gate structure 200 includes a pseudo-gate layer. The material of the pseudo-gate layer includes polycrystalline silicon, amorphous silicon, or amorphous carbon.

[0141] In this embodiment, the forming method further includes forming a gate sidewall 210 on the sidewall of the pseudo-gate structure 200.

[0142] The gate sidewall 210 is used to protect the sidewalls of the pseudo-gate structure 200 and the sidewalls of the gate structure subsequently formed, and is also used to define the formation positions of the source and drain doped layers.

[0143] The gate sidewall 210 can be a single-layer structure or a multilayer structure, and the material of the gate sidewall 210 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the gate sidewall 210 is a single-layer structure, and the material of the gate sidewall 210 is silicon nitride.

[0144] Continue to refer to Figure 5 and Figure 6 The formation method further includes: forming source / drain doped layers 150 in the stacked structures 120 on both sides of the pseudo-gate structure 200, and the source / drain doped layers 150 of adjacent sub-device regions 100a are isolated by the isolation wall 170.

[0145] Specifically, after the gate sidewall 210 is formed, a source / drain doped layer 150 is formed in the stacked structure 120 on both sides of the pseudo-gate structure 200.

[0146] The source / drain doped layer 150 is used as the source or drain region of a transistor.

[0147] Specifically, the doping type of the source / drain doped layer 150 is the same as the channel conductivity type of the corresponding transistor. When the transistor is a PMOS transistor, the material of the source / drain doped layer 150 includes silicon germanide doped with P-type ions or silicon doped with P-type ions, where the P-type ions include B, Ga, or In. When the transistor is an NMOS transistor, the material of the source / drain doped layer 150 includes silicon doped with N-type ions or silicon carbide doped with N-type ions, where the N-type ions include P, As, or Sb.

[0148] In this embodiment, in the first direction (e.g.) Figure 5 In the Y direction (as shown), the source and drain doped layers 150 of adjacent sub-device regions 100a are isolated by the isolation wall 170, thereby reducing the probability of bridging between the source and drain doped layers 150 of adjacent sub-device regions 100a.

[0149] In this embodiment, before forming the source / drain doped layer 150 in the stacked structure 120 on both sides of the dummy gate structure 200, the method further includes: forming source / drain grooves (not shown) in the stacked structure 120 on both sides of the dummy gate structure 200 in the sub-device region 100a.

[0150] The source / drain grooves provide space for the formation of the source / drain doped layer 150 and also provide a process basis for the subsequent formation of the inner grooves.

[0151] In this embodiment, the fin 110 is exposed at the bottom of the source / drain groove.

[0152] As an example, in the sub-device region 100a, an anisotropic etching process (e.g., dry etching process) is used to etch the stacked structure 120 on both sides of the pseudo-gate structure 200 to form the source-drain groove.

[0153] In this embodiment, after forming the source / drain groove, along the second direction (e.g.) Figure 5 (As shown in the X direction), the first sacrificial layer 132 exposed by the source / drain groove is etched laterally to form an inner groove (not shown). The inner groove is located between adjacent first channel layers 131, or between the first channel layer 131 and the substrate.

[0154] The groove is used to provide space for the subsequent formation of the inner sidewall.

[0155] In this embodiment, an isotropic etching process (e.g., wet etching) is used to perform lateral etching on the first sacrificial layer 132 exposed in the source / drain groove. Here, "lateral" refers to the direction perpendicular to the sidewall of the pseudo-gate structure 200.

[0156] In this embodiment, during the step of lateral etching of the first sacrificial layer 132 exposed by the source-drain groove, the second sacrificial layer 140 exposed by the source-drain groove is also laterally etched. Therefore, the inner groove is also formed between the gate sidewall 210 and the first channel layer 132.

[0157] Accordingly, after forming the inner groove, an inner sidewall 160 is formed in the inner groove; after forming the inner sidewall 160 in the inner groove, a source / drain doped layer 150 is formed in the source / drain groove.

[0158] The inner wall 160 serves to isolate the gate structure and the source / drain doped layer 150, increasing the distance between the gate structure and the source / drain doped layer 150, thereby helping to reduce the parasitic capacitance between the gate structure and the source / drain doped layer 150.

[0159] The material of the inner sidewall 160 may include one or more of silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric materials, and ultra-low-k dielectric materials. In this embodiment, the material of the inner sidewall 160 is silicon nitride.

[0160] It should be noted that, in this embodiment, the sub-device region 100a includes a first sub-device region 100n for forming a first type transistor and a second sub-device region 100p for forming a second type transistor. Therefore, after forming a corresponding source / drain doped layer 150 in either the first sub-device region 100n or the second sub-device region 100p, a source / drain groove, an inner groove, an inner sidewall 160, and a corresponding source / drain doped layer 150 are sequentially formed in the other sub-device region 100a.

[0161] In this process, after a corresponding source / drain doped layer 150 is formed in either the first sub-device region 100n or the second sub-device region 100p, a mask layer is used to shield and protect the sub-device region 100a in which the source / drain doped layer 150 is formed, thereby selectively performing various process steps on the other sub-device region 100a.

[0162] Continue to refer to Figure 5 and Figure 6 and in conjunction with references Figure 7 and Figure 8 , Figure 7 It is a top view. Figure 8 (a) is Figure 7 A cross-sectional view along the AA1 direction. Figure 8 (b) is Figure 7 A cross-sectional view along the BB1 ​​direction shows a dielectric layer 102 formed on the substrate, covering a portion of the stacked structure 120. A gate opening 205 is formed in the dielectric layer 102, extending through the dielectric layer 102 and along the first direction. The gate opening 205 spans the stacked structure 120 and the isolation wall 170 of the device cell region 100A, and exposes a portion of the top and a portion of the sidewalls of the stacked structure 120.

[0163] The gate opening 205 provides space for the subsequent formation of the second channel layer. Specifically, the gate opening 205 exposes the stacked structure 120 of the channel region, and the dielectric layer 102 covers the stacked structure of the remaining regions, so that the second channel layer is formed only on the surface of the first channel layer exposed at the gate opening 205, preventing the formation of the second channel layer in the remaining regions.

[0164] In this embodiment, the dielectric layer 102 is the interlayer dielectric layer 102, which is used to achieve electrical isolation between adjacent devices.

[0165] Accordingly, the gate opening 205 is also used to provide space for the subsequent formation of the gate structure.

[0166] Therefore, in this embodiment, the step of forming a dielectric layer 102 covering a portion of the stacked structure 120 on the substrate includes: after forming the source / drain doping 150, forming a dielectric layer 102 covering the sidewalls of the dummy gate structure 200 on the substrate, wherein the dielectric layer 102 exposes the top of the dummy gate structure 200.

[0167] The dielectric layer 102 exposes the top of the dummy gate structure 200, preparing for the subsequent removal of the dummy gate structure 200.

[0168] Specifically, the step of forming the dielectric layer 102 includes: forming a dielectric material layer (not shown) on the substrate on the side of the pseudo-gate structure 200, the dielectric material layer also covering the top of the pseudo-gate structure 200; removing the dielectric material layer above the top of the pseudo-gate structure 200 to form the dielectric layer 102.

[0169] The dielectric layer 102 is made of an insulating material. As an example, the dielectric layer 102 is made of silicon oxide.

[0170] Accordingly, refer to Figure 7 and Figure 8 The step of forming the gate opening 205 includes: removing the pseudo-gate structure 200.

[0171] Specifically, the process for removing the pseudo-gate structure 200 includes one or both of dry etching and wet etching.

[0172] refer to Figure 9 and Figure 10 , Figure 9 It is a top view. Figure 10 (a) is Figure 9 A cross-sectional view along the AA1 direction. Figure 10 (b) is Figure 9 A cross-sectional view along the BB1 ​​direction shows that the first sacrificial layer 131 is removed through the gate opening 205, forming a through groove 206 that communicates with the gate opening 205.

[0173] The through slot 206 is connected to the gate opening 205, and the through slot 206 is also used to provide space for the subsequent formation of the gate structure.

[0174] Furthermore, the first channel layer 132 of the channel region is exposed through the gate opening 205 and the through slot 206, thereby enabling the subsequent second channel layer to cover each surface of the first channel layer 132 exposed by the gate opening 205 and the through slot 206.

[0175] Specifically, the channel 206 is formed by the adjacent first channel layer 132 and the side wall of the isolation wall 170, or by the fin 110, the side wall of the isolation wall 170, and the first channel layer 132 adjacent to the fin 110.

[0176] In this embodiment, in the first direction (e.g.) Figure 9 In the Y direction (as shown), the through slots 206 of adjacent sub-device regions 100a are isolated by the isolation wall 170.

[0177] In this embodiment, a wet etching process is used to remove the first sacrificial layer 131.

[0178] Specifically, the material of the first channel layer 132 is silicon, and the material of the first sacrificial layer 131 is silicon germanide. Therefore, the first sacrificial layer 131 exposed by the gate opening 40 is removed by HCl vapor. The etching rate of the first sacrificial layer 131 by this wet etching process is much greater than the etching rate of the first channel layer 132 and the fin 110.

[0179] It should be noted that the first sacrificial layer 131 is removed after the source / drain doped layer 150 is formed. After the first sacrificial layer 131 is removed, along the extension direction of the first channel layer 132, both ends of the first channel layer 132 are connected to the source / drain doped layer 150 and suspended in the gate opening 205, thereby providing a process basis for the subsequent gate structure to cover the channel layer of the channel region.

[0180] After removing the first sacrificial layer 131, the first channel layer 132 exposed by the gate opening 205 is spaced apart in the longitudinal direction, thereby providing a process basis for the subsequent formation of the second channel layer on the top and bottom surfaces of the first channel layer 132. Here, longitudinal direction refers to the direction perpendicular to the substrate surface.

[0181] It is understandable that when the materials of the first sacrificial layer of the first sub-device region and the second sub-device region are different, the sacrificial layer of the first sub-device region and the first sacrificial layer of the second sub-device region can be removed in different steps respectively.

[0182] It should be noted that, in this embodiment, a second sacrificial layer 140 is also formed on the top surface of the topmost first channel layer 132. Therefore, in the step of removing the first sacrificial layer 131 through the gate opening 205, the second sacrificial layer 140 exposed by the gate opening 205 is also removed.

[0183] Accordingly, in this embodiment, after removing the first sacrificial layer 131, the top surface of the isolation wall 170 is higher than the top surface of the topmost first channel layer 132.

[0184] refer to Figure 11 and Figure 12 , Figure 11 It is a top view. Figure 12 (a) is Figure 11 A cross-sectional view along the AA1 direction. Figure 12 (b) is Figure 11In a cross-sectional view along the BB1 ​​direction, after the through-slot 206 is formed, a second channel layer 133 is formed on the top, bottom, and side surfaces of the first channel layer 132 exposed by the gate opening 205 and the through-slot 206. At the junction of the top surface of the first channel layer 132 and the side wall of the isolation wall 170, and at the junction of the bottom surface of the first channel layer 132 and the side wall of the isolation wall 170, the included angle α between the end face of the second channel layer 133 and the side wall of the isolation wall 170 exposed by the first channel layer 132 is an acute angle. The second channel layer 133 and the first channel layer 132 are used to form the channel layer 135.

[0185] The first channel layer 132 and the second channel layer 133 located on the surface of the first channel layer 132 constitute a channel layer 135, thereby jointly providing a conductive channel for the transistor. That is, each channel layer 135 includes a first channel layer 132 and a second channel layer 133 covering the top, bottom and side surfaces of the first channel layer 132.

[0186] The second channel layer 133 is formed on the top, bottom, and side surfaces of the first channel layer 132 exposed by the isolation wall 170. At the junction of the top surface of the first channel layer 132 and the side wall of the isolation wall 170, and at the junction of the bottom surface of the first channel layer 132 and the side wall of the isolation wall 170, the angle α between the end face of the second channel layer 133 and the side wall of the isolation wall 170 exposed by the first channel layer 132 is acute. Compared to a scheme without a second channel layer, in this embodiment, at the junction of the top surface of the channel layer 135 and the side wall of the isolation wall 170, At the junction of the bottom surface of the channel layer 135 and the sidewall of the isolation wall 170, the channel layer 135 is recessed inward. On the one hand, this helps to reduce the channel width near the isolation wall 170. On the other hand, it allows the subsequently formed gate structure to cover the end face of the second channel layer 133 facing the isolation wall 170, thereby improving the gate structure's ability to cover the channel layer 135. Both of these aspects help to improve the gate structure's control over the channel near the sidewall of the isolation wall 170, thereby improving the leakage current problem and correspondingly improving the performance of the semiconductor structure.

[0187] Moreover, in this embodiment, after removing the pseudo-gate structure 200 and the first sacrificial layer 131, the second channel layer 133 is formed before forming the gate structure, which requires little modification to the current process and has high process compatibility.

[0188] Furthermore, by forming the second channel layer 333 on the surface of the first channel layer 332, the channel layer 335 can be recessed inward, which helps to reduce process risks (e.g., avoid the introduction of etching processes).

[0189] In this embodiment, an epitaxial growth process is used to form the second channel layer 133.

[0190] Among them, epitaxial growth process in <111> The growth rate of one crystal face is greater than that of other crystal faces (e.g., crystal face). <100> The growth rate of the crystal planes, therefore, at the corners of the end and top surfaces of the first channel layer 132, the corners of the end and bottom surfaces of the first channel layer 132, the junction of the top surface of the first channel layer 132 and the sidewall of the isolation wall 170, and the junction of the bottom surface of the first channel layer 132 and the sidewall of the isolation wall 170, the surface of the second channel layer 333 is closer to the growth rate of the crystal planes. <111> The crystal plane, that is, the second channel layer 333, has a bevel, such that at the junction of the top surface of the first channel layer 132 and the side wall of the isolation wall 170, and at the junction of the bottom surface of the first channel layer 132 and the side wall of the isolation wall 170, the included angle α between the end face of the second channel layer 133 and the exposed side wall of the isolation wall 170 of the first channel layer 132 is an acute angle.

[0191] The angle α between the end face of the second channel layer 133 and the exposed sidewall of the isolation wall 170 of the first channel layer 132 should not be too small or too large. If the angle α is too small, the filling ability of the subsequent gate structure between the end face of the second channel layer 133 and the sidewall of the isolation wall 170 will be poor, resulting in poor coverage of the channel layer 135 near the isolation wall 170 by the gate structure. If the angle α is too large, it will be difficult to obtain a significant slope on the end face of the second channel layer 133 near the isolation wall 170, resulting in poor inward indentation of the channel layer 135, and thus poor control of the channel near the sidewall of the isolation wall 170 by the gate structure. Therefore, in this embodiment, at the junction of the top surface of the first channel layer 132 and the sidewall of the isolation wall 170, and at the junction of the bottom surface of the first channel layer 132 and the sidewall of the isolation wall 170, the included angle α between the end face of the second channel layer 133 and the exposed sidewall of the isolation wall 170 of the first channel layer 132 is 35 degrees to 75 degrees. For example, the included angle α is 45 degrees or 55 degrees.

[0192] It should be noted that, in the actual process, appropriate epitaxial process parameters can be adjusted according to the material properties of the first channel layer 132 to obtain the required included angle α.

[0193] It should also be noted that the process temperature of the epitaxial growth process should not be too low or too high. If the process temperature is too low, it can easily lead to poor epitaxial quality and may also prevent the formation of the second channel layer 133 on the surface of the first channel layer 132. If the process temperature is too high, it can easily damage the crystal lattice of the first channel layer 132, thereby adversely affecting the performance of the first channel layer 132. Therefore, in this embodiment, the process temperature of the epitaxial growth process is between 200°C and 500°C. For example, the process temperature of the epitaxial growth process is 250°C, 300°C, 350°C, or 400°C.

[0194] The second channel layer 133 and the first channel layer 132 together constitute the channel layer 135. Therefore, the material of the second channel layer 133 includes silicon, silicon germanide, germanium, or group III-V semiconductor materials.

[0195] Specifically, the material of the second channel layer 133 is determined according to the type of transistor and performance requirements. For example, if the first sub-device region 100n is used to form an NMOS transistor and the second sub-device region 100p is used to form a PMOS transistor, then the material of the second channel layer 133 formed in the first sub-device region 100n is silicon, and the material of the second channel layer 133 formed in the second sub-device region 100p is silicon germanide.

[0196] In other embodiments, the material of the second channel layer formed in each sub-device region may also be the same, depending on the process requirements.

[0197] It is understandable that when the materials of the second channel layers in the first sub-device region and the second sub-device region are different, corresponding second channel layers are formed in the first sub-device region and the second sub-device region respectively in different steps.

[0198] It should also be noted that, since the second channel layer 133 is located on the surface of the first channel layer 132 exposed by the isolation wall 170, the thickness of the channel layer 135 is equal to the sum of the thickness of the first channel layer 132 and twice the thickness of the second channel layer 133 in the direction perpendicular to the substrate surface, and the width of the channel layer 135 is equal to the width of the first channel layer 132 and the thickness of the second channel layer 133 in the direction perpendicular to the sidewall of the isolation wall 170.

[0199] The thickness of the second channel layer 133 should not be too small or too large.

[0200] If the thickness of the second channel layer 133 is too small, it is easy to make it difficult to obtain a sufficiently obvious slope at the end face of the second channel layer 133. This results in poor coverage of the end face of the second channel layer 133 facing the isolation wall 170 by the gate structure, which is not conducive to improving the control capability of the gate structure over the channel near the side wall of the isolation wall 170. Moreover, the smaller the thickness of the second channel layer 133, the smaller the formation process window of the second channel layer 133, which is also easy to lead to poor formation quality of the second channel layer 133. Both of the above aspects can easily lead to poor performance of the semiconductor structure.

[0201] If the thickness of the second channel layer 133 is too large, along the direction perpendicular to the substrate surface, it is easy to cause the distance between adjacent channel layers 135 to be too small, thereby easily reducing the window of the subsequent gate structure formation process. Alternatively, when the thickness of the channel layer 135 meets the process requirements, it will result in the formation thickness of the first channel layer 132 being too small. This will not only easily reduce the mechanical properties of the first channel layer 132 and increase the probability of deformation of the first channel layer 132, but will also affect the height of the source / drain doped layer 150, thereby affecting the volume of the source / drain doped layer 150 and consequently affecting the performance of the source / drain doped layer 150.

[0202] Therefore, in this embodiment, the thickness of the second trench layer 133 is... to For example, the thickness of the second channel layer 133 is or

[0203] It is understandable that, based on actual process requirements, compared with the scheme without a second channel layer, this embodiment can appropriately reduce the thickness of the first channel layer 132 so that the thickness and width of the channel layer 135 meet the process requirements.

[0204] refer to Figure 13 and Figure 14 , Figure 13 It is a top view. Figure 14 (a) is Figure 13 A cross-sectional view along the AA1 direction. Figure 14 (b) is Figure 13 A cross-sectional view along the BB1 ​​direction shows a gate structure 220 formed in the gate opening 205 and the through-slot 206. The gate structure 220 includes a gate dielectric layer 230 surrounding the second channel layer 133 and a gate electrode layer 240 covering the gate dielectric layer 230.

[0205] The gate structure 220 is used to control the opening or closing of the conductive channel of the corresponding transistor.

[0206] The gate dielectric layer 230 is used to isolate the gate electrode layer 240 and the conductive channel.

[0207] The material of the gate dielectric layer 230 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0208] In this embodiment, the gate structure 220 is a metal gate structure. Therefore, the gate dielectric layer 230 includes a high-k gate dielectric layer.

[0209] The high-k gate dielectric layer is made of a high-k dielectric material, which refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc. As an example, the material of the high-k gate dielectric layer is HfO2.

[0210] It should be noted that the gate dielectric layer 230 may further include a gate oxide layer located between the high-k gate dielectric layer and the second channel layer 133. As an example, the material of the gate oxide layer may be silicon oxide.

[0211] The gate electrode layer 240 is used to draw out the electrical properties of the gate structure 220.

[0212] The material of the gate electrode layer 240 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0213] In this embodiment, the gate electrode layer 240 includes a work function layer 241 and an electrode layer 242 covering the work function layer 241. The work function layer 241 is used to adjust the threshold voltage of the corresponding transistor.

[0214] In other embodiments, the gate electrode layer may also consist only of a work function layer.

[0215] As an example, the first sub-device region 100n is used to form an NMOS transistor, and the second sub-device region 100p is used to form a PMOS transistor. Therefore, the work function layer 241 located in the first sub-device region 100n is made of a different material than the work function layer 241 located in the second sub-device region 100p.

[0216] It should be noted that an isolation wall 170 is provided on the substrate between adjacent sub-device regions 100a, which helps to reduce the probability of mutual influence between the work function layers 241 of adjacent sub-device regions 100a (for example, reducing the probability of ions diffusing into each other in the work function layers 241), thereby helping to further improve the performance of the semiconductor structure.

[0217] It should also be noted that the top of the isolation wall 170 is higher than the top of the top first channel layer 132. Therefore, the gate structure 220 also covers the sidewall of the isolation wall 170, which is higher than the top surface of the top channel layer 135.

[0218] As an example, the top of the gate structure 220 is flush with the top of the isolation wall 170, so that the gate structures 220 of adjacent sub-device regions 100a are isolated from each other by the isolation wall 170, thereby further reducing the probability of mutual interference between the gate structures 220 of adjacent sub-device regions 100a.

[0219] In other embodiments, each sub-device region may share an electrode layer within the same device unit region.

[0220] Figures 15 to 16 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming the semiconductor structure of the present invention.

[0221] The similarities between this embodiment and the previous embodiments will not be repeated here. The differences between this embodiment and the previous embodiments are as follows: Figure 15 As shown, in the step of providing the substrate, an isolation layer 804 is formed between the laminated structure 820 and the substrate, that is, an isolation layer 804 is also formed between the bottommost channel laminate (not shown) and the substrate.

[0222] Accordingly, before forming the laminated structure 820 on the substrate, the method further includes forming a third sacrificial layer (not shown) on the substrate.

[0223] The third sacrificial layer is used to occupy space for the subsequent formation of the isolation layer 804.

[0224] Specifically, the third sacrificial layer is formed on the top of the fin 810.

[0225] In this embodiment, the stacked structure 820 is formed on the third sacrificial layer.

[0226] It should be noted that the third sacrificial layer and the stacked structure 820 are patterned in the same etching process. That is, after the material layer corresponding to the third sacrificial layer and the material layer corresponding to the stacked structure 820 are formed in sequence, they are etched from top to bottom to form the stacked structure 820 and the third sacrificial layer located at the bottom of the stacked structure 820.

[0227] In this embodiment, the third sacrificial layer is made of a material with an etching selectivity ratio to the stacked structure 820, so as to reduce damage to the stacked structure 820 when the third sacrificial layer is removed in the future.

[0228] As an example, in the stacked structure 820, the material of the first channel layer (not shown) is silicon, the material of the first sacrificial layer (not shown) is silicon germanide, therefore, the material of the third sacrificial layer is also silicon germanide, and the germanium concentration in the third sacrificial layer is greater than the germanium concentration in the first sacrificial layer.

[0229] In silicon germanide materials, the higher the germanium concentration, the greater the etching rate. Therefore, the third sacrificial layer is made of silicon germanide with a higher germanium concentration, which makes it easier to remove the third sacrificial layer and causes less damage to the stacked structure 820.

[0230] Moreover, the material of the third sacrificial layer is also a semiconductor material, so that epitaxial growth can be performed on the third sacrificial layer, which reduces the impact on the stacked structure 820 and has high process compatibility.

[0231] Accordingly, in this embodiment, the isolation wall 870 also penetrates the third sacrificial layer.

[0232] In this embodiment, after the isolation wall 870 is formed, the third sacrificial layer is removed, and a trench (not shown) is formed between the laminated structure 820 and the substrate.

[0233] The trench is formed by the bottom of the laminated structure 820, the top of the base, and the sidewalls of the isolation wall 870.

[0234] The trenches provide space for the formation of subsequent isolation layers.

[0235] In this embodiment, an isotropic etching process is used to remove the third sacrificial layer so as to completely remove the third sacrificial layer at the bottom of the stacked structure 820.

[0236] It should be noted that the isolation wall 870 is located on the substrate between adjacent sub-device areas (not shown). Specifically, the isolation wall 870 is located between the stacked structures 820. The isolation wall 870 covers the sidewalls of the stacked structures 120 on both sides. Therefore, the ends of the stacked structures 120 are in contact with the sidewalls of the isolation wall 870. With the support of the isolation wall 870, after the third sacrificial layer is removed, the stacked structure 120 can be suspended on the substrate.

[0237] refer to Figure 15 An isolation layer 804 is formed in the trench.

[0238] The isolation layer 804 is used to isolate the subsequently formed gate structure and substrate, thereby reducing the probability of leakage current between the gate structure and the substrate, and helping to suppress the formation of parasitic devices.

[0239] Specifically, the step of forming the isolation layer 804 in the trench includes: forming an isolation film covering the top and sidewalls of the stacked structure 120, the top and sidewalls of the isolation wall 870, the top of the substrate, and the sidewalls of the fin 810, the isolation film also filling the trench; etching away the isolation film covering the top and sidewalls of the stacked structure 120, the top and sidewalls of the isolation wall 870, the top of the substrate, and the sidewalls of the fin 810, leaving the remaining isolation film in the trench as the isolation layer 804.

[0240] The trench is formed by the bottom of the stacked structure 820, the top of the substrate, and the sidewall of the isolation wall 870. Therefore, during the etching of the isolation film, the isolation film in the trench can be retained under the shielding effect of the stacked structure 820.

[0241] As an example, an atomic layer deposition process is used to form an isolation membrane to improve the filling effect of the isolation membrane in the trench.

[0242] The insulating layer 804 is made of a dielectric material. Specifically, the dielectric material includes one or more of silicon oxide, silicon oxynitride, and silicon nitride. As an example, the insulating layer 804 is made of silicon oxide.

[0243] In this embodiment, the isolation layer 804 is a film structure. Compared with the scheme of forming the isolation layer by ion implantation of the substrate (that is, the isolation layer is an ion-doped layer), this embodiment can avoid the problem of increased parasitic capacitance caused by ion implantation of the substrate.

[0244] In this embodiment, after the isolation layer 804 is formed, an isolation structure 801 is formed on the substrate on the side of the fin 810. The isolation structure 801 covers the sidewall of the fin 810 and the sidewall of the isolation layer 804, and exposes the stacked structure 820.

[0245] Specifically, the top of the isolation structure 801 is flush with the top of the isolation layer 804.

[0246] Reference Figure 16 The diagram shows the structure after the gate structure is formed. Figure 16 (a) is a sectional view along the direction perpendicular to the sidewall of the isolation wall. Figure 16(b) is a cross-sectional view located on one side of the isolation wall and extending along the direction of the isolation wall. Accordingly, the second channel layer (not shown) is epitaxially grown on the surface of the first channel layer exposed by the isolation wall (not shown). Since the isolation layer 804 covers the substrate below the first channel layer, the second channel layer will not be formed on the surface of the isolation layer 804 during the epitaxial growth of the second channel layer, thereby making the bottom of the gate structure (not shown) contact with the isolation layer 804.

[0247] As an example, during the formation of the source / drain doped layer (not shown), the bottom of the source / drain groove exposes the isolation layer 804. Therefore, the bottom of the source / drain doped layer is in contact with the isolation layer 804, thereby effectively isolating the source / drain doped layer through the isolation layer 804 and reducing the probability of punch-through between the source / drain doped layers.

[0248] In other embodiments, the bottom of the source / drain groove is also etched to expose the top of the fin 810. Accordingly, the source / drain doped layer is in contact with the substrate, thereby increasing the growth rate of the source / drain doped layer and improving the growth quality of the source / drain doped layer, and reducing defects generated during the growth process.

[0249] It should be noted that the process after forming the isolation layer 804 is the same as in the previous embodiment, and will not be described again in this embodiment.

[0250] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes discrete device cell regions, each of which includes a plurality of adjacent sub-device regions in a first direction; Multiple channel structure layers extending along a second direction are respectively located on the substrate of the sub-device region and spaced apart from the substrate. The second direction is perpendicular to the first direction. The channel structure layer includes one or more spaced first channel layers. An isolation wall is located on a substrate between adjacent sub-device areas and extends along the second direction, the isolation wall covers the sidewalls of the channel structure layer on both sides, and the top of the isolation wall is higher than the top of the channel structure layer; The second channel layer is located on the top, bottom, and side surfaces of the first channel layer exposed by the isolation wall. At the junction of the top surface of the first channel layer and the side wall of the isolation wall, and at the junction of the bottom surface of the first channel layer and the side wall of the isolation wall, the angle between the end face of the second channel layer and the side wall of the isolation wall exposed by the first channel layer is an acute angle. The second channel layer and the first channel layer are used to form a channel layer. A gate structure is located on the substrate of the sub-device region and spans the channel structure layer along the first direction. The gate structure covers the top and sidewalls of the channel structure layer of the sub-device region. The gate structure includes a gate dielectric layer surrounding the second channel layer covering the sub-device region and a gate electrode layer covering the gate dielectric layer. The source and drain doped layers are located on the substrates on both sides of the gate structure of the sub-device region and cover the end face of the channel structure layer below the gate structure. The source and drain doped layers of adjacent sub-device regions are isolated by the isolation wall.

2. The semiconductor structure as described in claim 1, characterized in that, The angle between the end face of the second trench layer and the exposed sidewall of the isolation wall of the first trench layer is 35 degrees to 75 degrees.

3. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes an isolation layer located below the channel structure layer and between the bottom of the gate structure and the top of the substrate.

4. The semiconductor structure as described in claim 1, characterized in that, In the device cell region, the sub-device region includes a first sub-device region for forming a first type transistor and a second sub-device region for forming a second type transistor, wherein the first type transistor and the second type transistor have different channel conductivity types; The isolation wall is located on the substrate between the first sub-device area and the second sub-device area.

5. The semiconductor structure as described in claim 1, characterized in that, The substrate includes a substrate and fins protruding from the substrate of the device unit region; The channel structure layers are located on the fins of the sub-device area and are spaced apart from the fins; The bottom of the isolation wall extends into the fin.

6. The semiconductor structure as described in claim 1, characterized in that, The portion of the gate structure located between adjacent channel layers and between the channel layer and the substrate is designated as the first portion; The semiconductor structure further includes an inner sidewall located between the source / drain doped layer and the first portion.

7. The semiconductor structure as described in claim 6, characterized in that, The remaining portion of the gate structure serves as the second part; The top surface of the source / drain doped layer is higher than the top surface of the channel structure layer; The inner wall is also located between the source / drain doped layer and the second part.

8. The semiconductor structure as described in claim 1, characterized in that, The material of the first channel layer includes silicon, silicon germanide, germanium, or a group III-V semiconductor material, and the material of the second channel layer includes silicon, silicon germanide, germanium, or a group III-V semiconductor material.

9. The semiconductor structure as described in claim 1, characterized in that, The thickness of the second channel layer is to 10. The semiconductor structure as claimed in claim 1, characterized in that, The material of the isolation wall includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, and silicon carbonitride.

11. The semiconductor structure as described in claim 3, characterized in that, The material of the isolation layer includes a dielectric material, which includes one or more of silicon oxide, silicon oxynitride, and silicon nitride.

12. The semiconductor structure as claimed in claim 1, characterized in that, The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3, and the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

13. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, including discrete device cell regions, each device cell region comprising a plurality of adjacent sub-device regions in a first direction. A stacked structure extending in a second direction, perpendicular to the first direction, is formed on the substrate of each of the plurality of sub-device regions. The stacked structure includes one or more stacked channel layers, each channel layer including a first sacrificial layer and a first channel layer located on the first sacrificial layer. An isolation wall extending in the second direction is formed on the substrate between adjacent sub-device regions, the isolation wall covering the sidewalls of the stacked structure on both sides. A dielectric layer is formed on the substrate, covering a portion of the stacked structure. A gate opening is formed in the dielectric layer, penetrating the dielectric layer and extending along the first direction. The gate opening spans the stacked structure and isolation wall of the device cell region, and exposes a portion of the top and a portion of the sidewalls of the stacked structure. The first sacrificial layer is removed through the gate opening to form a through slot connected to the gate opening; After the through-slot is formed, a second channel layer is formed on the top, bottom, and side surfaces of the first channel layer exposed at the gate opening and through-slot. At the junction of the top surface of the first channel layer and the side wall of the isolation wall, and at the junction of the bottom surface of the first channel layer and the side wall of the isolation wall, the angle between the end face of the second channel layer and the side wall of the isolation wall exposed by the first channel layer is an acute angle. The second channel layer and the first channel layer are used to constitute a channel layer. A gate structure is formed in the gate opening and the through-slot, the gate structure including a gate dielectric layer surrounding the second channel layer and a gate electrode layer covering the gate dielectric layer.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The second trench layer is formed using an epitaxial growth process.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The process temperature for the epitaxial growth process is 200℃ to 500℃.

16. The method for forming a semiconductor structure as described in claim 13, characterized in that, Before forming a dielectric layer covering a portion of the stacked structure on the substrate, the forming method further includes: forming a pseudo-gate structure on the substrate that spans the stacked structure and the isolation wall along the first direction; forming source / drain doped layers in the stacked structures on both sides of the pseudo-gate structure, wherein the source / drain doped layers of adjacent sub-device regions are isolated from each other by the isolation wall; The step of forming a dielectric layer covering a portion of the stacked structure on the substrate includes: after forming the source and drain doping, forming a dielectric layer covering the sidewalls of the dummy gate structure on the substrate, wherein the dielectric layer exposes the top of the dummy gate structure; The step of forming the gate opening includes: removing the dummy gate structure.

17. The method for forming a semiconductor structure as described in claim 13, characterized in that, In the step of providing the substrate, the laminated structure further includes a second sacrificial layer located on top of the topmost channel laminate, the second sacrificial layer being made of the same material as the first sacrificial layer; In the step of removing the first sacrificial layer through the gate opening, the second sacrificial layer exposed by the gate opening is also removed.

18. The method for forming a semiconductor structure as described in claim 13, characterized in that, In the step of providing the substrate, an isolation layer is also formed between the bottommost channel stack and the substrate.

19. The method for forming a semiconductor structure as described in claim 13, characterized in that, In the step of providing the substrate, in the device cell region, the sub-device region includes a first sub-device region for forming a first type transistor and a second sub-device region for forming a second type transistor, wherein the first type transistor and the second type transistor have different channel conductivity types; The isolation wall is formed on the substrate between the first sub-device area and the second sub-device area.

20. The method for forming a semiconductor structure as described in claim 13, characterized in that, In the step of providing a substrate, the substrate includes a substrate and fins protruding from the substrate of the device unit region; the stacked structure is located on top of the fins, and the bottom of the isolation wall extends into the fins.

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